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Searched refs:TRANSCONF (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_pch_display.c278 pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)); in ilk_enable_pch_transcoder()
421 u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5; in ilk_pch_enable()
566 TRANSCONF(dev_priv, cpu_transcoder)); in lpt_enable_pch_transcoder()
H A Dintel_display.c414 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_wait_for_pipe_off()
438 TRANSCONF(dev_priv, cpu_transcoder)); in assert_transcoder()
562 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_enable_transcoder()
577 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), in intel_enable_transcoder()
579 intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_enable_transcoder()
608 val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); in intel_disable_transcoder()
628 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); in intel_disable_transcoder()
2935 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
2938 TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; in intel_pipe_is_interlaced()
3090 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); in i9xx_set_pipeconf()
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H A Dintel_fdi.c1046 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_pll_enable()
1102 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_disable()
1128 temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; in ilk_fdi_disable()
H A Dicl_dsi.c1028 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0, in gen11_dsi_enable_transcoder()
1032 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans), in gen11_dsi_enable_transcoder()
1295 intel_de_rmw(display, TRANSCONF(display, dsi_trans), in gen11_dsi_disable_transcoder()
1299 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans), in gen11_dsi_disable_transcoder()
1732 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans)); in gen11_dsi_get_hw_state()
H A Dintel_display_power_well.c1075 if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1077 if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1095 return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1096 intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
H A Dvlv_dsi.c978 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c133 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
134 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B)); in iterate_generic_mmio()
135 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C)); in iterate_generic_mmio()
136 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP)); in iterate_generic_mmio()
H A Di915_reg.h1584 #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) macro