xref: /linux/arch/powerpc/include/asm/nohash/mmu-e500.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_MMU_BOOK3E_H_
3 #define _ASM_POWERPC_MMU_BOOK3E_H_
4 /*
5  * Freescale Book-E/Book-3e (ISA 2.06+) MMU support
6  */
7 
8 /* Book-3e defined page sizes */
9 #define BOOK3E_PAGESZ_1K	0
10 #define BOOK3E_PAGESZ_2K	1
11 #define BOOK3E_PAGESZ_4K	2
12 #define BOOK3E_PAGESZ_8K	3
13 #define BOOK3E_PAGESZ_16K	4
14 #define BOOK3E_PAGESZ_32K	5
15 #define BOOK3E_PAGESZ_64K	6
16 #define BOOK3E_PAGESZ_128K	7
17 #define BOOK3E_PAGESZ_256K	8
18 #define BOOK3E_PAGESZ_512K	9
19 #define BOOK3E_PAGESZ_1M	10
20 #define BOOK3E_PAGESZ_2M	11
21 #define BOOK3E_PAGESZ_4M	12
22 #define BOOK3E_PAGESZ_8M	13
23 #define BOOK3E_PAGESZ_16M	14
24 #define BOOK3E_PAGESZ_32M	15
25 #define BOOK3E_PAGESZ_64M	16
26 #define BOOK3E_PAGESZ_128M	17
27 #define BOOK3E_PAGESZ_256M	18
28 #define BOOK3E_PAGESZ_512M	19
29 #define BOOK3E_PAGESZ_1GB	20
30 #define BOOK3E_PAGESZ_2GB	21
31 #define BOOK3E_PAGESZ_4GB	22
32 #define BOOK3E_PAGESZ_8GB	23
33 #define BOOK3E_PAGESZ_16GB	24
34 #define BOOK3E_PAGESZ_32GB	25
35 #define BOOK3E_PAGESZ_64GB	26
36 #define BOOK3E_PAGESZ_128GB	27
37 #define BOOK3E_PAGESZ_256GB	28
38 #define BOOK3E_PAGESZ_512GB	29
39 #define BOOK3E_PAGESZ_1TB	30
40 #define BOOK3E_PAGESZ_2TB	31
41 
42 /* MAS registers bit definitions */
43 
44 #define MAS0_TLBSEL_MASK	0x30000000
45 #define MAS0_TLBSEL_SHIFT	28
46 #define MAS0_TLBSEL(x)		(((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK)
47 #define MAS0_GET_TLBSEL(mas0)	(((mas0) & MAS0_TLBSEL_MASK) >> \
48 			MAS0_TLBSEL_SHIFT)
49 #define MAS0_ESEL_MASK		0x0FFF0000
50 #define MAS0_ESEL_SHIFT		16
51 #define MAS0_ESEL(x)		(((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK)
52 #define MAS0_NV(x)		((x) & 0x00000FFF)
53 #define MAS0_HES		0x00004000
54 #define MAS0_WQ_ALLWAYS		0x00000000
55 #define MAS0_WQ_COND		0x00001000
56 #define MAS0_WQ_CLR_RSRV       	0x00002000
57 
58 #define MAS1_VALID		0x80000000
59 #define MAS1_IPROT		0x40000000
60 #define MAS1_TID(x)		(((x) << 16) & 0x3FFF0000)
61 #define MAS1_IND		0x00002000
62 #define MAS1_TS			0x00001000
63 #define MAS1_TSIZE_MASK		0x00000f80
64 #define MAS1_TSIZE_SHIFT	7
65 #define MAS1_TSIZE(x)		(((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
66 #define MAS1_GET_TSIZE(mas1)	(((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT)
67 
68 #define MAS2_EPN		(~0xFFFUL)
69 #define MAS2_X0			0x00000040
70 #define MAS2_X1			0x00000020
71 #define MAS2_W			0x00000010
72 #define MAS2_I			0x00000008
73 #define MAS2_M			0x00000004
74 #define MAS2_G			0x00000002
75 #define MAS2_E			0x00000001
76 #define MAS2_WIMGE_MASK		0x0000001f
77 #define MAS2_EPN_MASK(size)		(~0 << (size + 10))
78 
79 #define MAS3_RPN		0xFFFFF000
80 #define MAS3_U0			0x00000200
81 #define MAS3_U1			0x00000100
82 #define MAS3_U2			0x00000080
83 #define MAS3_U3			0x00000040
84 #define MAS3_UX			0x00000020
85 #define MAS3_SX			0x00000010
86 #define MAS3_UW			0x00000008
87 #define MAS3_SW			0x00000004
88 #define MAS3_UR			0x00000002
89 #define MAS3_SR			0x00000001
90 #define MAS3_BAP_MASK		0x0000003f
91 #define MAS3_SPSIZE		0x0000003e
92 #define MAS3_SPSIZE_SHIFT	1
93 
94 #define MAS4_TLBSEL_MASK	MAS0_TLBSEL_MASK
95 #define MAS4_TLBSELD(x) 	MAS0_TLBSEL(x)
96 #define MAS4_INDD		0x00008000	/* Default IND */
97 #define MAS4_TSIZED(x)		MAS1_TSIZE(x)
98 #define MAS4_X0D		0x00000040
99 #define MAS4_X1D		0x00000020
100 #define MAS4_WD			0x00000010
101 #define MAS4_ID			0x00000008
102 #define MAS4_MD			0x00000004
103 #define MAS4_GD			0x00000002
104 #define MAS4_ED			0x00000001
105 #define MAS4_WIMGED_MASK	0x0000001f	/* Default WIMGE */
106 #define MAS4_WIMGED_SHIFT	0
107 #define MAS4_VLED		MAS4_X1D	/* Default VLE */
108 #define MAS4_ACMD		0x000000c0	/* Default ACM */
109 #define MAS4_ACMD_SHIFT		6
110 #define MAS4_TSIZED_MASK	0x00000f80	/* Default TSIZE */
111 #define MAS4_TSIZED_SHIFT	7
112 
113 #define MAS5_SGS		0x80000000
114 
115 #define MAS6_SPID0		0x3FFF0000
116 #define MAS6_SPID1		0x00007FFE
117 #define MAS6_ISIZE(x)		MAS1_TSIZE(x)
118 #define MAS6_SAS		0x00000001
119 #define MAS6_SPID		MAS6_SPID0
120 #define MAS6_SIND 		0x00000002	/* Indirect page */
121 #define MAS6_SIND_SHIFT		1
122 #define MAS6_SPID_MASK		0x3fff0000
123 #define MAS6_SPID_SHIFT		16
124 #define MAS6_ISIZE_MASK		0x00000f80
125 #define MAS6_ISIZE_SHIFT	7
126 
127 #define MAS7_RPN		0xFFFFFFFF
128 
129 #define MAS8_TGS		0x80000000 /* Guest space */
130 #define MAS8_VF			0x40000000 /* Virtualization Fault */
131 #define MAS8_TLPID		0x000000ff
132 
133 /* Bit definitions for MMUCFG */
134 #define MMUCFG_MAVN	0x00000003	/* MMU Architecture Version Number */
135 #define MMUCFG_MAVN_V1	0x00000000	/* v1.0 */
136 #define MMUCFG_MAVN_V2	0x00000001	/* v2.0 */
137 #define MMUCFG_NTLBS	0x0000000c	/* Number of TLBs */
138 #define MMUCFG_PIDSIZE	0x000007c0	/* PID Reg Size */
139 #define MMUCFG_TWC	0x00008000	/* TLB Write Conditional (v2.0) */
140 #define MMUCFG_LRAT	0x00010000	/* LRAT Supported (v2.0) */
141 #define MMUCFG_RASIZE	0x00fe0000	/* Real Addr Size */
142 #define MMUCFG_LPIDSIZE	0x0f000000	/* LPID Reg Size */
143 
144 /* Bit definitions for MMUCSR0 */
145 #define MMUCSR0_TLB1FI	0x00000002	/* TLB1 Flash invalidate */
146 #define MMUCSR0_TLB0FI	0x00000004	/* TLB0 Flash invalidate */
147 #define MMUCSR0_TLB2FI	0x00000040	/* TLB2 Flash invalidate */
148 #define MMUCSR0_TLB3FI	0x00000020	/* TLB3 Flash invalidate */
149 #define MMUCSR0_TLBFI	(MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
150 			 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
151 #define MMUCSR0_TLB0PS	0x00000780	/* TLB0 Page Size */
152 #define MMUCSR0_TLB1PS	0x00007800	/* TLB1 Page Size */
153 #define MMUCSR0_TLB2PS	0x00078000	/* TLB2 Page Size */
154 #define MMUCSR0_TLB3PS	0x00780000	/* TLB3 Page Size */
155 
156 /* MMUCFG bits */
157 #define MMUCFG_MAVN_NASK	0x00000003
158 #define MMUCFG_MAVN_V1_0	0x00000000
159 #define MMUCFG_MAVN_V2_0	0x00000001
160 #define MMUCFG_NTLB_MASK	0x0000000c
161 #define MMUCFG_NTLB_SHIFT	2
162 #define MMUCFG_PIDSIZE_MASK	0x000007c0
163 #define MMUCFG_PIDSIZE_SHIFT	6
164 #define MMUCFG_TWC		0x00008000
165 #define MMUCFG_LRAT		0x00010000
166 #define MMUCFG_RASIZE_MASK	0x00fe0000
167 #define MMUCFG_RASIZE_SHIFT	17
168 #define MMUCFG_LPIDSIZE_MASK	0x0f000000
169 #define MMUCFG_LPIDSIZE_SHIFT	24
170 
171 /* TLBnCFG encoding */
172 #define TLBnCFG_N_ENTRY		0x00000fff	/* number of entries */
173 #define TLBnCFG_HES		0x00002000	/* HW select supported */
174 #define TLBnCFG_IPROT		0x00008000	/* IPROT supported */
175 #define TLBnCFG_GTWE		0x00010000	/* Guest can write */
176 #define TLBnCFG_IND		0x00020000	/* IND entries supported */
177 #define TLBnCFG_PT		0x00040000	/* Can load from page table */
178 #define TLBnCFG_MINSIZE		0x00f00000	/* Minimum Page Size (v1.0) */
179 #define TLBnCFG_MINSIZE_SHIFT	20
180 #define TLBnCFG_MAXSIZE		0x000f0000	/* Maximum Page Size (v1.0) */
181 #define TLBnCFG_MAXSIZE_SHIFT	16
182 #define TLBnCFG_ASSOC		0xff000000	/* Associativity */
183 #define TLBnCFG_ASSOC_SHIFT	24
184 
185 /* TLBnPS encoding */
186 #define TLBnPS_4K		0x00000004
187 #define TLBnPS_8K		0x00000008
188 #define TLBnPS_16K		0x00000010
189 #define TLBnPS_32K		0x00000020
190 #define TLBnPS_64K		0x00000040
191 #define TLBnPS_128K		0x00000080
192 #define TLBnPS_256K		0x00000100
193 #define TLBnPS_512K		0x00000200
194 #define TLBnPS_1M 		0x00000400
195 #define TLBnPS_2M 		0x00000800
196 #define TLBnPS_4M 		0x00001000
197 #define TLBnPS_8M 		0x00002000
198 #define TLBnPS_16M		0x00004000
199 #define TLBnPS_32M		0x00008000
200 #define TLBnPS_64M		0x00010000
201 #define TLBnPS_128M		0x00020000
202 #define TLBnPS_256M		0x00040000
203 #define TLBnPS_512M		0x00080000
204 #define TLBnPS_1G		0x00100000
205 #define TLBnPS_2G		0x00200000
206 #define TLBnPS_4G		0x00400000
207 #define TLBnPS_8G		0x00800000
208 #define TLBnPS_16G		0x01000000
209 #define TLBnPS_32G		0x02000000
210 #define TLBnPS_64G		0x04000000
211 #define TLBnPS_128G		0x08000000
212 #define TLBnPS_256G		0x10000000
213 
214 /* tlbilx action encoding */
215 #define TLBILX_T_ALL			0
216 #define TLBILX_T_TID			1
217 #define TLBILX_T_FULLMATCH		3
218 #define TLBILX_T_CLASS0			4
219 #define TLBILX_T_CLASS1			5
220 #define TLBILX_T_CLASS2			6
221 #define TLBILX_T_CLASS3			7
222 
223 /*
224  * The mapping only needs to be cache-coherent on SMP, except on
225  * Freescale e500mc derivatives where it's also needed for coherent DMA.
226  */
227 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
228 #define MAS2_M_IF_NEEDED	MAS2_M
229 #else
230 #define MAS2_M_IF_NEEDED	0
231 #endif
232 
233 #ifndef __ASSEMBLY__
234 #include <asm/bug.h>
235 
236 extern unsigned int tlbcam_index;
237 
238 typedef struct {
239 	unsigned int	id;
240 	unsigned int	active;
241 	void __user	*vdso;
242 } mm_context_t;
243 
244 /* Page size definitions, common between 32 and 64-bit
245  *
246  *    shift : is the "PAGE_SHIFT" value for that page size
247  *
248  */
249 struct mmu_psize_def
250 {
251 	unsigned int	shift;	/* number of bits */
252 	unsigned int	flags;
253 #define MMU_PAGE_SIZE_DIRECT	0x1	/* Supported as a direct size */
254 #define MMU_PAGE_SIZE_INDIRECT	0x2	/* Supported as an indirect size */
255 };
256 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
257 
shift_to_mmu_psize(unsigned int shift)258 static inline int shift_to_mmu_psize(unsigned int shift)
259 {
260 	int psize;
261 
262 	for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
263 		if (mmu_psize_defs[psize].shift == shift)
264 			return psize;
265 	return -1;
266 }
267 
mmu_psize_to_shift(unsigned int mmu_psize)268 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
269 {
270 	if (mmu_psize_defs[mmu_psize].shift)
271 		return mmu_psize_defs[mmu_psize].shift;
272 	BUG();
273 }
274 
275 /* The page sizes use the same names as 64-bit hash but are
276  * constants
277  */
278 #if defined(CONFIG_PPC_4K_PAGES)
279 #define mmu_virtual_psize	MMU_PAGE_4K
280 #else
281 #error Unsupported page size
282 #endif
283 
284 extern int mmu_linear_psize;
285 extern int mmu_vmemmap_psize;
286 
287 struct tlb_core_data {
288 	/*
289 	 * Per-core spinlock for e6500 TLB handlers (no tlbsrx.)
290 	 * Must be the first struct element.
291 	 */
292 	u8 lock;
293 
294 	/* For software way selection, as on Freescale TLB1 */
295 	u8 esel_next, esel_max, esel_first;
296 };
297 
298 #ifdef CONFIG_PPC64
299 extern unsigned long linear_map_top;
300 extern int book3e_htw_mode;
301 
302 #define PPC_HTW_NONE	0
303 #define PPC_HTW_E6500	1
304 
305 /*
306  * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
307  * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
308  * return 1, indicating that the tlb requires preloading.
309  */
310 #define HUGETLB_NEED_PRELOAD
311 
312 #define mmu_cleanup_all NULL
313 
314 #define MAX_PHYSMEM_BITS        44
315 
316 #endif
317 
318 #include <asm/percpu.h>
319 DECLARE_PER_CPU(int, next_tlbcam_idx);
320 
321 #endif /* !__ASSEMBLY__ */
322 
323 #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
324