1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Digigram pcxhr compatible soundcards
4 *
5 * main file with alsa callbacks
6 *
7 * Copyright (c) 2004 by Digigram <alsa@digigram.com>
8 */
9
10
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/info.h>
23 #include <sound/control.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include "pcxhr.h"
27 #include "pcxhr_mixer.h"
28 #include "pcxhr_hwdep.h"
29 #include "pcxhr_core.h"
30 #include "pcxhr_mix22.h"
31
32 #define DRIVER_NAME "pcxhr"
33
34 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
35 "Marc Titinger <titinger@digigram.com>");
36 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
37 MODULE_LICENSE("GPL");
38
39 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
40 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
41 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
42 static bool mono[SNDRV_CARDS]; /* capture mono only */
43
44 module_param_array(index, int, NULL, 0444);
45 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
46 module_param_array(id, charp, NULL, 0444);
47 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
48 module_param_array(enable, bool, NULL, 0444);
49 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
50 module_param_array(mono, bool, NULL, 0444);
51 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
52
53 enum {
54 PCI_ID_VX882HR,
55 PCI_ID_PCX882HR,
56 PCI_ID_VX881HR,
57 PCI_ID_PCX881HR,
58 PCI_ID_VX882E,
59 PCI_ID_PCX882E,
60 PCI_ID_VX881E,
61 PCI_ID_PCX881E,
62 PCI_ID_VX1222HR,
63 PCI_ID_PCX1222HR,
64 PCI_ID_VX1221HR,
65 PCI_ID_PCX1221HR,
66 PCI_ID_VX1222E,
67 PCI_ID_PCX1222E,
68 PCI_ID_VX1221E,
69 PCI_ID_PCX1221E,
70 PCI_ID_VX222HR,
71 PCI_ID_VX222E,
72 PCI_ID_PCX22HR,
73 PCI_ID_PCX22E,
74 PCI_ID_VX222HRMIC,
75 PCI_ID_VX222E_MIC,
76 PCI_ID_PCX924HR,
77 PCI_ID_PCX924E,
78 PCI_ID_PCX924HRMIC,
79 PCI_ID_PCX924E_MIC,
80 PCI_ID_VX442HR,
81 PCI_ID_PCX442HR,
82 PCI_ID_VX442E,
83 PCI_ID_PCX442E,
84 PCI_ID_VX822HR,
85 PCI_ID_PCX822HR,
86 PCI_ID_VX822E,
87 PCI_ID_PCX822E,
88 PCI_ID_LAST
89 };
90
91 static const struct pci_device_id pcxhr_ids[] = {
92 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb001), .driver_data = PCI_ID_VX882HR },
93 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb101), .driver_data = PCI_ID_PCX882HR },
94 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb201), .driver_data = PCI_ID_VX881HR },
95 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb301), .driver_data = PCI_ID_PCX881HR },
96 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb021), .driver_data = PCI_ID_VX882E },
97 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb121), .driver_data = PCI_ID_PCX882E },
98 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb221), .driver_data = PCI_ID_VX881E },
99 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb321), .driver_data = PCI_ID_PCX881E },
100 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb401), .driver_data = PCI_ID_VX1222HR },
101 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb501), .driver_data = PCI_ID_PCX1222HR },
102 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb601), .driver_data = PCI_ID_VX1221HR },
103 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xb701), .driver_data = PCI_ID_PCX1221HR },
104 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb421), .driver_data = PCI_ID_VX1222E },
105 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb521), .driver_data = PCI_ID_PCX1222E },
106 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb621), .driver_data = PCI_ID_VX1221E },
107 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xb721), .driver_data = PCI_ID_PCX1221E },
108 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xba01), .driver_data = PCI_ID_VX222HR },
109 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xba21), .driver_data = PCI_ID_VX222E },
110 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbd01), .driver_data = PCI_ID_PCX22HR },
111 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbd21), .driver_data = PCI_ID_PCX22E },
112 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbc01), .driver_data = PCI_ID_VX222HRMIC },
113 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbc21), .driver_data = PCI_ID_VX222E_MIC },
114 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbb01), .driver_data = PCI_ID_PCX924HR },
115 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbb21), .driver_data = PCI_ID_PCX924E },
116 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbf01), .driver_data = PCI_ID_PCX924HRMIC },
117 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xbf21), .driver_data = PCI_ID_PCX924E_MIC },
118 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xd001), .driver_data = PCI_ID_VX442HR },
119 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xd101), .driver_data = PCI_ID_PCX442HR },
120 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xd021), .driver_data = PCI_ID_VX442E },
121 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xd121), .driver_data = PCI_ID_PCX442E },
122 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xd201), .driver_data = PCI_ID_VX822HR },
123 { PCI_DEVICE_SUB(0x10b5, 0x9656, 0x1369, 0xd301), .driver_data = PCI_ID_PCX822HR },
124 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xd221), .driver_data = PCI_ID_VX822E },
125 { PCI_DEVICE_SUB(0x10b5, 0x9056, 0x1369, 0xd321), .driver_data = PCI_ID_PCX822E },
126 { }
127 };
128
129 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
130
131 struct board_parameters {
132 char* board_name;
133 short playback_chips;
134 short capture_chips;
135 short fw_file_set;
136 short firmware_num;
137 };
138 static const struct board_parameters pcxhr_board_params[] = {
139 [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 },
140 [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 },
141 [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 },
142 [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 },
143 [PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 },
144 [PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 },
145 [PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 },
146 [PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 },
147 [PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 },
148 [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 },
149 [PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 },
150 [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 },
151 [PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 },
152 [PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 },
153 [PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 },
154 [PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 },
155 [PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 },
156 [PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 },
157 [PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 },
158 [PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 },
159 [PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 },
160 [PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 },
161 [PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 },
162 [PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 },
163 [PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 },
164 [PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 },
165 [PCI_ID_VX442HR] = { "VX442HR", 2, 2, 0, 41 },
166 [PCI_ID_PCX442HR] = { "PCX442HR", 2, 2, 0, 41 },
167 [PCI_ID_VX442E] = { "VX442e", 2, 2, 1, 41 },
168 [PCI_ID_PCX442E] = { "PCX442e", 2, 2, 1, 41 },
169 [PCI_ID_VX822HR] = { "VX822HR", 4, 1, 2, 42 },
170 [PCI_ID_PCX822HR] = { "PCX822HR", 4, 1, 2, 42 },
171 [PCI_ID_VX822E] = { "VX822e", 4, 1, 3, 42 },
172 [PCI_ID_PCX822E] = { "PCX822e", 4, 1, 3, 42 },
173 };
174
175 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
176 /* VX222HR, VX222e, PCX22HR and PCX22e */
177 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
178 /* some boards do not support 192kHz on digital AES input plugs */
179 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
180 (x->fw_file_set == 0) || \
181 (x->fw_file_set == 2))
182
pcxhr_pll_freq_register(unsigned int freq,unsigned int max_freq,unsigned int * pllreg,unsigned int * realfreq)183 int pcxhr_pll_freq_register(unsigned int freq, unsigned int max_freq,
184 unsigned int *pllreg, unsigned int *realfreq)
185 {
186 unsigned int reg;
187
188 if (freq < 6900 || freq > max_freq)
189 return -EINVAL;
190 reg = (28224000 * 2) / freq;
191 reg = (reg - 1) / 2;
192 if (reg < 0x100)
193 *pllreg = reg + 0xc00;
194 else if (reg < 0x200)
195 *pllreg = reg + 0x800;
196 else if (reg < 0x400)
197 *pllreg = reg & 0x1ff;
198 else if (reg < 0x800) {
199 *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
200 reg &= ~1;
201 } else {
202 *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
203 reg &= ~3;
204 }
205 if (realfreq)
206 *realfreq = (28224000 / (reg + 1));
207 return 0;
208 }
209
210
211 #define PCXHR_FREQ_REG_MASK 0x1f
212 #define PCXHR_FREQ_QUARTZ_48000 0x00
213 #define PCXHR_FREQ_QUARTZ_24000 0x01
214 #define PCXHR_FREQ_QUARTZ_12000 0x09
215 #define PCXHR_FREQ_QUARTZ_32000 0x08
216 #define PCXHR_FREQ_QUARTZ_16000 0x04
217 #define PCXHR_FREQ_QUARTZ_8000 0x0c
218 #define PCXHR_FREQ_QUARTZ_44100 0x02
219 #define PCXHR_FREQ_QUARTZ_22050 0x0a
220 #define PCXHR_FREQ_QUARTZ_11025 0x06
221 #define PCXHR_FREQ_PLL 0x05
222 #define PCXHR_FREQ_QUARTZ_192000 0x10
223 #define PCXHR_FREQ_QUARTZ_96000 0x18
224 #define PCXHR_FREQ_QUARTZ_176400 0x14
225 #define PCXHR_FREQ_QUARTZ_88200 0x1c
226 #define PCXHR_FREQ_QUARTZ_128000 0x12
227 #define PCXHR_FREQ_QUARTZ_64000 0x1a
228
229 #define PCXHR_FREQ_WORD_CLOCK 0x0f
230 #define PCXHR_FREQ_SYNC_AES 0x0e
231 #define PCXHR_FREQ_AES_1 0x07
232 #define PCXHR_FREQ_AES_2 0x0b
233 #define PCXHR_FREQ_AES_3 0x03
234 #define PCXHR_FREQ_AES_4 0x0d
235
pcxhr_get_clock_reg(struct pcxhr_mgr * mgr,unsigned int rate,unsigned int * reg,unsigned int * freq)236 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
237 unsigned int *reg, unsigned int *freq)
238 {
239 unsigned int val, realfreq, pllreg;
240 struct pcxhr_rmh rmh;
241 int err;
242
243 realfreq = rate;
244 switch (mgr->use_clock_type) {
245 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
246 switch (rate) {
247 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
248 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
249 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
250 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
251 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
252 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
253 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
254 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
255 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
256 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
257 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
258 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
259 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
260 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
261 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
262 default :
263 val = PCXHR_FREQ_PLL;
264 /* get the value for the pll register */
265 err = pcxhr_pll_freq_register(rate, 110000, &pllreg,
266 &realfreq);
267 if (err)
268 return err;
269 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
270 rmh.cmd[0] |= IO_NUM_REG_GENCLK;
271 rmh.cmd[1] = pllreg & MASK_DSP_WORD;
272 rmh.cmd[2] = pllreg >> 24;
273 rmh.cmd_len = 3;
274 err = pcxhr_send_msg(mgr, &rmh);
275 if (err < 0) {
276 dev_err(&mgr->pci->dev,
277 "error CMD_ACCESS_IO_WRITE "
278 "for PLL register : %x!\n", err);
279 return err;
280 }
281 }
282 break;
283 case PCXHR_CLOCK_TYPE_WORD_CLOCK:
284 val = PCXHR_FREQ_WORD_CLOCK;
285 break;
286 case PCXHR_CLOCK_TYPE_AES_SYNC:
287 val = PCXHR_FREQ_SYNC_AES;
288 break;
289 case PCXHR_CLOCK_TYPE_AES_1:
290 val = PCXHR_FREQ_AES_1;
291 break;
292 case PCXHR_CLOCK_TYPE_AES_2:
293 val = PCXHR_FREQ_AES_2;
294 break;
295 case PCXHR_CLOCK_TYPE_AES_3:
296 val = PCXHR_FREQ_AES_3;
297 break;
298 case PCXHR_CLOCK_TYPE_AES_4:
299 val = PCXHR_FREQ_AES_4;
300 break;
301 default:
302 return -EINVAL;
303 }
304 *reg = val;
305 *freq = realfreq;
306 return 0;
307 }
308
309
pcxhr_sub_set_clock(struct pcxhr_mgr * mgr,unsigned int rate,int * changed)310 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
311 unsigned int rate,
312 int *changed)
313 {
314 unsigned int val, realfreq, speed;
315 struct pcxhr_rmh rmh;
316 int err;
317
318 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
319 if (err)
320 return err;
321
322 /* codec speed modes */
323 if (rate < 55000)
324 speed = 0; /* single speed */
325 else if (rate < 100000)
326 speed = 1; /* dual speed */
327 else
328 speed = 2; /* quad speed */
329 if (mgr->codec_speed != speed) {
330 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
331 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
332 if (DSP_EXT_CMD_SET(mgr)) {
333 rmh.cmd[1] = 1;
334 rmh.cmd_len = 2;
335 }
336 err = pcxhr_send_msg(mgr, &rmh);
337 if (err)
338 return err;
339
340 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
341 rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
342 rmh.cmd[1] = speed;
343 rmh.cmd_len = 2;
344 err = pcxhr_send_msg(mgr, &rmh);
345 if (err)
346 return err;
347 }
348 /* set the new frequency */
349 dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val);
350 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
351 val, changed);
352 if (err)
353 return err;
354
355 mgr->sample_rate_real = realfreq;
356 mgr->cur_clock_type = mgr->use_clock_type;
357
358 /* unmute after codec speed modes */
359 if (mgr->codec_speed != speed) {
360 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
361 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
362 if (DSP_EXT_CMD_SET(mgr)) {
363 rmh.cmd[1] = 1;
364 rmh.cmd_len = 2;
365 }
366 err = pcxhr_send_msg(mgr, &rmh);
367 if (err)
368 return err;
369 mgr->codec_speed = speed; /* save new codec speed */
370 }
371
372 dev_dbg(&mgr->pci->dev, "%s to %dHz (realfreq=%d)\n", __func__,
373 rate, realfreq);
374 return 0;
375 }
376
377 #define PCXHR_MODIFY_CLOCK_S_BIT 0x04
378
379 #define PCXHR_IRQ_TIMER_FREQ 92000
380 #define PCXHR_IRQ_TIMER_PERIOD 48
381
pcxhr_set_clock(struct pcxhr_mgr * mgr,unsigned int rate)382 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
383 {
384 struct pcxhr_rmh rmh;
385 int err, changed;
386
387 if (rate == 0)
388 return 0; /* nothing to do */
389
390 if (mgr->is_hr_stereo)
391 err = hr222_sub_set_clock(mgr, rate, &changed);
392 else
393 err = pcxhr_sub_set_clock(mgr, rate, &changed);
394
395 if (err)
396 return err;
397
398 if (changed) {
399 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
400 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
401 if (rate < PCXHR_IRQ_TIMER_FREQ)
402 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
403 else
404 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
405 rmh.cmd[2] = rate;
406 rmh.cmd_len = 3;
407 err = pcxhr_send_msg(mgr, &rmh);
408 if (err)
409 return err;
410 }
411 return 0;
412 }
413
414
pcxhr_sub_get_external_clock(struct pcxhr_mgr * mgr,enum pcxhr_clock_type clock_type,int * sample_rate)415 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
416 enum pcxhr_clock_type clock_type,
417 int *sample_rate)
418 {
419 struct pcxhr_rmh rmh;
420 unsigned char reg;
421 int err, rate;
422
423 switch (clock_type) {
424 case PCXHR_CLOCK_TYPE_WORD_CLOCK:
425 reg = REG_STATUS_WORD_CLOCK;
426 break;
427 case PCXHR_CLOCK_TYPE_AES_SYNC:
428 reg = REG_STATUS_AES_SYNC;
429 break;
430 case PCXHR_CLOCK_TYPE_AES_1:
431 reg = REG_STATUS_AES_1;
432 break;
433 case PCXHR_CLOCK_TYPE_AES_2:
434 reg = REG_STATUS_AES_2;
435 break;
436 case PCXHR_CLOCK_TYPE_AES_3:
437 reg = REG_STATUS_AES_3;
438 break;
439 case PCXHR_CLOCK_TYPE_AES_4:
440 reg = REG_STATUS_AES_4;
441 break;
442 default:
443 return -EINVAL;
444 }
445 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
446 rmh.cmd_len = 2;
447 rmh.cmd[0] |= IO_NUM_REG_STATUS;
448 if (mgr->last_reg_stat != reg) {
449 rmh.cmd[1] = reg;
450 err = pcxhr_send_msg(mgr, &rmh);
451 if (err)
452 return err;
453 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
454 mgr->last_reg_stat = reg;
455 }
456 rmh.cmd[1] = REG_STATUS_CURRENT;
457 err = pcxhr_send_msg(mgr, &rmh);
458 if (err)
459 return err;
460 switch (rmh.stat[1] & 0x0f) {
461 case REG_STATUS_SYNC_32000 : rate = 32000; break;
462 case REG_STATUS_SYNC_44100 : rate = 44100; break;
463 case REG_STATUS_SYNC_48000 : rate = 48000; break;
464 case REG_STATUS_SYNC_64000 : rate = 64000; break;
465 case REG_STATUS_SYNC_88200 : rate = 88200; break;
466 case REG_STATUS_SYNC_96000 : rate = 96000; break;
467 case REG_STATUS_SYNC_128000 : rate = 128000; break;
468 case REG_STATUS_SYNC_176400 : rate = 176400; break;
469 case REG_STATUS_SYNC_192000 : rate = 192000; break;
470 default: rate = 0;
471 }
472 dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate);
473 *sample_rate = rate;
474 return 0;
475 }
476
477
pcxhr_get_external_clock(struct pcxhr_mgr * mgr,enum pcxhr_clock_type clock_type,int * sample_rate)478 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
479 enum pcxhr_clock_type clock_type,
480 int *sample_rate)
481 {
482 if (mgr->is_hr_stereo)
483 return hr222_get_external_clock(mgr, clock_type,
484 sample_rate);
485 else
486 return pcxhr_sub_get_external_clock(mgr, clock_type,
487 sample_rate);
488 }
489
490 /*
491 * start or stop playback/capture substream
492 */
pcxhr_set_stream_state(struct snd_pcxhr * chip,struct pcxhr_stream * stream)493 static int pcxhr_set_stream_state(struct snd_pcxhr *chip,
494 struct pcxhr_stream *stream)
495 {
496 int err;
497 struct pcxhr_rmh rmh;
498 int stream_mask, start;
499
500 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
501 start = 1;
502 else {
503 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
504 dev_err(chip->card->dev,
505 "%s CANNOT be stopped\n", __func__);
506 return -EINVAL;
507 }
508 start = 0;
509 }
510 if (!stream->substream)
511 return -EINVAL;
512
513 stream->timer_abs_periods = 0;
514 stream->timer_period_frag = 0; /* reset theoretical stream pos */
515 stream->timer_buf_periods = 0;
516 stream->timer_is_synced = 0;
517
518 stream_mask =
519 stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
520
521 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
522 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
523 stream->pipe->first_audio, 0, stream_mask);
524
525 chip = snd_pcm_substream_chip(stream->substream);
526
527 err = pcxhr_send_msg(chip->mgr, &rmh);
528 if (err)
529 dev_err(chip->card->dev,
530 "ERROR %s err=%x;\n", __func__, err);
531 stream->status =
532 start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
533 return err;
534 }
535
536 #define HEADER_FMT_BASE_LIN 0xfed00000
537 #define HEADER_FMT_BASE_FLOAT 0xfad00000
538 #define HEADER_FMT_INTEL 0x00008000
539 #define HEADER_FMT_24BITS 0x00004000
540 #define HEADER_FMT_16BITS 0x00002000
541 #define HEADER_FMT_UPTO11 0x00000200
542 #define HEADER_FMT_UPTO32 0x00000100
543 #define HEADER_FMT_MONO 0x00000080
544
pcxhr_set_format(struct pcxhr_stream * stream)545 static int pcxhr_set_format(struct pcxhr_stream *stream)
546 {
547 int err, is_capture, sample_rate, stream_num;
548 struct snd_pcxhr *chip;
549 struct pcxhr_rmh rmh;
550 unsigned int header;
551
552 chip = snd_pcm_substream_chip(stream->substream);
553 switch (stream->format) {
554 case SNDRV_PCM_FORMAT_U8:
555 header = HEADER_FMT_BASE_LIN;
556 break;
557 case SNDRV_PCM_FORMAT_S16_LE:
558 header = HEADER_FMT_BASE_LIN |
559 HEADER_FMT_16BITS | HEADER_FMT_INTEL;
560 break;
561 case SNDRV_PCM_FORMAT_S16_BE:
562 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
563 break;
564 case SNDRV_PCM_FORMAT_S24_3LE:
565 header = HEADER_FMT_BASE_LIN |
566 HEADER_FMT_24BITS | HEADER_FMT_INTEL;
567 break;
568 case SNDRV_PCM_FORMAT_S24_3BE:
569 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
570 break;
571 case SNDRV_PCM_FORMAT_FLOAT_LE:
572 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
573 break;
574 default:
575 dev_err(chip->card->dev,
576 "error %s() : unknown format\n", __func__);
577 return -EINVAL;
578 }
579
580 sample_rate = chip->mgr->sample_rate;
581 if (sample_rate <= 32000 && sample_rate !=0) {
582 if (sample_rate <= 11025)
583 header |= HEADER_FMT_UPTO11;
584 else
585 header |= HEADER_FMT_UPTO32;
586 }
587 if (stream->channels == 1)
588 header |= HEADER_FMT_MONO;
589
590 is_capture = stream->pipe->is_capture;
591 stream_num = is_capture ? 0 : stream->substream->number;
592
593 pcxhr_init_rmh(&rmh, is_capture ?
594 CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
595 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
596 stream_num, 0);
597 if (is_capture) {
598 /* bug with old dsp versions: */
599 /* bit 12 also sets the format of the playback stream */
600 if (DSP_EXT_CMD_SET(chip->mgr))
601 rmh.cmd[0] |= 1<<10;
602 else
603 rmh.cmd[0] |= 1<<12;
604 }
605 rmh.cmd[1] = 0;
606 rmh.cmd_len = 2;
607 if (DSP_EXT_CMD_SET(chip->mgr)) {
608 /* add channels and set bit 19 if channels>2 */
609 rmh.cmd[1] = stream->channels;
610 if (!is_capture) {
611 /* playback : add channel mask to command */
612 rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
613 rmh.cmd_len = 3;
614 }
615 }
616 rmh.cmd[rmh.cmd_len++] = header >> 8;
617 rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
618 err = pcxhr_send_msg(chip->mgr, &rmh);
619 if (err)
620 dev_err(chip->card->dev,
621 "ERROR %s err=%x;\n", __func__, err);
622 return err;
623 }
624
pcxhr_update_r_buffer(struct pcxhr_stream * stream)625 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
626 {
627 int err, is_capture, stream_num;
628 struct pcxhr_rmh rmh;
629 struct snd_pcm_substream *subs = stream->substream;
630 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
631
632 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
633 stream_num = is_capture ? 0 : subs->number;
634
635 dev_dbg(chip->card->dev,
636 "%s(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", __func__,
637 is_capture ? 'c' : 'p',
638 chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
639 subs->runtime->dma_bytes, subs->number);
640
641 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
642 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
643 stream_num, 0);
644
645 /* max buffer size is 2 MByte */
646 snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
647 /* size in bits */
648 rmh.cmd[1] = subs->runtime->dma_bytes * 8;
649 /* most significant byte */
650 rmh.cmd[2] = subs->runtime->dma_addr >> 24;
651 /* this is a circular buffer */
652 rmh.cmd[2] |= 1<<19;
653 /* least 3 significant bytes */
654 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
655 rmh.cmd_len = 4;
656 err = pcxhr_send_msg(chip->mgr, &rmh);
657 if (err)
658 dev_err(chip->card->dev,
659 "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
660 return err;
661 }
662
663
664 #if 0
665 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
666 snd_pcm_uframes_t *sample_count)
667 {
668 struct pcxhr_rmh rmh;
669 int err;
670 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
671 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
672 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
673 1<<stream->pipe->first_audio);
674 err = pcxhr_send_msg(chip->mgr, &rmh);
675 if (err == 0) {
676 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
677 *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
678 }
679 dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
680 return err;
681 }
682 #endif
683
pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream * stream,struct pcxhr_pipe ** pipe)684 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
685 struct pcxhr_pipe **pipe)
686 {
687 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
688 *pipe = stream->pipe;
689 return 1;
690 }
691 return 0;
692 }
693
pcxhr_start_linked_stream(struct pcxhr_mgr * mgr)694 static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr)
695 {
696 int i, j, err;
697 struct pcxhr_pipe *pipe;
698 struct snd_pcxhr *chip;
699 int capture_mask = 0;
700 int playback_mask = 0;
701
702 #ifdef CONFIG_SND_DEBUG_VERBOSE
703 ktime_t start_time, stop_time, diff_time;
704
705 start_time = ktime_get();
706 #endif
707 guard(mutex)(&mgr->setup_mutex);
708
709 /* check the pipes concerned and build pipe_array */
710 for (i = 0; i < mgr->num_cards; i++) {
711 chip = mgr->chip[i];
712 for (j = 0; j < chip->nb_streams_capt; j++) {
713 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
714 capture_mask |= (1 << pipe->first_audio);
715 }
716 for (j = 0; j < chip->nb_streams_play; j++) {
717 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
718 playback_mask |= (1 << pipe->first_audio);
719 break; /* add only once, as all playback
720 * streams of one chip use the same pipe
721 */
722 }
723 }
724 }
725 if (capture_mask == 0 && playback_mask == 0) {
726 dev_err(&mgr->pci->dev, "%s : no pipes\n", __func__);
727 return;
728 }
729
730 dev_dbg(&mgr->pci->dev, "%s : playback_mask=%x capture_mask=%x\n",
731 __func__, playback_mask, capture_mask);
732
733 /* synchronous stop of all the pipes concerned */
734 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
735 if (err) {
736 dev_err(&mgr->pci->dev, "%s : "
737 "error stop pipes (P%x C%x)\n",
738 __func__, playback_mask, capture_mask);
739 return;
740 }
741
742 /* the dsp lost format and buffer info with the stop pipe */
743 for (i = 0; i < mgr->num_cards; i++) {
744 struct pcxhr_stream *stream;
745 chip = mgr->chip[i];
746 for (j = 0; j < chip->nb_streams_capt; j++) {
747 stream = &chip->capture_stream[j];
748 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
749 err = pcxhr_set_format(stream);
750 err = pcxhr_update_r_buffer(stream);
751 }
752 }
753 for (j = 0; j < chip->nb_streams_play; j++) {
754 stream = &chip->playback_stream[j];
755 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
756 err = pcxhr_set_format(stream);
757 err = pcxhr_update_r_buffer(stream);
758 }
759 }
760 }
761 /* start all the streams */
762 for (i = 0; i < mgr->num_cards; i++) {
763 struct pcxhr_stream *stream;
764 chip = mgr->chip[i];
765 for (j = 0; j < chip->nb_streams_capt; j++) {
766 stream = &chip->capture_stream[j];
767 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
768 err = pcxhr_set_stream_state(chip, stream);
769 }
770 for (j = 0; j < chip->nb_streams_play; j++) {
771 stream = &chip->playback_stream[j];
772 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
773 err = pcxhr_set_stream_state(chip, stream);
774 }
775 }
776
777 /* synchronous start of all the pipes concerned */
778 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
779 if (err) {
780 dev_err(&mgr->pci->dev, "%s : "
781 "error start pipes (P%x C%x)\n",
782 __func__, playback_mask, capture_mask);
783 return;
784 }
785
786 /* put the streams into the running state now
787 * (increment pointer by interrupt)
788 */
789 guard(mutex)(&mgr->lock);
790 for ( i =0; i < mgr->num_cards; i++) {
791 struct pcxhr_stream *stream;
792 chip = mgr->chip[i];
793 for(j = 0; j < chip->nb_streams_capt; j++) {
794 stream = &chip->capture_stream[j];
795 if(stream->status == PCXHR_STREAM_STATUS_STARTED)
796 stream->status = PCXHR_STREAM_STATUS_RUNNING;
797 }
798 for (j = 0; j < chip->nb_streams_play; j++) {
799 stream = &chip->playback_stream[j];
800 if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
801 /* playback will already have advanced ! */
802 stream->timer_period_frag += mgr->granularity;
803 stream->status = PCXHR_STREAM_STATUS_RUNNING;
804 }
805 }
806 }
807
808 #ifdef CONFIG_SND_DEBUG_VERBOSE
809 stop_time = ktime_get();
810 diff_time = ktime_sub(stop_time, start_time);
811 dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n",
812 (long)(ktime_to_ns(diff_time)), err);
813 #endif
814 }
815
816
817 /*
818 * trigger callback
819 */
pcxhr_trigger(struct snd_pcm_substream * subs,int cmd)820 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
821 {
822 struct pcxhr_stream *stream;
823 struct snd_pcm_substream *s;
824 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
825
826 switch (cmd) {
827 case SNDRV_PCM_TRIGGER_START:
828 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n");
829 if (snd_pcm_stream_linked(subs)) {
830 snd_pcm_group_for_each_entry(s, subs) {
831 if (snd_pcm_substream_chip(s) != chip)
832 continue;
833 stream = s->runtime->private_data;
834 stream->status =
835 PCXHR_STREAM_STATUS_SCHEDULE_RUN;
836 snd_pcm_trigger_done(s, subs);
837 }
838 pcxhr_start_linked_stream(chip->mgr);
839 } else {
840 stream = subs->runtime->private_data;
841 dev_dbg(chip->card->dev, "Only one Substream %c %d\n",
842 stream->pipe->is_capture ? 'C' : 'P',
843 stream->pipe->first_audio);
844 if (pcxhr_set_format(stream))
845 return -EINVAL;
846 if (pcxhr_update_r_buffer(stream))
847 return -EINVAL;
848
849 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
850 if (pcxhr_set_stream_state(chip, stream))
851 return -EINVAL;
852 stream->status = PCXHR_STREAM_STATUS_RUNNING;
853 }
854 break;
855 case SNDRV_PCM_TRIGGER_STOP:
856 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n");
857 snd_pcm_group_for_each_entry(s, subs) {
858 stream = s->runtime->private_data;
859 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
860 if (pcxhr_set_stream_state(chip, stream))
861 return -EINVAL;
862 snd_pcm_trigger_done(s, subs);
863 }
864 break;
865 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
866 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
867 /* TODO */
868 default:
869 return -EINVAL;
870 }
871 return 0;
872 }
873
874
pcxhr_hardware_timer(struct pcxhr_mgr * mgr,int start)875 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
876 {
877 struct pcxhr_rmh rmh;
878 int err;
879
880 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
881 if (start) {
882 /* last dsp time invalid */
883 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
884 rmh.cmd[0] |= mgr->granularity;
885 }
886 err = pcxhr_send_msg(mgr, &rmh);
887 if (err < 0)
888 dev_err(&mgr->pci->dev, "error %s err(%x)\n", __func__,
889 err);
890 return err;
891 }
892
893 /*
894 * prepare callback for all pcms
895 */
pcxhr_prepare(struct snd_pcm_substream * subs)896 static int pcxhr_prepare(struct snd_pcm_substream *subs)
897 {
898 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
899 struct pcxhr_mgr *mgr = chip->mgr;
900 int err = 0;
901
902 dev_dbg(chip->card->dev,
903 "%s : period_size(%lx) periods(%x) buffer_size(%lx)\n", __func__,
904 subs->runtime->period_size, subs->runtime->periods,
905 subs->runtime->buffer_size);
906
907 guard(mutex)(&mgr->setup_mutex);
908
909 do {
910 /* only the first stream can choose the sample rate */
911 /* set the clock only once (first stream) */
912 if (mgr->sample_rate != subs->runtime->rate) {
913 err = pcxhr_set_clock(mgr, subs->runtime->rate);
914 if (err)
915 break;
916 if (mgr->sample_rate == 0)
917 /* start the DSP-timer */
918 err = pcxhr_hardware_timer(mgr, 1);
919 mgr->sample_rate = subs->runtime->rate;
920 }
921 } while(0); /* do only once (so we can use break instead of goto) */
922
923 return err;
924 }
925
926
927 /*
928 * HW_PARAMS callback for all pcms
929 */
pcxhr_hw_params(struct snd_pcm_substream * subs,struct snd_pcm_hw_params * hw)930 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
931 struct snd_pcm_hw_params *hw)
932 {
933 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
934 struct pcxhr_mgr *mgr = chip->mgr;
935 struct pcxhr_stream *stream = subs->runtime->private_data;
936
937 guard(mutex)(&mgr->setup_mutex);
938
939 /* set up channels */
940 stream->channels = params_channels(hw);
941 /* set up format for the stream */
942 stream->format = params_format(hw);
943
944 return 0;
945 }
946
947
948 /*
949 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
950 */
951 static const struct snd_pcm_hardware pcxhr_caps =
952 {
953 .info = (SNDRV_PCM_INFO_MMAP |
954 SNDRV_PCM_INFO_INTERLEAVED |
955 SNDRV_PCM_INFO_MMAP_VALID |
956 SNDRV_PCM_INFO_SYNC_START),
957 .formats = (SNDRV_PCM_FMTBIT_U8 |
958 SNDRV_PCM_FMTBIT_S16_LE |
959 SNDRV_PCM_FMTBIT_S16_BE |
960 SNDRV_PCM_FMTBIT_S24_3LE |
961 SNDRV_PCM_FMTBIT_S24_3BE |
962 SNDRV_PCM_FMTBIT_FLOAT_LE),
963 .rates = (SNDRV_PCM_RATE_CONTINUOUS |
964 SNDRV_PCM_RATE_8000_192000),
965 .rate_min = 8000,
966 .rate_max = 192000,
967 .channels_min = 1,
968 .channels_max = 2,
969 .buffer_bytes_max = (32*1024),
970 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
971 .period_bytes_min = (2*PCXHR_GRANULARITY),
972 .period_bytes_max = (16*1024),
973 .periods_min = 2,
974 .periods_max = (32*1024/PCXHR_GRANULARITY),
975 };
976
977
pcxhr_open(struct snd_pcm_substream * subs)978 static int pcxhr_open(struct snd_pcm_substream *subs)
979 {
980 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
981 struct pcxhr_mgr *mgr = chip->mgr;
982 struct snd_pcm_runtime *runtime = subs->runtime;
983 struct pcxhr_stream *stream;
984 int err;
985
986 guard(mutex)(&mgr->setup_mutex);
987
988 /* copy the struct snd_pcm_hardware struct */
989 runtime->hw = pcxhr_caps;
990
991 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
992 dev_dbg(chip->card->dev, "%s playback chip%d subs%d\n",
993 __func__, chip->chip_idx, subs->number);
994 stream = &chip->playback_stream[subs->number];
995 } else {
996 dev_dbg(chip->card->dev, "%s capture chip%d subs%d\n",
997 __func__, chip->chip_idx, subs->number);
998 if (mgr->mono_capture)
999 runtime->hw.channels_max = 1;
1000 else
1001 runtime->hw.channels_min = 2;
1002 stream = &chip->capture_stream[subs->number];
1003 }
1004 if (stream->status != PCXHR_STREAM_STATUS_FREE){
1005 /* streams in use */
1006 dev_err(chip->card->dev, "%s chip%d subs%d in use\n",
1007 __func__, chip->chip_idx, subs->number);
1008 return -EBUSY;
1009 }
1010
1011 /* float format support is in some cases buggy on stereo cards */
1012 if (mgr->is_hr_stereo)
1013 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1014
1015 /* buffer-size should better be multiple of period-size */
1016 err = snd_pcm_hw_constraint_integer(runtime,
1017 SNDRV_PCM_HW_PARAM_PERIODS);
1018 if (err < 0)
1019 return err;
1020
1021 /* if a sample rate is already used or fixed by external clock,
1022 * the stream cannot change
1023 */
1024 if (mgr->sample_rate)
1025 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1026 else {
1027 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1028 int external_rate;
1029 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
1030 &external_rate) ||
1031 external_rate == 0) {
1032 /* cannot detect the external clock rate */
1033 return -EBUSY;
1034 }
1035 runtime->hw.rate_min = external_rate;
1036 runtime->hw.rate_max = external_rate;
1037 }
1038 }
1039
1040 stream->status = PCXHR_STREAM_STATUS_OPEN;
1041 stream->substream = subs;
1042 stream->channels = 0; /* not configured yet */
1043
1044 runtime->private_data = stream;
1045
1046 /* better get a divisor of granularity values (96 or 192) */
1047 snd_pcm_hw_constraint_step(runtime, 0,
1048 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1049 snd_pcm_hw_constraint_step(runtime, 0,
1050 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
1051 snd_pcm_set_sync(subs);
1052
1053 mgr->ref_count_rate++;
1054
1055 return 0;
1056 }
1057
1058
pcxhr_close(struct snd_pcm_substream * subs)1059 static int pcxhr_close(struct snd_pcm_substream *subs)
1060 {
1061 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1062 struct pcxhr_mgr *mgr = chip->mgr;
1063 struct pcxhr_stream *stream = subs->runtime->private_data;
1064
1065 guard(mutex)(&mgr->setup_mutex);
1066
1067 dev_dbg(chip->card->dev, "%s chip%d subs%d\n", __func__,
1068 chip->chip_idx, subs->number);
1069
1070 /* sample rate released */
1071 if (--mgr->ref_count_rate == 0) {
1072 mgr->sample_rate = 0; /* the sample rate is no more locked */
1073 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
1074 }
1075
1076 stream->status = PCXHR_STREAM_STATUS_FREE;
1077 stream->substream = NULL;
1078
1079 return 0;
1080 }
1081
1082
pcxhr_stream_pointer(struct snd_pcm_substream * subs)1083 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1084 {
1085 u_int32_t timer_period_frag;
1086 int timer_buf_periods;
1087 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1088 struct snd_pcm_runtime *runtime = subs->runtime;
1089 struct pcxhr_stream *stream = runtime->private_data;
1090
1091 guard(mutex)(&chip->mgr->lock);
1092
1093 /* get the period fragment and the nb of periods in the buffer */
1094 timer_period_frag = stream->timer_period_frag;
1095 timer_buf_periods = stream->timer_buf_periods;
1096
1097 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1098 timer_period_frag);
1099 }
1100
1101
1102 static const struct snd_pcm_ops pcxhr_ops = {
1103 .open = pcxhr_open,
1104 .close = pcxhr_close,
1105 .prepare = pcxhr_prepare,
1106 .hw_params = pcxhr_hw_params,
1107 .trigger = pcxhr_trigger,
1108 .pointer = pcxhr_stream_pointer,
1109 };
1110
1111 /*
1112 */
pcxhr_create_pcm(struct snd_pcxhr * chip)1113 int pcxhr_create_pcm(struct snd_pcxhr *chip)
1114 {
1115 int err;
1116 struct snd_pcm *pcm;
1117 char name[32];
1118
1119 snprintf(name, sizeof(name), "pcxhr %d", chip->chip_idx);
1120 err = snd_pcm_new(chip->card, name, 0,
1121 chip->nb_streams_play,
1122 chip->nb_streams_capt, &pcm);
1123 if (err < 0) {
1124 dev_err(chip->card->dev, "cannot create pcm %s\n", name);
1125 return err;
1126 }
1127 pcm->private_data = chip;
1128
1129 if (chip->nb_streams_play)
1130 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
1131 if (chip->nb_streams_capt)
1132 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
1133
1134 pcm->info_flags = 0;
1135 pcm->nonatomic = true;
1136 strscpy(pcm->name, name);
1137
1138 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1139 &chip->mgr->pci->dev,
1140 32*1024, 32*1024);
1141 chip->pcm = pcm;
1142 return 0;
1143 }
1144
pcxhr_chip_free(struct snd_pcxhr * chip)1145 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1146 {
1147 kfree(chip);
1148 return 0;
1149 }
1150
pcxhr_chip_dev_free(struct snd_device * device)1151 static int pcxhr_chip_dev_free(struct snd_device *device)
1152 {
1153 struct snd_pcxhr *chip = device->device_data;
1154 return pcxhr_chip_free(chip);
1155 }
1156
1157
1158 /*
1159 */
pcxhr_create(struct pcxhr_mgr * mgr,struct snd_card * card,int idx)1160 static int pcxhr_create(struct pcxhr_mgr *mgr,
1161 struct snd_card *card, int idx)
1162 {
1163 int err;
1164 struct snd_pcxhr *chip;
1165 static const struct snd_device_ops ops = {
1166 .dev_free = pcxhr_chip_dev_free,
1167 };
1168
1169 chip = kzalloc_obj(*chip);
1170 if (!chip)
1171 return -ENOMEM;
1172
1173 chip->card = card;
1174 chip->chip_idx = idx;
1175 chip->mgr = mgr;
1176 card->sync_irq = mgr->irq;
1177
1178 if (idx < mgr->playback_chips)
1179 /* stereo or mono streams */
1180 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1181
1182 if (idx < mgr->capture_chips) {
1183 if (mgr->mono_capture)
1184 chip->nb_streams_capt = 2; /* 2 mono streams */
1185 else
1186 chip->nb_streams_capt = 1; /* or 1 stereo stream */
1187 }
1188
1189 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1190 if (err < 0) {
1191 pcxhr_chip_free(chip);
1192 return err;
1193 }
1194
1195 mgr->chip[idx] = chip;
1196
1197 return 0;
1198 }
1199
1200 /* proc interface */
pcxhr_proc_info(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1201 static void pcxhr_proc_info(struct snd_info_entry *entry,
1202 struct snd_info_buffer *buffer)
1203 {
1204 struct snd_pcxhr *chip = entry->private_data;
1205 struct pcxhr_mgr *mgr = chip->mgr;
1206
1207 snd_iprintf(buffer, "\n%s\n", mgr->name);
1208
1209 /* stats available when embedded DSP is running */
1210 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1211 struct pcxhr_rmh rmh;
1212 short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1213 short ver_min = (mgr->dsp_version >> 8) & 0xff;
1214 short ver_build = mgr->dsp_version & 0xff;
1215 snd_iprintf(buffer, "module version %s\n",
1216 PCXHR_DRIVER_VERSION_STRING);
1217 snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1218 ver_maj, ver_min, ver_build);
1219 if (mgr->board_has_analog)
1220 snd_iprintf(buffer, "analog io available\n");
1221 else
1222 snd_iprintf(buffer, "digital only board\n");
1223
1224 /* calc cpu load of the dsp */
1225 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1226 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1227 int cur = rmh.stat[0];
1228 int ref = rmh.stat[1];
1229 if (ref > 0) {
1230 if (mgr->sample_rate_real != 0 &&
1231 mgr->sample_rate_real != 48000) {
1232 ref = (ref * 48000) /
1233 mgr->sample_rate_real;
1234 if (mgr->sample_rate_real >=
1235 PCXHR_IRQ_TIMER_FREQ)
1236 ref *= 2;
1237 }
1238 cur = 100 - (100 * cur) / ref;
1239 snd_iprintf(buffer, "cpu load %d%%\n", cur);
1240 snd_iprintf(buffer, "buffer pool %d/%d\n",
1241 rmh.stat[2], rmh.stat[3]);
1242 }
1243 }
1244 snd_iprintf(buffer, "dma granularity : %d\n",
1245 mgr->granularity);
1246 snd_iprintf(buffer, "dsp time errors : %d\n",
1247 mgr->dsp_time_err);
1248 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1249 mgr->async_err_pipe_xrun);
1250 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1251 mgr->async_err_stream_xrun);
1252 snd_iprintf(buffer, "dsp async last other error : %x\n",
1253 mgr->async_err_other_last);
1254 /* debug zone dsp */
1255 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1256 rmh.cmd_len = 1;
1257 rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1258 rmh.dsp_stat = 0;
1259 rmh.cmd_idx = CMD_LAST_INDEX;
1260 if( ! pcxhr_send_msg(mgr, &rmh) ) {
1261 int i;
1262 if (rmh.stat_len > 8)
1263 rmh.stat_len = 8;
1264 for (i = 0; i < rmh.stat_len; i++)
1265 snd_iprintf(buffer, "debug[%02d] = %06x\n",
1266 i, rmh.stat[i]);
1267 }
1268 } else
1269 snd_iprintf(buffer, "no firmware loaded\n");
1270 snd_iprintf(buffer, "\n");
1271 }
pcxhr_proc_sync(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1272 static void pcxhr_proc_sync(struct snd_info_entry *entry,
1273 struct snd_info_buffer *buffer)
1274 {
1275 struct snd_pcxhr *chip = entry->private_data;
1276 struct pcxhr_mgr *mgr = chip->mgr;
1277 static const char *textsHR22[3] = {
1278 "Internal", "AES Sync", "AES 1"
1279 };
1280 static const char *textsPCXHR[7] = {
1281 "Internal", "Word", "AES Sync",
1282 "AES 1", "AES 2", "AES 3", "AES 4"
1283 };
1284 const char **texts;
1285 int max_clock;
1286 if (mgr->is_hr_stereo) {
1287 texts = textsHR22;
1288 max_clock = HR22_CLOCK_TYPE_MAX;
1289 } else {
1290 texts = textsPCXHR;
1291 max_clock = PCXHR_CLOCK_TYPE_MAX;
1292 }
1293
1294 snd_iprintf(buffer, "\n%s\n", mgr->name);
1295 snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1296 texts[mgr->cur_clock_type]);
1297 snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1298 mgr->sample_rate_real);
1299 /* commands available when embedded DSP is running */
1300 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1301 int i, err, sample_rate;
1302 for (i = 1; i <= max_clock; i++) {
1303 err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1304 if (err)
1305 break;
1306 snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1307 texts[i], sample_rate);
1308 }
1309 } else
1310 snd_iprintf(buffer, "no firmware loaded\n");
1311 snd_iprintf(buffer, "\n");
1312 }
1313
pcxhr_proc_gpio_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1314 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1315 struct snd_info_buffer *buffer)
1316 {
1317 struct snd_pcxhr *chip = entry->private_data;
1318 struct pcxhr_mgr *mgr = chip->mgr;
1319 /* commands available when embedded DSP is running */
1320 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1321 /* gpio ports on stereo boards only available */
1322 int value = 0;
1323 hr222_read_gpio(mgr, 1, &value); /* GPI */
1324 snd_iprintf(buffer, "GPI: 0x%x\n", value);
1325 hr222_read_gpio(mgr, 0, &value); /* GP0 */
1326 snd_iprintf(buffer, "GPO: 0x%x\n", value);
1327 } else
1328 snd_iprintf(buffer, "no firmware loaded\n");
1329 snd_iprintf(buffer, "\n");
1330 }
pcxhr_proc_gpo_write(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1331 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1332 struct snd_info_buffer *buffer)
1333 {
1334 struct snd_pcxhr *chip = entry->private_data;
1335 struct pcxhr_mgr *mgr = chip->mgr;
1336 char line[64];
1337 int value;
1338 /* commands available when embedded DSP is running */
1339 if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1340 return;
1341 while (!snd_info_get_line(buffer, line, sizeof(line))) {
1342 if (sscanf(line, "GPO: 0x%x", &value) != 1)
1343 continue;
1344 hr222_write_gpo(mgr, value); /* GP0 */
1345 }
1346 }
1347
1348 /* Access to the results of the CMD_GET_TIME_CODE RMH */
1349 #define TIME_CODE_VALID_MASK 0x00800000
1350 #define TIME_CODE_NEW_MASK 0x00400000
1351 #define TIME_CODE_BACK_MASK 0x00200000
1352 #define TIME_CODE_WAIT_MASK 0x00100000
1353
1354 /* Values for the CMD_MANAGE_SIGNAL RMH */
1355 #define MANAGE_SIGNAL_TIME_CODE 0x01
1356 #define MANAGE_SIGNAL_MIDI 0x02
1357
1358 /* linear time code read proc*/
pcxhr_proc_ltc(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1359 static void pcxhr_proc_ltc(struct snd_info_entry *entry,
1360 struct snd_info_buffer *buffer)
1361 {
1362 struct snd_pcxhr *chip = entry->private_data;
1363 struct pcxhr_mgr *mgr = chip->mgr;
1364 struct pcxhr_rmh rmh;
1365 unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm;
1366 int err;
1367 /* commands available when embedded DSP is running */
1368 if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) {
1369 snd_iprintf(buffer, "no firmware loaded\n");
1370 return;
1371 }
1372 if (!mgr->capture_ltc) {
1373 pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL);
1374 rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE;
1375 err = pcxhr_send_msg(mgr, &rmh);
1376 if (err) {
1377 snd_iprintf(buffer, "ltc not activated (%d)\n", err);
1378 return;
1379 }
1380 if (mgr->is_hr_stereo)
1381 hr222_manage_timecode(mgr, 1);
1382 else
1383 pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE,
1384 REG_CONT_VALSMPTE, NULL);
1385 mgr->capture_ltc = 1;
1386 }
1387 pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE);
1388 err = pcxhr_send_msg(mgr, &rmh);
1389 if (err) {
1390 snd_iprintf(buffer, "ltc read error (err=%d)\n", err);
1391 return ;
1392 }
1393 ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf);
1394 ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf);
1395 ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf);
1396 ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf);
1397
1398 snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n",
1399 ltcHrs, ltcMin, ltcSec, ltcFrm);
1400 snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff,
1401 rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff);
1402 /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n",
1403 rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/
1404 if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) {
1405 snd_iprintf(buffer, "warning: linear timecode not valid\n");
1406 }
1407 }
1408
pcxhr_proc_init(struct snd_pcxhr * chip)1409 static void pcxhr_proc_init(struct snd_pcxhr *chip)
1410 {
1411 snd_card_ro_proc_new(chip->card, "info", chip, pcxhr_proc_info);
1412 snd_card_ro_proc_new(chip->card, "sync", chip, pcxhr_proc_sync);
1413 /* gpio available on stereo sound cards only */
1414 if (chip->mgr->is_hr_stereo)
1415 snd_card_rw_proc_new(chip->card, "gpio", chip,
1416 pcxhr_proc_gpio_read,
1417 pcxhr_proc_gpo_write);
1418 snd_card_ro_proc_new(chip->card, "ltc", chip, pcxhr_proc_ltc);
1419 }
1420 /* end of proc interface */
1421
1422 /*
1423 * release all the cards assigned to a manager instance
1424 */
pcxhr_free(struct pcxhr_mgr * mgr)1425 static int pcxhr_free(struct pcxhr_mgr *mgr)
1426 {
1427 unsigned int i;
1428
1429 for (i = 0; i < mgr->num_cards; i++) {
1430 if (mgr->chip[i])
1431 snd_card_free(mgr->chip[i]->card);
1432 }
1433
1434 /* reset board if some firmware was loaded */
1435 if(mgr->dsp_loaded) {
1436 pcxhr_reset_board(mgr);
1437 dev_dbg(&mgr->pci->dev, "reset pcxhr !\n");
1438 }
1439
1440 /* release irq */
1441 if (mgr->irq >= 0)
1442 free_irq(mgr->irq, mgr);
1443
1444 pci_release_regions(mgr->pci);
1445
1446 /* free hostport purgebuffer */
1447 if (mgr->hostport.area) {
1448 snd_dma_free_pages(&mgr->hostport);
1449 mgr->hostport.area = NULL;
1450 }
1451
1452 kfree(mgr->prmh);
1453
1454 pci_disable_device(mgr->pci);
1455 kfree(mgr);
1456 return 0;
1457 }
1458
1459 /*
1460 * probe function - creates the card manager
1461 */
pcxhr_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)1462 static int pcxhr_probe(struct pci_dev *pci,
1463 const struct pci_device_id *pci_id)
1464 {
1465 static int dev;
1466 struct pcxhr_mgr *mgr;
1467 unsigned int i;
1468 int err;
1469 size_t size;
1470 char *card_name;
1471
1472 if (dev >= SNDRV_CARDS)
1473 return -ENODEV;
1474 if (! enable[dev]) {
1475 dev++;
1476 return -ENOENT;
1477 }
1478
1479 /* enable PCI device */
1480 err = pci_enable_device(pci);
1481 if (err < 0)
1482 return err;
1483 pci_set_master(pci);
1484
1485 /* check if we can restrict PCI DMA transfers to 32 bits */
1486 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
1487 dev_err(&pci->dev,
1488 "architecture does not support 32bit PCI busmaster DMA\n");
1489 pci_disable_device(pci);
1490 return -ENXIO;
1491 }
1492
1493 /* alloc card manager */
1494 mgr = kzalloc_obj(*mgr);
1495 if (! mgr) {
1496 pci_disable_device(pci);
1497 return -ENOMEM;
1498 }
1499
1500 if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1501 kfree(mgr);
1502 pci_disable_device(pci);
1503 return -ENODEV;
1504 }
1505 card_name =
1506 pcxhr_board_params[pci_id->driver_data].board_name;
1507 mgr->playback_chips =
1508 pcxhr_board_params[pci_id->driver_data].playback_chips;
1509 mgr->capture_chips =
1510 pcxhr_board_params[pci_id->driver_data].capture_chips;
1511 mgr->fw_file_set =
1512 pcxhr_board_params[pci_id->driver_data].fw_file_set;
1513 mgr->firmware_num =
1514 pcxhr_board_params[pci_id->driver_data].firmware_num;
1515 mgr->mono_capture = mono[dev];
1516 mgr->is_hr_stereo = (mgr->playback_chips == 1);
1517 mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1518 mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1519
1520 if (mgr->is_hr_stereo)
1521 mgr->granularity = PCXHR_GRANULARITY_HR22;
1522 else
1523 mgr->granularity = PCXHR_GRANULARITY;
1524
1525 /* resource assignment */
1526 err = pci_request_regions(pci, card_name);
1527 if (err < 0) {
1528 kfree(mgr);
1529 pci_disable_device(pci);
1530 return err;
1531 }
1532 for (i = 0; i < 3; i++)
1533 mgr->port[i] = pci_resource_start(pci, i);
1534
1535 mgr->pci = pci;
1536 mgr->irq = -1;
1537
1538 /* ISR lock */
1539 mutex_init(&mgr->lock);
1540 mutex_init(&mgr->msg_lock);
1541
1542 /* init setup mutex*/
1543 mutex_init(&mgr->setup_mutex);
1544
1545 if (request_threaded_irq(pci->irq, pcxhr_interrupt,
1546 pcxhr_threaded_irq, IRQF_SHARED,
1547 KBUILD_MODNAME, mgr)) {
1548 dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq);
1549 pcxhr_free(mgr);
1550 return -EBUSY;
1551 }
1552 mgr->irq = pci->irq;
1553
1554 snprintf(mgr->name, sizeof(mgr->name),
1555 "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i",
1556 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1557
1558 mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1559 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1560 PCXHR_SIZE_MAX_STATUS),
1561 GFP_KERNEL);
1562 if (! mgr->prmh) {
1563 pcxhr_free(mgr);
1564 return -ENOMEM;
1565 }
1566
1567 for (i=0; i < PCXHR_MAX_CARDS; i++) {
1568 struct snd_card *card;
1569 char tmpid[16];
1570 int idx;
1571
1572 if (i >= max(mgr->playback_chips, mgr->capture_chips))
1573 break;
1574 mgr->num_cards++;
1575
1576 if (index[dev] < 0)
1577 idx = index[dev];
1578 else
1579 idx = index[dev] + i;
1580
1581 snprintf(tmpid, sizeof(tmpid), "%s-%d",
1582 id[dev] ? id[dev] : card_name, i);
1583 err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE,
1584 0, &card);
1585
1586 if (err < 0) {
1587 dev_err(&pci->dev, "cannot allocate the card %d\n", i);
1588 pcxhr_free(mgr);
1589 return err;
1590 }
1591
1592 strscpy(card->driver, DRIVER_NAME);
1593 snprintf(card->shortname, sizeof(card->shortname),
1594 "Digigram [PCM #%d]", i);
1595 snprintf(card->longname, sizeof(card->longname),
1596 "%s [PCM #%d]", mgr->name, i);
1597
1598 err = pcxhr_create(mgr, card, i);
1599 if (err < 0) {
1600 snd_card_free(card);
1601 pcxhr_free(mgr);
1602 return err;
1603 }
1604
1605 if (i == 0)
1606 /* init proc interface only for chip0 */
1607 pcxhr_proc_init(mgr->chip[i]);
1608
1609 err = snd_card_register(card);
1610 if (err < 0) {
1611 pcxhr_free(mgr);
1612 return err;
1613 }
1614 }
1615
1616 /* create hostport purgebuffer */
1617 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1618 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
1619 size, &mgr->hostport) < 0) {
1620 pcxhr_free(mgr);
1621 return -ENOMEM;
1622 }
1623 /* init purgebuffer */
1624 memset(mgr->hostport.area, 0, size);
1625
1626 /* create a DSP loader */
1627 err = pcxhr_setup_firmware(mgr);
1628 if (err < 0) {
1629 pcxhr_free(mgr);
1630 return err;
1631 }
1632
1633 pci_set_drvdata(pci, mgr);
1634 dev++;
1635 return 0;
1636 }
1637
pcxhr_remove(struct pci_dev * pci)1638 static void pcxhr_remove(struct pci_dev *pci)
1639 {
1640 pcxhr_free(pci_get_drvdata(pci));
1641 }
1642
1643 static struct pci_driver pcxhr_driver = {
1644 .name = KBUILD_MODNAME,
1645 .id_table = pcxhr_ids,
1646 .probe = pcxhr_probe,
1647 .remove = pcxhr_remove,
1648 };
1649
1650 module_pci_driver(pcxhr_driver);
1651