1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_MCU_H 5 #define __MT7915_MCU_H 6 7 #include "../mt76_connac_mcu.h" 8 9 enum { 10 MCU_ATE_SET_TRX = 0x1, 11 MCU_ATE_SET_FREQ_OFFSET = 0xa, 12 MCU_ATE_SET_SLOT_TIME = 0x13, 13 MCU_ATE_CLEAN_TXQUEUE = 0x1c, 14 }; 15 16 struct mt7915_mcu_thermal_ctrl { 17 u8 ctrl_id; 18 u8 band_idx; 19 union { 20 struct { 21 u8 protect_type; /* 1: duty admit, 2: radio off */ 22 u8 trigger_type; /* 0: low, 1: high */ 23 } __packed type; 24 struct { 25 u8 duty_level; /* level 0~3 */ 26 u8 duty_cycle; 27 } __packed duty; 28 }; 29 } __packed; 30 31 struct mt7915_mcu_thermal_notify { 32 struct mt76_connac2_mcu_rxd_hdr rxd; 33 34 struct mt7915_mcu_thermal_ctrl ctrl; 35 __le32 temperature; 36 u8 rsv[8]; 37 } __packed; 38 39 struct mt7915_mcu_csa_notify { 40 struct mt76_connac2_mcu_rxd_hdr rxd; 41 42 u8 omac_idx; 43 u8 csa_count; 44 u8 band_idx; 45 u8 rsv; 46 } __packed; 47 48 struct mt7915_mcu_bcc_notify { 49 struct mt76_connac2_mcu_rxd_hdr rxd; 50 51 u8 band_idx; 52 u8 omac_idx; 53 u8 cca_count; 54 u8 rsv; 55 } __packed; 56 57 struct mt7915_mcu_ps_notify { 58 struct mt76_connac2_mcu_rxd_hdr rxd; 59 60 u8 wtbl_lower; 61 u8 ps_bit; 62 u8 wtbl_higher; 63 u8 rsv; 64 } __packed; 65 66 struct mt7915_mcu_rdd_report { 67 struct mt76_connac2_mcu_rxd_hdr rxd; 68 69 u8 rdd_idx; 70 u8 long_detected; 71 u8 constant_prf_detected; 72 u8 staggered_prf_detected; 73 u8 radar_type_idx; 74 u8 periodic_pulse_num; 75 u8 long_pulse_num; 76 u8 hw_pulse_num; 77 78 u8 out_lpn; 79 u8 out_spn; 80 u8 out_crpn; 81 u8 out_crpw; 82 u8 out_crbn; 83 u8 out_stgpn; 84 u8 out_stgpw; 85 86 u8 rsv; 87 88 __le32 out_pri_const; 89 __le32 out_pri_stg[3]; 90 91 struct { 92 __le32 start; 93 __le16 pulse_width; 94 __le16 pulse_power; 95 u8 mdrdy_flag; 96 u8 rsv[3]; 97 } long_pulse[32]; 98 99 struct { 100 __le32 start; 101 __le16 pulse_width; 102 __le16 pulse_power; 103 u8 mdrdy_flag; 104 u8 rsv[3]; 105 } periodic_pulse[32]; 106 107 struct { 108 __le32 start; 109 __le16 pulse_width; 110 __le16 pulse_power; 111 u8 sc_pass; 112 u8 sw_reset; 113 u8 mdrdy_flag; 114 u8 tx_active; 115 } hw_pulse[32]; 116 } __packed; 117 118 struct mt7915_mcu_background_chain_ctrl { 119 u8 chan; /* primary channel */ 120 u8 central_chan; /* central channel */ 121 u8 bw; 122 u8 tx_stream; 123 u8 rx_stream; 124 125 u8 monitor_chan; /* monitor channel */ 126 u8 monitor_central_chan;/* monitor central channel */ 127 u8 monitor_bw; 128 u8 monitor_tx_stream; 129 u8 monitor_rx_stream; 130 131 u8 scan_mode; /* 0: ScanStop 132 * 1: ScanStart 133 * 2: ScanRunning 134 */ 135 u8 band_idx; /* DBDC */ 136 u8 monitor_scan_type; 137 u8 band; /* 0: 2.4GHz, 1: 5GHz */ 138 u8 rsv[2]; 139 } __packed; 140 141 struct mt7915_mcu_sr_ctrl { 142 u8 action; 143 u8 argnum; 144 u8 band_idx; 145 u8 status; 146 u8 drop_ta_idx; 147 u8 sta_idx; /* 256 sta */ 148 u8 rsv[2]; 149 __le32 val; 150 } __packed; 151 152 struct mt7915_mcu_eeprom { 153 u8 buffer_mode; 154 u8 format; 155 __le16 len; 156 } __packed; 157 158 struct mt7915_mcu_eeprom_info { 159 __le32 addr; 160 __le32 valid; 161 u8 data[16]; 162 } __packed; 163 164 struct mt7915_mcu_phy_rx_info { 165 u8 category; 166 u8 rate; 167 u8 mode; 168 u8 nsts; 169 u8 gi; 170 u8 coding; 171 u8 stbc; 172 u8 bw; 173 }; 174 175 struct mt7915_mcu_mib { 176 __le32 band; 177 __le32 offs; 178 __le64 data; 179 } __packed; 180 181 enum mt7915_chan_mib_offs { 182 /* mt7915 */ 183 MIB_TX_TIME = 81, 184 MIB_RX_TIME, 185 MIB_OBSS_AIRTIME = 86, 186 MIB_NON_WIFI_TIME, 187 MIB_TXOP_INIT_COUNT, 188 189 /* mt7916 */ 190 MIB_TX_TIME_V2 = 6, 191 MIB_RX_TIME_V2 = 8, 192 MIB_OBSS_AIRTIME_V2 = 490, 193 MIB_NON_WIFI_TIME_V2 194 }; 195 196 struct mt7915_mcu_txpower_sku { 197 u8 format_id; 198 u8 limit_type; 199 u8 band_idx; 200 s8 txpower_sku[MT7915_SKU_RATE_NUM]; 201 } __packed; 202 203 struct edca { 204 u8 queue; 205 u8 set; 206 u8 aifs; 207 u8 cw_min; 208 __le16 cw_max; 209 __le16 txop; 210 }; 211 212 struct mt7915_mcu_tx { 213 u8 total; 214 u8 action; 215 u8 valid; 216 u8 mode; 217 218 struct edca edca[IEEE80211_NUM_ACS]; 219 } __packed; 220 221 struct mt7915_mcu_muru_stats { 222 __le32 event_id; 223 struct { 224 __le32 cck_cnt; 225 __le32 ofdm_cnt; 226 __le32 htmix_cnt; 227 __le32 htgf_cnt; 228 __le32 vht_su_cnt; 229 __le32 vht_2mu_cnt; 230 __le32 vht_3mu_cnt; 231 __le32 vht_4mu_cnt; 232 __le32 he_su_cnt; 233 __le32 he_ext_su_cnt; 234 __le32 he_2ru_cnt; 235 __le32 he_2mu_cnt; 236 __le32 he_3ru_cnt; 237 __le32 he_3mu_cnt; 238 __le32 he_4ru_cnt; 239 __le32 he_4mu_cnt; 240 __le32 he_5to8ru_cnt; 241 __le32 he_9to16ru_cnt; 242 __le32 he_gtr16ru_cnt; 243 } dl; 244 245 struct { 246 __le32 hetrig_su_cnt; 247 __le32 hetrig_2ru_cnt; 248 __le32 hetrig_3ru_cnt; 249 __le32 hetrig_4ru_cnt; 250 __le32 hetrig_5to8ru_cnt; 251 __le32 hetrig_9to16ru_cnt; 252 __le32 hetrig_gtr16ru_cnt; 253 __le32 hetrig_2mu_cnt; 254 __le32 hetrig_3mu_cnt; 255 __le32 hetrig_4mu_cnt; 256 } ul; 257 }; 258 259 #define WMM_AIFS_SET BIT(0) 260 #define WMM_CW_MIN_SET BIT(1) 261 #define WMM_CW_MAX_SET BIT(2) 262 #define WMM_TXOP_SET BIT(3) 263 #define WMM_PARAM_SET GENMASK(3, 0) 264 265 enum { 266 MCU_FW_LOG_WM, 267 MCU_FW_LOG_WA, 268 MCU_FW_LOG_TO_HOST, 269 }; 270 271 enum { 272 MCU_TWT_AGRT_ADD, 273 MCU_TWT_AGRT_MODIFY, 274 MCU_TWT_AGRT_DELETE, 275 MCU_TWT_AGRT_TEARDOWN, 276 MCU_TWT_AGRT_GET_TSF, 277 }; 278 279 enum { 280 MCU_WA_PARAM_CMD_QUERY, 281 MCU_WA_PARAM_CMD_SET, 282 MCU_WA_PARAM_CMD_CAPABILITY, 283 MCU_WA_PARAM_CMD_DEBUG, 284 }; 285 286 enum { 287 MCU_WA_PARAM_PDMA_RX = 0x04, 288 MCU_WA_PARAM_CPU_UTIL = 0x0b, 289 MCU_WA_PARAM_RED = 0x0e, 290 MCU_WA_PARAM_RED_SETTING = 0x40, 291 }; 292 293 enum mcu_mmps_mode { 294 MCU_MMPS_STATIC, 295 MCU_MMPS_DYNAMIC, 296 MCU_MMPS_RSV, 297 MCU_MMPS_DISABLE, 298 }; 299 300 struct bss_info_bmc_rate { 301 __le16 tag; 302 __le16 len; 303 __le16 bc_trans; 304 __le16 mc_trans; 305 u8 short_preamble; 306 u8 rsv[7]; 307 } __packed; 308 309 struct bss_info_ra { 310 __le16 tag; 311 __le16 len; 312 u8 op_mode; 313 u8 adhoc_en; 314 u8 short_preamble; 315 u8 tx_streams; 316 u8 rx_streams; 317 u8 algo; 318 u8 force_sgi; 319 u8 force_gf; 320 u8 ht_mode; 321 u8 has_20_sta; /* Check if any sta support GF. */ 322 u8 bss_width_trigger_events; 323 u8 vht_nss_cap; 324 u8 vht_bw_signal; /* not use */ 325 u8 vht_force_sgi; /* not use */ 326 u8 se_off; 327 u8 antenna_idx; 328 u8 train_up_rule; 329 u8 rsv[3]; 330 __le16 train_up_high_thres; 331 __le16 train_up_rule_rssi; 332 __le16 low_traffic_thres; 333 __le16 max_phyrate; 334 __le32 phy_cap; 335 __le32 interval; 336 __le32 fast_interval; 337 } __packed; 338 339 struct bss_info_hw_amsdu { 340 __le16 tag; 341 __le16 len; 342 __le32 cmp_bitmap_0; 343 __le32 cmp_bitmap_1; 344 __le16 trig_thres; 345 u8 enable; 346 u8 rsv; 347 } __packed; 348 349 struct bss_info_color { 350 __le16 tag; 351 __le16 len; 352 u8 disable; 353 u8 color; 354 u8 rsv[2]; 355 } __packed; 356 357 struct bss_info_he { 358 __le16 tag; 359 __le16 len; 360 u8 he_pe_duration; 361 u8 vht_op_info_present; 362 __le16 he_rts_thres; 363 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 364 u8 rsv[6]; 365 } __packed; 366 367 struct bss_info_bcn { 368 __le16 tag; 369 __le16 len; 370 u8 ver; 371 u8 enable; 372 __le16 sub_ntlv; 373 } __packed __aligned(4); 374 375 struct bss_info_bcn_cntdwn { 376 __le16 tag; 377 __le16 len; 378 u8 cnt; 379 u8 rsv[3]; 380 } __packed __aligned(4); 381 382 struct bss_info_bcn_mbss { 383 #define MAX_BEACON_NUM 32 384 __le16 tag; 385 __le16 len; 386 __le32 bitmap; 387 __le16 offset[MAX_BEACON_NUM]; 388 u8 rsv[8]; 389 } __packed __aligned(4); 390 391 struct bss_info_bcn_cont { 392 __le16 tag; 393 __le16 len; 394 __le16 tim_ofs; 395 __le16 csa_ofs; 396 __le16 bcc_ofs; 397 __le16 pkt_len; 398 } __packed __aligned(4); 399 400 struct bss_info_inband_discovery { 401 __le16 tag; 402 __le16 len; 403 u8 tx_type; 404 u8 tx_mode; 405 u8 tx_interval; 406 u8 enable; 407 __le16 rsv; 408 __le16 prob_rsp_len; 409 } __packed __aligned(4); 410 411 struct bss_info_prot { 412 __le16 tag; 413 __le16 len; 414 __le32 prot_type; 415 __le32 prot_mode; 416 __le32 rts_len_thres; 417 __le16 he_rts_thres; 418 u8 rts_pkt_thres; 419 u8 rsv[5]; 420 } __packed; 421 422 enum { 423 BSS_INFO_BCN_CSA, 424 BSS_INFO_BCN_BCC, 425 BSS_INFO_BCN_MBSSID, 426 BSS_INFO_BCN_CONTENT, 427 BSS_INFO_BCN_DISCOV, 428 BSS_INFO_BCN_MAX 429 }; 430 431 enum { 432 RATE_PARAM_FIXED = 3, 433 RATE_PARAM_MMPS_UPDATE = 5, 434 RATE_PARAM_FIXED_HE_LTF = 7, 435 RATE_PARAM_FIXED_MCS, 436 RATE_PARAM_FIXED_GI = 11, 437 RATE_PARAM_AUTO = 20, 438 RATE_PARAM_SPE_UPDATE = 22, 439 }; 440 441 #define RATE_CFG_MCS GENMASK(3, 0) 442 #define RATE_CFG_NSS GENMASK(7, 4) 443 #define RATE_CFG_GI GENMASK(11, 8) 444 #define RATE_CFG_BW GENMASK(15, 12) 445 #define RATE_CFG_STBC GENMASK(19, 16) 446 #define RATE_CFG_LDPC GENMASK(23, 20) 447 #define RATE_CFG_PHY_TYPE GENMASK(27, 24) 448 #define RATE_CFG_HE_LTF GENMASK(31, 28) 449 450 enum { 451 TX_POWER_LIMIT_ENABLE, 452 TX_POWER_LIMIT_PATH_ENABLE = 0x3, 453 TX_POWER_LIMIT_TABLE = 0x4, 454 TX_POWER_LIMIT_INFO = 0x7, 455 TX_POWER_LIMIT_FRAME = 0x11, 456 TX_POWER_LIMIT_FRAME_MIN = 0x12, 457 }; 458 459 enum { 460 TX_POWER_INFO_PATH = 1, 461 TX_POWER_INFO_RATE, 462 }; 463 464 enum { 465 SPR_ENABLE = 0x1, 466 SPR_ENABLE_SD = 0x3, 467 SPR_ENABLE_MODE = 0x5, 468 SPR_ENABLE_DPD = 0x23, 469 SPR_ENABLE_TX = 0x25, 470 SPR_SET_SRG_BITMAP = 0x80, 471 SPR_SET_PARAM = 0xc2, 472 SPR_SET_SIGA = 0xdc, 473 }; 474 475 enum { 476 THERMAL_PROTECT_PARAMETER_CTRL, 477 THERMAL_PROTECT_BASIC_INFO, 478 THERMAL_PROTECT_ENABLE, 479 THERMAL_PROTECT_DISABLE, 480 THERMAL_PROTECT_DUTY_CONFIG, 481 THERMAL_PROTECT_MECH_INFO, 482 THERMAL_PROTECT_DUTY_INFO, 483 THERMAL_PROTECT_STATE_ACT, 484 }; 485 486 enum { 487 MT_BF_SOUNDING_ON = 1, 488 MT_BF_TYPE_UPDATE = 20, 489 MT_BF_MODULE_UPDATE = 25 490 }; 491 492 enum { 493 MURU_SET_ARB_OP_MODE = 14, 494 MURU_SET_PLATFORM_TYPE = 25, 495 }; 496 497 enum { 498 MURU_PLATFORM_TYPE_PERF_LEVEL_1 = 1, 499 MURU_PLATFORM_TYPE_PERF_LEVEL_2, 500 }; 501 502 /* tx cmd tx statistics */ 503 enum { 504 MURU_SET_TXC_TX_STATS_EN = 150, 505 MURU_GET_TXC_TX_STATS = 151, 506 }; 507 508 enum { 509 SER_QUERY, 510 /* recovery */ 511 SER_SET_RECOVER_L1, 512 SER_SET_RECOVER_L2, 513 SER_SET_RECOVER_L3_RX_ABORT, 514 SER_SET_RECOVER_L3_TX_ABORT, 515 SER_SET_RECOVER_L3_TX_DISABLE, 516 SER_SET_RECOVER_L3_BF, 517 SER_SET_RECOVER_FULL, 518 SER_SET_SYSTEM_ASSERT, 519 /* action */ 520 SER_ENABLE = 2, 521 SER_RECOVER 522 }; 523 524 #define MT7915_MAX_BEACON_SIZE 1308 525 #define MT7915_BEACON_UPDATE_SIZE (sizeof(struct sta_req_hdr) + \ 526 sizeof(struct bss_info_bcn) + \ 527 sizeof(struct bss_info_bcn_cntdwn) + \ 528 sizeof(struct bss_info_bcn_mbss) + \ 529 MT_TXD_SIZE + \ 530 sizeof(struct bss_info_bcn_cont)) 531 #define MT7915_MAX_BSS_OFFLOAD_SIZE (MT7915_MAX_BEACON_SIZE + \ 532 MT7915_BEACON_UPDATE_SIZE) 533 534 #define MT7915_BSS_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 535 sizeof(struct bss_info_omac) + \ 536 sizeof(struct bss_info_basic) +\ 537 sizeof(struct bss_info_rf_ch) +\ 538 sizeof(struct bss_info_ra) + \ 539 sizeof(struct bss_info_hw_amsdu) +\ 540 sizeof(struct bss_info_he) + \ 541 sizeof(struct bss_info_bmc_rate) +\ 542 sizeof(struct bss_info_ext_bss)) 543 544 #endif 545