xref: /linux/include/dt-bindings/reset/tegra234-reset.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
3 
4 #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
5 #define DT_BINDINGS_RESET_TEGRA234_RESET_H
6 
7 /**
8  * @file
9  * @defgroup bpmp_reset_ids Reset ID's
10  * @brief Identifiers for Resets controllable by firmware
11  * @{
12  */
13 #define TEGRA234_RESET_ACTMON			1U
14 #define TEGRA234_RESET_ADSP_ALL			2U
15 #define TEGRA234_RESET_DSI_CORE			3U
16 #define TEGRA234_RESET_CAN1			4U
17 #define TEGRA234_RESET_CAN2			5U
18 #define TEGRA234_RESET_DLA0			6U
19 #define TEGRA234_RESET_DLA1			7U
20 #define TEGRA234_RESET_DPAUX			8U
21 #define TEGRA234_RESET_OFA			9U
22 #define TEGRA234_RESET_NVJPG1			10U
23 #define TEGRA234_RESET_PEX1_CORE_6		11U
24 #define TEGRA234_RESET_PEX1_CORE_6_APB		12U
25 #define TEGRA234_RESET_PEX1_COMMON_APB		13U
26 #define TEGRA234_RESET_PEX2_CORE_7		14U
27 #define TEGRA234_RESET_PEX2_CORE_7_APB		15U
28 #define TEGRA234_RESET_NVDISPLAY		16U
29 #define TEGRA234_RESET_EQOS			17U
30 #define TEGRA234_RESET_GPCDMA			18U
31 #define TEGRA234_RESET_GPU			19U
32 #define TEGRA234_RESET_HDA			20U
33 #define TEGRA234_RESET_HDACODEC			21U
34 #define TEGRA234_RESET_EQOS_MACSEC		22U
35 #define TEGRA234_RESET_EQOS_MACSEC_SECURE	23U
36 #define TEGRA234_RESET_I2C1			24U
37 #define TEGRA234_RESET_PEX2_CORE_8		25U
38 #define TEGRA234_RESET_PEX2_CORE_8_APB		26U
39 #define TEGRA234_RESET_PEX2_CORE_9		27U
40 #define TEGRA234_RESET_PEX2_CORE_9_APB		28U
41 #define TEGRA234_RESET_I2C2			29U
42 #define TEGRA234_RESET_I2C3			30U
43 #define TEGRA234_RESET_I2C4			31U
44 #define TEGRA234_RESET_I2C6			32U
45 #define TEGRA234_RESET_I2C7			33U
46 #define TEGRA234_RESET_I2C8			34U
47 #define TEGRA234_RESET_I2C9			35U
48 #define TEGRA234_RESET_ISP			36U
49 #define TEGRA234_RESET_MIPI_CAL			37U
50 #define TEGRA234_RESET_MPHY_CLK_CTL		38U
51 #define TEGRA234_RESET_MPHY_L0_RX		39U
52 #define TEGRA234_RESET_MPHY_L0_TX		40U
53 #define TEGRA234_RESET_MPHY_L1_RX		41U
54 #define TEGRA234_RESET_MPHY_L1_TX		42U
55 #define TEGRA234_RESET_NVCSI			43U
56 #define TEGRA234_RESET_NVDEC			44U
57 #define TEGRA234_RESET_MGBE0_PCS		45U
58 #define TEGRA234_RESET_MGBE0_MAC		46U
59 #define TEGRA234_RESET_MGBE0_MACSEC		47U
60 #define TEGRA234_RESET_MGBE0_MACSEC_SECURE	48U
61 #define TEGRA234_RESET_MGBE1_PCS		49U
62 #define TEGRA234_RESET_MGBE1_MAC		50U
63 #define TEGRA234_RESET_MGBE1_MACSEC		51U
64 #define TEGRA234_RESET_MGBE1_MACSEC_SECURE	52U
65 #define TEGRA234_RESET_MGBE2_PCS		53U
66 #define TEGRA234_RESET_MGBE2_MAC		54U
67 #define TEGRA234_RESET_MGBE2_MACSEC		55U
68 #define TEGRA234_RESET_PEX2_CORE_10		56U
69 #define TEGRA234_RESET_PEX2_CORE_10_APB		57U
70 #define TEGRA234_RESET_PEX2_COMMON_APB		58U
71 #define TEGRA234_RESET_NVENC			59U
72 #define TEGRA234_RESET_MGBE2_MACSEC_SECURE	60U
73 #define TEGRA234_RESET_NVJPG			61U
74 #define TEGRA234_RESET_LA			64U
75 #define TEGRA234_RESET_HWPM			65U
76 #define TEGRA234_RESET_PVA0_ALL			66U
77 #define TEGRA234_RESET_CEC			67U
78 #define TEGRA234_RESET_PWM1			68U
79 #define TEGRA234_RESET_PWM2			69U
80 #define TEGRA234_RESET_PWM3			70U
81 #define TEGRA234_RESET_PWM4			71U
82 #define TEGRA234_RESET_PWM5			72U
83 #define TEGRA234_RESET_PWM6			73U
84 #define TEGRA234_RESET_PWM7			74U
85 #define TEGRA234_RESET_PWM8			75U
86 #define TEGRA234_RESET_QSPI0			76U
87 #define TEGRA234_RESET_QSPI1			77U
88 #define TEGRA234_RESET_I2S7			78U
89 #define TEGRA234_RESET_I2S8			79U
90 #define TEGRA234_RESET_SCE_ALL			80U
91 #define TEGRA234_RESET_RCE_ALL			81U
92 #define TEGRA234_RESET_SDMMC1			82U
93 #define TEGRA234_RESET_RSVD_83			83U
94 #define TEGRA234_RESET_RSVD_84			84U
95 #define TEGRA234_RESET_SDMMC4			85U
96 #define TEGRA234_RESET_MGBE3_PCS		87U
97 #define TEGRA234_RESET_MGBE3_MAC		88U
98 #define TEGRA234_RESET_MGBE3_MACSEC		89U
99 #define TEGRA234_RESET_MGBE3_MACSEC_SECURE	90U
100 #define TEGRA234_RESET_SPI1			91U
101 #define TEGRA234_RESET_SPI2			92U
102 #define TEGRA234_RESET_SPI3			93U
103 #define TEGRA234_RESET_SPI4			94U
104 #define TEGRA234_RESET_TACH0			95U
105 #define TEGRA234_RESET_TACH1			96U
106 #define TEGRA234_RESET_SPI5			97U
107 #define TEGRA234_RESET_TSEC			98U
108 #define TEGRA234_RESET_UARTI			99U
109 #define TEGRA234_RESET_UARTA			100U
110 #define TEGRA234_RESET_UARTB			101U
111 #define TEGRA234_RESET_UARTC			102U
112 #define TEGRA234_RESET_UARTD			103U
113 #define TEGRA234_RESET_UARTE			104U
114 #define TEGRA234_RESET_UARTF			105U
115 #define TEGRA234_RESET_UARTJ			106U
116 #define TEGRA234_RESET_UARTH			107U
117 #define TEGRA234_RESET_UFSHC			108U
118 #define TEGRA234_RESET_UFSHC_AXI_M		109U
119 #define TEGRA234_RESET_UFSHC_LP_SEQ		110U
120 #define TEGRA234_RESET_RSVD_111			111U
121 #define TEGRA234_RESET_VI			112U
122 #define TEGRA234_RESET_VIC			113U
123 #define TEGRA234_RESET_XUSB_PADCTL		114U
124 #define TEGRA234_RESET_VI2			115U
125 #define TEGRA234_RESET_PEX0_CORE_0		116U
126 #define TEGRA234_RESET_PEX0_CORE_1		117U
127 #define TEGRA234_RESET_PEX0_CORE_2		118U
128 #define TEGRA234_RESET_PEX0_CORE_3		119U
129 #define TEGRA234_RESET_PEX0_CORE_4		120U
130 #define TEGRA234_RESET_PEX0_CORE_0_APB		121U
131 #define TEGRA234_RESET_PEX0_CORE_1_APB		122U
132 #define TEGRA234_RESET_PEX0_CORE_2_APB		123U
133 #define TEGRA234_RESET_PEX0_CORE_3_APB		124U
134 #define TEGRA234_RESET_PEX0_CORE_4_APB		125U
135 #define TEGRA234_RESET_PEX0_COMMON_APB		126U
136 #define TEGRA234_RESET_RSVD_127			127U
137 #define TEGRA234_RESET_NVHS_UPHY_PLL1		128U
138 #define TEGRA234_RESET_PEX1_CORE_5		129U
139 #define TEGRA234_RESET_PEX1_CORE_5_APB		130U
140 #define TEGRA234_RESET_GBE_UPHY			131U
141 #define TEGRA234_RESET_GBE_UPHY_PM		132U
142 #define TEGRA234_RESET_NVHS_UPHY		133U
143 #define TEGRA234_RESET_NVHS_UPHY_PLL0		134U
144 #define TEGRA234_RESET_NVHS_UPHY_L0		135U
145 #define TEGRA234_RESET_NVHS_UPHY_L1		136U
146 #define TEGRA234_RESET_NVHS_UPHY_L2		137U
147 #define TEGRA234_RESET_NVHS_UPHY_L3		138U
148 #define TEGRA234_RESET_NVHS_UPHY_L4		139U
149 #define TEGRA234_RESET_NVHS_UPHY_L5		140U
150 #define TEGRA234_RESET_NVHS_UPHY_L6		141U
151 #define TEGRA234_RESET_NVHS_UPHY_L7		142U
152 #define TEGRA234_RESET_NVHS_UPHY_PM		143U
153 #define TEGRA234_RESET_DMIC5			144U
154 #define TEGRA234_RESET_APE			145U
155 #define TEGRA234_RESET_PEX_USB_UPHY		146U
156 #define TEGRA234_RESET_PEX_USB_UPHY_L0		147U
157 #define TEGRA234_RESET_PEX_USB_UPHY_L1		148U
158 #define TEGRA234_RESET_PEX_USB_UPHY_L2		149U
159 #define TEGRA234_RESET_PEX_USB_UPHY_L3		150U
160 #define TEGRA234_RESET_PEX_USB_UPHY_L4		151U
161 #define TEGRA234_RESET_PEX_USB_UPHY_L5		152U
162 #define TEGRA234_RESET_PEX_USB_UPHY_L6		153U
163 #define TEGRA234_RESET_PEX_USB_UPHY_L7		154U
164 #define TEGRA234_RESET_PEX_USB_UPHY_PLL0	159U
165 #define TEGRA234_RESET_PEX_USB_UPHY_PLL1	160U
166 #define TEGRA234_RESET_PEX_USB_UPHY_PLL2	161U
167 #define TEGRA234_RESET_PEX_USB_UPHY_PLL3	162U
168 #define TEGRA234_RESET_GBE_UPHY_L0		163U
169 #define TEGRA234_RESET_GBE_UPHY_L1		164U
170 #define TEGRA234_RESET_GBE_UPHY_L2		165U
171 #define TEGRA234_RESET_GBE_UPHY_L3		166U
172 #define TEGRA234_RESET_GBE_UPHY_L4		167U
173 #define TEGRA234_RESET_GBE_UPHY_L5		168U
174 #define TEGRA234_RESET_GBE_UPHY_L6		169U
175 #define TEGRA234_RESET_GBE_UPHY_L7		170U
176 #define TEGRA234_RESET_GBE_UPHY_PLL0		171U
177 #define TEGRA234_RESET_GBE_UPHY_PLL1		172U
178 #define TEGRA234_RESET_GBE_UPHY_PLL2		173U
179 
180 /** @} */
181 
182 #endif
183