1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale i.MX7ULP LPSPI driver
4 //
5 // Copyright 2016 Freescale Semiconductor, Inc.
6 // Copyright 2018, 2023, 2025 NXP
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma/imx-dma.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
28 #include <linux/types.h>
29 #include <linux/minmax.h>
30
31 #define DRIVER_NAME "fsl_lpspi"
32
33 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
34
35 /* The maximum bytes that edma can transfer once.*/
36 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
37
38 /* i.MX7ULP LPSPI registers */
39 #define IMX7ULP_VERID 0x0
40 #define IMX7ULP_PARAM 0x4
41 #define IMX7ULP_CR 0x10
42 #define IMX7ULP_SR 0x14
43 #define IMX7ULP_IER 0x18
44 #define IMX7ULP_DER 0x1c
45 #define IMX7ULP_CFGR0 0x20
46 #define IMX7ULP_CFGR1 0x24
47 #define IMX7ULP_DMR0 0x30
48 #define IMX7ULP_DMR1 0x34
49 #define IMX7ULP_CCR 0x40
50 #define IMX7ULP_FCR 0x58
51 #define IMX7ULP_FSR 0x5c
52 #define IMX7ULP_TCR 0x60
53 #define IMX7ULP_TDR 0x64
54 #define IMX7ULP_RSR 0x70
55 #define IMX7ULP_RDR 0x74
56
57 /* General control register field define */
58 #define CR_RRF BIT(9)
59 #define CR_RTF BIT(8)
60 #define CR_RST BIT(1)
61 #define CR_MEN BIT(0)
62 #define SR_MBF BIT(24)
63 #define SR_TCF BIT(10)
64 #define SR_FCF BIT(9)
65 #define SR_RDF BIT(1)
66 #define SR_TDF BIT(0)
67 #define IER_TCIE BIT(10)
68 #define IER_FCIE BIT(9)
69 #define IER_RDIE BIT(1)
70 #define IER_TDIE BIT(0)
71 #define DER_RDDE BIT(1)
72 #define DER_TDDE BIT(0)
73 #define CFGR1_PCSCFG BIT(27)
74 #define CFGR1_PINCFG (BIT(24)|BIT(25))
75 #define CFGR1_PCSPOL_MASK GENMASK(11, 8)
76 #define CFGR1_NOSTALL BIT(3)
77 #define CFGR1_HOST BIT(0)
78 #define FCR_RXWATER GENMASK(18, 16)
79 #define FCR_TXWATER GENMASK(2, 0)
80 #define FSR_TXCOUNT (0xFF)
81 #define RSR_RXEMPTY BIT(1)
82 #define TCR_CPOL BIT(31)
83 #define TCR_CPHA BIT(30)
84 #define TCR_MODE GENMASK(31, 30)
85 #define TCR_PRESCALE GENMASK(29, 27)
86 #define TCR_PCS GENMASK(25, 24)
87 #define TCR_CONT BIT(21)
88 #define TCR_CONTC BIT(20)
89 #define TCR_RXMSK BIT(19)
90 #define TCR_TXMSK BIT(18)
91 #define TCR_FRAMESZ GENMASK(11, 0)
92
93 #define SR_CLEAR_MASK GENMASK(13, 8)
94
95 struct fsl_lpspi_devtype_data {
96 u8 prescale_max : 3; /* 0 == no limit */
97 bool query_hw_for_num_cs : 1;
98 };
99
100 struct lpspi_config {
101 u8 bpw;
102 u8 chip_select;
103 u8 prescale;
104 u32 mode;
105 u32 speed_hz;
106 u32 effective_speed_hz;
107 };
108
109 struct fsl_lpspi_data {
110 struct device *dev;
111 void __iomem *base;
112 unsigned long base_phys;
113 struct clk *clk_ipg;
114 struct clk *clk_per;
115 bool is_target;
116 bool is_only_cs1;
117 bool is_first_byte;
118
119 void *rx_buf;
120 const void *tx_buf;
121 void (*tx)(struct fsl_lpspi_data *fsl_lpspi);
122 void (*rx)(struct fsl_lpspi_data *fsl_lpspi);
123
124 u32 remain;
125 u8 watermark;
126 u8 txfifosize;
127 u8 rxfifosize;
128
129 struct lpspi_config config;
130 struct completion xfer_done;
131
132 bool target_aborted;
133
134 /* DMA */
135 bool usedma;
136 struct completion dma_rx_completion;
137 struct completion dma_tx_completion;
138
139 const struct fsl_lpspi_devtype_data *devtype_data;
140 };
141
142 /*
143 * Devices with ERR051608 have a max TCR_PRESCALE value of 1, otherwise there is
144 * no prescale limit: https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
145 */
146 static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
147 .prescale_max = 1,
148 .query_hw_for_num_cs = true,
149 };
150
151 static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
152 /* All defaults */
153 };
154
155 static const struct fsl_lpspi_devtype_data s32g_lpspi_devtype_data = {
156 .query_hw_for_num_cs = true,
157 };
158
159 static const struct of_device_id fsl_lpspi_dt_ids[] = {
160 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
161 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
162 { .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
163 { /* sentinel */ }
164 };
165 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
166
167 #define LPSPI_BUF_RX(type) \
168 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
169 { \
170 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
171 \
172 if (fsl_lpspi->rx_buf) { \
173 *(type *)fsl_lpspi->rx_buf = val; \
174 fsl_lpspi->rx_buf += sizeof(type); \
175 } \
176 }
177
178 #define LPSPI_BUF_TX(type) \
179 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
180 { \
181 type val = 0; \
182 \
183 if (fsl_lpspi->tx_buf) { \
184 val = *(type *)fsl_lpspi->tx_buf; \
185 fsl_lpspi->tx_buf += sizeof(type); \
186 } \
187 \
188 fsl_lpspi->remain -= sizeof(type); \
189 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
190 }
191
192 LPSPI_BUF_RX(u8)
LPSPI_BUF_TX(u8)193 LPSPI_BUF_TX(u8)
194 LPSPI_BUF_RX(u16)
195 LPSPI_BUF_TX(u16)
196 LPSPI_BUF_RX(u32)
197 LPSPI_BUF_TX(u32)
198
199 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
200 unsigned int enable)
201 {
202 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
203 }
204
fsl_lpspi_bytes_per_word(const int bpw)205 static int fsl_lpspi_bytes_per_word(const int bpw)
206 {
207 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
208 }
209
fsl_lpspi_can_dma(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * transfer)210 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
211 struct spi_device *spi,
212 struct spi_transfer *transfer)
213 {
214 unsigned int bytes_per_word;
215
216 if (!controller->dma_rx)
217 return false;
218
219 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
220
221 switch (bytes_per_word) {
222 case 1:
223 case 2:
224 case 4:
225 break;
226 default:
227 return false;
228 }
229
230 return true;
231 }
232
lpspi_prepare_xfer_hardware(struct spi_controller * controller)233 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
234 {
235 struct fsl_lpspi_data *fsl_lpspi =
236 spi_controller_get_devdata(controller);
237 int ret;
238
239 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
240 if (ret < 0) {
241 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
242 return ret;
243 }
244
245 return 0;
246 }
247
lpspi_unprepare_xfer_hardware(struct spi_controller * controller)248 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
249 {
250 struct fsl_lpspi_data *fsl_lpspi =
251 spi_controller_get_devdata(controller);
252
253 pm_runtime_put_autosuspend(fsl_lpspi->dev);
254
255 return 0;
256 }
257
fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data * fsl_lpspi)258 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
259 {
260 u8 txfifo_cnt;
261 u32 temp;
262
263 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
264
265 while (txfifo_cnt < fsl_lpspi->txfifosize && fsl_lpspi->remain) {
266 fsl_lpspi->tx(fsl_lpspi);
267 txfifo_cnt++;
268 }
269
270 if (txfifo_cnt < fsl_lpspi->txfifosize) {
271 if (!fsl_lpspi->is_target) {
272 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
273 temp &= ~TCR_CONTC;
274 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
275 }
276
277 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
278 } else {
279 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
280 }
281 }
282
fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data * fsl_lpspi)283 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
284 {
285 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
286 fsl_lpspi->rx(fsl_lpspi);
287 }
288
fsl_lpspi_set_cmd(struct fsl_lpspi_data * fsl_lpspi)289 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
290 {
291 u32 temp = 0;
292
293 temp |= FIELD_PREP(TCR_FRAMESZ, fsl_lpspi->config.bpw - 1);
294 temp |= FIELD_PREP(TCR_PCS, fsl_lpspi->config.chip_select);
295 if (!fsl_lpspi->is_target) {
296 temp |= FIELD_PREP(TCR_PRESCALE, fsl_lpspi->config.prescale);
297 /*
298 * Set TCR_CONT will keep SS asserted after current transfer.
299 * For the first transfer, clear TCR_CONTC to assert SS.
300 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
301 */
302 if (!fsl_lpspi->usedma) {
303 temp |= TCR_CONT;
304 if (fsl_lpspi->is_first_byte)
305 temp &= ~TCR_CONTC;
306 else
307 temp |= TCR_CONTC;
308 }
309 }
310
311 if (fsl_lpspi->config.mode & SPI_CPOL)
312 temp |= TCR_CPOL;
313
314 if (fsl_lpspi->config.mode & SPI_CPHA)
315 temp |= TCR_CPHA;
316
317 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
318
319 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
320 }
321
fsl_lpspi_set_watermark(struct fsl_lpspi_data * fsl_lpspi)322 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
323 {
324 u8 watermark = fsl_lpspi->watermark >> 1;
325 u32 temp;
326
327 if (!fsl_lpspi->usedma)
328 temp = FIELD_PREP(FCR_TXWATER, watermark) |
329 FIELD_PREP(FCR_RXWATER, watermark);
330 else
331 temp = FIELD_PREP(FCR_TXWATER, watermark);
332
333 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
334
335 dev_dbg(fsl_lpspi->dev, "FCR=0x%08x\n", temp);
336 }
337
fsl_lpspi_set_bitrate(struct fsl_lpspi_data * fsl_lpspi)338 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
339 {
340 struct lpspi_config config = fsl_lpspi->config;
341 unsigned int perclk_rate, div;
342 u8 prescale_max;
343 u8 prescale;
344 int scldiv;
345
346 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
347 prescale_max = fsl_lpspi->devtype_data->prescale_max ?: 7;
348
349 if (!config.speed_hz) {
350 dev_err(fsl_lpspi->dev,
351 "error: the transmission speed provided is 0!\n");
352 return -EINVAL;
353 }
354
355 if (config.speed_hz > perclk_rate / 2)
356 div = 2;
357 else
358 div = DIV_ROUND_UP(perclk_rate, config.speed_hz);
359
360 for (prescale = 0; prescale <= prescale_max; prescale++) {
361 scldiv = div / (1 << prescale) - 2;
362 if (scldiv >= 0 && scldiv < 256) {
363 fsl_lpspi->config.prescale = prescale;
364 break;
365 }
366 }
367
368 if (scldiv < 0 || scldiv >= 256)
369 return -EINVAL;
370
371 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
372 fsl_lpspi->base + IMX7ULP_CCR);
373
374 fsl_lpspi->config.effective_speed_hz = perclk_rate / (scldiv + 2) *
375 (1 << prescale);
376
377 dev_dbg(fsl_lpspi->dev, "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n",
378 perclk_rate, config.speed_hz, prescale, scldiv);
379
380 return 0;
381 }
382
fsl_lpspi_dma_configure(struct spi_controller * controller)383 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
384 {
385 int ret;
386 enum dma_slave_buswidth buswidth;
387 struct dma_slave_config rx = {}, tx = {};
388 struct fsl_lpspi_data *fsl_lpspi =
389 spi_controller_get_devdata(controller);
390
391 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
392 case 4:
393 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
394 break;
395 case 2:
396 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
397 break;
398 case 1:
399 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 tx.direction = DMA_MEM_TO_DEV;
406 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
407 tx.dst_addr_width = buswidth;
408 tx.dst_maxburst = 1;
409 ret = dmaengine_slave_config(controller->dma_tx, &tx);
410 if (ret) {
411 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
412 ret);
413 return ret;
414 }
415
416 rx.direction = DMA_DEV_TO_MEM;
417 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
418 rx.src_addr_width = buswidth;
419 rx.src_maxburst = 1;
420 ret = dmaengine_slave_config(controller->dma_rx, &rx);
421 if (ret) {
422 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
423 ret);
424 return ret;
425 }
426
427 return 0;
428 }
429
fsl_lpspi_config(struct fsl_lpspi_data * fsl_lpspi)430 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
431 {
432 u32 temp;
433 int ret;
434
435 if (!fsl_lpspi->is_target) {
436 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
437 if (ret)
438 return ret;
439 }
440
441 fsl_lpspi_set_watermark(fsl_lpspi);
442
443 if (!fsl_lpspi->is_target)
444 temp = CFGR1_HOST;
445 else
446 temp = CFGR1_PINCFG;
447 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
448 temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
449 BIT(fsl_lpspi->config.chip_select));
450
451 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
452
453 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
454 temp |= CR_RRF | CR_RTF | CR_MEN;
455 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
456
457 temp = 0;
458 if (fsl_lpspi->usedma)
459 temp = DER_TDDE | DER_RDDE;
460 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
461
462 return 0;
463 }
464
fsl_lpspi_setup_transfer(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)465 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
466 struct spi_device *spi,
467 struct spi_transfer *t)
468 {
469 struct fsl_lpspi_data *fsl_lpspi =
470 spi_controller_get_devdata(spi->controller);
471
472 fsl_lpspi->config.mode = spi->mode;
473 fsl_lpspi->config.bpw = t->bits_per_word;
474 fsl_lpspi->config.speed_hz = t->speed_hz;
475 if (fsl_lpspi->is_only_cs1)
476 fsl_lpspi->config.chip_select = 1;
477 else
478 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
479
480 if (!fsl_lpspi->config.speed_hz)
481 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
482 if (!fsl_lpspi->config.bpw)
483 fsl_lpspi->config.bpw = spi->bits_per_word;
484
485 /* Initialize the functions for transfer */
486 if (fsl_lpspi->config.bpw <= 8) {
487 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
488 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
489 } else if (fsl_lpspi->config.bpw <= 16) {
490 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
491 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
492 } else {
493 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
494 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
495 }
496
497 fsl_lpspi->watermark = min(fsl_lpspi->txfifosize, t->len);
498
499 return fsl_lpspi_config(fsl_lpspi);
500 }
501
fsl_lpspi_prepare_message(struct spi_controller * controller,struct spi_message * msg)502 static int fsl_lpspi_prepare_message(struct spi_controller *controller,
503 struct spi_message *msg)
504 {
505 struct fsl_lpspi_data *fsl_lpspi =
506 spi_controller_get_devdata(controller);
507 struct spi_device *spi = msg->spi;
508 struct spi_transfer *t;
509 int ret;
510
511 t = list_first_entry_or_null(&msg->transfers, struct spi_transfer,
512 transfer_list);
513 if (!t)
514 return 0;
515
516 fsl_lpspi->is_first_byte = true;
517 fsl_lpspi->usedma = false;
518 ret = fsl_lpspi_setup_transfer(controller, spi, t);
519
520 fsl_lpspi->usedma = fsl_lpspi_can_dma(controller, spi, t);
521
522 if (ret < 0)
523 return ret;
524
525 fsl_lpspi_set_cmd(fsl_lpspi);
526
527 /* No IRQs */
528 writel(0, fsl_lpspi->base + IMX7ULP_IER);
529
530 /* Controller disable, clear FIFOs, clear status */
531 writel(CR_RRF | CR_RTF, fsl_lpspi->base + IMX7ULP_CR);
532 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
533
534 return 0;
535 }
536
fsl_lpspi_target_abort(struct spi_controller * controller)537 static int fsl_lpspi_target_abort(struct spi_controller *controller)
538 {
539 struct fsl_lpspi_data *fsl_lpspi =
540 spi_controller_get_devdata(controller);
541
542 fsl_lpspi->target_aborted = true;
543 if (!fsl_lpspi->usedma)
544 complete(&fsl_lpspi->xfer_done);
545 else {
546 complete(&fsl_lpspi->dma_tx_completion);
547 complete(&fsl_lpspi->dma_rx_completion);
548 }
549
550 return 0;
551 }
552
fsl_lpspi_wait_for_completion(struct fsl_lpspi_data * fsl_lpspi)553 static int fsl_lpspi_wait_for_completion(struct fsl_lpspi_data *fsl_lpspi)
554 {
555 if (fsl_lpspi->is_target) {
556 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
557 fsl_lpspi->target_aborted) {
558 dev_dbg(fsl_lpspi->dev, "interrupted\n");
559 return -EINTR;
560 }
561 } else {
562 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
563 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
564 return -ETIMEDOUT;
565 }
566 }
567
568 return 0;
569 }
570
fsl_lpspi_reset(struct fsl_lpspi_data * fsl_lpspi)571 static void fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
572 {
573 u32 temp;
574
575 if (!fsl_lpspi->usedma) {
576 /* Disable all interrupt */
577 fsl_lpspi_intctrl(fsl_lpspi, 0);
578 }
579
580 /* Clear FIFO and disable module */
581 temp = CR_RRF | CR_RTF;
582 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
583
584 /* W1C for all flags in SR */
585 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
586 }
587
fsl_lpspi_dma_rx_callback(void * cookie)588 static void fsl_lpspi_dma_rx_callback(void *cookie)
589 {
590 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
591
592 complete(&fsl_lpspi->dma_rx_completion);
593 }
594
fsl_lpspi_dma_tx_callback(void * cookie)595 static void fsl_lpspi_dma_tx_callback(void *cookie)
596 {
597 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
598
599 complete(&fsl_lpspi->dma_tx_completion);
600 }
601
fsl_lpspi_calculate_timeout(struct fsl_lpspi_data * fsl_lpspi,int size)602 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
603 int size)
604 {
605 unsigned long timeout = 0;
606
607 /* Time with actual data transfer and CS change delay related to HW */
608 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
609
610 /* Add extra second for scheduler related activities */
611 timeout += 1;
612
613 /* Double calculated timeout */
614 return secs_to_jiffies(2 * timeout);
615 }
616
fsl_lpspi_dma_transfer(struct spi_controller * controller,struct fsl_lpspi_data * fsl_lpspi,struct spi_transfer * transfer)617 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
618 struct fsl_lpspi_data *fsl_lpspi,
619 struct spi_transfer *transfer)
620 {
621 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
622 unsigned long transfer_timeout;
623 unsigned long time_left;
624 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
625 int ret;
626
627 ret = fsl_lpspi_dma_configure(controller);
628 if (ret)
629 return ret;
630
631 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
632 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
633 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
634 if (!desc_rx)
635 return -EINVAL;
636
637 desc_rx->callback = fsl_lpspi_dma_rx_callback;
638 desc_rx->callback_param = (void *)fsl_lpspi;
639 dmaengine_submit(desc_rx);
640 reinit_completion(&fsl_lpspi->dma_rx_completion);
641 dma_async_issue_pending(controller->dma_rx);
642
643 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
644 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
645 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
646 if (!desc_tx) {
647 dmaengine_terminate_sync(controller->dma_rx);
648 return -EINVAL;
649 }
650
651 desc_tx->callback = fsl_lpspi_dma_tx_callback;
652 desc_tx->callback_param = (void *)fsl_lpspi;
653 dmaengine_submit(desc_tx);
654 reinit_completion(&fsl_lpspi->dma_tx_completion);
655 dma_async_issue_pending(controller->dma_tx);
656
657 fsl_lpspi->target_aborted = false;
658
659 if (!fsl_lpspi->is_target) {
660 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
661 transfer->len);
662
663 /* Wait eDMA to finish the data transfer.*/
664 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
665 transfer_timeout);
666 if (!time_left) {
667 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
668 dmaengine_terminate_sync(controller->dma_tx);
669 dmaengine_terminate_sync(controller->dma_rx);
670 fsl_lpspi_reset(fsl_lpspi);
671 return -ETIMEDOUT;
672 }
673
674 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
675 transfer_timeout);
676 if (!time_left) {
677 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
678 dmaengine_terminate_sync(controller->dma_tx);
679 dmaengine_terminate_sync(controller->dma_rx);
680 fsl_lpspi_reset(fsl_lpspi);
681 return -ETIMEDOUT;
682 }
683 } else {
684 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
685 fsl_lpspi->target_aborted) {
686 dev_dbg(fsl_lpspi->dev,
687 "I/O Error in DMA TX interrupted\n");
688 dmaengine_terminate_sync(controller->dma_tx);
689 dmaengine_terminate_sync(controller->dma_rx);
690 fsl_lpspi_reset(fsl_lpspi);
691 return -EINTR;
692 }
693
694 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
695 fsl_lpspi->target_aborted) {
696 dev_dbg(fsl_lpspi->dev,
697 "I/O Error in DMA RX interrupted\n");
698 dmaengine_terminate_sync(controller->dma_tx);
699 dmaengine_terminate_sync(controller->dma_rx);
700 fsl_lpspi_reset(fsl_lpspi);
701 return -EINTR;
702 }
703 }
704
705 fsl_lpspi_reset(fsl_lpspi);
706
707 return 0;
708 }
709
fsl_lpspi_dma_exit(struct spi_controller * controller)710 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
711 {
712 if (controller->dma_rx) {
713 dma_release_channel(controller->dma_rx);
714 controller->dma_rx = NULL;
715 }
716
717 if (controller->dma_tx) {
718 dma_release_channel(controller->dma_tx);
719 controller->dma_tx = NULL;
720 }
721 }
722
fsl_lpspi_dma_init(struct device * dev,struct fsl_lpspi_data * fsl_lpspi,struct spi_controller * controller)723 static int fsl_lpspi_dma_init(struct device *dev,
724 struct fsl_lpspi_data *fsl_lpspi,
725 struct spi_controller *controller)
726 {
727 int ret;
728
729 /* Prepare for TX DMA: */
730 controller->dma_tx = dma_request_chan(dev, "tx");
731 if (IS_ERR(controller->dma_tx)) {
732 ret = PTR_ERR(controller->dma_tx);
733 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
734 controller->dma_tx = NULL;
735 goto err;
736 }
737
738 /* Prepare for RX DMA: */
739 controller->dma_rx = dma_request_chan(dev, "rx");
740 if (IS_ERR(controller->dma_rx)) {
741 ret = PTR_ERR(controller->dma_rx);
742 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
743 controller->dma_rx = NULL;
744 goto err;
745 }
746
747 init_completion(&fsl_lpspi->dma_rx_completion);
748 init_completion(&fsl_lpspi->dma_tx_completion);
749 controller->can_dma = fsl_lpspi_can_dma;
750 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
751
752 return 0;
753 err:
754 fsl_lpspi_dma_exit(controller);
755 return ret;
756 }
757
fsl_lpspi_pio_transfer(struct fsl_lpspi_data * fsl_lpspi,struct spi_transfer * t)758 static int fsl_lpspi_pio_transfer(struct fsl_lpspi_data *fsl_lpspi,
759 struct spi_transfer *t)
760 {
761 int ret;
762
763 fsl_lpspi->tx_buf = t->tx_buf;
764 fsl_lpspi->rx_buf = t->rx_buf;
765 fsl_lpspi->remain = t->len;
766
767 reinit_completion(&fsl_lpspi->xfer_done);
768 fsl_lpspi->target_aborted = false;
769
770 fsl_lpspi_write_tx_fifo(fsl_lpspi);
771
772 ret = fsl_lpspi_wait_for_completion(fsl_lpspi);
773
774 fsl_lpspi_reset(fsl_lpspi);
775
776 return ret;
777 }
778
fsl_lpspi_transfer_one(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)779 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
780 struct spi_device *spi,
781 struct spi_transfer *t)
782 {
783 struct fsl_lpspi_data *fsl_lpspi =
784 spi_controller_get_devdata(controller);
785 int ret;
786
787 fsl_lpspi->usedma = fsl_lpspi_can_dma(controller, spi, t);
788
789 ret = fsl_lpspi_setup_transfer(controller, spi, t);
790 if (ret < 0)
791 return ret;
792
793 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz;
794
795 fsl_lpspi_set_cmd(fsl_lpspi);
796 fsl_lpspi->is_first_byte = false;
797
798 if (fsl_lpspi->usedma)
799 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
800 else
801 ret = fsl_lpspi_pio_transfer(fsl_lpspi, t);
802
803 return ret;
804 }
805
fsl_lpspi_isr(int irq,void * dev_id)806 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
807 {
808 u32 temp_SR, temp_IER;
809 struct fsl_lpspi_data *fsl_lpspi = dev_id;
810
811 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
812 fsl_lpspi_intctrl(fsl_lpspi, 0);
813 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
814
815 fsl_lpspi_read_rx_fifo(fsl_lpspi);
816
817 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
818 fsl_lpspi_write_tx_fifo(fsl_lpspi);
819 return IRQ_HANDLED;
820 }
821
822 if (temp_SR & SR_MBF ||
823 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
824 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
825 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE | (temp_IER & IER_TDIE));
826 return IRQ_HANDLED;
827 }
828
829 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
830 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
831 complete(&fsl_lpspi->xfer_done);
832 return IRQ_HANDLED;
833 }
834
835 return IRQ_NONE;
836 }
837
fsl_lpspi_runtime_resume(struct device * dev)838 static int fsl_lpspi_runtime_resume(struct device *dev)
839 {
840 struct spi_controller *controller = dev_get_drvdata(dev);
841 struct fsl_lpspi_data *fsl_lpspi;
842 int ret;
843
844 fsl_lpspi = spi_controller_get_devdata(controller);
845
846 ret = clk_prepare_enable(fsl_lpspi->clk_per);
847 if (ret)
848 return ret;
849
850 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
851 if (ret) {
852 clk_disable_unprepare(fsl_lpspi->clk_per);
853 return ret;
854 }
855
856 return 0;
857 }
858
fsl_lpspi_runtime_suspend(struct device * dev)859 static int fsl_lpspi_runtime_suspend(struct device *dev)
860 {
861 struct spi_controller *controller = dev_get_drvdata(dev);
862 struct fsl_lpspi_data *fsl_lpspi;
863
864 fsl_lpspi = spi_controller_get_devdata(controller);
865
866 clk_disable_unprepare(fsl_lpspi->clk_per);
867 clk_disable_unprepare(fsl_lpspi->clk_ipg);
868
869 return 0;
870 }
871
fsl_lpspi_init_rpm(struct fsl_lpspi_data * fsl_lpspi)872 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
873 {
874 struct device *dev = fsl_lpspi->dev;
875
876 pm_runtime_enable(dev);
877 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
878 pm_runtime_use_autosuspend(dev);
879
880 return 0;
881 }
882
fsl_lpspi_probe(struct platform_device * pdev)883 static int fsl_lpspi_probe(struct platform_device *pdev)
884 {
885 const struct fsl_lpspi_devtype_data *devtype_data;
886 struct fsl_lpspi_data *fsl_lpspi;
887 struct spi_controller *controller;
888 struct resource *res;
889 int ret, irq;
890 u32 num_cs;
891 u32 temp;
892 bool is_target;
893
894 devtype_data = of_device_get_match_data(&pdev->dev);
895 if (!devtype_data)
896 return -ENODEV;
897
898 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
899 if (is_target)
900 controller = devm_spi_alloc_target(&pdev->dev,
901 sizeof(struct fsl_lpspi_data));
902 else
903 controller = devm_spi_alloc_host(&pdev->dev,
904 sizeof(struct fsl_lpspi_data));
905
906 if (!controller)
907 return -ENOMEM;
908
909 platform_set_drvdata(pdev, controller);
910
911 fsl_lpspi = spi_controller_get_devdata(controller);
912 fsl_lpspi->dev = &pdev->dev;
913 fsl_lpspi->is_target = is_target;
914 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
915 "fsl,spi-only-use-cs1-sel");
916 fsl_lpspi->devtype_data = devtype_data;
917
918 init_completion(&fsl_lpspi->xfer_done);
919
920 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
921 if (IS_ERR(fsl_lpspi->base)) {
922 ret = PTR_ERR(fsl_lpspi->base);
923 return ret;
924 }
925 fsl_lpspi->base_phys = res->start;
926
927 irq = platform_get_irq(pdev, 0);
928 if (irq < 0) {
929 ret = irq;
930 return ret;
931 }
932
933 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN,
934 dev_name(&pdev->dev), fsl_lpspi);
935 if (ret) {
936 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
937 return ret;
938 }
939
940 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
941 if (IS_ERR(fsl_lpspi->clk_per)) {
942 ret = PTR_ERR(fsl_lpspi->clk_per);
943 return ret;
944 }
945
946 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
947 if (IS_ERR(fsl_lpspi->clk_ipg)) {
948 ret = PTR_ERR(fsl_lpspi->clk_ipg);
949 return ret;
950 }
951
952 /* enable the clock */
953 ret = fsl_lpspi_init_rpm(fsl_lpspi);
954 if (ret)
955 return ret;
956
957 ret = pm_runtime_get_sync(fsl_lpspi->dev);
958 if (ret < 0) {
959 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
960 goto out_pm_get;
961 }
962
963 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
964 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
965 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
966 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
967 &num_cs)) {
968 if (devtype_data->query_hw_for_num_cs)
969 num_cs = ((temp >> 16) & 0xf);
970 else
971 num_cs = 1;
972 }
973
974 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
975 controller->prepare_message = fsl_lpspi_prepare_message;
976 controller->transfer_one = fsl_lpspi_transfer_one;
977 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
978 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
979 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
980 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
981 controller->bus_num = pdev->id;
982 controller->num_chipselect = num_cs;
983 controller->target_abort = fsl_lpspi_target_abort;
984 if (!fsl_lpspi->is_target)
985 controller->use_gpio_descriptors = true;
986
987 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
988 if (ret == -EPROBE_DEFER)
989 goto out_pm_get;
990 if (ret < 0) {
991 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
992 enable_irq(irq);
993 }
994
995 ret = spi_register_controller(controller);
996 if (ret < 0) {
997 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
998 goto free_dma;
999 }
1000
1001 pm_runtime_put_autosuspend(fsl_lpspi->dev);
1002
1003 return 0;
1004
1005 free_dma:
1006 fsl_lpspi_dma_exit(controller);
1007 out_pm_get:
1008 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
1009 pm_runtime_put_sync(fsl_lpspi->dev);
1010 pm_runtime_disable(fsl_lpspi->dev);
1011
1012 return ret;
1013 }
1014
fsl_lpspi_remove(struct platform_device * pdev)1015 static void fsl_lpspi_remove(struct platform_device *pdev)
1016 {
1017 struct spi_controller *controller = platform_get_drvdata(pdev);
1018 struct fsl_lpspi_data *fsl_lpspi =
1019 spi_controller_get_devdata(controller);
1020
1021 spi_unregister_controller(controller);
1022 fsl_lpspi_dma_exit(controller);
1023
1024 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
1025 pm_runtime_disable(fsl_lpspi->dev);
1026 }
1027
fsl_lpspi_suspend(struct device * dev)1028 static int fsl_lpspi_suspend(struct device *dev)
1029 {
1030 pinctrl_pm_select_sleep_state(dev);
1031 return pm_runtime_force_suspend(dev);
1032 }
1033
fsl_lpspi_resume(struct device * dev)1034 static int fsl_lpspi_resume(struct device *dev)
1035 {
1036 int ret;
1037
1038 ret = pm_runtime_force_resume(dev);
1039 if (ret) {
1040 dev_err(dev, "Error in resume: %d\n", ret);
1041 return ret;
1042 }
1043
1044 pinctrl_pm_select_default_state(dev);
1045
1046 return 0;
1047 }
1048
1049 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
1050 RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
1051 fsl_lpspi_runtime_resume, NULL)
1052 SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
1053 };
1054
1055 static struct platform_driver fsl_lpspi_driver = {
1056 .driver = {
1057 .name = DRIVER_NAME,
1058 .of_match_table = fsl_lpspi_dt_ids,
1059 .pm = pm_ptr(&fsl_lpspi_pm_ops),
1060 },
1061 .probe = fsl_lpspi_probe,
1062 .remove = fsl_lpspi_remove,
1063 };
1064 module_platform_driver(fsl_lpspi_driver);
1065
1066 MODULE_DESCRIPTION("LPSPI Controller driver");
1067 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1068 MODULE_LICENSE("GPL");
1069