1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Freescale i.MX7ULP LPSPI driver
4 //
5 // Copyright 2016 Freescale Semiconductor, Inc.
6 // Copyright 2018, 2023, 2025 NXP
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/completion.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma/imx-dma.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
28 #include <linux/types.h>
29 #include <linux/minmax.h>
30
31 #define DRIVER_NAME "fsl_lpspi"
32
33 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
34
35 /* The maximum bytes that edma can transfer once.*/
36 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
37
38 /* i.MX7ULP LPSPI registers */
39 #define IMX7ULP_VERID 0x0
40 #define IMX7ULP_PARAM 0x4
41 #define IMX7ULP_CR 0x10
42 #define IMX7ULP_SR 0x14
43 #define IMX7ULP_IER 0x18
44 #define IMX7ULP_DER 0x1c
45 #define IMX7ULP_CFGR0 0x20
46 #define IMX7ULP_CFGR1 0x24
47 #define IMX7ULP_DMR0 0x30
48 #define IMX7ULP_DMR1 0x34
49 #define IMX7ULP_CCR 0x40
50 #define IMX7ULP_FCR 0x58
51 #define IMX7ULP_FSR 0x5c
52 #define IMX7ULP_TCR 0x60
53 #define IMX7ULP_TDR 0x64
54 #define IMX7ULP_RSR 0x70
55 #define IMX7ULP_RDR 0x74
56
57 /* General control register field define */
58 #define CR_RRF BIT(9)
59 #define CR_RTF BIT(8)
60 #define CR_RST BIT(1)
61 #define CR_MEN BIT(0)
62 #define SR_MBF BIT(24)
63 #define SR_TCF BIT(10)
64 #define SR_FCF BIT(9)
65 #define SR_RDF BIT(1)
66 #define SR_TDF BIT(0)
67 #define IER_TCIE BIT(10)
68 #define IER_FCIE BIT(9)
69 #define IER_RDIE BIT(1)
70 #define IER_TDIE BIT(0)
71 #define DER_RDDE BIT(1)
72 #define DER_TDDE BIT(0)
73 #define CFGR1_PCSCFG BIT(27)
74 #define CFGR1_PINCFG (BIT(24)|BIT(25))
75 #define CFGR1_PCSPOL_MASK GENMASK(11, 8)
76 #define CFGR1_NOSTALL BIT(3)
77 #define CFGR1_HOST BIT(0)
78 #define FCR_RXWATER GENMASK(18, 16)
79 #define FCR_TXWATER GENMASK(2, 0)
80 #define FSR_TXCOUNT (0xFF)
81 #define RSR_RXEMPTY BIT(1)
82 #define TCR_CPOL BIT(31)
83 #define TCR_CPHA BIT(30)
84 #define TCR_MODE GENMASK(31, 30)
85 #define TCR_PRESCALE GENMASK(29, 27)
86 #define TCR_PCS GENMASK(25, 24)
87 #define TCR_CONT BIT(21)
88 #define TCR_CONTC BIT(20)
89 #define TCR_RXMSK BIT(19)
90 #define TCR_TXMSK BIT(18)
91 #define TCR_FRAMESZ GENMASK(11, 0)
92
93 #define SR_CLEAR_MASK GENMASK(13, 8)
94
95 struct fsl_lpspi_devtype_data {
96 u8 prescale_max : 3; /* 0 == no limit */
97 bool query_hw_for_num_cs : 1;
98 };
99
100 struct lpspi_config {
101 u8 bpw;
102 u8 chip_select;
103 u8 prescale;
104 u32 mode;
105 u32 speed_hz;
106 u32 effective_speed_hz;
107 };
108
109 struct fsl_lpspi_data {
110 struct device *dev;
111 void __iomem *base;
112 unsigned long base_phys;
113 struct clk *clk_ipg;
114 struct clk *clk_per;
115 bool is_target;
116 bool is_only_cs1;
117 bool is_first_byte;
118
119 void *rx_buf;
120 const void *tx_buf;
121 void (*tx)(struct fsl_lpspi_data *fsl_lpspi);
122 void (*rx)(struct fsl_lpspi_data *fsl_lpspi);
123
124 u32 remain;
125 u8 watermark;
126 u8 txfifosize;
127 u8 rxfifosize;
128
129 struct lpspi_config config;
130 struct completion xfer_done;
131
132 bool target_aborted;
133
134 /* DMA */
135 bool usedma;
136 struct completion dma_rx_completion;
137 struct completion dma_tx_completion;
138
139 const struct fsl_lpspi_devtype_data *devtype_data;
140 };
141
142 /*
143 * Devices with ERR051608 have a max TCR_PRESCALE value of 1, otherwise there is
144 * no prescale limit: https://www.nxp.com/docs/en/errata/i.MX93_1P87f.pdf
145 */
146 static const struct fsl_lpspi_devtype_data imx93_lpspi_devtype_data = {
147 .prescale_max = 1,
148 .query_hw_for_num_cs = true,
149 };
150
151 static const struct fsl_lpspi_devtype_data imx7ulp_lpspi_devtype_data = {
152 /* All defaults */
153 };
154
155 static const struct fsl_lpspi_devtype_data s32g_lpspi_devtype_data = {
156 .query_hw_for_num_cs = true,
157 };
158
159 static const struct of_device_id fsl_lpspi_dt_ids[] = {
160 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
161 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
162 { .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
163 { /* sentinel */ }
164 };
165 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
166
167 #define LPSPI_BUF_RX(type) \
168 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
169 { \
170 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
171 \
172 if (fsl_lpspi->rx_buf) { \
173 *(type *)fsl_lpspi->rx_buf = val; \
174 fsl_lpspi->rx_buf += sizeof(type); \
175 } \
176 }
177
178 #define LPSPI_BUF_TX(type) \
179 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
180 { \
181 type val = 0; \
182 \
183 if (fsl_lpspi->tx_buf) { \
184 val = *(type *)fsl_lpspi->tx_buf; \
185 fsl_lpspi->tx_buf += sizeof(type); \
186 } \
187 \
188 fsl_lpspi->remain -= sizeof(type); \
189 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
190 }
191
192 LPSPI_BUF_RX(u8)
LPSPI_BUF_TX(u8)193 LPSPI_BUF_TX(u8)
194 LPSPI_BUF_RX(u16)
195 LPSPI_BUF_TX(u16)
196 LPSPI_BUF_RX(u32)
197 LPSPI_BUF_TX(u32)
198
199 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
200 unsigned int enable)
201 {
202 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
203 }
204
fsl_lpspi_bytes_per_word(const int bpw)205 static int fsl_lpspi_bytes_per_word(const int bpw)
206 {
207 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
208 }
209
fsl_lpspi_can_dma(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * transfer)210 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
211 struct spi_device *spi,
212 struct spi_transfer *transfer)
213 {
214 unsigned int bytes_per_word;
215
216 if (!controller->dma_rx)
217 return false;
218
219 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
220
221 switch (bytes_per_word) {
222 case 1:
223 case 2:
224 case 4:
225 break;
226 default:
227 return false;
228 }
229
230 return true;
231 }
232
lpspi_prepare_xfer_hardware(struct spi_controller * controller)233 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
234 {
235 struct fsl_lpspi_data *fsl_lpspi =
236 spi_controller_get_devdata(controller);
237 int ret;
238
239 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
240 if (ret < 0) {
241 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
242 return ret;
243 }
244
245 return 0;
246 }
247
lpspi_unprepare_xfer_hardware(struct spi_controller * controller)248 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
249 {
250 struct fsl_lpspi_data *fsl_lpspi =
251 spi_controller_get_devdata(controller);
252
253 pm_runtime_put_autosuspend(fsl_lpspi->dev);
254
255 return 0;
256 }
257
fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data * fsl_lpspi)258 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
259 {
260 u8 txfifo_cnt;
261 u32 temp;
262
263 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
264
265 while (txfifo_cnt < fsl_lpspi->txfifosize && fsl_lpspi->remain) {
266 fsl_lpspi->tx(fsl_lpspi);
267 txfifo_cnt++;
268 }
269
270 if (txfifo_cnt < fsl_lpspi->txfifosize) {
271 if (!fsl_lpspi->is_target) {
272 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
273 temp &= ~TCR_CONTC;
274 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
275 }
276
277 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
278 } else {
279 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
280 }
281 }
282
fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data * fsl_lpspi)283 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
284 {
285 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
286 fsl_lpspi->rx(fsl_lpspi);
287 }
288
fsl_lpspi_set_cmd(struct fsl_lpspi_data * fsl_lpspi)289 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
290 {
291 u32 temp = 0;
292
293 temp |= FIELD_PREP(TCR_FRAMESZ, fsl_lpspi->config.bpw - 1);
294 temp |= FIELD_PREP(TCR_PCS, fsl_lpspi->config.chip_select);
295 if (!fsl_lpspi->is_target) {
296 temp |= FIELD_PREP(TCR_PRESCALE, fsl_lpspi->config.prescale);
297 /*
298 * Set TCR_CONT will keep SS asserted after current transfer.
299 * For the first transfer, clear TCR_CONTC to assert SS.
300 * For subsequent transfer, set TCR_CONTC to keep SS asserted.
301 */
302 if (!fsl_lpspi->usedma) {
303 temp |= TCR_CONT;
304 if (fsl_lpspi->is_first_byte)
305 temp &= ~TCR_CONTC;
306 else
307 temp |= TCR_CONTC;
308 }
309 }
310
311 if (fsl_lpspi->config.mode & SPI_CPOL)
312 temp |= TCR_CPOL;
313
314 if (fsl_lpspi->config.mode & SPI_CPHA)
315 temp |= TCR_CPHA;
316
317 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
318
319 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
320 }
321
fsl_lpspi_set_watermark(struct fsl_lpspi_data * fsl_lpspi)322 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
323 {
324 u8 watermark = fsl_lpspi->watermark >> 1;
325 u32 temp;
326
327 if (!fsl_lpspi->usedma)
328 temp = FIELD_PREP(FCR_TXWATER, watermark) |
329 FIELD_PREP(FCR_RXWATER, watermark);
330 else
331 temp = FIELD_PREP(FCR_TXWATER, watermark);
332
333 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
334
335 dev_dbg(fsl_lpspi->dev, "FCR=0x%08x\n", temp);
336 }
337
fsl_lpspi_set_bitrate(struct fsl_lpspi_data * fsl_lpspi)338 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
339 {
340 struct lpspi_config config = fsl_lpspi->config;
341 unsigned int perclk_rate, div;
342 u8 prescale_max;
343 u8 prescale;
344 int scldiv;
345
346 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
347 prescale_max = fsl_lpspi->devtype_data->prescale_max ?: 7;
348
349 if (!config.speed_hz) {
350 dev_err(fsl_lpspi->dev,
351 "error: the transmission speed provided is 0!\n");
352 return -EINVAL;
353 }
354
355 if (config.speed_hz > perclk_rate / 2)
356 div = 2;
357 else
358 div = DIV_ROUND_UP(perclk_rate, config.speed_hz);
359
360 for (prescale = 0; prescale <= prescale_max; prescale++) {
361 scldiv = div / (1 << prescale) - 2;
362 if (scldiv >= 0 && scldiv < 256) {
363 fsl_lpspi->config.prescale = prescale;
364 break;
365 }
366 }
367
368 if (scldiv < 0 || scldiv >= 256)
369 return -EINVAL;
370
371 writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
372 fsl_lpspi->base + IMX7ULP_CCR);
373
374 fsl_lpspi->config.effective_speed_hz = perclk_rate / (scldiv + 2) *
375 (1 << prescale);
376
377 dev_dbg(fsl_lpspi->dev, "perclk=%u, speed=%u, prescale=%u, scldiv=%d\n",
378 perclk_rate, config.speed_hz, prescale, scldiv);
379
380 return 0;
381 }
382
fsl_lpspi_dma_configure(struct spi_controller * controller)383 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
384 {
385 int ret;
386 enum dma_slave_buswidth buswidth;
387 struct dma_slave_config rx = {}, tx = {};
388 struct fsl_lpspi_data *fsl_lpspi =
389 spi_controller_get_devdata(controller);
390
391 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
392 case 4:
393 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
394 break;
395 case 2:
396 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
397 break;
398 case 1:
399 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
400 break;
401 default:
402 return -EINVAL;
403 }
404
405 tx.direction = DMA_MEM_TO_DEV;
406 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
407 tx.dst_addr_width = buswidth;
408 tx.dst_maxburst = 1;
409 ret = dmaengine_slave_config(controller->dma_tx, &tx);
410 if (ret) {
411 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
412 ret);
413 return ret;
414 }
415
416 rx.direction = DMA_DEV_TO_MEM;
417 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
418 rx.src_addr_width = buswidth;
419 rx.src_maxburst = 1;
420 ret = dmaengine_slave_config(controller->dma_rx, &rx);
421 if (ret) {
422 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
423 ret);
424 return ret;
425 }
426
427 return 0;
428 }
429
fsl_lpspi_config(struct fsl_lpspi_data * fsl_lpspi)430 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
431 {
432 u32 temp;
433 int ret;
434
435 if (!fsl_lpspi->is_target) {
436 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
437 if (ret)
438 return ret;
439 }
440
441 fsl_lpspi_set_watermark(fsl_lpspi);
442
443 if (!fsl_lpspi->is_target)
444 temp = CFGR1_HOST;
445 else
446 temp = CFGR1_PINCFG;
447 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
448 temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
449 BIT(fsl_lpspi->config.chip_select));
450
451 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
452
453 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
454 temp |= CR_RRF | CR_RTF | CR_MEN;
455 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
456
457 temp = 0;
458 if (fsl_lpspi->usedma)
459 temp = DER_TDDE | DER_RDDE;
460 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
461
462 return 0;
463 }
464
fsl_lpspi_setup_transfer(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)465 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
466 struct spi_device *spi,
467 struct spi_transfer *t)
468 {
469 struct fsl_lpspi_data *fsl_lpspi =
470 spi_controller_get_devdata(spi->controller);
471
472 fsl_lpspi->config.mode = spi->mode;
473 fsl_lpspi->config.bpw = t->bits_per_word;
474 fsl_lpspi->config.speed_hz = t->speed_hz;
475 if (fsl_lpspi->is_only_cs1)
476 fsl_lpspi->config.chip_select = 1;
477 else
478 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
479
480 if (!fsl_lpspi->config.speed_hz)
481 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
482 if (!fsl_lpspi->config.bpw)
483 fsl_lpspi->config.bpw = spi->bits_per_word;
484
485 /* Initialize the functions for transfer */
486 if (fsl_lpspi->config.bpw <= 8) {
487 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
488 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
489 } else if (fsl_lpspi->config.bpw <= 16) {
490 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
491 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
492 } else {
493 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
494 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
495 }
496
497 fsl_lpspi->watermark = min(fsl_lpspi->txfifosize, t->len);
498
499 return fsl_lpspi_config(fsl_lpspi);
500 }
501
fsl_lpspi_prepare_message(struct spi_controller * controller,struct spi_message * msg)502 static int fsl_lpspi_prepare_message(struct spi_controller *controller,
503 struct spi_message *msg)
504 {
505 struct fsl_lpspi_data *fsl_lpspi =
506 spi_controller_get_devdata(controller);
507 struct spi_device *spi = msg->spi;
508 struct spi_transfer *t;
509 int ret;
510
511 t = list_first_entry_or_null(&msg->transfers, struct spi_transfer,
512 transfer_list);
513 if (!t)
514 return 0;
515
516 fsl_lpspi->is_first_byte = true;
517 fsl_lpspi->usedma = false;
518 ret = fsl_lpspi_setup_transfer(controller, spi, t);
519
520 fsl_lpspi->usedma = fsl_lpspi_can_dma(controller, spi, t);
521
522 if (ret < 0)
523 return ret;
524
525 fsl_lpspi_set_cmd(fsl_lpspi);
526
527 /* No IRQs */
528 writel(0, fsl_lpspi->base + IMX7ULP_IER);
529
530 /* Controller disable, clear FIFOs, clear status */
531 writel(CR_RRF | CR_RTF, fsl_lpspi->base + IMX7ULP_CR);
532 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
533
534 return 0;
535 }
536
fsl_lpspi_target_abort(struct spi_controller * controller)537 static int fsl_lpspi_target_abort(struct spi_controller *controller)
538 {
539 struct fsl_lpspi_data *fsl_lpspi =
540 spi_controller_get_devdata(controller);
541
542 fsl_lpspi->target_aborted = true;
543 if (!fsl_lpspi->usedma)
544 complete(&fsl_lpspi->xfer_done);
545 else {
546 complete(&fsl_lpspi->dma_tx_completion);
547 complete(&fsl_lpspi->dma_rx_completion);
548 }
549
550 return 0;
551 }
552
fsl_lpspi_wait_for_completion(struct spi_controller * controller)553 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
554 {
555 struct fsl_lpspi_data *fsl_lpspi =
556 spi_controller_get_devdata(controller);
557
558 if (fsl_lpspi->is_target) {
559 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
560 fsl_lpspi->target_aborted) {
561 dev_dbg(fsl_lpspi->dev, "interrupted\n");
562 return -EINTR;
563 }
564 } else {
565 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
566 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
567 return -ETIMEDOUT;
568 }
569 }
570
571 return 0;
572 }
573
fsl_lpspi_reset(struct fsl_lpspi_data * fsl_lpspi)574 static void fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
575 {
576 u32 temp;
577
578 if (!fsl_lpspi->usedma) {
579 /* Disable all interrupt */
580 fsl_lpspi_intctrl(fsl_lpspi, 0);
581 }
582
583 /* Clear FIFO and disable module */
584 temp = CR_RRF | CR_RTF;
585 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
586
587 /* W1C for all flags in SR */
588 writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
589 }
590
fsl_lpspi_dma_rx_callback(void * cookie)591 static void fsl_lpspi_dma_rx_callback(void *cookie)
592 {
593 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
594
595 complete(&fsl_lpspi->dma_rx_completion);
596 }
597
fsl_lpspi_dma_tx_callback(void * cookie)598 static void fsl_lpspi_dma_tx_callback(void *cookie)
599 {
600 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
601
602 complete(&fsl_lpspi->dma_tx_completion);
603 }
604
fsl_lpspi_calculate_timeout(struct fsl_lpspi_data * fsl_lpspi,int size)605 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
606 int size)
607 {
608 unsigned long timeout = 0;
609
610 /* Time with actual data transfer and CS change delay related to HW */
611 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
612
613 /* Add extra second for scheduler related activities */
614 timeout += 1;
615
616 /* Double calculated timeout */
617 return secs_to_jiffies(2 * timeout);
618 }
619
fsl_lpspi_dma_transfer(struct spi_controller * controller,struct fsl_lpspi_data * fsl_lpspi,struct spi_transfer * transfer)620 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
621 struct fsl_lpspi_data *fsl_lpspi,
622 struct spi_transfer *transfer)
623 {
624 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
625 unsigned long transfer_timeout;
626 unsigned long time_left;
627 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
628 int ret;
629
630 ret = fsl_lpspi_dma_configure(controller);
631 if (ret)
632 return ret;
633
634 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
635 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
636 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
637 if (!desc_rx)
638 return -EINVAL;
639
640 desc_rx->callback = fsl_lpspi_dma_rx_callback;
641 desc_rx->callback_param = (void *)fsl_lpspi;
642 dmaengine_submit(desc_rx);
643 reinit_completion(&fsl_lpspi->dma_rx_completion);
644 dma_async_issue_pending(controller->dma_rx);
645
646 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
647 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
648 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
649 if (!desc_tx) {
650 dmaengine_terminate_all(controller->dma_tx);
651 return -EINVAL;
652 }
653
654 desc_tx->callback = fsl_lpspi_dma_tx_callback;
655 desc_tx->callback_param = (void *)fsl_lpspi;
656 dmaengine_submit(desc_tx);
657 reinit_completion(&fsl_lpspi->dma_tx_completion);
658 dma_async_issue_pending(controller->dma_tx);
659
660 fsl_lpspi->target_aborted = false;
661
662 if (!fsl_lpspi->is_target) {
663 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
664 transfer->len);
665
666 /* Wait eDMA to finish the data transfer.*/
667 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
668 transfer_timeout);
669 if (!time_left) {
670 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
671 dmaengine_terminate_all(controller->dma_tx);
672 dmaengine_terminate_all(controller->dma_rx);
673 fsl_lpspi_reset(fsl_lpspi);
674 return -ETIMEDOUT;
675 }
676
677 time_left = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
678 transfer_timeout);
679 if (!time_left) {
680 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
681 dmaengine_terminate_all(controller->dma_tx);
682 dmaengine_terminate_all(controller->dma_rx);
683 fsl_lpspi_reset(fsl_lpspi);
684 return -ETIMEDOUT;
685 }
686 } else {
687 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
688 fsl_lpspi->target_aborted) {
689 dev_dbg(fsl_lpspi->dev,
690 "I/O Error in DMA TX interrupted\n");
691 dmaengine_terminate_all(controller->dma_tx);
692 dmaengine_terminate_all(controller->dma_rx);
693 fsl_lpspi_reset(fsl_lpspi);
694 return -EINTR;
695 }
696
697 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
698 fsl_lpspi->target_aborted) {
699 dev_dbg(fsl_lpspi->dev,
700 "I/O Error in DMA RX interrupted\n");
701 dmaengine_terminate_all(controller->dma_tx);
702 dmaengine_terminate_all(controller->dma_rx);
703 fsl_lpspi_reset(fsl_lpspi);
704 return -EINTR;
705 }
706 }
707
708 fsl_lpspi_reset(fsl_lpspi);
709
710 return 0;
711 }
712
fsl_lpspi_dma_exit(struct spi_controller * controller)713 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
714 {
715 if (controller->dma_rx) {
716 dma_release_channel(controller->dma_rx);
717 controller->dma_rx = NULL;
718 }
719
720 if (controller->dma_tx) {
721 dma_release_channel(controller->dma_tx);
722 controller->dma_tx = NULL;
723 }
724 }
725
fsl_lpspi_dma_init(struct device * dev,struct fsl_lpspi_data * fsl_lpspi,struct spi_controller * controller)726 static int fsl_lpspi_dma_init(struct device *dev,
727 struct fsl_lpspi_data *fsl_lpspi,
728 struct spi_controller *controller)
729 {
730 int ret;
731
732 /* Prepare for TX DMA: */
733 controller->dma_tx = dma_request_chan(dev, "tx");
734 if (IS_ERR(controller->dma_tx)) {
735 ret = PTR_ERR(controller->dma_tx);
736 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
737 controller->dma_tx = NULL;
738 goto err;
739 }
740
741 /* Prepare for RX DMA: */
742 controller->dma_rx = dma_request_chan(dev, "rx");
743 if (IS_ERR(controller->dma_rx)) {
744 ret = PTR_ERR(controller->dma_rx);
745 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
746 controller->dma_rx = NULL;
747 goto err;
748 }
749
750 init_completion(&fsl_lpspi->dma_rx_completion);
751 init_completion(&fsl_lpspi->dma_tx_completion);
752 controller->can_dma = fsl_lpspi_can_dma;
753 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
754
755 return 0;
756 err:
757 fsl_lpspi_dma_exit(controller);
758 return ret;
759 }
760
fsl_lpspi_pio_transfer(struct spi_controller * controller,struct spi_transfer * t)761 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
762 struct spi_transfer *t)
763 {
764 struct fsl_lpspi_data *fsl_lpspi =
765 spi_controller_get_devdata(controller);
766 int ret;
767
768 fsl_lpspi->tx_buf = t->tx_buf;
769 fsl_lpspi->rx_buf = t->rx_buf;
770 fsl_lpspi->remain = t->len;
771
772 reinit_completion(&fsl_lpspi->xfer_done);
773 fsl_lpspi->target_aborted = false;
774
775 fsl_lpspi_write_tx_fifo(fsl_lpspi);
776
777 ret = fsl_lpspi_wait_for_completion(controller);
778
779 fsl_lpspi_reset(fsl_lpspi);
780
781 return ret;
782 }
783
fsl_lpspi_transfer_one(struct spi_controller * controller,struct spi_device * spi,struct spi_transfer * t)784 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
785 struct spi_device *spi,
786 struct spi_transfer *t)
787 {
788 struct fsl_lpspi_data *fsl_lpspi =
789 spi_controller_get_devdata(controller);
790 int ret;
791
792 fsl_lpspi->usedma = fsl_lpspi_can_dma(controller, spi, t);
793
794 ret = fsl_lpspi_setup_transfer(controller, spi, t);
795 if (ret < 0)
796 return ret;
797
798 t->effective_speed_hz = fsl_lpspi->config.effective_speed_hz;
799
800 fsl_lpspi_set_cmd(fsl_lpspi);
801 fsl_lpspi->is_first_byte = false;
802
803 if (fsl_lpspi->usedma)
804 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
805 else
806 ret = fsl_lpspi_pio_transfer(controller, t);
807 if (ret < 0)
808 return ret;
809
810 return 0;
811 }
812
fsl_lpspi_isr(int irq,void * dev_id)813 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
814 {
815 u32 temp_SR, temp_IER;
816 struct fsl_lpspi_data *fsl_lpspi = dev_id;
817
818 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
819 fsl_lpspi_intctrl(fsl_lpspi, 0);
820 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
821
822 fsl_lpspi_read_rx_fifo(fsl_lpspi);
823
824 if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
825 fsl_lpspi_write_tx_fifo(fsl_lpspi);
826 return IRQ_HANDLED;
827 }
828
829 if (temp_SR & SR_MBF ||
830 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
831 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
832 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE | (temp_IER & IER_TDIE));
833 return IRQ_HANDLED;
834 }
835
836 if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
837 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
838 complete(&fsl_lpspi->xfer_done);
839 return IRQ_HANDLED;
840 }
841
842 return IRQ_NONE;
843 }
844
845 #ifdef CONFIG_PM
fsl_lpspi_runtime_resume(struct device * dev)846 static int fsl_lpspi_runtime_resume(struct device *dev)
847 {
848 struct spi_controller *controller = dev_get_drvdata(dev);
849 struct fsl_lpspi_data *fsl_lpspi;
850 int ret;
851
852 fsl_lpspi = spi_controller_get_devdata(controller);
853
854 ret = clk_prepare_enable(fsl_lpspi->clk_per);
855 if (ret)
856 return ret;
857
858 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
859 if (ret) {
860 clk_disable_unprepare(fsl_lpspi->clk_per);
861 return ret;
862 }
863
864 return 0;
865 }
866
fsl_lpspi_runtime_suspend(struct device * dev)867 static int fsl_lpspi_runtime_suspend(struct device *dev)
868 {
869 struct spi_controller *controller = dev_get_drvdata(dev);
870 struct fsl_lpspi_data *fsl_lpspi;
871
872 fsl_lpspi = spi_controller_get_devdata(controller);
873
874 clk_disable_unprepare(fsl_lpspi->clk_per);
875 clk_disable_unprepare(fsl_lpspi->clk_ipg);
876
877 return 0;
878 }
879 #endif
880
fsl_lpspi_init_rpm(struct fsl_lpspi_data * fsl_lpspi)881 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
882 {
883 struct device *dev = fsl_lpspi->dev;
884
885 pm_runtime_enable(dev);
886 pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
887 pm_runtime_use_autosuspend(dev);
888
889 return 0;
890 }
891
fsl_lpspi_probe(struct platform_device * pdev)892 static int fsl_lpspi_probe(struct platform_device *pdev)
893 {
894 const struct fsl_lpspi_devtype_data *devtype_data;
895 struct fsl_lpspi_data *fsl_lpspi;
896 struct spi_controller *controller;
897 struct resource *res;
898 int ret, irq;
899 u32 num_cs;
900 u32 temp;
901 bool is_target;
902
903 devtype_data = of_device_get_match_data(&pdev->dev);
904 if (!devtype_data)
905 return -ENODEV;
906
907 is_target = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
908 if (is_target)
909 controller = devm_spi_alloc_target(&pdev->dev,
910 sizeof(struct fsl_lpspi_data));
911 else
912 controller = devm_spi_alloc_host(&pdev->dev,
913 sizeof(struct fsl_lpspi_data));
914
915 if (!controller)
916 return -ENOMEM;
917
918 platform_set_drvdata(pdev, controller);
919
920 fsl_lpspi = spi_controller_get_devdata(controller);
921 fsl_lpspi->dev = &pdev->dev;
922 fsl_lpspi->is_target = is_target;
923 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
924 "fsl,spi-only-use-cs1-sel");
925 fsl_lpspi->devtype_data = devtype_data;
926
927 init_completion(&fsl_lpspi->xfer_done);
928
929 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
930 if (IS_ERR(fsl_lpspi->base)) {
931 ret = PTR_ERR(fsl_lpspi->base);
932 return ret;
933 }
934 fsl_lpspi->base_phys = res->start;
935
936 irq = platform_get_irq(pdev, 0);
937 if (irq < 0) {
938 ret = irq;
939 return ret;
940 }
941
942 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, IRQF_NO_AUTOEN,
943 dev_name(&pdev->dev), fsl_lpspi);
944 if (ret) {
945 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
946 return ret;
947 }
948
949 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
950 if (IS_ERR(fsl_lpspi->clk_per)) {
951 ret = PTR_ERR(fsl_lpspi->clk_per);
952 return ret;
953 }
954
955 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
956 if (IS_ERR(fsl_lpspi->clk_ipg)) {
957 ret = PTR_ERR(fsl_lpspi->clk_ipg);
958 return ret;
959 }
960
961 /* enable the clock */
962 ret = fsl_lpspi_init_rpm(fsl_lpspi);
963 if (ret)
964 return ret;
965
966 ret = pm_runtime_get_sync(fsl_lpspi->dev);
967 if (ret < 0) {
968 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
969 goto out_pm_get;
970 }
971
972 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
973 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
974 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
975 if (of_property_read_u32((&pdev->dev)->of_node, "num-cs",
976 &num_cs)) {
977 if (devtype_data->query_hw_for_num_cs)
978 num_cs = ((temp >> 16) & 0xf);
979 else
980 num_cs = 1;
981 }
982
983 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
984 controller->prepare_message = fsl_lpspi_prepare_message;
985 controller->transfer_one = fsl_lpspi_transfer_one;
986 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
987 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
988 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
989 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
990 controller->bus_num = pdev->id;
991 controller->num_chipselect = num_cs;
992 controller->target_abort = fsl_lpspi_target_abort;
993 if (!fsl_lpspi->is_target)
994 controller->use_gpio_descriptors = true;
995
996 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
997 if (ret == -EPROBE_DEFER)
998 goto out_pm_get;
999 if (ret < 0) {
1000 dev_warn(&pdev->dev, "dma setup error %d, use pio\n", ret);
1001 enable_irq(irq);
1002 }
1003
1004 ret = spi_register_controller(controller);
1005 if (ret < 0) {
1006 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n");
1007 goto free_dma;
1008 }
1009
1010 pm_runtime_put_autosuspend(fsl_lpspi->dev);
1011
1012 return 0;
1013
1014 free_dma:
1015 fsl_lpspi_dma_exit(controller);
1016 out_pm_get:
1017 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
1018 pm_runtime_put_sync(fsl_lpspi->dev);
1019 pm_runtime_disable(fsl_lpspi->dev);
1020
1021 return ret;
1022 }
1023
fsl_lpspi_remove(struct platform_device * pdev)1024 static void fsl_lpspi_remove(struct platform_device *pdev)
1025 {
1026 struct spi_controller *controller = platform_get_drvdata(pdev);
1027 struct fsl_lpspi_data *fsl_lpspi =
1028 spi_controller_get_devdata(controller);
1029
1030 spi_unregister_controller(controller);
1031 fsl_lpspi_dma_exit(controller);
1032
1033 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
1034 pm_runtime_disable(fsl_lpspi->dev);
1035 }
1036
fsl_lpspi_suspend(struct device * dev)1037 static int fsl_lpspi_suspend(struct device *dev)
1038 {
1039 pinctrl_pm_select_sleep_state(dev);
1040 return pm_runtime_force_suspend(dev);
1041 }
1042
fsl_lpspi_resume(struct device * dev)1043 static int fsl_lpspi_resume(struct device *dev)
1044 {
1045 int ret;
1046
1047 ret = pm_runtime_force_resume(dev);
1048 if (ret) {
1049 dev_err(dev, "Error in resume: %d\n", ret);
1050 return ret;
1051 }
1052
1053 pinctrl_pm_select_default_state(dev);
1054
1055 return 0;
1056 }
1057
1058 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
1059 SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
1060 fsl_lpspi_runtime_resume, NULL)
1061 SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
1062 };
1063
1064 static struct platform_driver fsl_lpspi_driver = {
1065 .driver = {
1066 .name = DRIVER_NAME,
1067 .of_match_table = fsl_lpspi_dt_ids,
1068 .pm = pm_ptr(&fsl_lpspi_pm_ops),
1069 },
1070 .probe = fsl_lpspi_probe,
1071 .remove = fsl_lpspi_remove,
1072 };
1073 module_platform_driver(fsl_lpspi_driver);
1074
1075 MODULE_DESCRIPTION("LPSPI Controller driver");
1076 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
1077 MODULE_LICENSE("GPL");
1078