xref: /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h (revision fd143856b094b1798318d6816f37ea7380668c4c)
1 /*
2  * Copyright 2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef SMU14_DRIVER_IF_V14_0_H
25 #define SMU14_DRIVER_IF_V14_0_H
26 
27 //Increment this version if SkuTable_t or BoardTable_t change
28 #define PPTABLE_VERSION 0x1B
29 
30 #define NUM_GFXCLK_DPM_LEVELS    16
31 #define NUM_SOCCLK_DPM_LEVELS    8
32 #define NUM_MP0CLK_DPM_LEVELS    2
33 #define NUM_DCLK_DPM_LEVELS      8
34 #define NUM_VCLK_DPM_LEVELS      8
35 #define NUM_DISPCLK_DPM_LEVELS   8
36 #define NUM_DPPCLK_DPM_LEVELS    8
37 #define NUM_DPREFCLK_DPM_LEVELS  8
38 #define NUM_DCFCLK_DPM_LEVELS    8
39 #define NUM_DTBCLK_DPM_LEVELS    8
40 #define NUM_UCLK_DPM_LEVELS      6
41 #define NUM_LINK_LEVELS          3
42 #define NUM_FCLK_DPM_LEVELS      8
43 #define NUM_OD_FAN_MAX_POINTS    6
44 
45 // Feature Control Defines
46 #define FEATURE_FW_DATA_READ_BIT              0
47 #define FEATURE_DPM_GFXCLK_BIT                1
48 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT   2
49 #define FEATURE_DPM_UCLK_BIT                  3
50 #define FEATURE_DPM_FCLK_BIT                  4
51 #define FEATURE_DPM_SOCCLK_BIT                5
52 #define FEATURE_DPM_LINK_BIT                  6
53 #define FEATURE_DPM_DCN_BIT                   7
54 #define FEATURE_VMEMP_SCALING_BIT             8
55 #define FEATURE_VDDIO_MEM_SCALING_BIT         9
56 #define FEATURE_DS_GFXCLK_BIT                 10
57 #define FEATURE_DS_SOCCLK_BIT                 11
58 #define FEATURE_DS_FCLK_BIT                   12
59 #define FEATURE_DS_LCLK_BIT                   13
60 #define FEATURE_DS_DCFCLK_BIT                 14
61 #define FEATURE_DS_UCLK_BIT                   15
62 #define FEATURE_GFX_ULV_BIT                   16
63 #define FEATURE_FW_DSTATE_BIT                 17
64 #define FEATURE_GFXOFF_BIT                    18
65 #define FEATURE_BACO_BIT                      19
66 #define FEATURE_MM_DPM_BIT                    20
67 #define FEATURE_SOC_MPCLK_DS_BIT              21
68 #define FEATURE_BACO_MPCLK_DS_BIT             22
69 #define FEATURE_THROTTLERS_BIT                23
70 #define FEATURE_SMARTSHIFT_BIT                24
71 #define FEATURE_GTHR_BIT                      25
72 #define FEATURE_ACDC_BIT                      26
73 #define FEATURE_VR0HOT_BIT                    27
74 #define FEATURE_FW_CTF_BIT                    28
75 #define FEATURE_FAN_CONTROL_BIT               29
76 #define FEATURE_GFX_DCS_BIT                   30
77 #define FEATURE_GFX_READ_MARGIN_BIT           31
78 #define FEATURE_LED_DISPLAY_BIT               32
79 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT    33
80 #define FEATURE_OUT_OF_BAND_MONITOR_BIT       34
81 #define FEATURE_OPTIMIZED_VMIN_BIT            35
82 #define FEATURE_GFX_IMU_BIT                   36
83 #define FEATURE_BOOT_TIME_CAL_BIT             37
84 #define FEATURE_GFX_PCC_DFLL_BIT              38
85 #define FEATURE_SOC_CG_BIT                    39
86 #define FEATURE_DF_CSTATE_BIT                 40
87 #define FEATURE_GFX_EDC_BIT                   41
88 #define FEATURE_BOOT_POWER_OPT_BIT            42
89 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT   43
90 #define FEATURE_DS_VCN_BIT                    44
91 #define FEATURE_BACO_CG_BIT                   45
92 #define FEATURE_MEM_TEMP_READ_BIT             46
93 #define FEATURE_ATHUB_MMHUB_PG_BIT            47
94 #define FEATURE_SOC_PCC_BIT                   48
95 #define FEATURE_EDC_PWRBRK_BIT                49
96 #define FEATURE_SOC_EDC_XVMIN_BIT             50
97 #define FEATURE_GFX_PSM_DIDT_BIT              51
98 #define FEATURE_APT_ALL_ENABLE_BIT            52
99 #define FEATURE_APT_SQ_THROTTLE_BIT           53
100 #define FEATURE_APT_PF_DCS_BIT                54
101 #define FEATURE_GFX_EDC_XVMIN_BIT             55
102 #define FEATURE_GFX_DIDT_XVMIN_BIT            56
103 #define FEATURE_FAN_ABNORMAL_BIT              57
104 #define FEATURE_CLOCK_STRETCH_COMPENSATOR     58
105 #define FEATURE_SPARE_59_BIT                  59
106 #define FEATURE_SPARE_60_BIT                  60
107 #define FEATURE_SPARE_61_BIT                  61
108 #define FEATURE_SPARE_62_BIT                  62
109 #define FEATURE_SPARE_63_BIT                  63
110 #define NUM_FEATURES                          64
111 
112 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL
113 #define ALLOWED_FEATURE_CTRL_SCPM        (1 << FEATURE_DPM_GFXCLK_BIT) | \
114                                          (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \
115                                          (1 << FEATURE_DPM_UCLK_BIT) | \
116                                          (1 << FEATURE_DPM_FCLK_BIT) | \
117                                          (1 << FEATURE_DPM_SOCCLK_BIT) | \
118                                          (1 << FEATURE_DPM_LINK_BIT) | \
119                                          (1 << FEATURE_DPM_DCN_BIT) | \
120                                          (1 << FEATURE_DS_GFXCLK_BIT) | \
121                                          (1 << FEATURE_DS_SOCCLK_BIT) | \
122                                          (1 << FEATURE_DS_FCLK_BIT) | \
123                                          (1 << FEATURE_DS_LCLK_BIT) | \
124                                          (1 << FEATURE_DS_DCFCLK_BIT) | \
125                                          (1 << FEATURE_DS_UCLK_BIT) | \
126                                          (1ULL << FEATURE_DS_VCN_BIT)
127 
128 
129 //For use with feature control messages
130 typedef enum {
131   FEATURE_PWR_ALL,
132   FEATURE_PWR_S5,
133   FEATURE_PWR_BACO,
134   FEATURE_PWR_SOC,
135   FEATURE_PWR_GFX,
136   FEATURE_PWR_DOMAIN_COUNT,
137 } FEATURE_PWR_DOMAIN_e;
138 
139 //For use with feature control + BTC save restore
140 typedef enum {
141   FEATURE_BTC_NOP,
142   FEATURE_BTC_SAVE,
143   FEATURE_BTC_RESTORE,
144   FEATURE_BTC_COUNT,
145 } FEATURE_BTC_e;
146 
147 // Debug Overrides Bitmask
148 #define DEBUG_OVERRIDE_NOT_USE      				   0x00000001
149 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK      0x00000002
150 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK      0x00000004
151 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK    0x00000008
152 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER         0x00000010
153 #define DEBUG_OVERRIDE_DISABLE_VCN_PG                  0x00000020
154 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX               0x00000040
155 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS           0x00000080
156 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100
157 #define DEBUG_OVERRIDE_DISABLE_DFLL                    0x00000200
158 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE      0x00000400
159 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE                0x00000800
160 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE           0x00001000
161 #define DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE      0x00002000
162 #define DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY         0x00004000
163 #define DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING  0x00008000
164 #define DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG                0x00010000
165 
166 // VR Mapping Bit Defines
167 #define VR_MAPPING_VR_SELECT_MASK  0x01
168 #define VR_MAPPING_VR_SELECT_SHIFT 0x00
169 
170 #define VR_MAPPING_PLANE_SELECT_MASK  0x02
171 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
172 
173 // PSI Bit Defines
174 #define PSI_SEL_VR0_PLANE0_PSI0  0x01
175 #define PSI_SEL_VR0_PLANE0_PSI1  0x02
176 #define PSI_SEL_VR0_PLANE1_PSI0  0x04
177 #define PSI_SEL_VR0_PLANE1_PSI1  0x08
178 #define PSI_SEL_VR1_PLANE0_PSI0  0x10
179 #define PSI_SEL_VR1_PLANE0_PSI1  0x20
180 #define PSI_SEL_VR1_PLANE1_PSI0  0x40
181 #define PSI_SEL_VR1_PLANE1_PSI1  0x80
182 
183 typedef enum {
184   SVI_PSI_0, // Full phase count (default)
185   SVI_PSI_1, // Phase count 1st level
186   SVI_PSI_2, // Phase count 2nd level
187   SVI_PSI_3, // Single phase operation + active diode emulation
188   SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
189   SVI_PSI_5, // Reserved
190   SVI_PSI_6, // Power down to 0V (voltage regulation disabled)
191   SVI_PSI_7, // Automated phase shedding and diode emulation
192 } SVI_PSI_e;
193 
194 // Throttler Control/Status Bits
195 #define THROTTLER_TEMP_EDGE_BIT        0
196 #define THROTTLER_TEMP_HOTSPOT_BIT     1
197 #define THROTTLER_TEMP_HOTSPOT_GFX_BIT 2
198 #define THROTTLER_TEMP_HOTSPOT_SOC_BIT 3
199 #define THROTTLER_TEMP_MEM_BIT         4
200 #define THROTTLER_TEMP_VR_GFX_BIT      5
201 #define THROTTLER_TEMP_VR_SOC_BIT      6
202 #define THROTTLER_TEMP_VR_MEM0_BIT     7
203 #define THROTTLER_TEMP_VR_MEM1_BIT     8
204 #define THROTTLER_TEMP_LIQUID0_BIT     9
205 #define THROTTLER_TEMP_LIQUID1_BIT     10
206 #define THROTTLER_TEMP_PLX_BIT         11
207 #define THROTTLER_TDC_GFX_BIT          12
208 #define THROTTLER_TDC_SOC_BIT          13
209 #define THROTTLER_PPT0_BIT             14
210 #define THROTTLER_PPT1_BIT             15
211 #define THROTTLER_PPT2_BIT             16
212 #define THROTTLER_PPT3_BIT             17
213 #define THROTTLER_FIT_BIT              18
214 #define THROTTLER_GFX_APCC_PLUS_BIT    19
215 #define THROTTLER_GFX_DVO_BIT          20
216 #define THROTTLER_COUNT                21
217 
218 // FW DState Features Control Bits
219 #define FW_DSTATE_SOC_ULV_BIT               0
220 #define FW_DSTATE_G6_HSR_BIT                1
221 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT      2
222 #define FW_DSTATE_SMN_DS_BIT                3
223 #define FW_DSTATE_MP1_WHISPER_MODE_BIT      4
224 #define FW_DSTATE_SOC_LIV_MIN_BIT           5
225 #define FW_DSTATE_SOC_PLL_PWRDN_BIT         6
226 #define FW_DSTATE_MEM_PLL_PWRDN_BIT         7
227 #define FW_DSTATE_MALL_ALLOC_BIT            8
228 #define FW_DSTATE_MEM_PSI_BIT               9
229 #define FW_DSTATE_HSR_NON_STROBE_BIT        10
230 #define FW_DSTATE_MP0_ENTER_WFI_BIT         11
231 #define FW_DSTATE_MALL_FLUSH_BIT            12
232 #define FW_DSTATE_SOC_PSI_BIT               13
233 #define FW_DSTATE_MMHUB_INTERLOCK_BIT       14
234 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT       15
235 #define FW_DSTATE_CLDO_PRG_BIT              16
236 #define FW_DSTATE_DF_PLL_PWRDN_BIT          17
237 
238 //LED Display Mask & Control Bits
239 #define LED_DISPLAY_GFX_DPM_BIT            0
240 #define LED_DISPLAY_PCIE_BIT               1
241 #define LED_DISPLAY_ERROR_BIT              2
242 
243 
244 #define MEM_TEMP_READ_OUT_OF_BAND_BIT          0
245 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT      1
246 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2
247 
248 typedef enum {
249   SMARTSHIFT_VERSION_1,
250   SMARTSHIFT_VERSION_2,
251   SMARTSHIFT_VERSION_3,
252 } SMARTSHIFT_VERSION_e;
253 
254 typedef enum {
255   FOPT_CALC_AC_CALC_DC,
256   FOPT_PPTABLE_AC_CALC_DC,
257   FOPT_CALC_AC_PPTABLE_DC,
258   FOPT_PPTABLE_AC_PPTABLE_DC,
259 } FOPT_CALC_e;
260 
261 typedef enum {
262   DRAM_BIT_WIDTH_DISABLED = 0,
263   DRAM_BIT_WIDTH_X_8 = 8,
264   DRAM_BIT_WIDTH_X_16 = 16,
265   DRAM_BIT_WIDTH_X_32 = 32,
266   DRAM_BIT_WIDTH_X_64 = 64,
267   DRAM_BIT_WIDTH_X_128 = 128,
268   DRAM_BIT_WIDTH_COUNT,
269 } DRAM_BIT_WIDTH_TYPE_e;
270 
271 //I2C Interface
272 #define NUM_I2C_CONTROLLERS                8
273 
274 #define I2C_CONTROLLER_ENABLED             1
275 #define I2C_CONTROLLER_DISABLED            0
276 
277 #define MAX_SW_I2C_COMMANDS                24
278 
279 typedef enum {
280   I2C_CONTROLLER_PORT_0 = 0,  //CKSVII2C0
281   I2C_CONTROLLER_PORT_1 = 1,  //CKSVII2C1
282   I2C_CONTROLLER_PORT_COUNT,
283 } I2cControllerPort_e;
284 
285 typedef enum {
286   I2C_CONTROLLER_NAME_VR_GFX = 0,
287   I2C_CONTROLLER_NAME_VR_SOC,
288   I2C_CONTROLLER_NAME_VR_VMEMP,
289   I2C_CONTROLLER_NAME_VR_VDDIO,
290   I2C_CONTROLLER_NAME_LIQUID0,
291   I2C_CONTROLLER_NAME_LIQUID1,
292   I2C_CONTROLLER_NAME_PLX,
293   I2C_CONTROLLER_NAME_FAN_INTAKE,
294   I2C_CONTROLLER_NAME_COUNT,
295 } I2cControllerName_e;
296 
297 typedef enum {
298   I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
299   I2C_CONTROLLER_THROTTLER_VR_GFX,
300   I2C_CONTROLLER_THROTTLER_VR_SOC,
301   I2C_CONTROLLER_THROTTLER_VR_VMEMP,
302   I2C_CONTROLLER_THROTTLER_VR_VDDIO,
303   I2C_CONTROLLER_THROTTLER_LIQUID0,
304   I2C_CONTROLLER_THROTTLER_LIQUID1,
305   I2C_CONTROLLER_THROTTLER_PLX,
306   I2C_CONTROLLER_THROTTLER_FAN_INTAKE,
307   I2C_CONTROLLER_THROTTLER_INA3221,
308   I2C_CONTROLLER_THROTTLER_COUNT,
309 } I2cControllerThrottler_e;
310 
311 typedef enum {
312   I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
313   I2C_CONTROLLER_PROTOCOL_VR_IR35217,
314   I2C_CONTROLLER_PROTOCOL_TMP_MAX31875,
315   I2C_CONTROLLER_PROTOCOL_INA3221,
316   I2C_CONTROLLER_PROTOCOL_TMP_MAX6604,
317   I2C_CONTROLLER_PROTOCOL_COUNT,
318 } I2cControllerProtocol_e;
319 
320 typedef struct {
321   uint8_t   Enabled;
322   uint8_t   Speed;
323   uint8_t   SlaveAddress;
324   uint8_t   ControllerPort;
325   uint8_t   ControllerName;
326   uint8_t   ThermalThrotter;
327   uint8_t   I2cProtocol;
328   uint8_t   PaddingConfig;
329 } I2cControllerConfig_t;
330 
331 typedef enum {
332   I2C_PORT_SVD_SCL = 0,
333   I2C_PORT_GPIO,
334 } I2cPort_e;
335 
336 typedef enum {
337   I2C_SPEED_FAST_50K = 0,      //50  Kbits/s
338   I2C_SPEED_FAST_100K,         //100 Kbits/s
339   I2C_SPEED_FAST_400K,         //400 Kbits/s
340   I2C_SPEED_FAST_PLUS_1M,      //1   Mbits/s (in fast mode)
341   I2C_SPEED_HIGH_1M,           //1   Mbits/s (in high speed mode)
342   I2C_SPEED_HIGH_2M,           //2.3 Mbits/s
343   I2C_SPEED_COUNT,
344 } I2cSpeed_e;
345 
346 typedef enum {
347   I2C_CMD_READ = 0,
348   I2C_CMD_WRITE,
349   I2C_CMD_COUNT,
350 } I2cCmdType_e;
351 
352 #define CMDCONFIG_STOP_BIT             0
353 #define CMDCONFIG_RESTART_BIT          1
354 #define CMDCONFIG_READWRITE_BIT        2 //bit should be 0 for read, 1 for write
355 
356 #define CMDCONFIG_STOP_MASK           (1 << CMDCONFIG_STOP_BIT)
357 #define CMDCONFIG_RESTART_MASK        (1 << CMDCONFIG_RESTART_BIT)
358 #define CMDCONFIG_READWRITE_MASK      (1 << CMDCONFIG_READWRITE_BIT)
359 
360 typedef struct {
361   uint8_t ReadWriteData;  //Return data for read. Data to send for write
362   uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
363 } SwI2cCmd_t; //SW I2C Command Table
364 
365 typedef struct {
366   uint8_t     I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
367   uint8_t     I2CSpeed;          //Use I2cSpeed_e to indicate speed to select
368   uint8_t     SlaveAddress;      //Slave address of device
369   uint8_t     NumCmds;           //Number of commands
370 
371   SwI2cCmd_t  SwI2cCmds[MAX_SW_I2C_COMMANDS];
372 } SwI2cRequest_t; // SW I2C Request Table
373 
374 typedef struct {
375   SwI2cRequest_t SwI2cRequest;
376 
377   uint32_t Spare[8];
378   uint32_t MmHubPadding[8]; // SMU internal use
379 } SwI2cRequestExternal_t;
380 
381 typedef struct {
382   uint64_t mca_umc_status;
383   uint64_t mca_umc_addr;
384 
385   uint16_t ce_count_lo_chip;
386   uint16_t ce_count_hi_chip;
387 
388   uint32_t eccPadding;
389 } EccInfo_t;
390 
391 typedef struct {
392   EccInfo_t  EccInfo[24];
393 } EccInfoTable_t;
394 
395 #define EPCS_HIGH_POWER                  600
396 #define EPCS_NORMAL_POWER                450
397 #define EPCS_LOW_POWER                   300
398 #define EPCS_SHORTED_POWER               150
399 #define EPCS_NO_BOOTUP                   0
400 
401 typedef enum{
402   EPCS_SHORTED_LIMIT,
403   EPCS_LOW_POWER_LIMIT,
404   EPCS_NORMAL_POWER_LIMIT,
405   EPCS_HIGH_POWER_LIMIT,
406   EPCS_NOT_CONFIGURED,
407   EPCS_STATUS_COUNT,
408 } EPCS_STATUS_e;
409 
410 //D3HOT sequences
411 typedef enum {
412   BACO_SEQUENCE,
413   MSR_SEQUENCE,
414   BAMACO_SEQUENCE,
415   ULPS_SEQUENCE,
416   D3HOT_SEQUENCE_COUNT,
417 } D3HOTSequence_e;
418 
419 //This is aligned with RSMU PGFSM Register Mapping
420 typedef enum {
421   PG_DYNAMIC_MODE = 0,
422   PG_STATIC_MODE,
423 } PowerGatingMode_e;
424 
425 //This is aligned with RSMU PGFSM Register Mapping
426 typedef enum {
427   PG_POWER_DOWN = 0,
428   PG_POWER_UP,
429 } PowerGatingSettings_e;
430 
431 typedef struct {
432   uint32_t a;  // store in IEEE float format in this variable
433   uint32_t b;  // store in IEEE float format in this variable
434   uint32_t c;  // store in IEEE float format in this variable
435 } QuadraticInt_t;
436 
437 typedef struct {
438   uint32_t m;  // store in IEEE float format in this variable
439   uint32_t b;  // store in IEEE float format in this variable
440 } LinearInt_t;
441 
442 typedef struct {
443   uint32_t a;  // store in IEEE float format in this variable
444   uint32_t b;  // store in IEEE float format in this variable
445   uint32_t c;  // store in IEEE float format in this variable
446 } DroopInt_t;
447 
448 typedef enum {
449   DCS_ARCH_DISABLED,
450   DCS_ARCH_FADCS,
451   DCS_ARCH_ASYNC,
452 } DCS_ARCH_e;
453 
454 //Only Clks that have DPM descriptors are listed here
455 typedef enum {
456   PPCLK_GFXCLK = 0,
457   PPCLK_SOCCLK,
458   PPCLK_UCLK,
459   PPCLK_FCLK,
460   PPCLK_DCLK_0,
461   PPCLK_VCLK_0,
462   PPCLK_DISPCLK,
463   PPCLK_DPPCLK,
464   PPCLK_DPREFCLK,
465   PPCLK_DCFCLK,
466   PPCLK_DTBCLK,
467   PPCLK_COUNT,
468 } PPCLK_e;
469 
470 typedef enum {
471   VOLTAGE_MODE_PPTABLE = 0,
472   VOLTAGE_MODE_FUSES,
473   VOLTAGE_MODE_COUNT,
474 } VOLTAGE_MODE_e;
475 
476 typedef enum {
477   AVFS_VOLTAGE_GFX = 0,
478   AVFS_VOLTAGE_SOC,
479   AVFS_VOLTAGE_COUNT,
480 } AVFS_VOLTAGE_TYPE_e;
481 
482 typedef enum {
483   AVFS_TEMP_COLD = 0,
484   AVFS_TEMP_HOT,
485   AVFS_TEMP_COUNT,
486 } AVFS_TEMP_e;
487 
488 typedef enum {
489   AVFS_D_G,
490   AVFS_D_COUNT,
491 } AVFS_D_e;
492 
493 
494 typedef enum {
495   UCLK_DIV_BY_1 = 0,
496   UCLK_DIV_BY_2,
497   UCLK_DIV_BY_4,
498   UCLK_DIV_BY_8,
499 } UCLK_DIV_e;
500 
501 typedef enum {
502   GPIO_INT_POLARITY_ACTIVE_LOW = 0,
503   GPIO_INT_POLARITY_ACTIVE_HIGH,
504 } GpioIntPolarity_e;
505 
506 typedef enum {
507   PWR_CONFIG_TDP = 0,
508   PWR_CONFIG_TGP,
509   PWR_CONFIG_TCP_ESTIMATED,
510   PWR_CONFIG_TCP_MEASURED,
511   PWR_CONFIG_TBP_DESKTOP,
512   PWR_CONFIG_TBP_MOBILE,
513 } PwrConfig_e;
514 
515 typedef struct {
516   uint8_t        Padding;
517   uint8_t        SnapToDiscrete;      // 0 - Fine grained DPM, 1 - Discrete DPM
518   uint8_t        NumDiscreteLevels;   // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
519   uint8_t        CalculateFopt;       // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e
520   LinearInt_t    ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
521   uint32_t       Padding3[3];
522   uint16_t       Padding4;
523   uint16_t       FoptimalDc;          //Foptimal frequency in DC power mode.
524   uint16_t       FoptimalAc;          //Foptimal frequency in AC power mode.
525   uint16_t       Padding2;
526 } DpmDescriptor_t;
527 
528 typedef enum  {
529   PPT_THROTTLER_PPT0,
530   PPT_THROTTLER_PPT1,
531   PPT_THROTTLER_PPT2,
532   PPT_THROTTLER_PPT3,
533   PPT_THROTTLER_COUNT
534 } PPT_THROTTLER_e;
535 
536 typedef enum  {
537   TEMP_EDGE,
538   TEMP_HOTSPOT,
539   TEMP_HOTSPOT_GFX,
540   TEMP_HOTSPOT_SOC,
541   TEMP_MEM,
542   TEMP_VR_GFX,
543   TEMP_VR_SOC,
544   TEMP_VR_MEM0,
545   TEMP_VR_MEM1,
546   TEMP_LIQUID0,
547   TEMP_LIQUID1,
548   TEMP_PLX,
549   TEMP_COUNT,
550 } TEMP_e;
551 
552 typedef enum {
553   TDC_THROTTLER_GFX,
554   TDC_THROTTLER_SOC,
555   TDC_THROTTLER_COUNT
556 } TDC_THROTTLER_e;
557 
558 typedef enum {
559   SVI_PLANE_VDD_GFX,
560   SVI_PLANE_VDD_SOC,
561   SVI_PLANE_VDDCI_MEM,
562   SVI_PLANE_VDDIO_MEM,
563   SVI_PLANE_COUNT,
564 } SVI_PLANE_e;
565 
566 typedef enum {
567   PMFW_VOLT_PLANE_GFX,
568   PMFW_VOLT_PLANE_SOC,
569   PMFW_VOLT_PLANE_COUNT
570 } PMFW_VOLT_PLANE_e;
571 
572 typedef enum {
573   CUSTOMER_VARIANT_ROW,
574   CUSTOMER_VARIANT_FALCON,
575   CUSTOMER_VARIANT_COUNT,
576 } CUSTOMER_VARIANT_e;
577 
578 typedef enum {
579   POWER_SOURCE_AC,
580   POWER_SOURCE_DC,
581   POWER_SOURCE_COUNT,
582 } POWER_SOURCE_e;
583 
584 typedef enum {
585   MEM_VENDOR_PLACEHOLDER0,  // 0
586   MEM_VENDOR_SAMSUNG,       // 1
587   MEM_VENDOR_INFINEON,      // 2
588   MEM_VENDOR_ELPIDA,        // 3
589   MEM_VENDOR_ETRON,         // 4
590   MEM_VENDOR_NANYA,         // 5
591   MEM_VENDOR_HYNIX,         // 6
592   MEM_VENDOR_MOSEL,         // 7
593   MEM_VENDOR_WINBOND,       // 8
594   MEM_VENDOR_ESMT,          // 9
595   MEM_VENDOR_PLACEHOLDER1,  // 10
596   MEM_VENDOR_PLACEHOLDER2,  // 11
597   MEM_VENDOR_PLACEHOLDER3,  // 12
598   MEM_VENDOR_PLACEHOLDER4,  // 13
599   MEM_VENDOR_PLACEHOLDER5,  // 14
600   MEM_VENDOR_MICRON,        // 15
601   MEM_VENDOR_COUNT,
602 } MEM_VENDOR_e;
603 
604 typedef enum {
605   PP_GRTAVFS_HW_CPO_CTL_ZONE0,
606   PP_GRTAVFS_HW_CPO_CTL_ZONE1,
607   PP_GRTAVFS_HW_CPO_CTL_ZONE2,
608   PP_GRTAVFS_HW_CPO_CTL_ZONE3,
609   PP_GRTAVFS_HW_CPO_CTL_ZONE4,
610   PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0,
611   PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0,
612   PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1,
613   PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1,
614   PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2,
615   PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2,
616   PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3,
617   PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3,
618   PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4,
619   PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4,
620   PP_GRTAVFS_HW_ZONE0_VF,
621   PP_GRTAVFS_HW_ZONE1_VF1,
622   PP_GRTAVFS_HW_ZONE2_VF2,
623   PP_GRTAVFS_HW_ZONE3_VF3,
624   PP_GRTAVFS_HW_VOLTAGE_GB,
625   PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0,
626   PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1,
627   PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2,
628   PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3,
629   PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4,
630   PP_GRTAVFS_HW_RESERVED_0,
631   PP_GRTAVFS_HW_RESERVED_1,
632   PP_GRTAVFS_HW_RESERVED_2,
633   PP_GRTAVFS_HW_RESERVED_3,
634   PP_GRTAVFS_HW_RESERVED_4,
635   PP_GRTAVFS_HW_RESERVED_5,
636   PP_GRTAVFS_HW_RESERVED_6,
637   PP_GRTAVFS_HW_FUSE_COUNT,
638 } PP_GRTAVFS_HW_FUSE_e;
639 
640 typedef enum {
641   PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0,
642   PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0,
643   PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0,
644   PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0,
645   PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0,
646   PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0,
647   PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0,
648   PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0,
649   PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0,
650   PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1,
651   PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2,
652   PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3,
653   PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4,
654   PP_GRTAVFS_FW_COMMON_FUSE_COUNT,
655 } PP_GRTAVFS_FW_COMMON_FUSE_e;
656 
657 typedef enum {
658   PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1,
659   PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0,
660   PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1,
661   PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2,
662   PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3,
663   PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4,
664   PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1,
665   PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0,
666   PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1,
667   PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2,
668   PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3,
669   PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4,
670   PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY,
671   PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY,
672   PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0,
673   PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1,
674   PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2,
675   PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3,
676   PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4,
677   PP_GRTAVFS_FW_SEP_FUSE_COUNT,
678 } PP_GRTAVFS_FW_SEP_FUSE_e;
679 
680 #define PP_NUM_RTAVFS_PWL_ZONES 5
681 #define PP_NUM_PSM_DIDT_PWL_ZONES 3
682 
683 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3
684 // Slope Q1.7, Offset Q1.2
685 typedef struct {
686   int8_t   Offset; // in Amps
687   uint8_t  Padding;
688   uint16_t MaxCurrent; // in Amps
689 } SviTelemetryScale_t;
690 
691 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1
692 
693 #define PP_OD_FEATURE_GFX_VF_CURVE_BIT       0
694 #define PP_OD_FEATURE_GFX_VMAX_BIT           1
695 #define PP_OD_FEATURE_SOC_VMAX_BIT           2
696 #define PP_OD_FEATURE_PPT_BIT                3
697 #define PP_OD_FEATURE_FAN_CURVE_BIT          4
698 #define PP_OD_FEATURE_FAN_LEGACY_BIT         5
699 #define PP_OD_FEATURE_FULL_CTRL_BIT          6
700 #define PP_OD_FEATURE_TDC_BIT                7
701 #define PP_OD_FEATURE_GFXCLK_BIT             8
702 #define PP_OD_FEATURE_UCLK_BIT               9
703 #define PP_OD_FEATURE_FCLK_BIT               10
704 #define PP_OD_FEATURE_ZERO_FAN_BIT           11
705 #define PP_OD_FEATURE_TEMPERATURE_BIT        12
706 #define PP_OD_FEATURE_EDC_BIT                13
707 #define PP_OD_FEATURE_COUNT                  14
708 
709 typedef enum {
710   PP_OD_POWER_FEATURE_ALWAYS_ENABLED,
711   PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING,
712   PP_OD_POWER_FEATURE_ALWAYS_DISABLED,
713 } PP_OD_POWER_FEATURE_e;
714 
715 typedef enum {
716   FAN_MODE_AUTO = 0,
717   FAN_MODE_MANUAL_LINEAR,
718 } FanMode_e;
719 
720 typedef enum {
721   OD_NO_ERROR,
722   OD_REQUEST_ADVANCED_NOT_SUPPORTED,
723   OD_UNSUPPORTED_FEATURE,
724   OD_INVALID_FEATURE_COMBO_ERROR,
725   OD_GFXCLK_VF_CURVE_OFFSET_ERROR,
726   OD_VDD_GFX_VMAX_ERROR,
727   OD_VDD_SOC_VMAX_ERROR,
728   OD_PPT_ERROR,
729   OD_FAN_MIN_PWM_ERROR,
730   OD_FAN_ACOUSTIC_TARGET_ERROR,
731   OD_FAN_ACOUSTIC_LIMIT_ERROR,
732   OD_FAN_TARGET_TEMP_ERROR,
733   OD_FAN_ZERO_RPM_STOP_TEMP_ERROR,
734   OD_FAN_CURVE_PWM_ERROR,
735   OD_FAN_CURVE_TEMP_ERROR,
736   OD_FULL_CTRL_GFXCLK_ERROR,
737   OD_FULL_CTRL_UCLK_ERROR,
738   OD_FULL_CTRL_FCLK_ERROR,
739   OD_FULL_CTRL_VDD_GFX_ERROR,
740   OD_FULL_CTRL_VDD_SOC_ERROR,
741   OD_TDC_ERROR,
742   OD_GFXCLK_ERROR,
743   OD_UCLK_ERROR,
744   OD_FCLK_ERROR,
745   OD_OP_TEMP_ERROR,
746   OD_OP_GFX_EDC_ERROR,
747   OD_OP_GFX_PCC_ERROR,
748   OD_POWER_FEATURE_CTRL_ERROR,
749 } OD_FAIL_e;
750 
751 typedef struct {
752   uint32_t               FeatureCtrlMask;
753 
754   //Voltage control
755   int16_t                VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
756 
757   uint16_t               VddGfxVmax;         // in mV
758   uint16_t               VddSocVmax;
759 
760   uint8_t                IdlePwrSavingFeaturesCtrl;
761   uint8_t                RuntimePwrSavingFeaturesCtrl;
762   uint16_t               Padding;
763 
764   //Frequency changes
765   int16_t                GfxclkFoffset;
766   uint16_t               Padding1;
767   uint16_t               UclkFmin;
768   uint16_t               UclkFmax;
769   uint16_t               FclkFmin;
770   uint16_t               FclkFmax;
771 
772   //PPT
773   int16_t                Ppt;         // %
774   int16_t                Tdc;
775 
776   //Fan control
777   uint8_t                FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
778   uint8_t                FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
779   uint16_t               FanMinimumPwm;
780   uint16_t               AcousticTargetRpmThreshold;
781   uint16_t               AcousticLimitRpmThreshold;
782   uint16_t               FanTargetTemperature; // Degree Celcius
783   uint8_t                FanZeroRpmEnable;
784   uint8_t                FanZeroRpmStopTemp;
785   uint8_t                FanMode;
786   uint8_t                MaxOpTemp;
787 
788   uint8_t                AdvancedOdModeEnabled;
789   uint8_t                Padding2[3];
790 
791   uint16_t               GfxVoltageFullCtrlMode;
792   uint16_t               SocVoltageFullCtrlMode;
793   uint16_t               GfxclkFullCtrlMode;
794   uint16_t               UclkFullCtrlMode;
795   uint16_t               FclkFullCtrlMode;
796   uint16_t               Padding3;
797 
798   int16_t                GfxEdc;
799   int16_t                GfxPccLimitControl;
800 
801   uint16_t               GfxclkFmaxVmax;
802   uint8_t                GfxclkFmaxVmaxTemperature;
803   uint8_t                Padding4[1];
804 
805   uint32_t               Spare[9];
806   uint32_t               MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround
807 } OverDriveTable_t;
808 
809 typedef struct {
810   OverDriveTable_t OverDriveTable;
811 
812 } OverDriveTableExternal_t;
813 
814 typedef struct {
815   uint32_t               FeatureCtrlMask;
816 
817   //Gfx Vf Curve
818   int16_t                VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS];
819   //gfx Vmax
820   uint16_t               VddGfxVmax;         // in mV
821   //soc Vmax
822   uint16_t               VddSocVmax;
823 
824   //gfxclk
825   int16_t                GfxclkFoffset;
826   uint16_t               Padding;
827   //uclk
828   uint16_t               UclkFmin;             // MHz
829   uint16_t               UclkFmax;             // MHz
830   //fclk
831   uint16_t               FclkFmin;
832   uint16_t               FclkFmax;
833 
834   //PPT
835   int16_t                Ppt;         // %
836   //TDC
837   int16_t                Tdc;
838 
839   //Fan Curve
840   uint8_t                FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
841   uint8_t                FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
842   //Fan Legacy
843   uint16_t               FanMinimumPwm;
844   uint16_t               AcousticTargetRpmThreshold;
845   uint16_t               AcousticLimitRpmThreshold;
846   uint16_t               FanTargetTemperature; // Degree Celcius
847   //zero fan
848   uint8_t                FanZeroRpmEnable;
849   //temperature
850   uint8_t                MaxOpTemp;
851   uint8_t                Padding1[2];
852 
853   //Full Ctrl
854   uint16_t               GfxVoltageFullCtrlMode;
855   uint16_t               SocVoltageFullCtrlMode;
856   uint16_t               GfxclkFullCtrlMode;
857   uint16_t               UclkFullCtrlMode;
858   uint16_t               FclkFullCtrlMode;
859   //EDC
860   int16_t                GfxEdc;
861   int16_t                GfxPccLimitControl;
862   int16_t                Padding2;
863 
864   uint32_t               Spare[5];
865 } OverDriveLimits_t;
866 
867 typedef enum {
868   BOARD_GPIO_SMUIO_0,
869   BOARD_GPIO_SMUIO_1,
870   BOARD_GPIO_SMUIO_2,
871   BOARD_GPIO_SMUIO_3,
872   BOARD_GPIO_SMUIO_4,
873   BOARD_GPIO_SMUIO_5,
874   BOARD_GPIO_SMUIO_6,
875   BOARD_GPIO_SMUIO_7,
876   BOARD_GPIO_SMUIO_8,
877   BOARD_GPIO_SMUIO_9,
878   BOARD_GPIO_SMUIO_10,
879   BOARD_GPIO_SMUIO_11,
880   BOARD_GPIO_SMUIO_12,
881   BOARD_GPIO_SMUIO_13,
882   BOARD_GPIO_SMUIO_14,
883   BOARD_GPIO_SMUIO_15,
884   BOARD_GPIO_SMUIO_16,
885   BOARD_GPIO_SMUIO_17,
886   BOARD_GPIO_SMUIO_18,
887   BOARD_GPIO_SMUIO_19,
888   BOARD_GPIO_SMUIO_20,
889   BOARD_GPIO_SMUIO_21,
890   BOARD_GPIO_SMUIO_22,
891   BOARD_GPIO_SMUIO_23,
892   BOARD_GPIO_SMUIO_24,
893   BOARD_GPIO_SMUIO_25,
894   BOARD_GPIO_SMUIO_26,
895   BOARD_GPIO_SMUIO_27,
896   BOARD_GPIO_SMUIO_28,
897   BOARD_GPIO_SMUIO_29,
898   BOARD_GPIO_SMUIO_30,
899   BOARD_GPIO_SMUIO_31,
900   MAX_BOARD_GPIO_SMUIO_NUM,
901   BOARD_GPIO_DC_GEN_A,
902   BOARD_GPIO_DC_GEN_B,
903   BOARD_GPIO_DC_GEN_C,
904   BOARD_GPIO_DC_GEN_D,
905   BOARD_GPIO_DC_GEN_E,
906   BOARD_GPIO_DC_GEN_F,
907   BOARD_GPIO_DC_GEN_G,
908   BOARD_GPIO_DC_GENLK_CLK,
909   BOARD_GPIO_DC_GENLK_VSYNC,
910   BOARD_GPIO_DC_SWAPLOCK_A,
911   BOARD_GPIO_DC_SWAPLOCK_B,
912   MAX_BOARD_DC_GPIO_NUM,
913   BOARD_GPIO_LV_EN,
914 } BOARD_GPIO_TYPE_e;
915 
916 #define INVALID_BOARD_GPIO 0xFF
917 
918 
919 typedef struct {
920   //PLL 0
921   uint16_t InitImuClk;
922   uint16_t InitSocclk;
923   uint16_t InitMpioclk;
924   uint16_t InitSmnclk;
925   //PLL 1
926   uint16_t InitDispClk;
927   uint16_t InitDppClk;
928   uint16_t InitDprefclk;
929   uint16_t InitDcfclk;
930   uint16_t InitDtbclk;
931   uint16_t InitDbguSocClk;
932   //PLL 2
933   uint16_t InitGfxclk_bypass;
934   uint16_t InitMp1clk;
935   uint16_t InitLclk;
936   uint16_t InitDbguBacoClk;
937   uint16_t InitBaco400clk;
938   uint16_t InitBaco1200clk_bypass;
939   uint16_t InitBaco700clk_bypass;
940   uint16_t InitBaco500clk;
941   // PLL 3
942   uint16_t InitDclk0;
943   uint16_t InitVclk0;
944   // PLL 4
945   uint16_t InitFclk;
946   uint16_t Padding1;
947   // PLL 5
948   //UCLK clocks, assumed all UCLK instances will be the same.
949   uint8_t InitUclkLevel;    // =0,1,2,3,4,5 frequency from FreqTableUclk
950 
951   uint8_t Padding[3];
952 
953   uint32_t InitVcoFreqPll0; //smu_socclk_t
954   uint32_t InitVcoFreqPll1; //smu_displayclk_t
955   uint32_t InitVcoFreqPll2; //smu_nbioclk_t
956   uint32_t InitVcoFreqPll3; //smu_vcnclk_t
957   uint32_t InitVcoFreqPll4; //smu_fclk_t
958   uint32_t InitVcoFreqPll5; //smu_uclk_01_t
959   uint32_t InitVcoFreqPll6; //smu_uclk_23_t
960   uint32_t InitVcoFreqPll7; //smu_uclk_45_t
961   uint32_t InitVcoFreqPll8; //smu_uclk_67_t
962 
963   //encoding will be SVI3
964   uint16_t InitGfx;       // In mV(Q2) ,  should be 0?
965   uint16_t InitSoc;       // In mV(Q2)
966   uint16_t InitVddIoMem;  // In mV(Q2) MemVdd
967   uint16_t InitVddCiMem;  // In mV(Q2) VMemP
968 
969   //uint16_t Padding2;
970 
971   uint32_t Spare[8];
972 } BootValues_t;
973 
974 typedef struct {
975    uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts
976   uint16_t Tdc[TDC_THROTTLER_COUNT];             // Amps
977 
978   uint16_t Temperature[TEMP_COUNT]; // Celsius
979 
980   uint8_t  PwmLimitMin;
981   uint8_t  PwmLimitMax;
982   uint8_t  FanTargetTemperature;
983   uint8_t  Spare1[1];
984 
985   uint16_t AcousticTargetRpmThresholdMin;
986   uint16_t AcousticTargetRpmThresholdMax;
987 
988   uint16_t AcousticLimitRpmThresholdMin;
989   uint16_t AcousticLimitRpmThresholdMax;
990 
991   uint16_t  PccLimitMin;
992   uint16_t  PccLimitMax;
993 
994   uint16_t  FanStopTempMin;
995   uint16_t  FanStopTempMax;
996   uint16_t  FanStartTempMin;
997   uint16_t  FanStartTempMax;
998 
999   uint16_t  PowerMinPpt0[POWER_SOURCE_COUNT];
1000   uint32_t  Spare[11];
1001 } MsgLimits_t;
1002 
1003 typedef struct {
1004   uint16_t BaseClockAc;
1005   uint16_t GameClockAc;
1006   uint16_t BoostClockAc;
1007   uint16_t BaseClockDc;
1008   uint16_t GameClockDc;
1009   uint16_t BoostClockDc;
1010   uint16_t MaxReportedClock;
1011   uint16_t Padding;
1012   uint32_t Reserved[3];
1013 } DriverReportedClocks_t;
1014 
1015 typedef struct {
1016   uint8_t           DcBtcEnabled;
1017   uint8_t           Padding[3];
1018 
1019   uint16_t          DcTol;            // mV Q2
1020   uint16_t          DcBtcGb;       // mV Q2
1021 
1022   uint16_t          DcBtcMin;       // mV Q2
1023   uint16_t          DcBtcMax;       // mV Q2
1024 
1025   LinearInt_t       DcBtcGbScalar;
1026 } AvfsDcBtcParams_t;
1027 
1028 typedef struct {
1029   uint16_t       AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C
1030   uint16_t      VftFMin;  // in MHz
1031   uint16_t      VInversion; // in mV Q2
1032   QuadraticInt_t qVft[AVFS_TEMP_COUNT];
1033   QuadraticInt_t qAvfsGb;
1034   QuadraticInt_t qAvfsGb2;
1035 } AvfsFuseOverride_t;
1036 
1037 //all settings maintained by PFE team
1038 typedef struct {
1039   uint8_t      Version;
1040   uint8_t      Spare8[3];
1041   // SECTION: Feature Control
1042   uint32_t     FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping
1043   // SECTION: FW DSTATE Settings
1044   uint32_t     FwDStateMask;           // See FW_DSTATE_*_BIT for mapping
1045   // SECTION: Advanced Options
1046   uint32_t     DebugOverrides;
1047 
1048   uint32_t     Spare[2];
1049 } PFE_Settings_t;
1050 
1051 typedef struct {
1052   // SECTION: Version
1053   uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different)
1054 
1055   // SECTION: Miscellaneous Configuration
1056   uint8_t      TotalPowerConfig;    // Determines how PMFW calculates the power. Use defines from PwrConfig_e
1057   uint8_t      CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e
1058   uint8_t      MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT
1059   uint8_t      SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e
1060 
1061   // SECTION: Infrastructure Limits
1062   uint8_t  SocketPowerLimitSpare[10];
1063 
1064   //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars
1065   //relative index 0
1066   uint8_t  EnableLegacyPptLimit;
1067   uint8_t  UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support
1068 
1069   uint8_t  SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting
1070 
1071   uint8_t  PaddingPpt[7];
1072 
1073   uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only
1074 
1075   uint16_t PaddingInfra;
1076 
1077   // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years)
1078   uint32_t FitControllerFailureRateLimit; //in IEEE float
1079   //Expected GFX Duty Cycle at Vmax.
1080   uint32_t FitControllerGfxDutyCycle; // in IEEE float
1081   //Expected SOC Duty Cycle at Vmax.
1082   uint32_t FitControllerSocDutyCycle; // in IEEE float
1083 
1084   //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block.
1085   uint32_t FitControllerSocOffset;  //in IEEE float
1086 
1087   uint32_t     GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value
1088 
1089   // SECTION: Throttler settings
1090   uint32_t ThrottlerControlMask;   // See THROTTLER_*_BIT for mapping
1091 
1092 
1093   // SECTION: Voltage Control Parameters
1094   uint16_t  UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE)
1095 
1096   uint8_t      Padding[2];
1097   uint16_t     DeepUlvVoltageOffsetSoc;        // In mV(Q2)  Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE
1098 
1099   // Voltage Limits
1100   uint16_t     DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled
1101   uint16_t     BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled
1102 
1103   //Vmin Optimizations
1104   int16_t         VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin
1105   int16_t         VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin
1106   uint16_t        Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT];            //In mV(Q2) Initial (pre-aging) Vset to be used at hot.
1107   uint16_t        Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT];           //In mV(Q2) Initial (pre-aging) Vset to be used at cold.
1108   uint16_t        Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT];           //In mV(Q2) End-of-life Vset to be used at hot.
1109   uint16_t        Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT];          //In mV(Q2) End-of-life Vset to be used at cold.
1110   uint16_t        Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT];      //In mV(Q2) Worst-case aging margin
1111   uint16_t        Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT];   //In mV(Q2) Platform offset apply to T0 Hot
1112   uint16_t        Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT];  //In mV(Q2) Platform offset apply to T0 Cold
1113 
1114   //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for.
1115   uint16_t        VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT];
1116   //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts.
1117   uint16_t        VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT];
1118   //Scalar coefficient of the PSM aging degradation function
1119   uint32_t        VcBtcPsmA[PMFW_VOLT_PLANE_COUNT];                   // A_PSM
1120   //Exponential coefficient of the PSM aging degradation function
1121   uint32_t        VcBtcPsmB[PMFW_VOLT_PLANE_COUNT];                   // B_PSM
1122   //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold.
1123   uint32_t        VcBtcVminA[PMFW_VOLT_PLANE_COUNT];                  // A_VMIN
1124   //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold.
1125   uint32_t        VcBtcVminB[PMFW_VOLT_PLANE_COUNT];                  // B_VMIN
1126 
1127   uint8_t         PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT];
1128   uint8_t         VcBtcEnabled[PMFW_VOLT_PLANE_COUNT];
1129 
1130   uint16_t        SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
1131   uint16_t        SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms
1132 
1133   QuadraticInt_t  Gfx_Vmin_droop;
1134   QuadraticInt_t  Soc_Vmin_droop;
1135   uint32_t        SpareVmin[6];
1136 
1137   //SECTION: DPM Configuration 1
1138   DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
1139 
1140   uint16_t      FreqTableGfx        [NUM_GFXCLK_DPM_LEVELS  ];     // In MHz
1141   uint16_t      FreqTableVclk       [NUM_VCLK_DPM_LEVELS    ];     // In MHz
1142   uint16_t      FreqTableDclk       [NUM_DCLK_DPM_LEVELS    ];     // In MHz
1143   uint16_t      FreqTableSocclk     [NUM_SOCCLK_DPM_LEVELS  ];     // In MHz
1144   uint16_t      FreqTableUclk       [NUM_UCLK_DPM_LEVELS    ];     // In MHz
1145   uint16_t      FreqTableShadowUclk [NUM_UCLK_DPM_LEVELS    ];     // In MHz
1146   uint16_t      FreqTableDispclk    [NUM_DISPCLK_DPM_LEVELS ];     // In MHz
1147   uint16_t      FreqTableDppClk     [NUM_DPPCLK_DPM_LEVELS  ];     // In MHz
1148   uint16_t      FreqTableDprefclk   [NUM_DPREFCLK_DPM_LEVELS];     // In MHz
1149   uint16_t      FreqTableDcfclk     [NUM_DCFCLK_DPM_LEVELS  ];     // In MHz
1150   uint16_t      FreqTableDtbclk     [NUM_DTBCLK_DPM_LEVELS  ];     // In MHz
1151   uint16_t      FreqTableFclk       [NUM_FCLK_DPM_LEVELS    ];     // In MHz
1152 
1153   uint32_t      DcModeMaxFreq     [PPCLK_COUNT            ];     // In MHz
1154 
1155   uint16_t      GfxclkAibFmax;
1156   uint16_t      GfxDpmPadding;
1157 
1158   //GFX Idle Power Settings
1159   uint16_t      GfxclkFgfxoffEntry;   // Entry in RLC stage (PLL), in Mhz
1160   uint16_t      GfxclkFgfxoffExitImu; // Exit/Entry in IMU stage (BYPASS), in Mhz
1161   uint16_t      GfxclkFgfxoffExitRlc; // Exit in RLC stage (PLL), in Mhz
1162   uint16_t      GfxclkThrottleClock;  //Used primarily in DCS
1163   uint8_t       EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
1164   uint8_t       GfxIdlePadding;
1165 
1166   uint8_t       SmsRepairWRCKClkDivEn;
1167   uint8_t       SmsRepairWRCKClkDivVal;
1168   uint8_t       GfxOffEntryEarlyMGCGEn;
1169   uint8_t       GfxOffEntryForceCGCGEn;
1170   uint8_t       GfxOffEntryForceCGCGDelayEn;
1171   uint8_t       GfxOffEntryForceCGCGDelayVal; // in microseconds
1172 
1173   uint16_t      GfxclkFreqGfxUlv; // in MHz
1174   uint8_t       GfxIdlePadding2[2];
1175   uint32_t      GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry
1176   uint32_t      GfxoffSpare[15];
1177 
1178   // DFLL
1179   uint16_t      DfllMstrOscConfigA; //Used for voltage sensitivity slope tuning: 0 = (en_leaker << 9) | (en_vint1_reduce << 8) | (gain_code << 6) | (bias_code << 3) | (vint1_code << 1) | en_bias
1180   uint16_t      DfllSlvOscConfigA; //Used for voltage sensitivity slope tuning: 0 = (en_leaker << 9) | (en_vint1_reduce << 8) | (gain_code << 6) | (bias_code << 3) | (vint1_code << 1) | en_bias
1181   uint32_t      DfllBtcMasterScalerM;
1182   int32_t       DfllBtcMasterScalerB;
1183   uint32_t      DfllBtcSlaveScalerM;
1184   int32_t       DfllBtcSlaveScalerB;
1185 
1186   uint32_t      DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg
1187   uint32_t      DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg
1188   uint32_t      GfxDfllSpare[9];
1189 
1190   // DVO
1191   uint32_t        DvoPsmDownThresholdVoltage; //Voltage float
1192   uint32_t        DvoPsmUpThresholdVoltage; //Voltage float
1193   uint32_t        DvoFmaxLowScaler; //Unitless float
1194 
1195   // GFX DCS
1196   uint32_t      PaddingDcs;
1197 
1198   uint16_t      DcsMinGfxOffTime;     //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
1199   uint16_t      DcsMaxGfxOffTime;      //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
1200 
1201   uint32_t      DcsMinCreditAccum;    //Min amount of positive credit accumulation before waking GFX up as part of DCS.
1202 
1203   uint16_t      DcsExitHysteresis;    //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
1204   uint16_t      DcsTimeout;           //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
1205 
1206   uint32_t      DcsPfGfxFopt;         //Default to GFX FMIN
1207   uint32_t      DcsPfUclkFopt;        //Default to UCLK FMIN
1208 
1209   uint8_t       FoptEnabled;
1210   uint8_t       DcsSpare2[3];
1211   uint32_t      DcsFoptM;             //Tuning paramters to shift Fopt calculation, IEEE754 float
1212   uint32_t      DcsFoptB;             //Tuning paramters to shift Fopt calculation, IEEE754 float
1213   uint32_t      DcsSpare[9];
1214 
1215   // UCLK section
1216   uint8_t       UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations
1217   uint8_t       PaddingMem[3];
1218 
1219   uint8_t       UclkDpmPstates             [NUM_UCLK_DPM_LEVELS];     // 6 Primary SW DPM states (6 + 6 Shadow)
1220   uint8_t       UclkDpmShadowPstates       [NUM_UCLK_DPM_LEVELS];      // 6 Shadow SW DPM states (6 + 6 Shadow)
1221   uint8_t       FreqTableUclkDiv           [NUM_UCLK_DPM_LEVELS];     // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
1222   uint8_t       FreqTableShadowUclkDiv     [NUM_UCLK_DPM_LEVELS];     // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
1223   uint16_t      MemVmempVoltage            [NUM_UCLK_DPM_LEVELS];     // mV(Q2)
1224   uint16_t      MemVddioVoltage            [NUM_UCLK_DPM_LEVELS];     // mV(Q2)
1225   uint16_t      DalDcModeMaxUclkFreq;
1226   uint8_t       PaddingsMem[2];
1227   //FCLK Section
1228   uint32_t      PaddingFclk;
1229 
1230   // Link DPM Settings
1231   uint8_t       PcieGenSpeed[NUM_LINK_LEVELS];           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 4:PciE-gen5
1232   uint8_t       PcieLaneCount[NUM_LINK_LEVELS];          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
1233   uint16_t      LclkFreq[NUM_LINK_LEVELS];
1234 
1235   // SECTION: VDD_GFX AVFS
1236   uint8_t       OverrideGfxAvfsFuses;
1237   uint8_t       GfxAvfsPadding[1];
1238   uint16_t      DroopGBStDev;
1239 
1240   uint32_t      SocHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT];   //new added for Soc domain
1241   uint32_t      GfxL2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding
1242   //uint32_t      GfxSeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT];
1243 
1244   uint16_t      PsmDidt_Vcross[PP_NUM_PSM_DIDT_PWL_ZONES-1];
1245   uint32_t      PsmDidt_StaticDroop_A[PP_NUM_PSM_DIDT_PWL_ZONES];
1246   uint32_t      PsmDidt_StaticDroop_B[PP_NUM_PSM_DIDT_PWL_ZONES];
1247   uint32_t      PsmDidt_DynDroop_A[PP_NUM_PSM_DIDT_PWL_ZONES];
1248   uint32_t      PsmDidt_DynDroop_B[PP_NUM_PSM_DIDT_PWL_ZONES];
1249   uint32_t      spare_HwRtAvfsFuses[19];
1250 
1251   uint32_t      SocCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];
1252   uint32_t      GfxCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT];
1253 
1254   uint32_t      SocFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1255   uint32_t      GfxL2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1256   //uint32_t      GfxSeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1257   uint32_t      spare_FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT];
1258 
1259   uint32_t      Soc_Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];
1260   uint32_t      Soc_Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];
1261   uint32_t      Soc_Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];
1262   uint32_t      Soc_Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];
1263 
1264   uint32_t      Gfx_Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES];
1265   uint32_t      Gfx_Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES];
1266   uint32_t      Gfx_Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES];
1267   uint32_t      Gfx_Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES];
1268 
1269   uint32_t      Gfx_Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];
1270   uint32_t      Soc_Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES];
1271 
1272   uint32_t      dGbV_dT_vmin;
1273   uint32_t      dGbV_dT_vmax;
1274 
1275   uint32_t      PaddingV2F[4];
1276 
1277   AvfsDcBtcParams_t DcBtcGfxParams;
1278   QuadraticInt_t    SSCurve_GFX;
1279   uint32_t   GfxAvfsSpare[29];
1280 
1281   //SECTION: VDD_SOC AVFS
1282   uint8_t      OverrideSocAvfsFuses;
1283   uint8_t      MinSocAvfsRevision;
1284   uint8_t      SocAvfsPadding[2];
1285 
1286   AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT];
1287 
1288   DroopInt_t        dBtcGbSoc[AVFS_D_COUNT];            // GHz->V BtcGb
1289 
1290   LinearInt_t       qAgingGb[AVFS_D_COUNT];          // GHz->V
1291 
1292   QuadraticInt_t    qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V
1293 
1294   AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT];
1295 
1296   QuadraticInt_t    SSCurve_SOC;
1297   uint32_t   SocAvfsSpare[29];
1298 
1299   //SECTION: Boot clock and voltage values
1300   BootValues_t BootValues;
1301 
1302   //SECTION: Driver Reported Clocks
1303   DriverReportedClocks_t DriverReportedClocks;
1304 
1305   //SECTION: Message Limits
1306   MsgLimits_t MsgLimits;
1307 
1308   //SECTION: OverDrive Limits
1309   OverDriveLimits_t OverDriveLimitsBasicMin;
1310   OverDriveLimits_t OverDriveLimitsBasicMax;
1311   OverDriveLimits_t OverDriveLimitsAdvancedMin;
1312   OverDriveLimits_t OverDriveLimitsAdvancedMax;
1313 
1314   // Section: Total Board Power idle vs active coefficients
1315   uint8_t     TotalBoardPowerSupport;
1316   uint8_t     TotalBoardPowerPadding[1];
1317   uint16_t    TotalBoardPowerRoc;
1318 
1319   //PMFW-11158
1320   QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT];
1321   QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT];
1322   QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT];
1323 
1324   // APT GFX to UCLK mapping
1325   int32_t     AptUclkGfxclkLookup[POWER_SOURCE_COUNT][6];
1326   uint32_t    AptUclkGfxclkLookupHyst[POWER_SOURCE_COUNT][6];
1327   uint32_t    AptPadding;
1328 
1329   // Xvmin didt
1330   QuadraticInt_t  GfxXvminDidtDroopThresh;
1331   uint32_t        GfxXvminDidtResetDDWait;
1332   uint32_t        GfxXvminDidtClkStopWait;
1333   uint32_t        GfxXvminDidtFcsStepCtrl;
1334   uint32_t        GfxXvminDidtFcsWaitCtrl;
1335 
1336   // PSM based didt controller
1337   uint32_t        PsmModeEnabled; //0: all disabled 1: static mode only 2: dynamic mode only 3:static + dynamic mode
1338   uint32_t        P2v_a; // floating point in U32 format
1339   uint32_t        P2v_b;
1340   uint32_t        P2v_c;
1341   uint32_t        T2p_a;
1342   uint32_t        T2p_b;
1343   uint32_t        T2p_c;
1344   uint32_t        P2vTemp;
1345   QuadraticInt_t  PsmDidtStaticSettings;
1346   QuadraticInt_t  PsmDidtDynamicSettings;
1347   uint8_t         PsmDidtAvgDiv;
1348   uint8_t         PsmDidtForceStall;
1349   uint16_t        PsmDidtReleaseTimer;
1350   uint32_t        PsmDidtStallPattern; //Will be written to both pattern 1 and didt_static_level_prog
1351   // CAC EDC
1352   uint32_t        CacEdcCacLeakageC0;
1353   uint32_t        CacEdcCacLeakageC1;
1354   uint32_t        CacEdcCacLeakageC2;
1355   uint32_t        CacEdcCacLeakageC3;
1356   uint32_t        CacEdcCacLeakageC4;
1357   uint32_t        CacEdcCacLeakageC5;
1358   uint32_t        CacEdcGfxClkScalar;
1359   uint32_t        CacEdcGfxClkIntercept;
1360   uint32_t        CacEdcCac_m;
1361   uint32_t        CacEdcCac_b;
1362   uint32_t        CacEdcCurrLimitGuardband;
1363   uint32_t        CacEdcDynToTotalCacRatio;
1364   // GFX EDC XVMIN
1365   uint32_t        XVmin_Gfx_EdcThreshScalar;
1366   uint32_t        XVmin_Gfx_EdcEnableFreq;
1367   uint32_t        XVmin_Gfx_EdcPccAsStepCtrl;
1368   uint32_t        XVmin_Gfx_EdcPccAsWaitCtrl;
1369   uint16_t        XVmin_Gfx_EdcThreshold;
1370   uint16_t        XVmin_Gfx_EdcFiltHysWaitCtrl;
1371   // SOC EDC XVMIN
1372   uint32_t        XVmin_Soc_EdcThreshScalar;
1373   uint32_t        XVmin_Soc_EdcEnableFreq;
1374   uint32_t        XVmin_Soc_EdcThreshold; // LPF: number of cycles Xvmin_trig_filt will react.
1375   uint16_t        XVmin_Soc_EdcStepUpTime; // 10 bit, refclk count to step up throttle when PCC remains asserted.
1376   uint16_t        XVmin_Soc_EdcStepDownTime;// 10 bit, refclk count to step down throttle when PCC remains asserted.
1377   uint8_t         XVmin_Soc_EdcInitPccStep; // 3 bit, First Pcc Step number that will applied when PCC asserts.
1378   uint8_t         PaddingSocEdc[3];
1379 
1380   // Fuse Override for SOC and GFX XVMIN
1381   uint8_t         GfxXvminFuseOverride;
1382   uint8_t         SocXvminFuseOverride;
1383   uint8_t         PaddingXvminFuseOverride[2];
1384   uint8_t         GfxXvminFddTempLow;  // bit 7: sign, bit 0-6: ABS value
1385   uint8_t         GfxXvminFddTempHigh; // bit 7: sign, bit 0-6: ABS value
1386   uint8_t         SocXvminFddTempLow;  // bit 7: sign, bit 0-6: ABS value
1387   uint8_t         SocXvminFddTempHigh; // bit 7: sign, bit 0-6: ABS value
1388 
1389 
1390   uint16_t        GfxXvminFddVolt0;    // low voltage, in VID
1391   uint16_t        GfxXvminFddVolt1;    // mid voltage, in VID
1392   uint16_t        GfxXvminFddVolt2;    // high voltage, in VID
1393   uint16_t        SocXvminFddVolt0;    // low voltage, in VID
1394   uint16_t        SocXvminFddVolt1;    // mid voltage, in VID
1395   uint16_t        SocXvminFddVolt2;    // high voltage, in VID
1396   uint16_t        GfxXvminDsFddDsm[6]; // XVMIN DS, same organization with fuse
1397   uint16_t        GfxXvminEdcFddDsm[6];// XVMIN GFX EDC, same organization with fuse
1398   uint16_t        SocXvminEdcFddDsm[6];// XVMIN SOC EDC, same organization with fuse
1399 
1400   // SECTION: Sku Reserved
1401   uint32_t        Spare;
1402 
1403   // Padding for MMHUB - do not modify this
1404   uint32_t     MmHubPadding[8];
1405 } SkuTable_t;
1406 
1407 typedef struct {
1408   uint8_t SlewRateConditions;
1409   uint8_t LoadLineAdjust;
1410   uint8_t VoutOffset;
1411   uint8_t VidMax;
1412   uint8_t VidMin;
1413   uint8_t TenBitTelEn;
1414   uint8_t SixteenBitTelEn;
1415   uint8_t OcpThresh;
1416   uint8_t OcpWarnThresh;
1417   uint8_t OcpSettings;
1418   uint8_t VrhotThresh;
1419   uint8_t OtpThresh;
1420   uint8_t UvpOvpDeltaRef;
1421   uint8_t PhaseShed;
1422   uint8_t Padding[10];
1423   uint32_t SettingOverrideMask;
1424 } Svi3RegulatorSettings_t;
1425 
1426 typedef struct {
1427   // SECTION: Version
1428   uint32_t    Version; //should be unique to each board type
1429 
1430   // SECTION: I2C Control
1431   I2cControllerConfig_t  I2cControllers[NUM_I2C_CONTROLLERS];
1432 
1433   //SECTION SVI3 Board Parameters
1434   uint8_t      SlaveAddrMapping[SVI_PLANE_COUNT];
1435   uint8_t      VrPsiSupport[SVI_PLANE_COUNT];
1436 
1437   uint32_t     Svi3SvcSpeed;
1438   uint8_t      EnablePsi6[SVI_PLANE_COUNT];       // only applicable in SVI3
1439 
1440   // SECTION: Voltage Regulator Settings
1441   Svi3RegulatorSettings_t  Svi3RegSettings[SVI_PLANE_COUNT];
1442 
1443   // SECTION: GPIO Settings
1444   uint8_t      LedOffGpio;
1445   uint8_t      FanOffGpio;
1446   uint8_t      GfxVrPowerStageOffGpio;
1447 
1448   uint8_t      AcDcGpio;        // GPIO pin configured for AC/DC switching
1449   uint8_t      AcDcPolarity;    // GPIO polarity for AC/DC switching
1450   uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
1451   uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
1452 
1453   uint8_t      GthrGpio;        // GPIO pin configured for GTHR Event
1454   uint8_t      GthrPolarity;    // replace GPIO polarity for GTHR
1455 
1456   // LED Display Settings
1457   uint8_t      LedPin0;         // GPIO number for LedPin[0]
1458   uint8_t      LedPin1;         // GPIO number for LedPin[1]
1459   uint8_t      LedPin2;         // GPIO number for LedPin[2]
1460   uint8_t      LedEnableMask;
1461 
1462   uint8_t      LedPcie;        // GPIO number for PCIE results
1463   uint8_t      LedError;       // GPIO number for Error Cases
1464   uint8_t      PaddingLed;
1465 
1466   // SECTION: Clock Spread Spectrum
1467 
1468   // UCLK Spread Spectrum
1469   uint8_t      UclkTrainingModeSpreadPercent; // Q4.4
1470   uint8_t      UclkSpreadPadding;
1471   uint16_t     UclkSpreadFreq;      // kHz
1472 
1473   // UCLK Spread Spectrum
1474   uint8_t      UclkSpreadPercent[MEM_VENDOR_COUNT];
1475 
1476   // DFLL Spread Spectrum
1477   uint8_t      GfxclkSpreadEnable;
1478 
1479   // FCLK Spread Spectrum
1480   uint8_t      FclkSpreadPercent;   // Q4.4
1481   uint16_t     FclkSpreadFreq;      // kHz
1482 
1483   // Section: Memory Config
1484   uint8_t      DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e
1485   uint8_t      PaddingMem1[7];
1486 
1487   // SECTION: UMC feature flags
1488   uint8_t      HsrEnabled;
1489   uint8_t      VddqOffEnabled;
1490   uint8_t      PaddingUmcFlags[2];
1491 
1492   uint32_t    Paddign1;
1493   uint32_t    BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS
1494 
1495   uint8_t     FuseWritePowerMuxPresent;
1496   uint8_t     FuseWritePadding[3];
1497 
1498   // SECTION: EDC Params
1499   uint32_t    LoadlineGfx;
1500   uint32_t    LoadlineSoc;
1501   uint32_t    GfxEdcLimit;
1502   uint32_t    SocEdcLimit;
1503 
1504   uint32_t    RestBoardPower;         //power consumed by board that is not captured by the SVI3 input telemetry
1505   uint32_t    ConnectorsImpedance;   // impedance of the input ATX power connectors
1506 
1507   uint8_t      EpcsSens0;       //GPIO number for External Power Connector Support Sense0
1508   uint8_t      EpcsSens1;       //GPIO Number for External Power Connector Support Sense1
1509   uint8_t      PaddingEpcs[2];
1510 
1511   // SECTION: Board Reserved
1512   uint32_t    BoardSpare[52];
1513 
1514   // SECTION: Structure Padding
1515 
1516   // Padding for MMHUB - do not modify this
1517   uint32_t     MmHubPadding[8];
1518 } BoardTable_t;
1519 
1520 typedef struct {
1521   // SECTION: Infrastructure Limits
1522   uint16_t    SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported
1523 
1524   uint16_t    VrTdcLimit[TDC_THROTTLER_COUNT];         // In Amperes. Current limit associated with VR regulator maximum temperature
1525 
1526   int16_t     TotalIdleBoardPowerM;
1527   int16_t     TotalIdleBoardPowerB;
1528   int16_t     TotalBoardPowerM;
1529   int16_t     TotalBoardPowerB;
1530 
1531   uint16_t    TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input
1532 
1533   // SECTION: Fan Control
1534   uint16_t    FanStopTemp[TEMP_COUNT];          //Celsius
1535   uint16_t    FanStartTemp[TEMP_COUNT];         //Celsius
1536 
1537   uint16_t    FanGain[TEMP_COUNT];
1538 
1539   uint16_t    FanPwmMin;
1540   uint16_t    AcousticTargetRpmThreshold;
1541   uint16_t    AcousticLimitRpmThreshold;
1542   uint16_t    FanMaximumRpm;
1543   uint16_t    MGpuAcousticLimitRpmThreshold;
1544   uint16_t    FanTargetGfxclk;
1545   uint32_t    TempInputSelectMask;
1546   uint8_t     FanZeroRpmEnable;
1547   uint8_t     FanTachEdgePerRev;
1548   uint16_t    FanPadding;
1549   uint16_t    FanTargetTemperature[TEMP_COUNT];
1550 
1551   // The following are AFC override parameters. Leave at 0 to use FW defaults.
1552   int16_t     FuzzyFan_ErrorSetDelta;
1553   int16_t     FuzzyFan_ErrorRateSetDelta;
1554   int16_t     FuzzyFan_PwmSetDelta;
1555   uint16_t    FanPadding2;
1556 
1557   uint16_t    FwCtfLimit[TEMP_COUNT];
1558 
1559   uint16_t    IntakeTempEnableRPM;
1560   int16_t     IntakeTempOffsetTemp;
1561   uint16_t    IntakeTempReleaseTemp;
1562   uint16_t    IntakeTempHighIntakeAcousticLimit;
1563 
1564   uint16_t    IntakeTempAcouticLimitReleaseRate;
1565   int16_t     FanAbnormalTempLimitOffset;    // FanStalledTempLimitOffset
1566   uint16_t    FanStalledTriggerRpm;          //
1567   uint16_t    FanAbnormalTriggerRpmCoeff;    // FanAbnormalTriggerRpm
1568 
1569   uint16_t    FanSpare[1];
1570   uint8_t     FanIntakeSensorSupport;
1571   uint8_t     FanIntakePadding;
1572   uint32_t    FanSpare2[12];
1573 
1574   uint32_t ODFeatureCtrlMask;
1575 
1576   uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix
1577   uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron
1578   uint16_t TemperatureFwCtfLimit_Hynix;
1579   uint16_t TemperatureFwCtfLimit_Micron;
1580 
1581   // SECTION: Board Reserved
1582   uint16_t    PlatformTdcLimit[TDC_THROTTLER_COUNT];             // In Amperes. Current limit associated with platform maximum temperature per VR current rail
1583   uint16_t    SocketPowerLimitDc[PPT_THROTTLER_COUNT];  // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported
1584   uint16_t    SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift
1585   uint16_t    CustomSkuSpare16b;
1586   uint32_t    CustomSkuSpare32b[10];
1587 
1588   // SECTION: Structure Padding
1589 
1590   // Padding for MMHUB - do not modify this
1591   uint32_t    MmHubPadding[8];
1592 } CustomSkuTable_t;
1593 
1594 typedef struct {
1595   PFE_Settings_t PFE_Settings;
1596   SkuTable_t SkuTable;
1597   CustomSkuTable_t CustomSkuTable;
1598   BoardTable_t BoardTable;
1599 } PPTable_t;
1600 
1601 typedef struct {
1602   // Time constant parameters for clock averages in ms
1603   uint16_t     GfxclkAverageLpfTau;
1604   uint16_t     FclkAverageLpfTau;
1605   uint16_t     UclkAverageLpfTau;
1606   uint16_t     GfxActivityLpfTau;
1607   uint16_t     UclkActivityLpfTau;
1608   uint16_t     UclkMaxActivityLpfTau;
1609   uint16_t     SocketPowerLpfTau;
1610   uint16_t     VcnClkAverageLpfTau;
1611   uint16_t     VcnUsageAverageLpfTau;
1612   uint16_t     PcieActivityLpTau;
1613 } DriverSmuConfig_t;
1614 
1615 typedef struct {
1616   DriverSmuConfig_t DriverSmuConfig;
1617 
1618   uint32_t     Spare[8];
1619   // Padding - ignore
1620   uint32_t     MmHubPadding[8]; // SMU internal use
1621 } DriverSmuConfigExternal_t;
1622 
1623 
1624 typedef struct {
1625 
1626   uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];     // In MHz
1627   uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];     // In MHz
1628   uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];     // In MHz
1629   uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];     // In MHz
1630   uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];     // In MHz
1631   uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];     // In MHz
1632   uint16_t       FreqTableDppClk   [NUM_DPPCLK_DPM_LEVELS  ];     // In MHz
1633   uint16_t       FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS];     // In MHz
1634   uint16_t       FreqTableDcfclk   [NUM_DCFCLK_DPM_LEVELS  ];     // In MHz
1635   uint16_t       FreqTableDtbclk   [NUM_DTBCLK_DPM_LEVELS  ];     // In MHz
1636   uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];     // In MHz
1637 
1638   uint16_t       DcModeMaxFreq     [PPCLK_COUNT            ];     // In MHz
1639 
1640   uint16_t       Padding;
1641 
1642   uint32_t Spare[32];
1643 
1644   // Padding - ignore
1645   uint32_t     MmHubPadding[8]; // SMU internal use
1646 
1647 } DriverInfoTable_t;
1648 
1649 typedef struct {
1650   uint32_t CurrClock[PPCLK_COUNT];
1651 
1652   uint16_t AverageGfxclkFrequencyTarget;
1653   uint16_t AverageGfxclkFrequencyPreDs;
1654   uint16_t AverageGfxclkFrequencyPostDs;
1655   uint16_t AverageFclkFrequencyPreDs;
1656   uint16_t AverageFclkFrequencyPostDs;
1657   uint16_t AverageMemclkFrequencyPreDs  ; // this is scaled to actual memory clock
1658   uint16_t AverageMemclkFrequencyPostDs  ; // this is scaled to actual memory clock
1659   uint16_t AverageVclk0Frequency  ;
1660   uint16_t AverageDclk0Frequency  ;
1661   uint16_t AverageVclk1Frequency  ;
1662   uint16_t AverageDclk1Frequency  ;
1663   uint16_t AveragePCIeBusy        ;
1664   uint16_t dGPU_W_MAX             ;
1665   uint16_t padding                ;
1666 
1667   uint16_t MovingAverageGfxclkFrequencyTarget;
1668   uint16_t MovingAverageGfxclkFrequencyPreDs;
1669   uint16_t MovingAverageGfxclkFrequencyPostDs;
1670   uint16_t MovingAverageFclkFrequencyPreDs;
1671   uint16_t MovingAverageFclkFrequencyPostDs;
1672   uint16_t MovingAverageMemclkFrequencyPreDs;
1673   uint16_t MovingAverageMemclkFrequencyPostDs;
1674   uint16_t MovingAverageVclk0Frequency;
1675   uint16_t MovingAverageDclk0Frequency;
1676   uint16_t MovingAverageGfxActivity;
1677   uint16_t MovingAverageUclkActivity;
1678   uint16_t MovingAverageVcn0ActivityPercentage;
1679   uint16_t MovingAveragePCIeBusy;
1680   uint16_t MovingAverageUclkActivity_MAX;
1681   uint16_t MovingAverageSocketPower;
1682   uint16_t MovingAveragePadding;
1683 
1684   uint32_t MetricsCounter         ;
1685 
1686   uint16_t AvgVoltage[SVI_PLANE_COUNT];
1687   uint16_t AvgCurrent[SVI_PLANE_COUNT];
1688 
1689   uint16_t AverageGfxActivity    ;
1690   uint16_t AverageUclkActivity   ;
1691   uint16_t AverageVcn0ActivityPercentage;
1692   uint16_t Vcn1ActivityPercentage  ;
1693 
1694   uint32_t EnergyAccumulator;
1695   uint16_t AverageSocketPower;
1696   uint16_t AverageTotalBoardPower;
1697 
1698   uint16_t AvgTemperature[TEMP_COUNT];
1699   uint16_t AvgTemperatureFanIntake;
1700 
1701   uint8_t  PcieRate               ;
1702   uint8_t  PcieWidth              ;
1703 
1704   uint8_t  AvgFanPwm;
1705   uint8_t  Padding[1];
1706   uint16_t AvgFanRpm;
1707 
1708 
1709   uint8_t  ThrottlingPercentage[THROTTLER_COUNT];
1710   uint8_t  VmaxThrottlingPercentage;
1711   uint8_t  padding1[2];
1712 
1713   //metrics for D3hot entry/exit and driver ARM msgs
1714   uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
1715   uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
1716   uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
1717 
1718   uint16_t ApuSTAPMSmartShiftLimit;
1719   uint16_t ApuSTAPMLimit;
1720   uint16_t AvgApuSocketPower;
1721 
1722   uint16_t AverageUclkActivity_MAX;
1723 
1724   uint32_t PublicSerialNumberLower;
1725   uint32_t PublicSerialNumberUpper;
1726 
1727 } SmuMetrics_t;
1728 
1729 typedef struct {
1730   SmuMetrics_t SmuMetrics;
1731   uint32_t Spare[30];
1732 
1733   // Padding - ignore
1734   uint32_t     MmHubPadding[8]; // SMU internal use
1735 } SmuMetricsExternal_t;
1736 
1737 typedef struct {
1738   uint8_t  WmSetting;
1739   uint8_t  Flags;
1740   uint8_t  Padding[2];
1741 
1742 } WatermarkRowGeneric_t;
1743 
1744 #define NUM_WM_RANGES 4
1745 
1746 typedef enum {
1747   WATERMARKS_CLOCK_RANGE = 0,
1748   WATERMARKS_DUMMY_PSTATE,
1749   WATERMARKS_MALL,
1750   WATERMARKS_COUNT,
1751 } WATERMARKS_FLAGS_e;
1752 
1753 typedef struct {
1754   // Watermarks
1755   WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
1756 } Watermarks_t;
1757 
1758 typedef struct {
1759   Watermarks_t Watermarks;
1760   uint32_t  Spare[16];
1761 
1762   uint32_t     MmHubPadding[8]; // SMU internal use
1763 } WatermarksExternal_t;
1764 
1765 typedef struct {
1766   uint16_t avgPsmCount[76];
1767   uint16_t minPsmCount[76];
1768   uint16_t maxPsmCount[76];
1769   float    avgPsmVoltage[76];
1770   float    minPsmVoltage[76];
1771   float    maxPsmVoltage[76];
1772 } AvfsDebugTable_t;
1773 
1774 typedef struct {
1775   AvfsDebugTable_t AvfsDebugTable;
1776 
1777   uint32_t     MmHubPadding[8]; // SMU internal use
1778 } AvfsDebugTableExternal_t;
1779 
1780 
1781 typedef struct {
1782   uint8_t   Gfx_ActiveHystLimit;
1783   uint8_t   Gfx_IdleHystLimit;
1784   uint8_t   Gfx_FPS;
1785   uint8_t   Gfx_MinActiveFreqType;
1786   uint8_t   Gfx_BoosterFreqType;
1787   uint8_t   PaddingGfx;
1788   uint16_t  Gfx_MinActiveFreq;              // MHz
1789   uint16_t  Gfx_BoosterFreq;                // MHz
1790   uint16_t  Gfx_PD_Data_time_constant;      // Time constant of PD controller in ms
1791   uint32_t  Gfx_PD_Data_limit_a;            // Q16
1792   uint32_t  Gfx_PD_Data_limit_b;            // Q16
1793   uint32_t  Gfx_PD_Data_limit_c;            // Q16
1794   uint32_t  Gfx_PD_Data_error_coeff;        // Q16
1795   uint32_t  Gfx_PD_Data_error_rate_coeff;   // Q16
1796 
1797   uint8_t   Fclk_ActiveHystLimit;
1798   uint8_t   Fclk_IdleHystLimit;
1799   uint8_t   Fclk_FPS;
1800   uint8_t   Fclk_MinActiveFreqType;
1801   uint8_t   Fclk_BoosterFreqType;
1802   uint8_t   PaddingFclk;
1803   uint16_t  Fclk_MinActiveFreq;              // MHz
1804   uint16_t  Fclk_BoosterFreq;                // MHz
1805   uint16_t  Fclk_PD_Data_time_constant;      // Time constant of PD controller in ms
1806   uint32_t  Fclk_PD_Data_limit_a;            // Q16
1807   uint32_t  Fclk_PD_Data_limit_b;            // Q16
1808   uint32_t  Fclk_PD_Data_limit_c;            // Q16
1809   uint32_t  Fclk_PD_Data_error_coeff;        // Q16
1810   uint32_t  Fclk_PD_Data_error_rate_coeff;   // Q16
1811 
1812   uint32_t  Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS];          // Q16
1813   uint8_t   Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];
1814   uint16_t  Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];
1815   uint16_t  Mem_Fps;
1816 
1817 } DpmActivityMonitorCoeffInt_t;
1818 
1819 
1820 typedef struct {
1821   DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt;
1822   uint32_t     MmHubPadding[8]; // SMU internal use
1823 } DpmActivityMonitorCoeffIntExternal_t;
1824 
1825 
1826 
1827 // Workload bits
1828 #define WORKLOAD_PPLIB_DEFAULT_BIT        0
1829 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
1830 #define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
1831 #define WORKLOAD_PPLIB_VIDEO_BIT          3
1832 #define WORKLOAD_PPLIB_VR_BIT             4
1833 #define WORKLOAD_PPLIB_COMPUTE_BIT        5
1834 #define WORKLOAD_PPLIB_CUSTOM_BIT         6
1835 #define WORKLOAD_PPLIB_WINDOW_3D_BIT      7
1836 #define WORKLOAD_PPLIB_DIRECT_ML_BIT      8
1837 #define WORKLOAD_PPLIB_CGVDI_BIT          9
1838 #define WORKLOAD_PPLIB_COUNT              10
1839 
1840 
1841 // These defines are used with the following messages:
1842 // SMC_MSG_TransferTableDram2Smu
1843 // SMC_MSG_TransferTableSmu2Dram
1844 
1845 // Table transfer status
1846 #define TABLE_TRANSFER_OK         0x0
1847 #define TABLE_TRANSFER_FAILED     0xFF
1848 #define TABLE_TRANSFER_PENDING    0xAB
1849 
1850 #define TABLE_PPT_FAILED                          0x100
1851 #define TABLE_TDC_FAILED                          0x200
1852 #define TABLE_TEMP_FAILED                         0x400
1853 #define TABLE_FAN_TARGET_TEMP_FAILED              0x800
1854 #define TABLE_FAN_STOP_TEMP_FAILED               0x1000
1855 #define TABLE_FAN_START_TEMP_FAILED              0x2000
1856 #define TABLE_FAN_PWM_MIN_FAILED                 0x4000
1857 #define TABLE_ACOUSTIC_TARGET_RPM_FAILED         0x8000
1858 #define TABLE_ACOUSTIC_LIMIT_RPM_FAILED         0x10000
1859 #define TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED   0x20000
1860 
1861 // Table types
1862 #define TABLE_PPTABLE            0
1863 #define TABLE_COMBO_PPTABLE           1
1864 #define TABLE_WATERMARKS              2
1865 #define TABLE_AVFS_PSM_DEBUG          3
1866 #define TABLE_PMSTATUSLOG             4
1867 #define TABLE_SMU_METRICS             5
1868 #define TABLE_DRIVER_SMU_CONFIG       6
1869 #define TABLE_ACTIVITY_MONITOR_COEFF  7
1870 #define TABLE_OVERDRIVE               8
1871 #define TABLE_I2C_COMMANDS            9
1872 #define TABLE_DRIVER_INFO             10
1873 #define TABLE_ECCINFO                 11
1874 #define TABLE_CUSTOM_SKUTABLE         12
1875 #define TABLE_COUNT                   13
1876 
1877 //IH Interupt ID
1878 #define IH_INTERRUPT_ID_TO_DRIVER                   0xFE
1879 #define IH_INTERRUPT_CONTEXT_ID_BACO                0x2
1880 #define IH_INTERRUPT_CONTEXT_ID_AC                  0x3
1881 #define IH_INTERRUPT_CONTEXT_ID_DC                  0x4
1882 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0            0x5
1883 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3            0x6
1884 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING  0x7
1885 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL        0x8
1886 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY        0x9
1887 #define IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE       0xA
1888 
1889 #endif
1890