1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright 2019 NXP
4 //
5 // Author: Daniel Baluta <daniel.baluta@nxp.com>
6 //
7 // Hardware interface for audio DSP on i.MX8
8
9 #include <linux/firmware.h>
10 #include <linux/of_platform.h>
11 #include <linux/of_address.h>
12 #include <linux/of_irq.h>
13 #include <linux/pm_domain.h>
14
15 #include <linux/module.h>
16 #include <sound/sof.h>
17 #include <sound/sof/xtensa.h>
18 #include <linux/firmware/imx/ipc.h>
19 #include <linux/firmware/imx/dsp.h>
20
21 #include <linux/firmware/imx/svc/misc.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
23 #include "../ops.h"
24 #include "../sof-of-dev.h"
25 #include "imx-common.h"
26
27 /* DSP memories */
28 #define IRAM_OFFSET 0x10000
29 #define IRAM_SIZE (2 * 1024)
30 #define DRAM0_OFFSET 0x0
31 #define DRAM0_SIZE (32 * 1024)
32 #define DRAM1_OFFSET 0x8000
33 #define DRAM1_SIZE (32 * 1024)
34 #define SYSRAM_OFFSET 0x18000
35 #define SYSRAM_SIZE (256 * 1024)
36 #define SYSROM_OFFSET 0x58000
37 #define SYSROM_SIZE (192 * 1024)
38
39 #define RESET_VECTOR_VADDR 0x596f8000
40
41 #define MBOX_OFFSET 0x800000
42 #define MBOX_SIZE 0x1000
43
44 struct imx8_priv {
45 struct device *dev;
46 struct snd_sof_dev *sdev;
47
48 /* DSP IPC handler */
49 struct imx_dsp_ipc *dsp_ipc;
50 struct platform_device *ipc_dev;
51
52 /* System Controller IPC handler */
53 struct imx_sc_ipc *sc_ipc;
54
55 /* Power domain handling */
56 int num_domains;
57 struct device **pd_dev;
58 struct device_link **link;
59
60 struct clk_bulk_data *clks;
61 int clk_num;
62 };
63
imx8_get_mailbox_offset(struct snd_sof_dev * sdev)64 static int imx8_get_mailbox_offset(struct snd_sof_dev *sdev)
65 {
66 return MBOX_OFFSET;
67 }
68
imx8_get_window_offset(struct snd_sof_dev * sdev,u32 id)69 static int imx8_get_window_offset(struct snd_sof_dev *sdev, u32 id)
70 {
71 return MBOX_OFFSET;
72 }
73
imx8_dsp_handle_reply(struct imx_dsp_ipc * ipc)74 static void imx8_dsp_handle_reply(struct imx_dsp_ipc *ipc)
75 {
76 struct imx8_priv *priv = imx_dsp_get_data(ipc);
77 unsigned long flags;
78
79 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
80 snd_sof_ipc_process_reply(priv->sdev, 0);
81 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
82 }
83
imx8_dsp_handle_request(struct imx_dsp_ipc * ipc)84 static void imx8_dsp_handle_request(struct imx_dsp_ipc *ipc)
85 {
86 struct imx8_priv *priv = imx_dsp_get_data(ipc);
87 u32 p; /* panic code */
88
89 /* Read the message from the debug box. */
90 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p));
91
92 /* Check to see if the message is a panic code (0x0dead***) */
93 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC)
94 snd_sof_dsp_panic(priv->sdev, p, true);
95 else
96 snd_sof_ipc_msgs_rx(priv->sdev);
97 }
98
99 static struct imx_dsp_ops dsp_ops = {
100 .handle_reply = imx8_dsp_handle_reply,
101 .handle_request = imx8_dsp_handle_request,
102 };
103
imx8_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)104 static int imx8_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
105 {
106 struct imx8_priv *priv = sdev->pdata->hw_pdata;
107
108 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
109 msg->msg_size);
110 imx_dsp_ring_doorbell(priv->dsp_ipc, 0);
111
112 return 0;
113 }
114
115 /*
116 * DSP control.
117 */
imx8x_run(struct snd_sof_dev * sdev)118 static int imx8x_run(struct snd_sof_dev *sdev)
119 {
120 struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
121 int ret;
122
123 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
124 IMX_SC_C_OFS_SEL, 1);
125 if (ret < 0) {
126 dev_err(sdev->dev, "Error system address offset source select\n");
127 return ret;
128 }
129
130 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
131 IMX_SC_C_OFS_AUDIO, 0x80);
132 if (ret < 0) {
133 dev_err(sdev->dev, "Error system address offset of AUDIO\n");
134 return ret;
135 }
136
137 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
138 IMX_SC_C_OFS_PERIPH, 0x5A);
139 if (ret < 0) {
140 dev_err(sdev->dev, "Error system address offset of PERIPH %d\n",
141 ret);
142 return ret;
143 }
144
145 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
146 IMX_SC_C_OFS_IRQ, 0x51);
147 if (ret < 0) {
148 dev_err(sdev->dev, "Error system address offset of IRQ\n");
149 return ret;
150 }
151
152 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
153 RESET_VECTOR_VADDR);
154
155 return 0;
156 }
157
imx8_run(struct snd_sof_dev * sdev)158 static int imx8_run(struct snd_sof_dev *sdev)
159 {
160 struct imx8_priv *dsp_priv = sdev->pdata->hw_pdata;
161 int ret;
162
163 ret = imx_sc_misc_set_control(dsp_priv->sc_ipc, IMX_SC_R_DSP,
164 IMX_SC_C_OFS_SEL, 0);
165 if (ret < 0) {
166 dev_err(sdev->dev, "Error system address offset source select\n");
167 return ret;
168 }
169
170 imx_sc_pm_cpu_start(dsp_priv->sc_ipc, IMX_SC_R_DSP, true,
171 RESET_VECTOR_VADDR);
172
173 return 0;
174 }
175
imx8_probe(struct snd_sof_dev * sdev)176 static int imx8_probe(struct snd_sof_dev *sdev)
177 {
178 struct platform_device *pdev = to_platform_device(sdev->dev);
179 struct device_node *np = pdev->dev.of_node;
180 struct device_node *res_node;
181 struct resource *mmio;
182 struct imx8_priv *priv;
183 struct resource res;
184 u32 base, size;
185 int ret = 0;
186 int i;
187
188 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
189 if (!priv)
190 return -ENOMEM;
191
192 sdev->num_cores = 1;
193 sdev->pdata->hw_pdata = priv;
194 priv->dev = sdev->dev;
195 priv->sdev = sdev;
196
197 /* power up device associated power domains */
198 priv->num_domains = of_count_phandle_with_args(np, "power-domains",
199 "#power-domain-cells");
200 if (priv->num_domains < 0) {
201 dev_err(sdev->dev, "no power-domains property in %pOF\n", np);
202 return priv->num_domains;
203 }
204
205 priv->pd_dev = devm_kmalloc_array(&pdev->dev, priv->num_domains,
206 sizeof(*priv->pd_dev), GFP_KERNEL);
207 if (!priv->pd_dev)
208 return -ENOMEM;
209
210 priv->link = devm_kmalloc_array(&pdev->dev, priv->num_domains,
211 sizeof(*priv->link), GFP_KERNEL);
212 if (!priv->link)
213 return -ENOMEM;
214
215 for (i = 0; i < priv->num_domains; i++) {
216 priv->pd_dev[i] = dev_pm_domain_attach_by_id(&pdev->dev, i);
217 if (IS_ERR(priv->pd_dev[i])) {
218 ret = PTR_ERR(priv->pd_dev[i]);
219 goto exit_unroll_pm;
220 }
221 priv->link[i] = device_link_add(&pdev->dev, priv->pd_dev[i],
222 DL_FLAG_STATELESS |
223 DL_FLAG_PM_RUNTIME |
224 DL_FLAG_RPM_ACTIVE);
225 if (!priv->link[i]) {
226 ret = -ENOMEM;
227 dev_pm_domain_detach(priv->pd_dev[i], false);
228 goto exit_unroll_pm;
229 }
230 }
231
232 ret = imx_scu_get_handle(&priv->sc_ipc);
233 if (ret) {
234 dev_err(sdev->dev, "Cannot obtain SCU handle (err = %d)\n",
235 ret);
236 goto exit_unroll_pm;
237 }
238
239 priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp",
240 PLATFORM_DEVID_NONE,
241 pdev, sizeof(*pdev));
242 if (IS_ERR(priv->ipc_dev)) {
243 ret = PTR_ERR(priv->ipc_dev);
244 goto exit_unroll_pm;
245 }
246
247 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
248 if (!priv->dsp_ipc) {
249 /* DSP IPC driver not probed yet, try later */
250 ret = -EPROBE_DEFER;
251 dev_err(sdev->dev, "Failed to get drvdata\n");
252 goto exit_pdev_unregister;
253 }
254
255 imx_dsp_set_data(priv->dsp_ipc, priv);
256 priv->dsp_ipc->ops = &dsp_ops;
257
258 /* DSP base */
259 mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
260 if (mmio) {
261 base = mmio->start;
262 size = resource_size(mmio);
263 } else {
264 dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n");
265 ret = -EINVAL;
266 goto exit_pdev_unregister;
267 }
268
269 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size);
270 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
271 dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n",
272 base, size);
273 ret = -ENODEV;
274 goto exit_pdev_unregister;
275 }
276 sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM;
277
278 res_node = of_parse_phandle(np, "memory-region", 0);
279 if (!res_node) {
280 dev_err(&pdev->dev, "failed to get memory region node\n");
281 ret = -ENODEV;
282 goto exit_pdev_unregister;
283 }
284
285 ret = of_address_to_resource(res_node, 0, &res);
286 of_node_put(res_node);
287 if (ret) {
288 dev_err(&pdev->dev, "failed to get reserved region address\n");
289 goto exit_pdev_unregister;
290 }
291
292 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start,
293 resource_size(&res));
294 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
295 dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n",
296 base, size);
297 ret = -ENOMEM;
298 goto exit_pdev_unregister;
299 }
300 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
301
302 /* set default mailbox offset for FW ready message */
303 sdev->dsp_box.offset = MBOX_OFFSET;
304
305 ret = devm_clk_bulk_get_all(sdev->dev, &priv->clks);
306 if (ret < 0) {
307 dev_err(sdev->dev, "failed to fetch clocks: %d\n", ret);
308 goto exit_pdev_unregister;
309 }
310 priv->clk_num = ret;
311
312 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
313 if (ret < 0) {
314 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
315 goto exit_pdev_unregister;
316 }
317
318 return 0;
319
320 exit_pdev_unregister:
321 platform_device_unregister(priv->ipc_dev);
322 exit_unroll_pm:
323 while (--i >= 0) {
324 device_link_del(priv->link[i]);
325 dev_pm_domain_detach(priv->pd_dev[i], false);
326 }
327
328 return ret;
329 }
330
imx8_remove(struct snd_sof_dev * sdev)331 static void imx8_remove(struct snd_sof_dev *sdev)
332 {
333 struct imx8_priv *priv = sdev->pdata->hw_pdata;
334 int i;
335
336 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
337 platform_device_unregister(priv->ipc_dev);
338
339 for (i = 0; i < priv->num_domains; i++) {
340 device_link_del(priv->link[i]);
341 dev_pm_domain_detach(priv->pd_dev[i], false);
342 }
343 }
344
345 /* on i.MX8 there is 1 to 1 match between type and BAR idx */
imx8_get_bar_index(struct snd_sof_dev * sdev,u32 type)346 static int imx8_get_bar_index(struct snd_sof_dev *sdev, u32 type)
347 {
348 /* Only IRAM and SRAM bars are valid */
349 switch (type) {
350 case SOF_FW_BLK_TYPE_IRAM:
351 case SOF_FW_BLK_TYPE_SRAM:
352 return type;
353 default:
354 return -EINVAL;
355 }
356 }
357
imx8_suspend(struct snd_sof_dev * sdev)358 static void imx8_suspend(struct snd_sof_dev *sdev)
359 {
360 int i;
361 struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
362
363 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
364 imx_dsp_free_channel(priv->dsp_ipc, i);
365
366 clk_bulk_disable_unprepare(priv->clk_num, priv->clks);
367 }
368
imx8_resume(struct snd_sof_dev * sdev)369 static int imx8_resume(struct snd_sof_dev *sdev)
370 {
371 struct imx8_priv *priv = (struct imx8_priv *)sdev->pdata->hw_pdata;
372 int ret;
373 int i;
374
375 ret = clk_bulk_prepare_enable(priv->clk_num, priv->clks);
376 if (ret < 0) {
377 dev_err(sdev->dev, "failed to enable clocks: %d\n", ret);
378 return ret;
379 }
380
381 for (i = 0; i < DSP_MU_CHAN_NUM; i++)
382 imx_dsp_request_channel(priv->dsp_ipc, i);
383
384 return 0;
385 }
386
imx8_dsp_runtime_resume(struct snd_sof_dev * sdev)387 static int imx8_dsp_runtime_resume(struct snd_sof_dev *sdev)
388 {
389 int ret;
390 const struct sof_dsp_power_state target_dsp_state = {
391 .state = SOF_DSP_PM_D0,
392 };
393
394 ret = imx8_resume(sdev);
395 if (ret < 0)
396 return ret;
397
398 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
399 }
400
imx8_dsp_runtime_suspend(struct snd_sof_dev * sdev)401 static int imx8_dsp_runtime_suspend(struct snd_sof_dev *sdev)
402 {
403 const struct sof_dsp_power_state target_dsp_state = {
404 .state = SOF_DSP_PM_D3,
405 };
406
407 imx8_suspend(sdev);
408
409 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
410 }
411
imx8_dsp_suspend(struct snd_sof_dev * sdev,unsigned int target_state)412 static int imx8_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state)
413 {
414 const struct sof_dsp_power_state target_dsp_state = {
415 .state = target_state,
416 };
417
418 if (!pm_runtime_suspended(sdev->dev))
419 imx8_suspend(sdev);
420
421 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
422 }
423
imx8_dsp_resume(struct snd_sof_dev * sdev)424 static int imx8_dsp_resume(struct snd_sof_dev *sdev)
425 {
426 int ret;
427 const struct sof_dsp_power_state target_dsp_state = {
428 .state = SOF_DSP_PM_D0,
429 };
430
431 ret = imx8_resume(sdev);
432 if (ret < 0)
433 return ret;
434
435 if (pm_runtime_suspended(sdev->dev)) {
436 pm_runtime_disable(sdev->dev);
437 pm_runtime_set_active(sdev->dev);
438 pm_runtime_mark_last_busy(sdev->dev);
439 pm_runtime_enable(sdev->dev);
440 pm_runtime_idle(sdev->dev);
441 }
442
443 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
444 }
445
446 static struct snd_soc_dai_driver imx8_dai[] = {
447 {
448 .name = "esai0",
449 .playback = {
450 .channels_min = 1,
451 .channels_max = 8,
452 },
453 .capture = {
454 .channels_min = 1,
455 .channels_max = 8,
456 },
457 },
458 {
459 .name = "sai1",
460 .playback = {
461 .channels_min = 1,
462 .channels_max = 32,
463 },
464 .capture = {
465 .channels_min = 1,
466 .channels_max = 32,
467 },
468 },
469 };
470
imx8_dsp_set_power_state(struct snd_sof_dev * sdev,const struct sof_dsp_power_state * target_state)471 static int imx8_dsp_set_power_state(struct snd_sof_dev *sdev,
472 const struct sof_dsp_power_state *target_state)
473 {
474 sdev->dsp_power_state = *target_state;
475
476 return 0;
477 }
478
479 /* i.MX8 ops */
480 static const struct snd_sof_dsp_ops sof_imx8_ops = {
481 /* probe and remove */
482 .probe = imx8_probe,
483 .remove = imx8_remove,
484 /* DSP core boot */
485 .run = imx8_run,
486
487 /* Block IO */
488 .block_read = sof_block_read,
489 .block_write = sof_block_write,
490
491 /* Mailbox IO */
492 .mailbox_read = sof_mailbox_read,
493 .mailbox_write = sof_mailbox_write,
494
495 /* ipc */
496 .send_msg = imx8_send_msg,
497 .get_mailbox_offset = imx8_get_mailbox_offset,
498 .get_window_offset = imx8_get_window_offset,
499
500 .ipc_msg_data = sof_ipc_msg_data,
501 .set_stream_data_offset = sof_set_stream_data_offset,
502
503 .get_bar_index = imx8_get_bar_index,
504
505 /* firmware loading */
506 .load_firmware = snd_sof_load_firmware_memcpy,
507
508 /* Debug information */
509 .dbg_dump = imx8_dump,
510 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
511
512 /* stream callbacks */
513 .pcm_open = sof_stream_pcm_open,
514 .pcm_close = sof_stream_pcm_close,
515
516 /* Firmware ops */
517 .dsp_arch_ops = &sof_xtensa_arch_ops,
518
519 /* DAI drivers */
520 .drv = imx8_dai,
521 .num_drv = ARRAY_SIZE(imx8_dai),
522
523 /* ALSA HW info flags */
524 .hw_info = SNDRV_PCM_INFO_MMAP |
525 SNDRV_PCM_INFO_MMAP_VALID |
526 SNDRV_PCM_INFO_INTERLEAVED |
527 SNDRV_PCM_INFO_PAUSE |
528 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
529
530 /* PM */
531 .runtime_suspend = imx8_dsp_runtime_suspend,
532 .runtime_resume = imx8_dsp_runtime_resume,
533
534 .suspend = imx8_dsp_suspend,
535 .resume = imx8_dsp_resume,
536
537 .set_power_state = imx8_dsp_set_power_state,
538 };
539
540 /* i.MX8X ops */
541 static const struct snd_sof_dsp_ops sof_imx8x_ops = {
542 /* probe and remove */
543 .probe = imx8_probe,
544 .remove = imx8_remove,
545 /* DSP core boot */
546 .run = imx8x_run,
547
548 /* Block IO */
549 .block_read = sof_block_read,
550 .block_write = sof_block_write,
551
552 /* Mailbox IO */
553 .mailbox_read = sof_mailbox_read,
554 .mailbox_write = sof_mailbox_write,
555
556 /* ipc */
557 .send_msg = imx8_send_msg,
558 .get_mailbox_offset = imx8_get_mailbox_offset,
559 .get_window_offset = imx8_get_window_offset,
560
561 .ipc_msg_data = sof_ipc_msg_data,
562 .set_stream_data_offset = sof_set_stream_data_offset,
563
564 .get_bar_index = imx8_get_bar_index,
565
566 /* firmware loading */
567 .load_firmware = snd_sof_load_firmware_memcpy,
568
569 /* Debug information */
570 .dbg_dump = imx8_dump,
571 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
572
573 /* stream callbacks */
574 .pcm_open = sof_stream_pcm_open,
575 .pcm_close = sof_stream_pcm_close,
576
577 /* Firmware ops */
578 .dsp_arch_ops = &sof_xtensa_arch_ops,
579
580 /* DAI drivers */
581 .drv = imx8_dai,
582 .num_drv = ARRAY_SIZE(imx8_dai),
583
584 /* PM */
585 .runtime_suspend = imx8_dsp_runtime_suspend,
586 .runtime_resume = imx8_dsp_runtime_resume,
587
588 .suspend = imx8_dsp_suspend,
589 .resume = imx8_dsp_resume,
590
591 .set_power_state = imx8_dsp_set_power_state,
592
593 /* ALSA HW info flags */
594 .hw_info = SNDRV_PCM_INFO_MMAP |
595 SNDRV_PCM_INFO_MMAP_VALID |
596 SNDRV_PCM_INFO_INTERLEAVED |
597 SNDRV_PCM_INFO_PAUSE |
598 SNDRV_PCM_INFO_BATCH |
599 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
600 };
601
602 static struct snd_sof_of_mach sof_imx8_machs[] = {
603 {
604 .compatible = "fsl,imx8qxp-mek",
605 .sof_tplg_filename = "sof-imx8-wm8960.tplg",
606 .drv_name = "asoc-audio-graph-card2",
607 },
608 {
609 .compatible = "fsl,imx8qxp-mek-wcpu",
610 .sof_tplg_filename = "sof-imx8-wm8962.tplg",
611 .drv_name = "asoc-audio-graph-card2",
612 },
613 {
614 .compatible = "fsl,imx8qm-mek",
615 .sof_tplg_filename = "sof-imx8-wm8960.tplg",
616 .drv_name = "asoc-audio-graph-card2",
617 },
618 {
619 .compatible = "fsl,imx8qm-mek-revd",
620 .sof_tplg_filename = "sof-imx8-wm8962.tplg",
621 .drv_name = "asoc-audio-graph-card2",
622 },
623 {
624 .compatible = "fsl,imx8qxp-mek-bb",
625 .sof_tplg_filename = "sof-imx8-cs42888.tplg",
626 .drv_name = "asoc-audio-graph-card2",
627 },
628 {
629 .compatible = "fsl,imx8qm-mek-bb",
630 .sof_tplg_filename = "sof-imx8-cs42888.tplg",
631 .drv_name = "asoc-audio-graph-card2",
632 },
633
634 {}
635 };
636
637 static struct sof_dev_desc sof_of_imx8qxp_desc = {
638 .of_machines = sof_imx8_machs,
639 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
640 .ipc_default = SOF_IPC_TYPE_3,
641 .default_fw_path = {
642 [SOF_IPC_TYPE_3] = "imx/sof",
643 },
644 .default_tplg_path = {
645 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
646 },
647 .default_fw_filename = {
648 [SOF_IPC_TYPE_3] = "sof-imx8x.ri",
649 },
650 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
651 .ops = &sof_imx8x_ops,
652 };
653
654 static struct sof_dev_desc sof_of_imx8qm_desc = {
655 .of_machines = sof_imx8_machs,
656 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
657 .ipc_default = SOF_IPC_TYPE_3,
658 .default_fw_path = {
659 [SOF_IPC_TYPE_3] = "imx/sof",
660 },
661 .default_tplg_path = {
662 [SOF_IPC_TYPE_3] = "imx/sof-tplg",
663 },
664 .default_fw_filename = {
665 [SOF_IPC_TYPE_3] = "sof-imx8.ri",
666 },
667 .nocodec_tplg_filename = "sof-imx8-nocodec.tplg",
668 .ops = &sof_imx8_ops,
669 };
670
671 static const struct of_device_id sof_of_imx8_ids[] = {
672 { .compatible = "fsl,imx8qxp-dsp", .data = &sof_of_imx8qxp_desc},
673 { .compatible = "fsl,imx8qm-dsp", .data = &sof_of_imx8qm_desc},
674 { }
675 };
676 MODULE_DEVICE_TABLE(of, sof_of_imx8_ids);
677
678 /* DT driver definition */
679 static struct platform_driver snd_sof_of_imx8_driver = {
680 .probe = sof_of_probe,
681 .remove = sof_of_remove,
682 .driver = {
683 .name = "sof-audio-of-imx8",
684 .pm = &sof_of_pm,
685 .of_match_table = sof_of_imx8_ids,
686 },
687 };
688 module_platform_driver(snd_sof_of_imx8_driver);
689
690 MODULE_LICENSE("Dual BSD/GPL");
691 MODULE_DESCRIPTION("SOF support for IMX8 platforms");
692 MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
693