xref: /linux/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h (revision db5d28c0bfe566908719bec8e25443aabecbb802)
1 /*
2  * Copyright (C) 2017  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _gc_9_0_SH_MASK_HEADER
22 #define _gc_9_0_SH_MASK_HEADER
23 
24 //GCEA_EDC_CNT
25 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
26 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
27 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
28 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
29 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
30 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
31 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                            0xc
32 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                            0xe
33 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                            0x10
34 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                            0x12
35 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                         0x14
36 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                         0x16
37 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                            0x18
38 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                            0x1a
39 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                           0x1c
40 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
41 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
42 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
43 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
44 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
45 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
46 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                              0x00003000L
47 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                              0x0000C000L
48 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                              0x00030000L
49 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                              0x000C0000L
50 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                           0x00300000L
51 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                           0x00C00000L
52 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                              0x03000000L
53 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                              0x0C000000L
54 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                             0x30000000L
55 
56 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
57 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
58 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
59 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
60 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
61 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
62 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                         0xc
63 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                         0xe
64 #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                             0x10
65 #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                             0x12
66 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                             0x14
67 #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                             0x16
68 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
69 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
70 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
71 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
72 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
73 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
74 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                           0x00003000L
75 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                           0x0000C000L
76 #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                               0x00030000L
77 #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                               0x000C0000L
78 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                               0x00300000L
79 #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                               0x00C00000L
80 
81 // addressBlock: gc_cppdec2
82 //CPF_EDC_TAG_CNT
83 #define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
84 #define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
85 #define CPF_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
86 #define CPF_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
87 //CPF_EDC_ROQ_CNT
88 #define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT                                                                     0x0
89 #define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT                                                                     0x2
90 #define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK                                                                       0x00000003L
91 #define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK                                                                       0x0000000CL
92 //CPG_EDC_TAG_CNT
93 #define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
94 #define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
95 #define CPG_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
96 #define CPG_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
97 //CPG_EDC_DMA_CNT
98 #define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT                                                                     0x0
99 #define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT                                                                 0x2
100 #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT                                                                 0x4
101 #define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK                                                                       0x00000003L
102 #define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK                                                                   0x0000000CL
103 #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK                                                                   0x00000030L
104 //CPC_EDC_SCRATCH_CNT
105 #define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT                                                                 0x0
106 #define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT                                                                 0x2
107 #define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK                                                                   0x00000003L
108 #define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK                                                                   0x0000000CL
109 //CPC_EDC_UCODE_CNT
110 #define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT                                                                   0x0
111 #define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT                                                                   0x2
112 #define CPC_EDC_UCODE_CNT__DED_COUNT_MASK                                                                     0x00000003L
113 #define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK                                                                     0x0000000CL
114 //DC_EDC_STATE_CNT
115 #define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT                                                                    0x0
116 #define DC_EDC_STATE_CNT__COUNT_ME1_MASK                                                                      0x00000003L
117 //DC_EDC_CSINVOC_CNT
118 #define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT                                                                  0x0
119 #define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK                                                                    0x00000003L
120 //DC_EDC_RESTORE_CNT
121 #define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT                                                                  0x0
122 #define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK                                                                    0x00000003L
123 
124 // addressBlock: gc_grbmdec
125 //GRBM_CNTL
126 #define GRBM_CNTL__READ_TIMEOUT__SHIFT                                                                        0x0
127 #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT                                                                   0x1f
128 #define GRBM_CNTL__READ_TIMEOUT_MASK                                                                          0x000000FFL
129 #define GRBM_CNTL__REPORT_LAST_RDERR_MASK                                                                     0x80000000L
130 //GRBM_SKEW_CNTL
131 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT                                                             0x0
132 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT                                                                     0x6
133 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK                                                               0x0000003FL
134 #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK                                                                       0x00000FC0L
135 //GRBM_STATUS2
136 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT                                                           0x0
137 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT                                                           0x4
138 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT                                                           0x5
139 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT                                                              0x6
140 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT                                                              0x7
141 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT                                                              0x8
142 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT                                                              0x9
143 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT                                                              0xa
144 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT                                                              0xb
145 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT                                                              0xc
146 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT                                                              0xd
147 #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT                                                                   0xe
148 #define GRBM_STATUS2__UTCL2_BUSY__SHIFT                                                                       0xf
149 #define GRBM_STATUS2__EA_BUSY__SHIFT                                                                          0x10
150 #define GRBM_STATUS2__RMI_BUSY__SHIFT                                                                         0x11
151 #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT                                                                 0x12
152 #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT                                                                   0x13
153 #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT                                                                     0x14
154 #define GRBM_STATUS2__RLC_BUSY__SHIFT                                                                         0x18
155 #define GRBM_STATUS2__TC_BUSY__SHIFT                                                                          0x19
156 #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT                                                                  0x1a
157 #define GRBM_STATUS2__CPF_BUSY__SHIFT                                                                         0x1c
158 #define GRBM_STATUS2__CPC_BUSY__SHIFT                                                                         0x1d
159 #define GRBM_STATUS2__CPG_BUSY__SHIFT                                                                         0x1e
160 #define GRBM_STATUS2__CPAXI_BUSY__SHIFT                                                                       0x1f
161 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK                                                             0x0000000FL
162 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK                                                             0x00000010L
163 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK                                                             0x00000020L
164 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK                                                                0x00000040L
165 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK                                                                0x00000080L
166 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK                                                                0x00000100L
167 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK                                                                0x00000200L
168 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK                                                                0x00000400L
169 #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK                                                                0x00000800L
170 #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK                                                                0x00001000L
171 #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK                                                                0x00002000L
172 #define GRBM_STATUS2__RLC_RQ_PENDING_MASK                                                                     0x00004000L
173 #define GRBM_STATUS2__UTCL2_BUSY_MASK                                                                         0x00008000L
174 #define GRBM_STATUS2__EA_BUSY_MASK                                                                            0x00010000L
175 #define GRBM_STATUS2__RMI_BUSY_MASK                                                                           0x00020000L
176 #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK                                                                   0x00040000L
177 #define GRBM_STATUS2__CPF_RQ_PENDING_MASK                                                                     0x00080000L
178 #define GRBM_STATUS2__EA_LINK_BUSY_MASK                                                                       0x00100000L
179 #define GRBM_STATUS2__RLC_BUSY_MASK                                                                           0x01000000L
180 #define GRBM_STATUS2__TC_BUSY_MASK                                                                            0x02000000L
181 #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK                                                                    0x04000000L
182 #define GRBM_STATUS2__CPF_BUSY_MASK                                                                           0x10000000L
183 #define GRBM_STATUS2__CPC_BUSY_MASK                                                                           0x20000000L
184 #define GRBM_STATUS2__CPG_BUSY_MASK                                                                           0x40000000L
185 #define GRBM_STATUS2__CPAXI_BUSY_MASK                                                                         0x80000000L
186 //GRBM_PWR_CNTL
187 #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT                                                                    0x0
188 #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT                                                                    0x2
189 #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT                                                                    0x4
190 #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT                                                                    0x6
191 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT                                                                      0xe
192 #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT                                                                      0xf
193 #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK                                                                      0x00000003L
194 #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK                                                                      0x0000000CL
195 #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK                                                                      0x00000030L
196 #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK                                                                      0x000000C0L
197 #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK                                                                        0x00004000L
198 #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK                                                                        0x00008000L
199 //GRBM_STATUS
200 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT                                                            0x0
201 #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT                                                                   0x5
202 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT                                                            0x7
203 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT                                                            0x8
204 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT                                                                0x9
205 #define GRBM_STATUS__DB_CLEAN__SHIFT                                                                          0xc
206 #define GRBM_STATUS__CB_CLEAN__SHIFT                                                                          0xd
207 #define GRBM_STATUS__TA_BUSY__SHIFT                                                                           0xe
208 #define GRBM_STATUS__GDS_BUSY__SHIFT                                                                          0xf
209 #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT                                                                    0x10
210 #define GRBM_STATUS__VGT_BUSY__SHIFT                                                                          0x11
211 #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT                                                                    0x12
212 #define GRBM_STATUS__IA_BUSY__SHIFT                                                                           0x13
213 #define GRBM_STATUS__SX_BUSY__SHIFT                                                                           0x14
214 #define GRBM_STATUS__WD_BUSY__SHIFT                                                                           0x15
215 #define GRBM_STATUS__SPI_BUSY__SHIFT                                                                          0x16
216 #define GRBM_STATUS__BCI_BUSY__SHIFT                                                                          0x17
217 #define GRBM_STATUS__SC_BUSY__SHIFT                                                                           0x18
218 #define GRBM_STATUS__PA_BUSY__SHIFT                                                                           0x19
219 #define GRBM_STATUS__DB_BUSY__SHIFT                                                                           0x1a
220 #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT                                                                 0x1c
221 #define GRBM_STATUS__CP_BUSY__SHIFT                                                                           0x1d
222 #define GRBM_STATUS__CB_BUSY__SHIFT                                                                           0x1e
223 #define GRBM_STATUS__GUI_ACTIVE__SHIFT                                                                        0x1f
224 #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK                                                              0x0000000FL
225 #define GRBM_STATUS__RSMU_RQ_PENDING_MASK                                                                     0x00000020L
226 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK                                                              0x00000080L
227 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK                                                              0x00000100L
228 #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK                                                                  0x00000200L
229 #define GRBM_STATUS__DB_CLEAN_MASK                                                                            0x00001000L
230 #define GRBM_STATUS__CB_CLEAN_MASK                                                                            0x00002000L
231 #define GRBM_STATUS__TA_BUSY_MASK                                                                             0x00004000L
232 #define GRBM_STATUS__GDS_BUSY_MASK                                                                            0x00008000L
233 #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK                                                                      0x00010000L
234 #define GRBM_STATUS__VGT_BUSY_MASK                                                                            0x00020000L
235 #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK                                                                      0x00040000L
236 #define GRBM_STATUS__IA_BUSY_MASK                                                                             0x00080000L
237 #define GRBM_STATUS__SX_BUSY_MASK                                                                             0x00100000L
238 #define GRBM_STATUS__WD_BUSY_MASK                                                                             0x00200000L
239 #define GRBM_STATUS__SPI_BUSY_MASK                                                                            0x00400000L
240 #define GRBM_STATUS__BCI_BUSY_MASK                                                                            0x00800000L
241 #define GRBM_STATUS__SC_BUSY_MASK                                                                             0x01000000L
242 #define GRBM_STATUS__PA_BUSY_MASK                                                                             0x02000000L
243 #define GRBM_STATUS__DB_BUSY_MASK                                                                             0x04000000L
244 #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK                                                                   0x10000000L
245 #define GRBM_STATUS__CP_BUSY_MASK                                                                             0x20000000L
246 #define GRBM_STATUS__CB_BUSY_MASK                                                                             0x40000000L
247 #define GRBM_STATUS__GUI_ACTIVE_MASK                                                                          0x80000000L
248 //GRBM_STATUS_SE0
249 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT                                                                      0x1
250 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT                                                                      0x2
251 #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT                                                                      0x15
252 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT                                                                      0x16
253 #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT                                                                      0x17
254 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT                                                                       0x18
255 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT                                                                       0x19
256 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT                                                                       0x1a
257 #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT                                                                      0x1b
258 #define GRBM_STATUS_SE0__SC_BUSY__SHIFT                                                                       0x1d
259 #define GRBM_STATUS_SE0__DB_BUSY__SHIFT                                                                       0x1e
260 #define GRBM_STATUS_SE0__CB_BUSY__SHIFT                                                                       0x1f
261 #define GRBM_STATUS_SE0__DB_CLEAN_MASK                                                                        0x00000002L
262 #define GRBM_STATUS_SE0__CB_CLEAN_MASK                                                                        0x00000004L
263 #define GRBM_STATUS_SE0__RMI_BUSY_MASK                                                                        0x00200000L
264 #define GRBM_STATUS_SE0__BCI_BUSY_MASK                                                                        0x00400000L
265 #define GRBM_STATUS_SE0__VGT_BUSY_MASK                                                                        0x00800000L
266 #define GRBM_STATUS_SE0__PA_BUSY_MASK                                                                         0x01000000L
267 #define GRBM_STATUS_SE0__TA_BUSY_MASK                                                                         0x02000000L
268 #define GRBM_STATUS_SE0__SX_BUSY_MASK                                                                         0x04000000L
269 #define GRBM_STATUS_SE0__SPI_BUSY_MASK                                                                        0x08000000L
270 #define GRBM_STATUS_SE0__SC_BUSY_MASK                                                                         0x20000000L
271 #define GRBM_STATUS_SE0__DB_BUSY_MASK                                                                         0x40000000L
272 #define GRBM_STATUS_SE0__CB_BUSY_MASK                                                                         0x80000000L
273 //GRBM_STATUS_SE1
274 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT                                                                      0x1
275 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT                                                                      0x2
276 #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT                                                                      0x15
277 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT                                                                      0x16
278 #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT                                                                      0x17
279 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT                                                                       0x18
280 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT                                                                       0x19
281 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT                                                                       0x1a
282 #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT                                                                      0x1b
283 #define GRBM_STATUS_SE1__SC_BUSY__SHIFT                                                                       0x1d
284 #define GRBM_STATUS_SE1__DB_BUSY__SHIFT                                                                       0x1e
285 #define GRBM_STATUS_SE1__CB_BUSY__SHIFT                                                                       0x1f
286 #define GRBM_STATUS_SE1__DB_CLEAN_MASK                                                                        0x00000002L
287 #define GRBM_STATUS_SE1__CB_CLEAN_MASK                                                                        0x00000004L
288 #define GRBM_STATUS_SE1__RMI_BUSY_MASK                                                                        0x00200000L
289 #define GRBM_STATUS_SE1__BCI_BUSY_MASK                                                                        0x00400000L
290 #define GRBM_STATUS_SE1__VGT_BUSY_MASK                                                                        0x00800000L
291 #define GRBM_STATUS_SE1__PA_BUSY_MASK                                                                         0x01000000L
292 #define GRBM_STATUS_SE1__TA_BUSY_MASK                                                                         0x02000000L
293 #define GRBM_STATUS_SE1__SX_BUSY_MASK                                                                         0x04000000L
294 #define GRBM_STATUS_SE1__SPI_BUSY_MASK                                                                        0x08000000L
295 #define GRBM_STATUS_SE1__SC_BUSY_MASK                                                                         0x20000000L
296 #define GRBM_STATUS_SE1__DB_BUSY_MASK                                                                         0x40000000L
297 #define GRBM_STATUS_SE1__CB_BUSY_MASK                                                                         0x80000000L
298 //GRBM_SOFT_RESET
299 #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT                                                                 0x0
300 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT                                                                0x2
301 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT                                                                0x10
302 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT                                                                0x11
303 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT                                                                0x12
304 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT                                                                0x13
305 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT                                                                0x14
306 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT                                                              0x15
307 #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT                                                                 0x16
308 #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK                                                                   0x00000001L
309 #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK                                                                  0x00000004L
310 #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK                                                                  0x00010000L
311 #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK                                                                  0x00020000L
312 #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK                                                                  0x00040000L
313 #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK                                                                  0x00080000L
314 #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK                                                                  0x00100000L
315 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK                                                                0x00200000L
316 #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK                                                                   0x00400000L
317 //GRBM_CGTT_CLK_CNTL
318 #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT                                                                   0x0
319 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT                                                             0x4
320 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
321 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
322 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
323 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
324 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
325 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
326 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
327 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
328 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT                                                          0x1e
329 #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK                                                                     0x0000000FL
330 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
331 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
332 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
333 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
334 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
335 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
336 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
337 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
338 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
339 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK                                                            0x40000000L
340 //GRBM_GFX_CLKEN_CNTL
341 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT                                                          0x0
342 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT                                                            0x8
343 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK                                                            0x0000000FL
344 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK                                                              0x00001F00L
345 //GRBM_WAIT_IDLE_CLOCKS
346 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT                                                        0x0
347 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK                                                          0x000000FFL
348 //GRBM_STATUS_SE2
349 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT                                                                      0x1
350 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT                                                                      0x2
351 #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT                                                                      0x15
352 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT                                                                      0x16
353 #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT                                                                      0x17
354 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT                                                                       0x18
355 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT                                                                       0x19
356 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT                                                                       0x1a
357 #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT                                                                      0x1b
358 #define GRBM_STATUS_SE2__SC_BUSY__SHIFT                                                                       0x1d
359 #define GRBM_STATUS_SE2__DB_BUSY__SHIFT                                                                       0x1e
360 #define GRBM_STATUS_SE2__CB_BUSY__SHIFT                                                                       0x1f
361 #define GRBM_STATUS_SE2__DB_CLEAN_MASK                                                                        0x00000002L
362 #define GRBM_STATUS_SE2__CB_CLEAN_MASK                                                                        0x00000004L
363 #define GRBM_STATUS_SE2__RMI_BUSY_MASK                                                                        0x00200000L
364 #define GRBM_STATUS_SE2__BCI_BUSY_MASK                                                                        0x00400000L
365 #define GRBM_STATUS_SE2__VGT_BUSY_MASK                                                                        0x00800000L
366 #define GRBM_STATUS_SE2__PA_BUSY_MASK                                                                         0x01000000L
367 #define GRBM_STATUS_SE2__TA_BUSY_MASK                                                                         0x02000000L
368 #define GRBM_STATUS_SE2__SX_BUSY_MASK                                                                         0x04000000L
369 #define GRBM_STATUS_SE2__SPI_BUSY_MASK                                                                        0x08000000L
370 #define GRBM_STATUS_SE2__SC_BUSY_MASK                                                                         0x20000000L
371 #define GRBM_STATUS_SE2__DB_BUSY_MASK                                                                         0x40000000L
372 #define GRBM_STATUS_SE2__CB_BUSY_MASK                                                                         0x80000000L
373 //GRBM_STATUS_SE3
374 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT                                                                      0x1
375 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT                                                                      0x2
376 #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT                                                                      0x15
377 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT                                                                      0x16
378 #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT                                                                      0x17
379 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT                                                                       0x18
380 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT                                                                       0x19
381 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT                                                                       0x1a
382 #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT                                                                      0x1b
383 #define GRBM_STATUS_SE3__SC_BUSY__SHIFT                                                                       0x1d
384 #define GRBM_STATUS_SE3__DB_BUSY__SHIFT                                                                       0x1e
385 #define GRBM_STATUS_SE3__CB_BUSY__SHIFT                                                                       0x1f
386 #define GRBM_STATUS_SE3__DB_CLEAN_MASK                                                                        0x00000002L
387 #define GRBM_STATUS_SE3__CB_CLEAN_MASK                                                                        0x00000004L
388 #define GRBM_STATUS_SE3__RMI_BUSY_MASK                                                                        0x00200000L
389 #define GRBM_STATUS_SE3__BCI_BUSY_MASK                                                                        0x00400000L
390 #define GRBM_STATUS_SE3__VGT_BUSY_MASK                                                                        0x00800000L
391 #define GRBM_STATUS_SE3__PA_BUSY_MASK                                                                         0x01000000L
392 #define GRBM_STATUS_SE3__TA_BUSY_MASK                                                                         0x02000000L
393 #define GRBM_STATUS_SE3__SX_BUSY_MASK                                                                         0x04000000L
394 #define GRBM_STATUS_SE3__SPI_BUSY_MASK                                                                        0x08000000L
395 #define GRBM_STATUS_SE3__SC_BUSY_MASK                                                                         0x20000000L
396 #define GRBM_STATUS_SE3__DB_BUSY_MASK                                                                         0x40000000L
397 #define GRBM_STATUS_SE3__CB_BUSY_MASK                                                                         0x80000000L
398 //GRBM_READ_ERROR
399 #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT                                                                  0x2
400 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT                                                                   0x14
401 #define GRBM_READ_ERROR__READ_MEID__SHIFT                                                                     0x16
402 #define GRBM_READ_ERROR__READ_ERROR__SHIFT                                                                    0x1f
403 #define GRBM_READ_ERROR__READ_ADDRESS_MASK                                                                    0x0003FFFCL
404 #define GRBM_READ_ERROR__READ_PIPEID_MASK                                                                     0x00300000L
405 #define GRBM_READ_ERROR__READ_MEID_MASK                                                                       0x00C00000L
406 #define GRBM_READ_ERROR__READ_ERROR_MASK                                                                      0x80000000L
407 //GRBM_READ_ERROR2
408 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT                                                           0x10
409 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT                                                          0x11
410 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT                                                           0x12
411 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT                                                       0x13
412 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT                                                   0x14
413 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT                                                   0x15
414 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT                                                   0x16
415 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT                                                   0x17
416 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT                                                      0x18
417 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT                                                      0x19
418 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT                                                      0x1a
419 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT                                                      0x1b
420 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT                                                      0x1c
421 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT                                                      0x1d
422 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT                                                      0x1e
423 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT                                                      0x1f
424 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK                                                             0x00010000L
425 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK                                                            0x00020000L
426 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK                                                             0x00040000L
427 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK                                                         0x00080000L
428 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK                                                     0x00100000L
429 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK                                                     0x00200000L
430 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK                                                     0x00400000L
431 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK                                                     0x00800000L
432 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK                                                        0x01000000L
433 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK                                                        0x02000000L
434 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK                                                        0x04000000L
435 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK                                                        0x08000000L
436 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK                                                        0x10000000L
437 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK                                                        0x20000000L
438 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK                                                        0x40000000L
439 #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK                                                        0x80000000L
440 //GRBM_INT_CNTL
441 #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT                                                                0x0
442 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT                                                             0x13
443 #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK                                                                  0x00000001L
444 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK                                                               0x00080000L
445 //GRBM_TRAP_OP
446 #define GRBM_TRAP_OP__RW__SHIFT                                                                               0x0
447 #define GRBM_TRAP_OP__RW_MASK                                                                                 0x00000001L
448 //GRBM_TRAP_ADDR
449 #define GRBM_TRAP_ADDR__DATA__SHIFT                                                                           0x0
450 #define GRBM_TRAP_ADDR__DATA_MASK                                                                             0x0003FFFFL
451 //GRBM_TRAP_ADDR_MSK
452 #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT                                                                       0x0
453 #define GRBM_TRAP_ADDR_MSK__DATA_MASK                                                                         0x0003FFFFL
454 //GRBM_TRAP_WD
455 #define GRBM_TRAP_WD__DATA__SHIFT                                                                             0x0
456 #define GRBM_TRAP_WD__DATA_MASK                                                                               0xFFFFFFFFL
457 //GRBM_TRAP_WD_MSK
458 #define GRBM_TRAP_WD_MSK__DATA__SHIFT                                                                         0x0
459 #define GRBM_TRAP_WD_MSK__DATA_MASK                                                                           0xFFFFFFFFL
460 //GRBM_DSM_BYPASS
461 #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT                                                                   0x0
462 #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT                                                                     0x2
463 #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK                                                                     0x00000003L
464 #define GRBM_DSM_BYPASS__BYPASS_EN_MASK                                                                       0x00000004L
465 //GRBM_WRITE_ERROR
466 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT                                                          0x0
467 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT                                                         0x1
468 #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT                                                                 0x2
469 #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT                                                                   0x5
470 #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT                                                                     0xc
471 #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT                                                                   0xd
472 #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT                                                                 0x14
473 #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT                                                                   0x16
474 #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT                                                                  0x1f
475 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK                                                            0x00000001L
476 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK                                                           0x00000002L
477 #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK                                                                   0x0000001CL
478 #define GRBM_WRITE_ERROR__WRITE_VFID_MASK                                                                     0x000001E0L
479 #define GRBM_WRITE_ERROR__WRITE_VF_MASK                                                                       0x00001000L
480 #define GRBM_WRITE_ERROR__WRITE_VMID_MASK                                                                     0x0001E000L
481 #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK                                                                   0x00300000L
482 #define GRBM_WRITE_ERROR__WRITE_MEID_MASK                                                                     0x00C00000L
483 #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK                                                                    0x80000000L
484 //GRBM_IOV_ERROR
485 #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT                                                                       0x2
486 #define GRBM_IOV_ERROR__IOV_VFID__SHIFT                                                                       0x14
487 #define GRBM_IOV_ERROR__IOV_VF__SHIFT                                                                         0x1a
488 #define GRBM_IOV_ERROR__IOV_OP__SHIFT                                                                         0x1b
489 #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT                                                                      0x1f
490 #define GRBM_IOV_ERROR__IOV_ADDR_MASK                                                                         0x000FFFFCL
491 #define GRBM_IOV_ERROR__IOV_VFID_MASK                                                                         0x03F00000L
492 #define GRBM_IOV_ERROR__IOV_VF_MASK                                                                           0x04000000L
493 #define GRBM_IOV_ERROR__IOV_OP_MASK                                                                           0x08000000L
494 #define GRBM_IOV_ERROR__IOV_ERROR_MASK                                                                        0x80000000L
495 //GRBM_CHIP_REVISION
496 #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT                                                              0x0
497 #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK                                                                0x000000FFL
498 //GRBM_GFX_CNTL
499 #define GRBM_GFX_CNTL__PIPEID__SHIFT                                                                          0x0
500 #define GRBM_GFX_CNTL__MEID__SHIFT                                                                            0x2
501 #define GRBM_GFX_CNTL__VMID__SHIFT                                                                            0x4
502 #define GRBM_GFX_CNTL__QUEUEID__SHIFT                                                                         0x8
503 #define GRBM_GFX_CNTL__PIPEID_MASK                                                                            0x00000003L
504 #define GRBM_GFX_CNTL__MEID_MASK                                                                              0x0000000CL
505 #define GRBM_GFX_CNTL__VMID_MASK                                                                              0x000000F0L
506 #define GRBM_GFX_CNTL__QUEUEID_MASK                                                                           0x00000700L
507 //GRBM_RSMU_CFG
508 #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT                                                                     0x0
509 #define GRBM_RSMU_CFG__QOS__SHIFT                                                                             0xc
510 #define GRBM_RSMU_CFG__POSTED_WR__SHIFT                                                                       0x10
511 #define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT                                                                      0x11
512 #define GRBM_RSMU_CFG__APERTURE_ID_MASK                                                                       0x00000FFFL
513 #define GRBM_RSMU_CFG__QOS_MASK                                                                               0x0000F000L
514 #define GRBM_RSMU_CFG__POSTED_WR_MASK                                                                         0x00010000L
515 #define GRBM_RSMU_CFG__DEBUG_MASK_MASK                                                                        0x00020000L
516 //GRBM_IH_CREDIT
517 #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                   0x0
518 #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT                                                                   0x10
519 #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK                                                                     0x00000003L
520 #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK                                                                     0x00FF0000L
521 //GRBM_PWR_CNTL2
522 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT                                                               0x10
523 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT                                                         0x14
524 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK                                                                 0x00010000L
525 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK                                                           0x00100000L
526 //GRBM_UTCL2_INVAL_RANGE_START
527 #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT                                                             0x0
528 #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK                                                               0x0003FFFFL
529 //GRBM_UTCL2_INVAL_RANGE_END
530 #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT                                                               0x0
531 #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK                                                                 0x0003FFFFL
532 //GRBM_RSMU_READ_ERROR
533 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT                                                        0x2
534 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT                                                             0x14
535 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT                                                           0x15
536 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT                                                     0x1b
537 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT                                                          0x1f
538 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK                                                          0x000FFFFCL
539 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK                                                               0x00100000L
540 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK                                                             0x07E00000L
541 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK                                                       0x08000000L
542 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK                                                            0x80000000L
543 //GRBM_CHICKEN_BITS
544 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT                                                   0x0
545 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK                                                     0x00000001L
546 //GRBM_NOWHERE
547 #define GRBM_NOWHERE__DATA__SHIFT                                                                             0x0
548 #define GRBM_NOWHERE__DATA_MASK                                                                               0xFFFFFFFFL
549 //GRBM_SCRATCH_REG0
550 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                0x0
551 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK                                                                  0xFFFFFFFFL
552 //GRBM_SCRATCH_REG1
553 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                0x0
554 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK                                                                  0xFFFFFFFFL
555 //GRBM_SCRATCH_REG2
556 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                0x0
557 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK                                                                  0xFFFFFFFFL
558 //GRBM_SCRATCH_REG3
559 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                0x0
560 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK                                                                  0xFFFFFFFFL
561 //GRBM_SCRATCH_REG4
562 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                0x0
563 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK                                                                  0xFFFFFFFFL
564 //GRBM_SCRATCH_REG5
565 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                0x0
566 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK                                                                  0xFFFFFFFFL
567 //GRBM_SCRATCH_REG6
568 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                0x0
569 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK                                                                  0xFFFFFFFFL
570 //GRBM_SCRATCH_REG7
571 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                0x0
572 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK                                                                  0xFFFFFFFFL
573 
574 
575 // addressBlock: gc_cpdec
576 //CP_CPC_STATUS
577 #define CP_CPC_STATUS__MEC1_BUSY__SHIFT                                                                       0x0
578 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT                                                                       0x1
579 #define CP_CPC_STATUS__DC0_BUSY__SHIFT                                                                        0x2
580 #define CP_CPC_STATUS__DC1_BUSY__SHIFT                                                                        0x3
581 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT                                                                      0x4
582 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT                                                                      0x5
583 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT                                                                       0x6
584 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT                                                                       0x7
585 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT                                                                       0xa
586 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT                                                                0xb
587 #define CP_CPC_STATUS__QU_BUSY__SHIFT                                                                         0xc
588 #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0xd
589 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT                                                               0xe
590 #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT                                                                    0x1d
591 #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT                                                                    0x1e
592 #define CP_CPC_STATUS__CPC_BUSY__SHIFT                                                                        0x1f
593 #define CP_CPC_STATUS__MEC1_BUSY_MASK                                                                         0x00000001L
594 #define CP_CPC_STATUS__MEC2_BUSY_MASK                                                                         0x00000002L
595 #define CP_CPC_STATUS__DC0_BUSY_MASK                                                                          0x00000004L
596 #define CP_CPC_STATUS__DC1_BUSY_MASK                                                                          0x00000008L
597 #define CP_CPC_STATUS__RCIU1_BUSY_MASK                                                                        0x00000010L
598 #define CP_CPC_STATUS__RCIU2_BUSY_MASK                                                                        0x00000020L
599 #define CP_CPC_STATUS__ROQ1_BUSY_MASK                                                                         0x00000040L
600 #define CP_CPC_STATUS__ROQ2_BUSY_MASK                                                                         0x00000080L
601 #define CP_CPC_STATUS__TCIU_BUSY_MASK                                                                         0x00000400L
602 #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK                                                                  0x00000800L
603 #define CP_CPC_STATUS__QU_BUSY_MASK                                                                           0x00001000L
604 #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00002000L
605 #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK                                                                 0x00004000L
606 #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK                                                                      0x20000000L
607 #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK                                                                      0x40000000L
608 #define CP_CPC_STATUS__CPC_BUSY_MASK                                                                          0x80000000L
609 //CP_CPC_BUSY_STAT
610 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT                                                               0x0
611 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT                                                          0x1
612 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT                                                              0x2
613 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT                                                            0x3
614 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT                                                          0x4
615 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT                                                           0x5
616 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT                                                           0x6
617 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT                                                                 0x7
618 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT                                                                0x8
619 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x9
620 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT                                                              0xa
621 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT                                                              0xb
622 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT                                                              0xc
623 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT                                                              0xd
624 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT                                                               0x10
625 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT                                                          0x11
626 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT                                                              0x12
627 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT                                                            0x13
628 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT                                                          0x14
629 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT                                                           0x15
630 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT                                                           0x16
631 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT                                                                 0x17
632 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT                                                                0x18
633 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT                                                      0x19
634 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT                                                              0x1a
635 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT                                                              0x1b
636 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT                                                              0x1c
637 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT                                                              0x1d
638 #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK                                                                 0x00000001L
639 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK                                                            0x00000002L
640 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK                                                                0x00000004L
641 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK                                                              0x00000008L
642 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK                                                            0x00000010L
643 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK                                                             0x00000020L
644 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK                                                             0x00000040L
645 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK                                                                   0x00000080L
646 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK                                                                  0x00000100L
647 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK                                                        0x00000200L
648 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK                                                                0x00000400L
649 #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK                                                                0x00000800L
650 #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK                                                                0x00001000L
651 #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK                                                                0x00002000L
652 #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK                                                                 0x00010000L
653 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK                                                            0x00020000L
654 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK                                                                0x00040000L
655 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK                                                              0x00080000L
656 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK                                                            0x00100000L
657 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK                                                             0x00200000L
658 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK                                                             0x00400000L
659 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK                                                                   0x00800000L
660 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK                                                                  0x01000000L
661 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK                                                        0x02000000L
662 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK                                                                0x04000000L
663 #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK                                                                0x08000000L
664 #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK                                                                0x10000000L
665 #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK                                                                0x20000000L
666 //CP_CPC_STALLED_STAT1
667 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT                                                       0x3
668 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT                                                      0x4
669 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT                                                       0x6
670 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT                                                     0x8
671 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT                                                        0x9
672 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT                                                   0xa
673 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT                                                    0xd
674 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT                                                     0x10
675 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT                                                        0x11
676 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT                                                   0x12
677 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT                                                    0x15
678 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x16
679 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x17
680 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT                                                   0x18
681 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK                                                         0x00000008L
682 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK                                                        0x00000010L
683 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK                                                         0x00000040L
684 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK                                                       0x00000100L
685 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK                                                          0x00000200L
686 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK                                                     0x00000400L
687 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK                                                      0x00002000L
688 #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK                                                       0x00010000L
689 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK                                                          0x00020000L
690 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK                                                     0x00040000L
691 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK                                                      0x00200000L
692 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00400000L
693 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00800000L
694 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK                                                     0x01000000L
695 //CP_CPF_STATUS
696 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT                                                              0x0
697 #define CP_CPF_STATUS__CSF_BUSY__SHIFT                                                                        0x1
698 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT                                                                  0x4
699 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT                                                                   0x5
700 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT                                                              0x6
701 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT                                                              0x7
702 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT                                                                  0x8
703 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT                                                                0x9
704 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                           0xa
705 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                           0xb
706 #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT                                                                  0xc
707 #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT                                                                  0xd
708 #define CP_CPF_STATUS__TCIU_BUSY__SHIFT                                                                       0xe
709 #define CP_CPF_STATUS__HQD_BUSY__SHIFT                                                                        0xf
710 #define CP_CPF_STATUS__PRT_BUSY__SHIFT                                                                        0x10
711 #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT                                                                    0x11
712 #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT                                                                    0x1a
713 #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT                                                                    0x1b
714 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT                                                              0x1c
715 #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT                                                                    0x1e
716 #define CP_CPF_STATUS__CPF_BUSY__SHIFT                                                                        0x1f
717 #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK                                                                0x00000001L
718 #define CP_CPF_STATUS__CSF_BUSY_MASK                                                                          0x00000002L
719 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK                                                                    0x00000010L
720 #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK                                                                     0x00000020L
721 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK                                                                0x00000040L
722 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK                                                                0x00000080L
723 #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK                                                                    0x00000100L
724 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK                                                                  0x00000200L
725 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK                                                             0x00000400L
726 #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK                                                             0x00000800L
727 #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK                                                                    0x00001000L
728 #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK                                                                    0x00002000L
729 #define CP_CPF_STATUS__TCIU_BUSY_MASK                                                                         0x00004000L
730 #define CP_CPF_STATUS__HQD_BUSY_MASK                                                                          0x00008000L
731 #define CP_CPF_STATUS__PRT_BUSY_MASK                                                                          0x00010000L
732 #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK                                                                      0x00020000L
733 #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK                                                                      0x04000000L
734 #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK                                                                      0x08000000L
735 #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK                                                                0x30000000L
736 #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK                                                                      0x40000000L
737 #define CP_CPF_STATUS__CPF_BUSY_MASK                                                                          0x80000000L
738 //CP_CPF_BUSY_STAT
739 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                            0x0
740 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT                                                                0x1
741 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT                                                           0x2
742 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT                                                           0x3
743 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT                                                               0x4
744 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT                                                            0x5
745 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT                                                            0x6
746 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT                                                             0x7
747 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT                                                               0x8
748 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT                                                        0x9
749 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT                                                      0xb
750 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT                                                            0xc
751 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT                                                            0xd
752 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT                                                         0xe
753 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT                                                      0xf
754 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT                                                    0x10
755 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT                                                             0x11
756 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT                                                          0x12
757 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT                                                          0x13
758 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT                                                          0x14
759 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT                                                         0x15
760 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT                                                       0x16
761 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT                                                         0x17
762 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT                                                           0x18
763 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT                                                             0x19
764 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT                                                              0x1a
765 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT                                                              0x1b
766 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT                                                              0x1c
767 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT                                                           0x1d
768 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT                                                                  0x1e
769 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT                                                                  0x1f
770 #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                              0x00000001L
771 #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK                                                                  0x00000002L
772 #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK                                                             0x00000004L
773 #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK                                                             0x00000008L
774 #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK                                                                 0x00000010L
775 #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK                                                              0x00000020L
776 #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK                                                              0x00000040L
777 #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK                                                               0x00000080L
778 #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK                                                                 0x00000100L
779 #define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK                                                          0x00000200L
780 #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK                                                        0x00000800L
781 #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK                                                              0x00001000L
782 #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK                                                              0x00002000L
783 #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK                                                           0x00004000L
784 #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK                                                        0x00008000L
785 #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK                                                      0x00010000L
786 #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK                                                               0x00020000L
787 #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK                                                            0x00040000L
788 #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK                                                            0x00080000L
789 #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK                                                            0x00100000L
790 #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK                                                           0x00200000L
791 #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK                                                         0x00400000L
792 #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK                                                           0x00800000L
793 #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK                                                             0x01000000L
794 #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK                                                               0x02000000L
795 #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK                                                                0x04000000L
796 #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK                                                                0x08000000L
797 #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK                                                                0x10000000L
798 #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK                                                             0x20000000L
799 #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK                                                                    0x40000000L
800 #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK                                                                    0x80000000L
801 //CP_CPF_STALLED_STAT1
802 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT                                                       0x0
803 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT                                                      0x1
804 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT                                                      0x2
805 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT                                                      0x3
806 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT                                                     0x5
807 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT                                                     0x6
808 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT                                                  0x7
809 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                  0x8
810 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT                                               0x9
811 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT                                               0xa
812 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT                                                     0xb
813 #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK                                                         0x00000001L
814 #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK                                                        0x00000002L
815 #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK                                                        0x00000004L
816 #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK                                                        0x00000008L
817 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK                                                       0x00000020L
818 #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK                                                       0x00000040L
819 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK                                                    0x00000080L
820 #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK                                                    0x00000100L
821 #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000200L
822 #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK                                                 0x00000400L
823 #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK                                                       0x00000800L
824 //CP_CPC_GRBM_FREE_COUNT
825 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
826 #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x0000003FL
827 //CP_MEC_CNTL
828 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT                                                             0x4
829 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT                                                               0x10
830 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT                                                               0x11
831 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT                                                               0x12
832 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT                                                               0x13
833 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT                                                               0x14
834 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT                                                               0x15
835 #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT                                                                      0x1c
836 #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT                                                                      0x1d
837 #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT                                                                      0x1e
838 #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT                                                                      0x1f
839 #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK                                                               0x00000010L
840 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK                                                                 0x00010000L
841 #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK                                                                 0x00020000L
842 #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK                                                                 0x00040000L
843 #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK                                                                 0x00080000L
844 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK                                                                 0x00100000L
845 #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK                                                                 0x00200000L
846 #define CP_MEC_CNTL__MEC_ME2_HALT_MASK                                                                        0x10000000L
847 #define CP_MEC_CNTL__MEC_ME2_STEP_MASK                                                                        0x20000000L
848 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK                                                                        0x40000000L
849 #define CP_MEC_CNTL__MEC_ME1_STEP_MASK                                                                        0x80000000L
850 //CP_MEC_ME1_HEADER_DUMP
851 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
852 #define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
853 //CP_MEC_ME2_HEADER_DUMP
854 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT                                                            0x0
855 #define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK                                                              0xFFFFFFFFL
856 //CP_CPC_SCRATCH_INDEX
857 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                            0x0
858 #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                              0x000001FFL
859 //CP_CPC_SCRATCH_DATA
860 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                              0x0
861 #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                0xFFFFFFFFL
862 //CP_CPF_GRBM_FREE_COUNT
863 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                             0x0
864 #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                               0x00000007L
865 //CP_CPC_HALT_HYST_COUNT
866 #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT                                                                  0x0
867 #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK                                                                    0x0000000FL
868 //CP_PRT_LOD_STATS_CNTL0
869 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT                                                                0x0
870 #define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK                                                                  0xFFFFFFFFL
871 //CP_PRT_LOD_STATS_CNTL1
872 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT                                                                0x0
873 #define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK                                                                  0xFFFFFFFFL
874 //CP_PRT_LOD_STATS_CNTL2
875 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT                                                                0x0
876 #define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK                                                                  0x000003FFL
877 //CP_PRT_LOD_STATS_CNTL3
878 #define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT                                                               0x2
879 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT                                                              0xa
880 #define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT                                                            0x12
881 #define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT                                                       0x13
882 #define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT                                                                0x17
883 #define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT                                                           0x1c
884 #define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK                                                                 0x000003FCL
885 #define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK                                                                0x0003FC00L
886 #define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK                                                              0x00040000L
887 #define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK                                                         0x00080000L
888 #define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK                                                                  0x07800000L
889 #define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK                                                             0x10000000L
890 //CP_CE_COMPARE_COUNT
891 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT                                                             0x0
892 #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK                                                               0xFFFFFFFFL
893 //CP_CE_DE_COUNT
894 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
895 #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
896 //CP_DE_CE_COUNT
897 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT                                                             0x0
898 #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK                                                               0xFFFFFFFFL
899 //CP_DE_LAST_INVAL_COUNT
900 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT                                                       0x0
901 #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK                                                         0xFFFFFFFFL
902 //CP_DE_DE_COUNT
903 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT                                                              0x0
904 #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
905 //CP_STALLED_STAT3
906 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                     0x0
907 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT                                        0x1
908 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT                                     0x2
909 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT                                                       0x3
910 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT                                                       0x4
911 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT                                                      0x5
912 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT                                                0x6
913 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT                                                 0x7
914 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT                                                    0xa
915 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT                                                 0xb
916 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT                                                     0xc
917 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT                                           0xd
918 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT                                                         0xe
919 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT                                                         0xf
920 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0x10
921 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0x11
922 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT                                                      0x12
923 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT                                                      0x13
924 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT                                                       0x14
925 #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK                                                       0x00000001L
926 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK                                          0x00000002L
927 #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK                                       0x00000004L
928 #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK                                                         0x00000008L
929 #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK                                                         0x00000010L
930 #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK                                                        0x00000020L
931 #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK                                                  0x00000040L
932 #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK                                                   0x00000080L
933 #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK                                                      0x00000400L
934 #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK                                                   0x00000800L
935 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK                                                       0x00001000L
936 #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK                                             0x00002000L
937 #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK                                                           0x00004000L
938 #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK                                                           0x00008000L
939 #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00010000L
940 #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00020000L
941 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK                                                        0x00040000L
942 #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK                                                        0x00080000L
943 #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK                                                         0x00100000L
944 //CP_STALLED_STAT1
945 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT                                                   0x0
946 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT                                                   0x2
947 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT                                                 0x4
948 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT                                                 0xa
949 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT                                                 0xb
950 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                  0xc
951 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                                0xd
952 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT                                                   0xe
953 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT                                                  0xf
954 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT                                                     0x17
955 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT                                                    0x18
956 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT                                                     0x19
957 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT                                                      0x1a
958 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT                                                     0x1b
959 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT                                                  0x1c
960 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT                                                 0x1d
961 #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK                                                     0x00000001L
962 #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
963 #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK                                                   0x00000010L
964 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK                                                   0x00000400L
965 #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK                                                   0x00000800L
966 #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK                                                    0x00001000L
967 #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                  0x00002000L
968 #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK                                                     0x00004000L
969 #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK                                                    0x00008000L
970 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK                                                       0x00800000L
971 #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK                                                      0x01000000L
972 #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK                                                       0x02000000L
973 #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK                                                        0x04000000L
974 #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK                                                       0x08000000L
975 #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK                                                    0x10000000L
976 #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK                                                   0x20000000L
977 //CP_STALLED_STAT2
978 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT                                                    0x0
979 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT                                                    0x1
980 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT                                                   0x2
981 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT                                                    0x4
982 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT                                                        0x5
983 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT                                                   0x8
984 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT                                                        0x9
985 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT                                                      0xa
986 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT                                                     0xb
987 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT                                                       0xc
988 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT                                                   0xd
989 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT                                                     0xe
990 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT                                                  0xf
991 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x10
992 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT                                                     0x11
993 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT                                                     0x12
994 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT                                                 0x13
995 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT                                               0x14
996 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT                                                  0x15
997 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT                                                   0x16
998 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT                                                0x17
999 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT                                                   0x18
1000 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT                                                   0x19
1001 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT                                                   0x1a
1002 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT                                                    0x1b
1003 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT                                                      0x1c
1004 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT                                              0x1d
1005 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT                                                   0x1e
1006 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT                                                    0x1f
1007 #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK                                                      0x00000001L
1008 #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK                                                      0x00000002L
1009 #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK                                                     0x00000004L
1010 #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK                                                      0x00000010L
1011 #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK                                                          0x00000020L
1012 #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK                                                     0x00000100L
1013 #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK                                                          0x00000200L
1014 #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK                                                        0x00000400L
1015 #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK                                                       0x00000800L
1016 #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK                                                         0x00001000L
1017 #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK                                                     0x00002000L
1018 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK                                                       0x00004000L
1019 #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK                                                    0x00008000L
1020 #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00010000L
1021 #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK                                                       0x00020000L
1022 #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK                                                       0x00040000L
1023 #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK                                                   0x00080000L
1024 #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK                                                 0x00100000L
1025 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK                                                    0x00200000L
1026 #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK                                                     0x00400000L
1027 #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK                                                  0x00800000L
1028 #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK                                                     0x01000000L
1029 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK                                                     0x02000000L
1030 #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK                                                     0x04000000L
1031 #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK                                                      0x08000000L
1032 #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK                                                        0x10000000L
1033 #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK                                                0x20000000L
1034 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK                                                     0x40000000L
1035 #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK                                                      0x80000000L
1036 //CP_BUSY_STAT
1037 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT                                                                0x0
1038 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT                                                               0x6
1039 #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT                                                              0x7
1040 #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT                                                               0x8
1041 #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT                                                                    0x9
1042 #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT                                                                     0xa
1043 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT                                                            0xc
1044 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT                                                           0xd
1045 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT                                                             0xe
1046 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT                                                                 0xf
1047 #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT                                                                   0x11
1048 #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT                                                                    0x12
1049 #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT                                                                    0x13
1050 #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT                                                                  0x14
1051 #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT                                                                     0x15
1052 #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT                                                               0x16
1053 #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK                                                                  0x00000001L
1054 #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK                                                                 0x00000040L
1055 #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK                                                                0x00000080L
1056 #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK                                                                 0x00000100L
1057 #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK                                                                      0x00000200L
1058 #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK                                                                       0x00000400L
1059 #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK                                                              0x00001000L
1060 #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK                                                             0x00002000L
1061 #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK                                                               0x00004000L
1062 #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK                                                                   0x00008000L
1063 #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK                                                                     0x00020000L
1064 #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK                                                                      0x00040000L
1065 #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK                                                                      0x00080000L
1066 #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK                                                                    0x00100000L
1067 #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK                                                                       0x00200000L
1068 #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK                                                                 0x00400000L
1069 //CP_STAT
1070 #define CP_STAT__ROQ_RING_BUSY__SHIFT                                                                         0x9
1071 #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT                                                                    0xa
1072 #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT                                                                    0xb
1073 #define CP_STAT__ROQ_STATE_BUSY__SHIFT                                                                        0xc
1074 #define CP_STAT__DC_BUSY__SHIFT                                                                               0xd
1075 #define CP_STAT__UTCL2IU_BUSY__SHIFT                                                                          0xe
1076 #define CP_STAT__PFP_BUSY__SHIFT                                                                              0xf
1077 #define CP_STAT__MEQ_BUSY__SHIFT                                                                              0x10
1078 #define CP_STAT__ME_BUSY__SHIFT                                                                               0x11
1079 #define CP_STAT__QUERY_BUSY__SHIFT                                                                            0x12
1080 #define CP_STAT__SEMAPHORE_BUSY__SHIFT                                                                        0x13
1081 #define CP_STAT__INTERRUPT_BUSY__SHIFT                                                                        0x14
1082 #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT                                                                     0x15
1083 #define CP_STAT__DMA_BUSY__SHIFT                                                                              0x16
1084 #define CP_STAT__RCIU_BUSY__SHIFT                                                                             0x17
1085 #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT                                                                      0x18
1086 #define CP_STAT__CE_BUSY__SHIFT                                                                               0x1a
1087 #define CP_STAT__TCIU_BUSY__SHIFT                                                                             0x1b
1088 #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT                                                                      0x1c
1089 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT                                                                 0x1d
1090 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT                                                                 0x1e
1091 #define CP_STAT__CP_BUSY__SHIFT                                                                               0x1f
1092 #define CP_STAT__ROQ_RING_BUSY_MASK                                                                           0x00000200L
1093 #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK                                                                      0x00000400L
1094 #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK                                                                      0x00000800L
1095 #define CP_STAT__ROQ_STATE_BUSY_MASK                                                                          0x00001000L
1096 #define CP_STAT__DC_BUSY_MASK                                                                                 0x00002000L
1097 #define CP_STAT__UTCL2IU_BUSY_MASK                                                                            0x00004000L
1098 #define CP_STAT__PFP_BUSY_MASK                                                                                0x00008000L
1099 #define CP_STAT__MEQ_BUSY_MASK                                                                                0x00010000L
1100 #define CP_STAT__ME_BUSY_MASK                                                                                 0x00020000L
1101 #define CP_STAT__QUERY_BUSY_MASK                                                                              0x00040000L
1102 #define CP_STAT__SEMAPHORE_BUSY_MASK                                                                          0x00080000L
1103 #define CP_STAT__INTERRUPT_BUSY_MASK                                                                          0x00100000L
1104 #define CP_STAT__SURFACE_SYNC_BUSY_MASK                                                                       0x00200000L
1105 #define CP_STAT__DMA_BUSY_MASK                                                                                0x00400000L
1106 #define CP_STAT__RCIU_BUSY_MASK                                                                               0x00800000L
1107 #define CP_STAT__SCRATCH_RAM_BUSY_MASK                                                                        0x01000000L
1108 #define CP_STAT__CE_BUSY_MASK                                                                                 0x04000000L
1109 #define CP_STAT__TCIU_BUSY_MASK                                                                               0x08000000L
1110 #define CP_STAT__ROQ_CE_RING_BUSY_MASK                                                                        0x10000000L
1111 #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK                                                                   0x20000000L
1112 #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK                                                                   0x40000000L
1113 #define CP_STAT__CP_BUSY_MASK                                                                                 0x80000000L
1114 //CP_ME_HEADER_DUMP
1115 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT                                                              0x0
1116 #define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
1117 //CP_PFP_HEADER_DUMP
1118 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT                                                            0x0
1119 #define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK                                                              0xFFFFFFFFL
1120 //CP_GRBM_FREE_COUNT
1121 #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT                                                                 0x0
1122 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT                                                             0x8
1123 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT                                                             0x10
1124 #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK                                                                   0x0000003FL
1125 #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK                                                               0x00003F00L
1126 #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK                                                               0x003F0000L
1127 //CP_CE_HEADER_DUMP
1128 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT                                                              0x0
1129 #define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK                                                                0xFFFFFFFFL
1130 //CP_PFP_INSTR_PNTR
1131 #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                  0x0
1132 #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK                                                                    0x0000FFFFL
1133 //CP_ME_INSTR_PNTR
1134 #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
1135 #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
1136 //CP_CE_INSTR_PNTR
1137 #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                   0x0
1138 #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK                                                                     0x0000FFFFL
1139 //CP_MEC1_INSTR_PNTR
1140 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
1141 #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
1142 //CP_MEC2_INSTR_PNTR
1143 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT                                                                 0x0
1144 #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK                                                                   0x0000FFFFL
1145 //CP_CSF_STAT
1146 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT                                                              0x8
1147 #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK                                                                0x0001FF00L
1148 //CP_ME_CNTL
1149 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT                                                               0x4
1150 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT                                                              0x6
1151 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT                                                               0x8
1152 #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT                                                                     0x10
1153 #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT                                                                     0x11
1154 #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT                                                                    0x12
1155 #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT                                                                    0x13
1156 #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT                                                                     0x14
1157 #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT                                                                     0x15
1158 #define CP_ME_CNTL__CE_HALT__SHIFT                                                                            0x18
1159 #define CP_ME_CNTL__CE_STEP__SHIFT                                                                            0x19
1160 #define CP_ME_CNTL__PFP_HALT__SHIFT                                                                           0x1a
1161 #define CP_ME_CNTL__PFP_STEP__SHIFT                                                                           0x1b
1162 #define CP_ME_CNTL__ME_HALT__SHIFT                                                                            0x1c
1163 #define CP_ME_CNTL__ME_STEP__SHIFT                                                                            0x1d
1164 #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK                                                                 0x00000010L
1165 #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK                                                                0x00000040L
1166 #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK                                                                 0x00000100L
1167 #define CP_ME_CNTL__CE_PIPE0_RESET_MASK                                                                       0x00010000L
1168 #define CP_ME_CNTL__CE_PIPE1_RESET_MASK                                                                       0x00020000L
1169 #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK                                                                      0x00040000L
1170 #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK                                                                      0x00080000L
1171 #define CP_ME_CNTL__ME_PIPE0_RESET_MASK                                                                       0x00100000L
1172 #define CP_ME_CNTL__ME_PIPE1_RESET_MASK                                                                       0x00200000L
1173 #define CP_ME_CNTL__CE_HALT_MASK                                                                              0x01000000L
1174 #define CP_ME_CNTL__CE_STEP_MASK                                                                              0x02000000L
1175 #define CP_ME_CNTL__PFP_HALT_MASK                                                                             0x04000000L
1176 #define CP_ME_CNTL__PFP_STEP_MASK                                                                             0x08000000L
1177 #define CP_ME_CNTL__ME_HALT_MASK                                                                              0x10000000L
1178 #define CP_ME_CNTL__ME_STEP_MASK                                                                              0x20000000L
1179 //CP_CNTX_STAT
1180 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT                                                             0x0
1181 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT                                                             0x8
1182 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT                                                              0x14
1183 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT                                                              0x1c
1184 #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK                                                               0x000000FFL
1185 #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK                                                               0x00000700L
1186 #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK                                                                0x0FF00000L
1187 #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK                                                                0x70000000L
1188 //CP_ME_PREEMPTION
1189 #define CP_ME_PREEMPTION__OBSOLETE__SHIFT                                                                     0x0
1190 #define CP_ME_PREEMPTION__OBSOLETE_MASK                                                                       0x00000001L
1191 //CP_ROQ_THRESHOLDS
1192 #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT                                                                   0x0
1193 #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT                                                                   0x8
1194 #define CP_ROQ_THRESHOLDS__IB1_START_MASK                                                                     0x000000FFL
1195 #define CP_ROQ_THRESHOLDS__IB2_START_MASK                                                                     0x0000FF00L
1196 //CP_MEQ_STQ_THRESHOLD
1197 #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT                                                                0x0
1198 #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK                                                                  0x000000FFL
1199 //CP_RB2_RPTR
1200 #define CP_RB2_RPTR__RB_RPTR__SHIFT                                                                           0x0
1201 #define CP_RB2_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1202 //CP_RB1_RPTR
1203 #define CP_RB1_RPTR__RB_RPTR__SHIFT                                                                           0x0
1204 #define CP_RB1_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1205 //CP_RB0_RPTR
1206 #define CP_RB0_RPTR__RB_RPTR__SHIFT                                                                           0x0
1207 #define CP_RB0_RPTR__RB_RPTR_MASK                                                                             0x000FFFFFL
1208 //CP_RB_RPTR
1209 #define CP_RB_RPTR__RB_RPTR__SHIFT                                                                            0x0
1210 #define CP_RB_RPTR__RB_RPTR_MASK                                                                              0x000FFFFFL
1211 //CP_RB_WPTR_DELAY
1212 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT                                                              0x0
1213 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT                                                              0x1c
1214 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK                                                                0x0FFFFFFFL
1215 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK                                                                0xF0000000L
1216 //CP_RB_WPTR_POLL_CNTL
1217 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT                                                           0x0
1218 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                          0x10
1219 #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK                                                             0x0000FFFFL
1220 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                            0xFFFF0000L
1221 //CP_ROQ1_THRESHOLDS
1222 #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT                                                                  0x0
1223 #define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT                                                                  0x8
1224 #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT                                                               0x10
1225 #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT                                                               0x18
1226 #define CP_ROQ1_THRESHOLDS__RB1_START_MASK                                                                    0x000000FFL
1227 #define CP_ROQ1_THRESHOLDS__RB2_START_MASK                                                                    0x0000FF00L
1228 #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK                                                                 0x00FF0000L
1229 #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK                                                                 0xFF000000L
1230 //CP_ROQ2_THRESHOLDS
1231 #define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT                                                               0x0
1232 #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT                                                               0x8
1233 #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT                                                               0x10
1234 #define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT                                                               0x18
1235 #define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK                                                                 0x000000FFL
1236 #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK                                                                 0x0000FF00L
1237 #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK                                                                 0x00FF0000L
1238 #define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK                                                                 0xFF000000L
1239 //CP_STQ_THRESHOLDS
1240 #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT                                                                  0x0
1241 #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT                                                                  0x8
1242 #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT                                                                  0x10
1243 #define CP_STQ_THRESHOLDS__STQ0_START_MASK                                                                    0x000000FFL
1244 #define CP_STQ_THRESHOLDS__STQ1_START_MASK                                                                    0x0000FF00L
1245 #define CP_STQ_THRESHOLDS__STQ2_START_MASK                                                                    0x00FF0000L
1246 //CP_QUEUE_THRESHOLDS
1247 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT                                                             0x0
1248 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT                                                             0x8
1249 #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK                                                               0x0000003FL
1250 #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK                                                               0x00003F00L
1251 //CP_MEQ_THRESHOLDS
1252 #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT                                                                  0x0
1253 #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT                                                                  0x8
1254 #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK                                                                    0x000000FFL
1255 #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK                                                                    0x0000FF00L
1256 //CP_ROQ_AVAIL
1257 #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT                                                                     0x0
1258 #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT                                                                      0x10
1259 #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK                                                                       0x000007FFL
1260 #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK                                                                        0x07FF0000L
1261 //CP_STQ_AVAIL
1262 #define CP_STQ_AVAIL__STQ_CNT__SHIFT                                                                          0x0
1263 #define CP_STQ_AVAIL__STQ_CNT_MASK                                                                            0x000001FFL
1264 //CP_ROQ2_AVAIL
1265 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT                                                                     0x0
1266 #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK                                                                       0x000007FFL
1267 //CP_MEQ_AVAIL
1268 #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT                                                                          0x0
1269 #define CP_MEQ_AVAIL__MEQ_CNT_MASK                                                                            0x000003FFL
1270 //CP_CMD_INDEX
1271 #define CP_CMD_INDEX__CMD_INDEX__SHIFT                                                                        0x0
1272 #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT                                                                       0xc
1273 #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT                                                                    0x10
1274 #define CP_CMD_INDEX__CMD_INDEX_MASK                                                                          0x000007FFL
1275 #define CP_CMD_INDEX__CMD_ME_SEL_MASK                                                                         0x00003000L
1276 #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK                                                                      0x00070000L
1277 //CP_CMD_DATA
1278 #define CP_CMD_DATA__CMD_DATA__SHIFT                                                                          0x0
1279 #define CP_CMD_DATA__CMD_DATA_MASK                                                                            0xFFFFFFFFL
1280 //CP_ROQ_RB_STAT
1281 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT                                                               0x0
1282 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT                                                               0x10
1283 #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK                                                                 0x000003FFL
1284 #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK                                                                 0x03FF0000L
1285 //CP_ROQ_IB1_STAT
1286 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT                                                            0x0
1287 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT                                                            0x10
1288 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK                                                              0x000003FFL
1289 #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK                                                              0x03FF0000L
1290 //CP_ROQ_IB2_STAT
1291 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT                                                            0x0
1292 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT                                                            0x10
1293 #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK                                                              0x000003FFL
1294 #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK                                                              0x03FF0000L
1295 //CP_STQ_STAT
1296 #define CP_STQ_STAT__STQ_RPTR__SHIFT                                                                          0x0
1297 #define CP_STQ_STAT__STQ_RPTR_MASK                                                                            0x000003FFL
1298 //CP_STQ_WR_STAT
1299 #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT                                                                       0x0
1300 #define CP_STQ_WR_STAT__STQ_WPTR_MASK                                                                         0x000003FFL
1301 //CP_MEQ_STAT
1302 #define CP_MEQ_STAT__MEQ_RPTR__SHIFT                                                                          0x0
1303 #define CP_MEQ_STAT__MEQ_WPTR__SHIFT                                                                          0x10
1304 #define CP_MEQ_STAT__MEQ_RPTR_MASK                                                                            0x000003FFL
1305 #define CP_MEQ_STAT__MEQ_WPTR_MASK                                                                            0x03FF0000L
1306 //CP_CEQ1_AVAIL
1307 #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT                                                                    0x0
1308 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT                                                                     0x10
1309 #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK                                                                      0x000007FFL
1310 #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK                                                                       0x07FF0000L
1311 //CP_CEQ2_AVAIL
1312 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT                                                                     0x0
1313 #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK                                                                       0x000007FFL
1314 //CP_CE_ROQ_RB_STAT
1315 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT                                                            0x0
1316 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT                                                            0x10
1317 #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK                                                              0x000003FFL
1318 #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK                                                              0x03FF0000L
1319 //CP_CE_ROQ_IB1_STAT
1320 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT                                                         0x0
1321 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT                                                         0x10
1322 #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK                                                           0x000003FFL
1323 #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK                                                           0x03FF0000L
1324 //CP_CE_ROQ_IB2_STAT
1325 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT                                                         0x0
1326 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT                                                         0x10
1327 #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK                                                           0x000003FFL
1328 #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK                                                           0x03FF0000L
1329 //CP_INT_STAT_DEBUG
1330 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT                                              0xb
1331 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                                   0xe
1332 #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                            0x10
1333 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                               0x11
1334 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT                                                       0x12
1335 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT                                                      0x13
1336 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT                                                     0x14
1337 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT                                                       0x15
1338 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT                                                     0x16
1339 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                       0x17
1340 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                                   0x18
1341 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                     0x1a
1342 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                             0x1b
1343 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                       0x1d
1344 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                       0x1e
1345 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                       0x1f
1346 #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK                                                0x00000800L
1347 #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                     0x00004000L
1348 #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                              0x00010000L
1349 #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                                 0x00020000L
1350 #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK                                                         0x00040000L
1351 #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK                                                        0x00080000L
1352 #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK                                                       0x00100000L
1353 #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK                                                         0x00200000L
1354 #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK                                                       0x00400000L
1355 #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                         0x00800000L
1356 #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                     0x01000000L
1357 #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                       0x04000000L
1358 #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                               0x08000000L
1359 #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                         0x20000000L
1360 #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                         0x40000000L
1361 #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                         0x80000000L
1362 
1363 
1364 // addressBlock: gc_padec
1365 //VGT_VTX_VECT_EJECT_REG
1366 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT                                                             0x0
1367 #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK                                                               0x0000007FL
1368 //VGT_DMA_DATA_FIFO_DEPTH
1369 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT                                                   0x0
1370 #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT                                                   0x9
1371 #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK                                                     0x000001FFL
1372 #define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK                                                     0x0007FE00L
1373 //VGT_DMA_REQ_FIFO_DEPTH
1374 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT                                                     0x0
1375 #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK                                                       0x0000003FL
1376 //VGT_DRAW_INIT_FIFO_DEPTH
1377 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT                                                 0x0
1378 #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK                                                   0x0000003FL
1379 //VGT_LAST_COPY_STATE
1380 #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT                                                              0x0
1381 #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT                                                              0x10
1382 #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK                                                                0x00000007L
1383 #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK                                                                0x00070000L
1384 //VGT_CACHE_INVALIDATION
1385 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT                                                     0x0
1386 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT                                                     0x4
1387 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT                                                     0x5
1388 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT                                                          0x6
1389 #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT                                                            0x9
1390 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT                                                   0xb
1391 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT                                                       0xc
1392 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT                                                   0xd
1393 #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT                                                               0x10
1394 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT                                                       0x15
1395 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT                                                        0x16
1396 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT                                                        0x19
1397 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT                                                          0x1c
1398 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT                                                   0x1d
1399 #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK                                                       0x00000003L
1400 #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK                                                       0x00000010L
1401 #define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK                                                       0x00000020L
1402 #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK                                                            0x000000C0L
1403 #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK                                                              0x00000200L
1404 #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK                                                     0x00000800L
1405 #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK                                                         0x00001000L
1406 #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK                                                     0x00002000L
1407 #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK                                                                 0x001F0000L
1408 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK                                                         0x00200000L
1409 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK                                                          0x01C00000L
1410 #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK                                                          0x0E000000L
1411 #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK                                                            0x10000000L
1412 #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK                                                     0x20000000L
1413 //VGT_RESET_DEBUG
1414 #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT                                                                    0x0
1415 #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT                                                                  0x1
1416 #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT                                                                    0x2
1417 #define VGT_RESET_DEBUG__GS_DISABLE_MASK                                                                      0x00000001L
1418 #define VGT_RESET_DEBUG__TESS_DISABLE_MASK                                                                    0x00000002L
1419 #define VGT_RESET_DEBUG__WD_DISABLE_MASK                                                                      0x00000004L
1420 //VGT_STRMOUT_DELAY
1421 #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT                                                                  0x0
1422 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT                                                                0x8
1423 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT                                                                0xb
1424 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT                                                                0xe
1425 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT                                                                0x11
1426 #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK                                                                    0x000000FFL
1427 #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK                                                                  0x00000700L
1428 #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK                                                                  0x00003800L
1429 #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK                                                                  0x0001C000L
1430 #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK                                                                  0x000E0000L
1431 //VGT_FIFO_DEPTHS
1432 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT                                                          0x0
1433 #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT                                                                    0x7
1434 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT                                                              0x8
1435 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT                                                            0x16
1436 #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK                                                            0x0000007FL
1437 #define VGT_FIFO_DEPTHS__RESERVED_0_MASK                                                                      0x00000080L
1438 #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK                                                                0x003FFF00L
1439 #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK                                                              0x0FC00000L
1440 //VGT_GS_VERTEX_REUSE
1441 #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT                                                                0x0
1442 #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK                                                                  0x0000001FL
1443 //VGT_MC_LAT_CNTL
1444 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT                                                             0x0
1445 #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK                                                               0x0000000FL
1446 //IA_CNTL_STATUS
1447 #define IA_CNTL_STATUS__IA_BUSY__SHIFT                                                                        0x0
1448 #define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT                                                                    0x1
1449 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT                                                                0x2
1450 #define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT                                                                    0x3
1451 #define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT                                                                    0x4
1452 #define IA_CNTL_STATUS__IA_BUSY_MASK                                                                          0x00000001L
1453 #define IA_CNTL_STATUS__IA_DMA_BUSY_MASK                                                                      0x00000002L
1454 #define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK                                                                  0x00000004L
1455 #define IA_CNTL_STATUS__IA_GRP_BUSY_MASK                                                                      0x00000008L
1456 #define IA_CNTL_STATUS__IA_ADC_BUSY_MASK                                                                      0x00000010L
1457 //VGT_CNTL_STATUS
1458 #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT                                                                      0x0
1459 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT                                                             0x1
1460 #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT                                                                  0x2
1461 #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT                                                                   0x3
1462 #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT                                                                   0x4
1463 #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT                                                                   0x5
1464 #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT                                                                   0x6
1465 #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT                                                                   0x7
1466 #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT                                                                   0x8
1467 #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT                                                                 0x9
1468 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT                                                              0xa
1469 #define VGT_CNTL_STATUS__VGT_BUSY_MASK                                                                        0x00000001L
1470 #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK                                                               0x00000002L
1471 #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK                                                                    0x00000004L
1472 #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK                                                                     0x00000008L
1473 #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK                                                                     0x00000010L
1474 #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK                                                                     0x00000020L
1475 #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK                                                                     0x00000040L
1476 #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK                                                                     0x00000080L
1477 #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK                                                                     0x00000100L
1478 #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK                                                                   0x00000200L
1479 #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK                                                                0x00000400L
1480 //WD_CNTL_STATUS
1481 #define WD_CNTL_STATUS__WD_BUSY__SHIFT                                                                        0x0
1482 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT                                                                0x1
1483 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT                                                                 0x2
1484 #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT                                                                    0x3
1485 #define WD_CNTL_STATUS__WD_BUSY_MASK                                                                          0x00000001L
1486 #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK                                                                  0x00000002L
1487 #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK                                                                   0x00000004L
1488 #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK                                                                      0x00000008L
1489 //CC_GC_PRIM_CONFIG
1490 #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                                 0x10
1491 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                             0x18
1492 #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK                                                                   0x00030000L
1493 #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                               0x0F000000L
1494 //GC_USER_PRIM_CONFIG
1495 #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT                                                               0x10
1496 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT                                                           0x18
1497 #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK                                                                 0x00030000L
1498 #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK                                                             0x0F000000L
1499 //WD_QOS
1500 #define WD_QOS__DRAW_STALL__SHIFT                                                                             0x0
1501 #define WD_QOS__DRAW_STALL_MASK                                                                               0x00000001L
1502 //WD_UTCL1_CNTL
1503 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
1504 #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
1505 #define WD_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
1506 #define WD_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
1507 #define WD_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
1508 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
1509 #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
1510 #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                             0x1d
1511 #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
1512 #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
1513 #define WD_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
1514 #define WD_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
1515 #define WD_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
1516 #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
1517 #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
1518 #define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                               0x20000000L
1519 //WD_UTCL1_STATUS
1520 #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
1521 #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
1522 #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
1523 #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
1524 #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
1525 #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
1526 #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
1527 #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
1528 #define WD_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
1529 #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
1530 #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
1531 #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
1532 //IA_UTCL1_CNTL
1533 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                            0x0
1534 #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                 0x17
1535 #define IA_UTCL1_CNTL__DROP_MODE__SHIFT                                                                       0x18
1536 #define IA_UTCL1_CNTL__BYPASS__SHIFT                                                                          0x19
1537 #define IA_UTCL1_CNTL__INVALIDATE__SHIFT                                                                      0x1a
1538 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                 0x1b
1539 #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                     0x1c
1540 #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                             0x1d
1541 #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                              0x000FFFFFL
1542 #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                   0x00800000L
1543 #define IA_UTCL1_CNTL__DROP_MODE_MASK                                                                         0x01000000L
1544 #define IA_UTCL1_CNTL__BYPASS_MASK                                                                            0x02000000L
1545 #define IA_UTCL1_CNTL__INVALIDATE_MASK                                                                        0x04000000L
1546 #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                   0x08000000L
1547 #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                       0x10000000L
1548 #define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                               0x20000000L
1549 //IA_UTCL1_STATUS
1550 #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
1551 #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
1552 #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
1553 #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                 0x8
1554 #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                 0x10
1555 #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                   0x18
1556 #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
1557 #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
1558 #define IA_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
1559 #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                   0x00003F00L
1560 #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                   0x003F0000L
1561 #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                     0x3F000000L
1562 //VGT_SYS_CONFIG
1563 #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT                                                                   0x0
1564 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT                                                               0x1
1565 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT                                                       0x7
1566 #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK                                                                     0x00000001L
1567 #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK                                                                 0x0000007EL
1568 #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK                                                         0x00000080L
1569 //VGT_VS_MAX_WAVE_ID
1570 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
1571 #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
1572 //VGT_GS_MAX_WAVE_ID
1573 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
1574 #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
1575 //GFX_PIPE_CONTROL
1576 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT                                                               0x0
1577 #define GFX_PIPE_CONTROL__RESERVED__SHIFT                                                                     0xd
1578 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT                                                           0x10
1579 #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK                                                                 0x00001FFFL
1580 #define GFX_PIPE_CONTROL__RESERVED_MASK                                                                       0x0000E000L
1581 #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK                                                             0x00010000L
1582 //CC_GC_SHADER_ARRAY_CONFIG
1583 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT                                                        0x10
1584 #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK                                                          0xFFFF0000L
1585 //GC_USER_SHADER_ARRAY_CONFIG
1586 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT                                                      0x10
1587 #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK                                                        0xFFFF0000L
1588 //VGT_DMA_PRIMITIVE_TYPE
1589 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                              0x0
1590 #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                0x0000003FL
1591 //VGT_DMA_CONTROL
1592 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT                                                                0x0
1593 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT                                                              0x11
1594 #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT                                                                 0x13
1595 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT                                                              0x14
1596 #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT                                                             0x15
1597 #define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT                                                               0x16
1598 #define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT                                                                   0x17
1599 #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK                                                                  0x0000FFFFL
1600 #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK                                                                0x00020000L
1601 #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK                                                                   0x00080000L
1602 #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK                                                                0x00100000L
1603 #define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK                                                               0x00200000L
1604 #define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK                                                                 0x00400000L
1605 #define VGT_DMA_CONTROL__HW_USE_ONLY_MASK                                                                     0x00800000L
1606 //VGT_DMA_LS_HS_CONFIG
1607 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                          0x8
1608 #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                            0x00003F00L
1609 //WD_BUF_RESOURCE_1
1610 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT                                                                0x0
1611 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT                                                              0x10
1612 #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK                                                                  0x0000FFFFL
1613 #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK                                                                0xFFFF0000L
1614 //WD_BUF_RESOURCE_2
1615 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT                                                              0x0
1616 #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT                                                                   0xf
1617 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT                                                            0x10
1618 #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK                                                                0x00001FFFL
1619 #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK                                                                     0x00008000L
1620 #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK                                                              0xFFFF0000L
1621 //PA_CL_CNTL_STATUS
1622 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT                                                          0x0
1623 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT                                                          0x1
1624 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT                                                            0x2
1625 #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK                                                            0x00000001L
1626 #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK                                                            0x00000002L
1627 #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK                                                              0x00000004L
1628 //PA_CL_ENHANCE
1629 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT                                                            0x0
1630 #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT                                                                    0x1
1631 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT                                                          0x3
1632 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT                                                             0x4
1633 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT                                                              0x5
1634 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT                                                           0x6
1635 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT                                                           0x7
1636 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT                                                                0x8
1637 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT                                                0x9
1638 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT                                                          0xb
1639 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT                                                       0xc
1640 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT                                                     0xe
1641 #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT                                                                      0x1c
1642 #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT                                                                      0x1d
1643 #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT                                                                      0x1e
1644 #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT                                                                      0x1f
1645 #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK                                                              0x00000001L
1646 #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK                                                                      0x00000006L
1647 #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK                                                            0x00000008L
1648 #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK                                                               0x00000010L
1649 #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK                                                                0x00000020L
1650 #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK                                                             0x00000040L
1651 #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK                                                             0x00000080L
1652 #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK                                                                  0x00000100L
1653 #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK                                                  0x00000600L
1654 #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK                                                            0x00000800L
1655 #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK                                                         0x00003000L
1656 #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK                                                       0x0001C000L
1657 #define PA_CL_ENHANCE__ECO_SPARE3_MASK                                                                        0x10000000L
1658 #define PA_CL_ENHANCE__ECO_SPARE2_MASK                                                                        0x20000000L
1659 #define PA_CL_ENHANCE__ECO_SPARE1_MASK                                                                        0x40000000L
1660 #define PA_CL_ENHANCE__ECO_SPARE0_MASK                                                                        0x80000000L
1661 //PA_CL_RESET_DEBUG
1662 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT                                                        0x0
1663 #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK                                                          0x00000001L
1664 //PA_SU_CNTL_STATUS
1665 #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT                                                                     0x1f
1666 #define PA_SU_CNTL_STATUS__SU_BUSY_MASK                                                                       0x80000000L
1667 //PA_SC_FIFO_DEPTH_CNTL
1668 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT                                                                   0x0
1669 #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK                                                                     0x000003FFL
1670 //PA_SC_P3D_TRAP_SCREEN_HV_LOCK
1671 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                         0x0
1672 #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                           0x00000001L
1673 //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
1674 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                        0x0
1675 #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                          0x00000001L
1676 //PA_SC_TRAP_SCREEN_HV_LOCK
1677 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT                                             0x0
1678 #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK                                               0x00000001L
1679 //PA_SC_FORCE_EOV_MAX_CNTS
1680 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT                                                0x0
1681 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT                                                0x10
1682 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK                                                  0x0000FFFFL
1683 #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK                                                  0xFFFF0000L
1684 //PA_SC_BINNER_EVENT_CNTL_0
1685 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT                                                          0x0
1686 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT                                              0x2
1687 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT                                              0x4
1688 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT                                              0x6
1689 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT                                                      0x8
1690 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT                                                        0xa
1691 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT                                                         0xc
1692 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT                                                    0xe
1693 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT                                                  0x10
1694 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT                                                          0x12
1695 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT                                                 0x14
1696 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT                                                 0x16
1697 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT                                                  0x18
1698 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT                                                         0x1a
1699 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT                                                         0x1c
1700 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT                                                    0x1e
1701 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK                                                            0x00000003L
1702 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK                                                0x0000000CL
1703 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK                                                0x00000030L
1704 #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK                                                0x000000C0L
1705 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK                                                        0x00000300L
1706 #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK                                                          0x00000C00L
1707 #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK                                                           0x00003000L
1708 #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK                                                      0x0000C000L
1709 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK                                                    0x00030000L
1710 #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK                                                            0x000C0000L
1711 #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK                                                   0x00300000L
1712 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK                                                   0x00C00000L
1713 #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK                                                    0x03000000L
1714 #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK                                                           0x0C000000L
1715 #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK                                                           0x30000000L
1716 #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK                                                      0xC0000000L
1717 //PA_SC_BINNER_EVENT_CNTL_1
1718 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT                                                    0x0
1719 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT                                                     0x2
1720 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT                                                          0x4
1721 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT                                                 0x6
1722 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT                                        0x8
1723 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT                                                          0xa
1724 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT                                           0xc
1725 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT                                                   0xe
1726 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT                                                    0x10
1727 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT                                                  0x12
1728 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT                                                   0x14
1729 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT                                                  0x16
1730 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT                                                     0x18
1731 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT                                                     0x1a
1732 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT                                                 0x1c
1733 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT                                               0x1e
1734 #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK                                                      0x00000003L
1735 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK                                                       0x0000000CL
1736 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK                                                            0x00000030L
1737 #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK                                                   0x000000C0L
1738 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK                                          0x00000300L
1739 #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK                                                            0x00000C00L
1740 #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK                                             0x00003000L
1741 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK                                                     0x0000C000L
1742 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK                                                      0x00030000L
1743 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK                                                    0x000C0000L
1744 #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK                                                     0x00300000L
1745 #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK                                                    0x00C00000L
1746 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK                                                       0x03000000L
1747 #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK                                                       0x0C000000L
1748 #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK                                                   0x30000000L
1749 #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK                                                 0xC0000000L
1750 //PA_SC_BINNER_EVENT_CNTL_2
1751 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT                                               0x0
1752 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT                                                       0x2
1753 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT                                                  0x4
1754 #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT                                                     0x6
1755 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT                                                           0x8
1756 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT                                                       0xa
1757 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT                                                        0xc
1758 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT                                                      0xe
1759 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT                                                   0x10
1760 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT                                                         0x12
1761 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT                                              0x14
1762 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT                                            0x16
1763 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT                                               0x18
1764 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT                                            0x1a
1765 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT                                               0x1c
1766 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT                                                             0x1e
1767 #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK                                                 0x00000003L
1768 #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK                                                         0x0000000CL
1769 #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK                                                    0x00000030L
1770 #define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK                                                       0x000000C0L
1771 #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK                                                             0x00000300L
1772 #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK                                                         0x00000C00L
1773 #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK                                                          0x00003000L
1774 #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK                                                        0x0000C000L
1775 #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK                                                     0x00030000L
1776 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK                                                           0x000C0000L
1777 #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK                                                0x00300000L
1778 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK                                              0x00C00000L
1779 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK                                                 0x03000000L
1780 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK                                              0x0C000000L
1781 #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK                                                 0x30000000L
1782 #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK                                                               0xC0000000L
1783 //PA_SC_BINNER_EVENT_CNTL_3
1784 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT                                                             0x0
1785 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT                                         0x2
1786 #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT                                               0x4
1787 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT                                                  0x6
1788 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT                                                   0x8
1789 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT                                                 0xa
1790 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT                                                  0xc
1791 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT                                                 0xe
1792 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT                                             0x10
1793 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT                                                0x12
1794 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT                                               0x14
1795 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT                                                     0x16
1796 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT                                                  0x18
1797 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT                                                 0x1a
1798 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT                                              0x1c
1799 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT                                                         0x1e
1800 #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK                                                               0x00000003L
1801 #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK                                           0x0000000CL
1802 #define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK                                                 0x00000030L
1803 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK                                                    0x000000C0L
1804 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK                                                     0x00000300L
1805 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK                                                   0x00000C00L
1806 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK                                                    0x00003000L
1807 #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK                                                   0x0000C000L
1808 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK                                               0x00030000L
1809 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK                                                  0x000C0000L
1810 #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK                                                 0x00300000L
1811 #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK                                                       0x00C00000L
1812 #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK                                                    0x03000000L
1813 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK                                                   0x0C000000L
1814 #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK                                                0x30000000L
1815 #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK                                                           0xC0000000L
1816 //PA_SC_BINNER_TIMEOUT_COUNTER
1817 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT                                                        0x0
1818 #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK                                                          0xFFFFFFFFL
1819 //PA_SC_BINNER_PERF_CNTL_0
1820 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                         0x0
1821 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT                                       0xa
1822 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                       0x14
1823 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT                                     0x17
1824 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK                                           0x000003FFL
1825 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK                                         0x000FFC00L
1826 #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK                                         0x00700000L
1827 #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK                                       0x03800000L
1828 //PA_SC_BINNER_PERF_CNTL_1
1829 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                              0x0
1830 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT                            0x5
1831 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT                         0xa
1832 #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                                0x0000001FL
1833 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK                              0x000003E0L
1834 #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK                           0x03FFFC00L
1835 //PA_SC_BINNER_PERF_CNTL_2
1836 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT                               0x0
1837 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT                             0xb
1838 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK                                 0x000007FFL
1839 #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK                               0x003FF800L
1840 //PA_SC_BINNER_PERF_CNTL_3
1841 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT                              0x0
1842 #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK                                0xFFFFFFFFL
1843 //PA_SC_FIFO_SIZE
1844 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT                                                    0x0
1845 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT                                                     0x6
1846 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT                                                         0xf
1847 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT                                                      0x15
1848 #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK                                                      0x0000003FL
1849 #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK                                                       0x00007FC0L
1850 #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK                                                           0x001F8000L
1851 #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK                                                        0xFFE00000L
1852 //PA_SC_IF_FIFO_SIZE
1853 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT                                                    0x0
1854 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT                                                    0x6
1855 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT                                                        0xc
1856 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT                                                        0x12
1857 #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK                                                      0x0000003FL
1858 #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK                                                      0x00000FC0L
1859 #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK                                                          0x0003F000L
1860 #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK                                                          0x00FC0000L
1861 //PA_SC_PKR_WAVE_TABLE_CNTL
1862 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT                                                                0x0
1863 #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK                                                                  0x0000003FL
1864 //PA_UTCL1_CNTL1
1865 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                               0x0
1866 #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                              0x1
1867 #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                                0x2
1868 #define PA_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                      0x3
1869 #define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                                0x5
1870 #define PA_UTCL1_CNTL1__CLIENTID__SHIFT                                                                       0x7
1871 #define PA_UTCL1_CNTL1__SPARE__SHIFT                                                                          0x10
1872 #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                              0x11
1873 #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                           0x12
1874 #define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                   0x13
1875 #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                               0x17
1876 #define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                 0x18
1877 #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT                                                            0x19
1878 #define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                     0x1a
1879 #define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                 0x1b
1880 #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                         0x1c
1881 #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                         0x1e
1882 #define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                 0x00000001L
1883 #define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK                                                                0x00000002L
1884 #define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                  0x00000004L
1885 #define PA_UTCL1_CNTL1__RESP_MODE_MASK                                                                        0x00000018L
1886 #define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                  0x00000060L
1887 #define PA_UTCL1_CNTL1__CLIENTID_MASK                                                                         0x0000FF80L
1888 #define PA_UTCL1_CNTL1__SPARE_MASK                                                                            0x00010000L
1889 #define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                                0x00020000L
1890 #define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                             0x00040000L
1891 #define PA_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                     0x00780000L
1892 #define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                 0x00800000L
1893 #define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                   0x01000000L
1894 #define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK                                                              0x02000000L
1895 #define PA_UTCL1_CNTL1__FORCE_MISS_MASK                                                                       0x04000000L
1896 #define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                   0x08000000L
1897 #define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                           0x30000000L
1898 #define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                           0xC0000000L
1899 //PA_UTCL1_CNTL2
1900 #define PA_UTCL1_CNTL2__SPARE1__SHIFT                                                                         0x0
1901 #define PA_UTCL1_CNTL2__SPARE2__SHIFT                                                                         0x8
1902 #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                 0x9
1903 #define PA_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                     0xa
1904 #define PA_UTCL1_CNTL2__SPARE3__SHIFT                                                                         0xb
1905 #define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                 0xc
1906 #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT                                                           0xd
1907 #define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                    0xe
1908 #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                            0xf
1909 #define PA_UTCL1_CNTL2__SPARE4__SHIFT                                                                         0x10
1910 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                        0x12
1911 #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                               0x13
1912 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                         0x14
1913 #define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                                0x15
1914 #define PA_UTCL1_CNTL2__SPARE5__SHIFT                                                                         0x19
1915 #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                           0x1a
1916 #define PA_UTCL1_CNTL2__RESERVED__SHIFT                                                                       0x1b
1917 #define PA_UTCL1_CNTL2__SPARE1_MASK                                                                           0x000000FFL
1918 #define PA_UTCL1_CNTL2__SPARE2_MASK                                                                           0x00000100L
1919 #define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                   0x00000200L
1920 #define PA_UTCL1_CNTL2__LINE_VALID_MASK                                                                       0x00000400L
1921 #define PA_UTCL1_CNTL2__SPARE3_MASK                                                                           0x00000800L
1922 #define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                   0x00001000L
1923 #define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK                                                             0x00002000L
1924 #define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                      0x00004000L
1925 #define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                              0x00008000L
1926 #define PA_UTCL1_CNTL2__SPARE4_MASK                                                                           0x00030000L
1927 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                          0x00040000L
1928 #define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                                 0x00080000L
1929 #define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                           0x00100000L
1930 #define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                                  0x01E00000L
1931 #define PA_UTCL1_CNTL2__SPARE5_MASK                                                                           0x02000000L
1932 #define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                             0x04000000L
1933 #define PA_UTCL1_CNTL2__RESERVED_MASK                                                                         0xF8000000L
1934 //PA_SIDEBAND_REQUEST_DELAYS
1935 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT                                                        0x0
1936 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT                                                      0x10
1937 #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK                                                          0x0000FFFFL
1938 #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK                                                        0xFFFF0000L
1939 //PA_SC_ENHANCE
1940 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT                                                       0x0
1941 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT                                                          0x1
1942 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT                                                        0x2
1943 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT                                                  0x3
1944 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT                                               0x4
1945 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT                                                             0x5
1946 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT                                                     0x6
1947 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT                                              0x7
1948 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT                                                   0x8
1949 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT                                              0x9
1950 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT                                                   0xa
1951 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT                                                          0xb
1952 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT                                          0xc
1953 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT                                                 0xd
1954 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT                                             0xe
1955 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT                                                   0xf
1956 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT                                   0x10
1957 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT                                        0x11
1958 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT                               0x12
1959 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT                               0x13
1960 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT                              0x14
1961 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT                                 0x15
1962 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT                                   0x16
1963 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT                           0x17
1964 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT                                          0x18
1965 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT                                       0x19
1966 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT                                                  0x1a
1967 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT                                              0x1b
1968 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT                      0x1c
1969 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT                              0x1d
1970 #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK                                                         0x00000001L
1971 #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK                                                            0x00000002L
1972 #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK                                                          0x00000004L
1973 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK                                                    0x00000008L
1974 #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK                                                 0x00000010L
1975 #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK                                                               0x00000020L
1976 #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK                                                       0x00000040L
1977 #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK                                                0x00000080L
1978 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK                                                     0x00000100L
1979 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK                                                0x00000200L
1980 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK                                                     0x00000400L
1981 #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK                                                            0x00000800L
1982 #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK                                            0x00001000L
1983 #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK                                                   0x00002000L
1984 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK                                               0x00004000L
1985 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK                                                     0x00008000L
1986 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK                                     0x00010000L
1987 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK                                          0x00020000L
1988 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK                                 0x00040000L
1989 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK                                 0x00080000L
1990 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK                                0x00100000L
1991 #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK                                   0x00200000L
1992 #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK                                     0x00400000L
1993 #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK                             0x00800000L
1994 #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK                                            0x01000000L
1995 #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK                                         0x02000000L
1996 #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK                                                    0x04000000L
1997 #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK                                                0x08000000L
1998 #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK                        0x10000000L
1999 #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK                                0x20000000L
2000 //PA_SC_ENHANCE_1
2001 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT                                                0x0
2002 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT                                                       0x1
2003 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT                                                            0x3
2004 #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT                                                                    0x4
2005 #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT                                                                    0x5
2006 #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT                                                                    0x6
2007 #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT                                                                    0x7
2008 #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT                                                                    0x8
2009 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT                                                  0x9
2010 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT                                                       0xa
2011 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT                                     0xb
2012 #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT                                                  0xc
2013 #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT                                              0xd
2014 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT                                       0xe
2015 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT                              0xf
2016 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT                                                    0x10
2017 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT                                       0x11
2018 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT                                                         0x12
2019 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT                                                  0x13
2020 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT                                                  0x14
2021 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT                                          0x15
2022 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT                                          0x16
2023 #define PA_SC_ENHANCE_1__RSVD__SHIFT                                                                          0x17
2024 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK                                                  0x00000001L
2025 #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK                                                         0x00000006L
2026 #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK                                                              0x00000008L
2027 #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK                                                                      0x00000010L
2028 #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK                                                                      0x00000020L
2029 #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK                                                                      0x00000040L
2030 #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK                                                                      0x00000080L
2031 #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK                                                                      0x00000100L
2032 #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK                                                    0x00000200L
2033 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK                                                         0x00000400L
2034 #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK                                       0x00000800L
2035 #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK                                                    0x00001000L
2036 #define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK                                                0x00002000L
2037 #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK                                         0x00004000L
2038 #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK                                0x00008000L
2039 #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK                                                      0x00010000L
2040 #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK                                         0x00020000L
2041 #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK                                                           0x00040000L
2042 #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK                                                    0x00080000L
2043 #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK                                                    0x00100000L
2044 #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK                                            0x00200000L
2045 #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK                                            0x00400000L
2046 #define PA_SC_ENHANCE_1__RSVD_MASK                                                                            0xFF800000L
2047 //PA_SC_DSM_CNTL
2048 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT                                                                0x0
2049 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT                                                                0x1
2050 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK                                                                  0x00000001L
2051 #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK                                                                  0x00000002L
2052 //PA_SC_TILE_STEERING_CREST_OVERRIDE
2053 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT                                         0x0
2054 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT                                                  0x1
2055 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT                                                  0x5
2056 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK                                           0x00000001L
2057 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK                                                    0x00000006L
2058 #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK                                                    0x00000060L
2059 
2060 
2061 // addressBlock: gc_sqdec
2062 //SQ_CONFIG
2063 #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT                                                             0x0
2064 #define SQ_CONFIG__UNUSED__SHIFT                                                                              0x1
2065 #define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT                                                                   0x7
2066 #define SQ_CONFIG__DEBUG_EN__SHIFT                                                                            0x8
2067 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT                                                                  0x9
2068 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT                                                               0xa
2069 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT                                                               0xb
2070 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT                                                               0xc
2071 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT                                                                0xd
2072 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT                                                              0xe
2073 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT                                                       0xf
2074 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT                                                            0x10
2075 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT                                                            0x11
2076 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT                                                         0x12
2077 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT                                                              0x13
2078 #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT                                                                    0x15
2079 #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT                                                          0x1c
2080 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT                                                  0x1d
2081 #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT                                                            0x1e
2082 #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT                                                            0x1f
2083 #define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK                                                               0x00000001L
2084 #define SQ_CONFIG__UNUSED_MASK                                                                                0x0000007EL
2085 #define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK                                                                     0x00000080L
2086 #define SQ_CONFIG__DEBUG_EN_MASK                                                                              0x00000100L
2087 #define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK                                                                    0x00000200L
2088 #define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK                                                                 0x00000400L
2089 #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK                                                                 0x00000800L
2090 #define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK                                                                 0x00001000L
2091 #define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK                                                                  0x00002000L
2092 #define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK                                                                0x00004000L
2093 #define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK                                                         0x00008000L
2094 #define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK                                                              0x00010000L
2095 #define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK                                                              0x00020000L
2096 #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK                                                           0x00040000L
2097 #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK                                                                0x00180000L
2098 #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK                                                                      0x0FE00000L
2099 #define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK                                                            0x10000000L
2100 #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK                                                    0x20000000L
2101 #define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK                                                              0x40000000L
2102 #define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK                                                              0x80000000L
2103 //SQC_CONFIG
2104 #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT                                                                    0x0
2105 #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT                                                                    0x2
2106 #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT                                                                    0x4
2107 #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT                                                                     0x6
2108 #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT                                                                  0x7
2109 #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT                                                                     0x8
2110 #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT                                                                 0x9
2111 #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT                                                                  0xa
2112 #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT                                                               0xb
2113 #define SQC_CONFIG__EVICT_LRU__SHIFT                                                                          0xc
2114 #define SQC_CONFIG__FORCE_2_BANK__SHIFT                                                                       0xe
2115 #define SQC_CONFIG__FORCE_1_BANK__SHIFT                                                                       0xf
2116 #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT                                                                  0x10
2117 #define SQC_CONFIG__INST_PRF_COUNT__SHIFT                                                                     0x18
2118 #define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT                                                                0x1a
2119 #define SQC_CONFIG__INST_CACHE_SIZE_MASK                                                                      0x00000003L
2120 #define SQC_CONFIG__DATA_CACHE_SIZE_MASK                                                                      0x0000000CL
2121 #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK                                                                      0x00000030L
2122 #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK                                                                       0x00000040L
2123 #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK                                                                    0x00000080L
2124 #define SQC_CONFIG__FORCE_IN_ORDER_MASK                                                                       0x00000100L
2125 #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK                                                                   0x00000200L
2126 #define SQC_CONFIG__IDENTITY_HASH_SET_MASK                                                                    0x00000400L
2127 #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK                                                                 0x00000800L
2128 #define SQC_CONFIG__EVICT_LRU_MASK                                                                            0x00003000L
2129 #define SQC_CONFIG__FORCE_2_BANK_MASK                                                                         0x00004000L
2130 #define SQC_CONFIG__FORCE_1_BANK_MASK                                                                         0x00008000L
2131 #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK                                                                    0x00FF0000L
2132 #define SQC_CONFIG__INST_PRF_COUNT_MASK                                                                       0x03000000L
2133 #define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK                                                                  0x04000000L
2134 //LDS_CONFIG
2135 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT                                                        0x0
2136 #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK                                                          0x00000001L
2137 //SQ_RANDOM_WAVE_PRI
2138 #define SQ_RANDOM_WAVE_PRI__RET__SHIFT                                                                        0x0
2139 #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT                                                                        0x7
2140 #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT                                                                        0xa
2141 #define SQ_RANDOM_WAVE_PRI__RET_MASK                                                                          0x0000007FL
2142 #define SQ_RANDOM_WAVE_PRI__RUI_MASK                                                                          0x00000380L
2143 #define SQ_RANDOM_WAVE_PRI__RNG_MASK                                                                          0x007FFC00L
2144 //SQ_REG_CREDITS
2145 #define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT                                                                   0x0
2146 #define SQ_REG_CREDITS__CMD_CREDITS__SHIFT                                                                    0x8
2147 #define SQ_REG_CREDITS__REG_BUSY__SHIFT                                                                       0x1c
2148 #define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT                                                                  0x1d
2149 #define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT                                                                 0x1e
2150 #define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT                                                                   0x1f
2151 #define SQ_REG_CREDITS__SRBM_CREDITS_MASK                                                                     0x0000003FL
2152 #define SQ_REG_CREDITS__CMD_CREDITS_MASK                                                                      0x00000F00L
2153 #define SQ_REG_CREDITS__REG_BUSY_MASK                                                                         0x10000000L
2154 #define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK                                                                    0x20000000L
2155 #define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK                                                                   0x40000000L
2156 #define SQ_REG_CREDITS__CMD_OVERFLOW_MASK                                                                     0x80000000L
2157 //SQ_FIFO_SIZES
2158 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT                                                             0x0
2159 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT                                                                0x8
2160 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT                                                                 0x10
2161 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT                                                             0x12
2162 #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK                                                               0x0000000FL
2163 #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK                                                                  0x00000F00L
2164 #define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK                                                                   0x00030000L
2165 #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK                                                               0x000C0000L
2166 //SQ_DSM_CNTL
2167 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT                                                                 0x0
2168 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT                                                                 0x1
2169 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT                                                                0x2
2170 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT                                                                0x3
2171 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT                                                      0x8
2172 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT                                                      0x9
2173 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT                                                          0xa
2174 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT                                                       0x10
2175 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT                                                       0x11
2176 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT                                                         0x12
2177 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT                                                       0x13
2178 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT                                                       0x14
2179 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT                                                         0x15
2180 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT                                                        0x18
2181 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT                                                        0x19
2182 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT                                                            0x1a
2183 #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK                                                                   0x00000001L
2184 #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK                                                                   0x00000002L
2185 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK                                                                  0x00000004L
2186 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK                                                                  0x00000008L
2187 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK                                                        0x00000100L
2188 #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK                                                        0x00000200L
2189 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK                                                            0x00000400L
2190 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK                                                         0x00010000L
2191 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK                                                         0x00020000L
2192 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK                                                           0x00040000L
2193 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK                                                         0x00080000L
2194 #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK                                                         0x00100000L
2195 #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK                                                           0x00200000L
2196 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK                                                          0x01000000L
2197 #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK                                                          0x02000000L
2198 #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK                                                              0x04000000L
2199 //SQ_DSM_CNTL2
2200 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT                                                         0x0
2201 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT                                                         0x2
2202 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT                                                        0x3
2203 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT                                                        0x5
2204 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT                                                        0x6
2205 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT                                                        0x8
2206 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT                                                           0x9
2207 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT                                                           0xb
2208 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT                                                                 0xe
2209 #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT                                                                  0x14
2210 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT                                                                  0x1a
2211 #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK                                                           0x00000003L
2212 #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK                                                           0x00000004L
2213 #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK                                                          0x00000018L
2214 #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK                                                          0x00000020L
2215 #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK                                                          0x000000C0L
2216 #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK                                                          0x00000100L
2217 #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK                                                             0x00000600L
2218 #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK                                                             0x00000800L
2219 #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK                                                                   0x000FC000L
2220 #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK                                                                    0x03F00000L
2221 #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK                                                                    0xFC000000L
2222 //SQ_RUNTIME_CONFIG
2223 #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT                                                       0x0
2224 #define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK                                                         0x00000001L
2225 //SH_MEM_BASES
2226 #define SH_MEM_BASES__PRIVATE_BASE__SHIFT                                                                     0x0
2227 #define SH_MEM_BASES__SHARED_BASE__SHIFT                                                                      0x10
2228 #define SH_MEM_BASES__PRIVATE_BASE_MASK                                                                       0x0000FFFFL
2229 #define SH_MEM_BASES__SHARED_BASE_MASK                                                                        0xFFFF0000L
2230 //SH_MEM_CONFIG
2231 #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT                                                                    0x0
2232 #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT                                                                  0x3
2233 #define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT                                                                   0xc
2234 #define SH_MEM_CONFIG__PRIVATE_NV__SHIFT                                                                      0xd
2235 #define SH_MEM_CONFIG__ADDRESS_MODE_MASK                                                                      0x00000001L
2236 #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK                                                                    0x00000018L
2237 #define SH_MEM_CONFIG__RETRY_DISABLE_MASK                                                                     0x00001000L
2238 #define SH_MEM_CONFIG__PRIVATE_NV_MASK                                                                        0x00002000L
2239 //CC_GC_SHADER_RATE_CONFIG
2240 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                            0x1
2241 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                  0x3
2242 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT                                                             0x4
2243 #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                              0x00000006L
2244 #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                    0x00000008L
2245 #define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK                                                               0x00000010L
2246 //GC_USER_SHADER_RATE_CONFIG
2247 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT                                                          0x1
2248 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT                                                0x3
2249 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT                                                           0x4
2250 #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK                                                            0x00000006L
2251 #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK                                                  0x00000008L
2252 #define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK                                                             0x00000010L
2253 //SQ_INTERRUPT_AUTO_MASK
2254 #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT                                                                   0x0
2255 #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK                                                                     0x00FFFFFFL
2256 //SQ_INTERRUPT_MSG_CTRL
2257 #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT                                                                   0x0
2258 #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK                                                                     0x00000001L
2259 //SQ_UTCL1_CNTL1
2260 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                               0x0
2261 #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                  0x1
2262 #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                                0x2
2263 #define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                      0x3
2264 #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                                0x5
2265 #define SQ_UTCL1_CNTL1__CLIENTID__SHIFT                                                                       0x7
2266 #define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                     0x10
2267 #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                              0x11
2268 #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                           0x12
2269 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                            0x13
2270 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                        0x17
2271 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                          0x18
2272 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT                                                             0x19
2273 #define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                     0x1a
2274 #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                 0x1b
2275 #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                         0x1c
2276 #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                         0x1e
2277 #define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                 0x00000001L
2278 #define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                    0x00000002L
2279 #define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                  0x00000004L
2280 #define SQ_UTCL1_CNTL1__RESP_MODE_MASK                                                                        0x00000018L
2281 #define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                  0x00000060L
2282 #define SQ_UTCL1_CNTL1__CLIENTID_MASK                                                                         0x0000FF80L
2283 #define SQ_UTCL1_CNTL1__USERVM_DIS_MASK                                                                       0x00010000L
2284 #define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                                0x00020000L
2285 #define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                             0x00040000L
2286 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                              0x00780000L
2287 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                          0x00800000L
2288 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                            0x01000000L
2289 #define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK                                                               0x02000000L
2290 #define SQ_UTCL1_CNTL1__FORCE_MISS_MASK                                                                       0x04000000L
2291 #define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                   0x08000000L
2292 #define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                           0x30000000L
2293 #define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                           0xC0000000L
2294 //SQ_UTCL1_CNTL2
2295 #define SQ_UTCL1_CNTL2__SPARE__SHIFT                                                                          0x0
2296 #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                             0x8
2297 #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                 0x9
2298 #define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                     0xa
2299 #define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                        0xb
2300 #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                 0xc
2301 #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                  0xd
2302 #define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                    0xe
2303 #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                            0xf
2304 #define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT                                                                    0x10
2305 #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                           0x1a
2306 #define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT                                                                  0x1c
2307 #define SQ_UTCL1_CNTL2__SPARE_MASK                                                                            0x000000FFL
2308 #define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                               0x00000100L
2309 #define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                   0x00000200L
2310 #define SQ_UTCL1_CNTL2__LINE_VALID_MASK                                                                       0x00000400L
2311 #define SQ_UTCL1_CNTL2__DIS_EDC_MASK                                                                          0x00000800L
2312 #define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                   0x00001000L
2313 #define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                    0x00002000L
2314 #define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                      0x00004000L
2315 #define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                              0x00008000L
2316 #define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK                                                                      0x007F0000L
2317 #define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                             0x04000000L
2318 #define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK                                                                    0xF0000000L
2319 //SQ_UTCL1_STATUS
2320 #define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                                0x0
2321 #define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                                0x1
2322 #define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                  0x2
2323 #define SQ_UTCL1_STATUS__RESERVED__SHIFT                                                                      0x3
2324 #define SQ_UTCL1_STATUS__UNUSED__SHIFT                                                                        0x10
2325 #define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                  0x00000001L
2326 #define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                  0x00000002L
2327 #define SQ_UTCL1_STATUS__PRT_DETECTED_MASK                                                                    0x00000004L
2328 #define SQ_UTCL1_STATUS__RESERVED_MASK                                                                        0x0000FFF8L
2329 #define SQ_UTCL1_STATUS__UNUSED_MASK                                                                          0xFFFF0000L
2330 //SQ_SHADER_TBA_LO
2331 #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT                                                                      0x0
2332 #define SQ_SHADER_TBA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
2333 //SQ_SHADER_TBA_HI
2334 #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT                                                                      0x0
2335 #define SQ_SHADER_TBA_HI__ADDR_HI_MASK                                                                        0x000000FFL
2336 //SQ_SHADER_TMA_LO
2337 #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT                                                                      0x0
2338 #define SQ_SHADER_TMA_LO__ADDR_LO_MASK                                                                        0xFFFFFFFFL
2339 //SQ_SHADER_TMA_HI
2340 #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT                                                                      0x0
2341 #define SQ_SHADER_TMA_HI__ADDR_HI_MASK                                                                        0x000000FFL
2342 //SQC_DSM_CNTL
2343 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                              0x0
2344 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                             0x2
2345 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x3
2346 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x5
2347 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x6
2348 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x8
2349 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0x9
2350 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0xb
2351 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0xc
2352 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0xe
2353 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT                                       0xf
2354 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT                                      0x11
2355 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT                                          0x12
2356 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT                                         0x14
2357 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                                0x00000003L
2358 #define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                               0x00000004L
2359 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00000018L
2360 #define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00000020L
2361 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x000000C0L
2362 #define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00000100L
2363 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00000600L
2364 #define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00000800L
2365 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x00003000L
2366 #define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00004000L
2367 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK                                         0x00018000L
2368 #define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK                                        0x00020000L
2369 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK                                            0x000C0000L
2370 #define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK                                           0x00100000L
2371 //SQC_DSM_CNTLA
2372 #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0x0
2373 #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0x2
2374 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                         0x3
2375 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                        0x5
2376 #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x6
2377 #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
2378 #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
2379 #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
2380 #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
2381 #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
2382 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                0xf
2383 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
2384 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x12
2385 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
2386 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT                                           0x15
2387 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT                                          0x17
2388 #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x18
2389 #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0x1a
2390 #define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00000003L
2391 #define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000004L
2392 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                           0x00000018L
2393 #define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                          0x00000020L
2394 #define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
2395 #define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
2396 #define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
2397 #define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
2398 #define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
2399 #define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
2400 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
2401 #define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
2402 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
2403 #define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
2404 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK                                             0x00600000L
2405 #define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK                                            0x00800000L
2406 #define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x03000000L
2407 #define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x04000000L
2408 //SQC_DSM_CNTLB
2409 #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0x0
2410 #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0x2
2411 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                         0x3
2412 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                        0x5
2413 #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x6
2414 #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
2415 #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
2416 #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
2417 #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
2418 #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
2419 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                0xf
2420 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
2421 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                               0x12
2422 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                              0x14
2423 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT                                           0x15
2424 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT                                          0x17
2425 #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT                                                0x18
2426 #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT                                               0x1a
2427 #define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00000003L
2428 #define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000004L
2429 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                           0x00000018L
2430 #define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                          0x00000020L
2431 #define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000000C0L
2432 #define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
2433 #define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
2434 #define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
2435 #define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
2436 #define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
2437 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
2438 #define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
2439 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK                                                 0x000C0000L
2440 #define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                0x00100000L
2441 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK                                             0x00600000L
2442 #define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK                                            0x00800000L
2443 #define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK                                                  0x03000000L
2444 #define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK                                                 0x04000000L
2445 //SQC_DSM_CNTL2
2446 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                            0x0
2447 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                            0x2
2448 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0x3
2449 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0x5
2450 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0x6
2451 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0x8
2452 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0x9
2453 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0xb
2454 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0xc
2455 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0xe
2456 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT                                     0xf
2457 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT                                     0x11
2458 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT                                        0x12
2459 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT                                        0x14
2460 #define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
2461 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                              0x00000003L
2462 #define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                              0x00000004L
2463 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00000018L
2464 #define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00000020L
2465 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x000000C0L
2466 #define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00000100L
2467 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00000600L
2468 #define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00000800L
2469 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x00003000L
2470 #define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00004000L
2471 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK                                       0x00018000L
2472 #define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK                                       0x00020000L
2473 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK                                          0x000C0000L
2474 #define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK                                          0x00100000L
2475 #define SQC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
2476 //SQC_DSM_CNTL2A
2477 #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0x0
2478 #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0x2
2479 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2480 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2481 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x6
2482 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x8
2483 #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
2484 #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0xb
2485 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
2486 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
2487 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT                                              0xf
2488 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT                                              0x11
2489 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x12
2490 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x14
2491 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0x15
2492 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x17
2493 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x18
2494 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x1a
2495 #define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
2496 #define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
2497 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2498 #define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2499 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
2500 #define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00000100L
2501 #define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
2502 #define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
2503 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
2504 #define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
2505 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
2506 #define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK                                                0x00020000L
2507 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
2508 #define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00100000L
2509 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
2510 #define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK                                           0x00800000L
2511 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x03000000L
2512 #define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x04000000L
2513 //SQC_DSM_CNTL2B
2514 #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0x0
2515 #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0x2
2516 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x3
2517 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x5
2518 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x6
2519 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x8
2520 #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
2521 #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0xb
2522 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
2523 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT                                               0xe
2524 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT                                              0xf
2525 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT                                              0x11
2526 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0x12
2527 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0x14
2528 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT                                         0x15
2529 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT                                         0x17
2530 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT                                              0x18
2531 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT                                              0x1a
2532 #define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
2533 #define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
2534 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x00000018L
2535 #define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                         0x00000020L
2536 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
2537 #define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00000100L
2538 #define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
2539 #define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
2540 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
2541 #define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
2542 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
2543 #define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK                                                0x00020000L
2544 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x000C0000L
2545 #define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00100000L
2546 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK                                           0x00600000L
2547 #define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK                                           0x00800000L
2548 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK                                                0x03000000L
2549 #define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK                                                0x04000000L
2550 //SQC_EDC_FUE_CNTL
2551 #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                              0x0
2552 #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                        0x10
2553 #define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                0x0000FFFFL
2554 #define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                          0xFFFF0000L
2555 //SQC_EDC_CNT2
2556 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT                                                     0x0
2557 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT                                                     0x2
2558 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT                                                    0x4
2559 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT                                                    0x6
2560 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT                                                     0x8
2561 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT                                                     0xa
2562 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT                                                    0xc
2563 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT                                                    0xe
2564 #define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT                                             0x10
2565 #define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT                                                   0x12
2566 #define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT                                                    0x14
2567 #define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT                                                   0x16
2568 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT                                               0x18
2569 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                       0x1a
2570 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT                                                       0x1c
2571 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK                                                       0x00000003L
2572 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK                                                       0x0000000CL
2573 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK                                                      0x00000030L
2574 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK                                                      0x000000C0L
2575 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK                                                       0x00000300L
2576 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK                                                       0x00000C00L
2577 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK                                                      0x00003000L
2578 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK                                                      0x0000C000L
2579 #define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK                                               0x00030000L
2580 #define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK                                                     0x000C0000L
2581 #define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK                                                      0x00300000L
2582 #define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK                                                     0x00C00000L
2583 #define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK                                                 0x03000000L
2584 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK                                                         0x0C000000L
2585 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK                                                         0x30000000L
2586 //SQC_EDC_CNT3
2587 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT                                                     0x0
2588 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT                                                     0x2
2589 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT                                                    0x4
2590 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT                                                    0x6
2591 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT                                                     0x8
2592 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT                                                     0xa
2593 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT                                                    0xc
2594 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT                                                    0xe
2595 #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT                                             0x10
2596 #define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT                                                   0x12
2597 #define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT                                                    0x14
2598 #define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT                                                   0x16
2599 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT                                               0x18
2600 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK                                                       0x00000003L
2601 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK                                                       0x0000000CL
2602 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK                                                      0x00000030L
2603 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK                                                      0x000000C0L
2604 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK                                                       0x00000300L
2605 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK                                                       0x00000C00L
2606 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK                                                      0x00003000L
2607 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK                                                      0x0000C000L
2608 #define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK                                               0x00030000L
2609 #define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK                                                     0x000C0000L
2610 #define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK                                                      0x00300000L
2611 #define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK                                                     0x00C00000L
2612 #define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK                                                 0x03000000L
2613 //SQ_REG_TIMESTAMP
2614 #define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT                                                                    0x0
2615 #define SQ_REG_TIMESTAMP__TIMESTAMP_MASK                                                                      0x000000FFL
2616 //SQ_CMD_TIMESTAMP
2617 #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT                                                                    0x0
2618 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK                                                                      0x000000FFL
2619 //SQ_IND_INDEX
2620 #define SQ_IND_INDEX__WAVE_ID__SHIFT                                                                          0x0
2621 #define SQ_IND_INDEX__SIMD_ID__SHIFT                                                                          0x4
2622 #define SQ_IND_INDEX__THREAD_ID__SHIFT                                                                        0x6
2623 #define SQ_IND_INDEX__AUTO_INCR__SHIFT                                                                        0xc
2624 #define SQ_IND_INDEX__FORCE_READ__SHIFT                                                                       0xd
2625 #define SQ_IND_INDEX__READ_TIMEOUT__SHIFT                                                                     0xe
2626 #define SQ_IND_INDEX__UNINDEXED__SHIFT                                                                        0xf
2627 #define SQ_IND_INDEX__INDEX__SHIFT                                                                            0x10
2628 #define SQ_IND_INDEX__WAVE_ID_MASK                                                                            0x0000000FL
2629 #define SQ_IND_INDEX__SIMD_ID_MASK                                                                            0x00000030L
2630 #define SQ_IND_INDEX__THREAD_ID_MASK                                                                          0x00000FC0L
2631 #define SQ_IND_INDEX__AUTO_INCR_MASK                                                                          0x00001000L
2632 #define SQ_IND_INDEX__FORCE_READ_MASK                                                                         0x00002000L
2633 #define SQ_IND_INDEX__READ_TIMEOUT_MASK                                                                       0x00004000L
2634 #define SQ_IND_INDEX__UNINDEXED_MASK                                                                          0x00008000L
2635 #define SQ_IND_INDEX__INDEX_MASK                                                                              0xFFFF0000L
2636 //SQ_IND_DATA
2637 #define SQ_IND_DATA__DATA__SHIFT                                                                              0x0
2638 #define SQ_IND_DATA__DATA_MASK                                                                                0xFFFFFFFFL
2639 //SQ_CMD
2640 #define SQ_CMD__CMD__SHIFT                                                                                    0x0
2641 #define SQ_CMD__MODE__SHIFT                                                                                   0x4
2642 #define SQ_CMD__CHECK_VMID__SHIFT                                                                             0x7
2643 #define SQ_CMD__DATA__SHIFT                                                                                   0x8
2644 #define SQ_CMD__WAVE_ID__SHIFT                                                                                0x10
2645 #define SQ_CMD__SIMD_ID__SHIFT                                                                                0x14
2646 #define SQ_CMD__QUEUE_ID__SHIFT                                                                               0x18
2647 #define SQ_CMD__VM_ID__SHIFT                                                                                  0x1c
2648 #define SQ_CMD__CMD_MASK                                                                                      0x00000007L
2649 #define SQ_CMD__MODE_MASK                                                                                     0x00000070L
2650 #define SQ_CMD__CHECK_VMID_MASK                                                                               0x00000080L
2651 #define SQ_CMD__DATA_MASK                                                                                     0x00000F00L
2652 #define SQ_CMD__WAVE_ID_MASK                                                                                  0x000F0000L
2653 #define SQ_CMD__SIMD_ID_MASK                                                                                  0x00300000L
2654 #define SQ_CMD__QUEUE_ID_MASK                                                                                 0x07000000L
2655 #define SQ_CMD__VM_ID_MASK                                                                                    0xF0000000L
2656 //SQ_TIME_HI
2657 #define SQ_TIME_HI__TIME__SHIFT                                                                               0x0
2658 #define SQ_TIME_HI__TIME_MASK                                                                                 0xFFFFFFFFL
2659 //SQ_TIME_LO
2660 #define SQ_TIME_LO__TIME__SHIFT                                                                               0x0
2661 #define SQ_TIME_LO__TIME_MASK                                                                                 0xFFFFFFFFL
2662 //SQ_DS_0
2663 #define SQ_DS_0__OFFSET0__SHIFT                                                                               0x0
2664 #define SQ_DS_0__OFFSET1__SHIFT                                                                               0x8
2665 #define SQ_DS_0__GDS__SHIFT                                                                                   0x10
2666 #define SQ_DS_0__OP__SHIFT                                                                                    0x11
2667 #define SQ_DS_0__ENCODING__SHIFT                                                                              0x1a
2668 #define SQ_DS_0__OFFSET0_MASK                                                                                 0x000000FFL
2669 #define SQ_DS_0__OFFSET1_MASK                                                                                 0x0000FF00L
2670 #define SQ_DS_0__GDS_MASK                                                                                     0x00010000L
2671 #define SQ_DS_0__OP_MASK                                                                                      0x01FE0000L
2672 #define SQ_DS_0__ENCODING_MASK                                                                                0xFC000000L
2673 //SQ_DS_1
2674 #define SQ_DS_1__ADDR__SHIFT                                                                                  0x0
2675 #define SQ_DS_1__DATA0__SHIFT                                                                                 0x8
2676 #define SQ_DS_1__DATA1__SHIFT                                                                                 0x10
2677 #define SQ_DS_1__VDST__SHIFT                                                                                  0x18
2678 #define SQ_DS_1__ADDR_MASK                                                                                    0x000000FFL
2679 #define SQ_DS_1__DATA0_MASK                                                                                   0x0000FF00L
2680 #define SQ_DS_1__DATA1_MASK                                                                                   0x00FF0000L
2681 #define SQ_DS_1__VDST_MASK                                                                                    0xFF000000L
2682 //SQ_EXP_0
2683 #define SQ_EXP_0__EN__SHIFT                                                                                   0x0
2684 #define SQ_EXP_0__TGT__SHIFT                                                                                  0x4
2685 #define SQ_EXP_0__COMPR__SHIFT                                                                                0xa
2686 #define SQ_EXP_0__DONE__SHIFT                                                                                 0xb
2687 #define SQ_EXP_0__VM__SHIFT                                                                                   0xc
2688 #define SQ_EXP_0__ENCODING__SHIFT                                                                             0x1a
2689 #define SQ_EXP_0__EN_MASK                                                                                     0x0000000FL
2690 #define SQ_EXP_0__TGT_MASK                                                                                    0x000003F0L
2691 #define SQ_EXP_0__COMPR_MASK                                                                                  0x00000400L
2692 #define SQ_EXP_0__DONE_MASK                                                                                   0x00000800L
2693 #define SQ_EXP_0__VM_MASK                                                                                     0x00001000L
2694 #define SQ_EXP_0__ENCODING_MASK                                                                               0xFC000000L
2695 //SQ_EXP_1
2696 #define SQ_EXP_1__VSRC0__SHIFT                                                                                0x0
2697 #define SQ_EXP_1__VSRC1__SHIFT                                                                                0x8
2698 #define SQ_EXP_1__VSRC2__SHIFT                                                                                0x10
2699 #define SQ_EXP_1__VSRC3__SHIFT                                                                                0x18
2700 #define SQ_EXP_1__VSRC0_MASK                                                                                  0x000000FFL
2701 #define SQ_EXP_1__VSRC1_MASK                                                                                  0x0000FF00L
2702 #define SQ_EXP_1__VSRC2_MASK                                                                                  0x00FF0000L
2703 #define SQ_EXP_1__VSRC3_MASK                                                                                  0xFF000000L
2704 //SQ_FLAT_0
2705 #define SQ_FLAT_0__OFFSET__SHIFT                                                                              0x0
2706 #define SQ_FLAT_0__LDS__SHIFT                                                                                 0xd
2707 #define SQ_FLAT_0__SEG__SHIFT                                                                                 0xe
2708 #define SQ_FLAT_0__GLC__SHIFT                                                                                 0x10
2709 #define SQ_FLAT_0__SLC__SHIFT                                                                                 0x11
2710 #define SQ_FLAT_0__OP__SHIFT                                                                                  0x12
2711 #define SQ_FLAT_0__ENCODING__SHIFT                                                                            0x1a
2712 #define SQ_FLAT_0__OFFSET_MASK                                                                                0x00000FFFL
2713 #define SQ_FLAT_0__LDS_MASK                                                                                   0x00002000L
2714 #define SQ_FLAT_0__SEG_MASK                                                                                   0x0000C000L
2715 #define SQ_FLAT_0__GLC_MASK                                                                                   0x00010000L
2716 #define SQ_FLAT_0__SLC_MASK                                                                                   0x00020000L
2717 #define SQ_FLAT_0__OP_MASK                                                                                    0x01FC0000L
2718 #define SQ_FLAT_0__ENCODING_MASK                                                                              0xFC000000L
2719 //SQ_FLAT_1
2720 #define SQ_FLAT_1__ADDR__SHIFT                                                                                0x0
2721 #define SQ_FLAT_1__DATA__SHIFT                                                                                0x8
2722 #define SQ_FLAT_1__SADDR__SHIFT                                                                               0x10
2723 #define SQ_FLAT_1__NV__SHIFT                                                                                  0x17
2724 #define SQ_FLAT_1__VDST__SHIFT                                                                                0x18
2725 #define SQ_FLAT_1__ADDR_MASK                                                                                  0x000000FFL
2726 #define SQ_FLAT_1__DATA_MASK                                                                                  0x0000FF00L
2727 #define SQ_FLAT_1__SADDR_MASK                                                                                 0x007F0000L
2728 #define SQ_FLAT_1__NV_MASK                                                                                    0x00800000L
2729 #define SQ_FLAT_1__VDST_MASK                                                                                  0xFF000000L
2730 //SQ_GLBL_0
2731 #define SQ_GLBL_0__OFFSET__SHIFT                                                                              0x0
2732 #define SQ_GLBL_0__LDS__SHIFT                                                                                 0xd
2733 #define SQ_GLBL_0__SEG__SHIFT                                                                                 0xe
2734 #define SQ_GLBL_0__GLC__SHIFT                                                                                 0x10
2735 #define SQ_GLBL_0__SLC__SHIFT                                                                                 0x11
2736 #define SQ_GLBL_0__OP__SHIFT                                                                                  0x12
2737 #define SQ_GLBL_0__ENCODING__SHIFT                                                                            0x1a
2738 #define SQ_GLBL_0__OFFSET_MASK                                                                                0x00001FFFL
2739 #define SQ_GLBL_0__LDS_MASK                                                                                   0x00002000L
2740 #define SQ_GLBL_0__SEG_MASK                                                                                   0x0000C000L
2741 #define SQ_GLBL_0__GLC_MASK                                                                                   0x00010000L
2742 #define SQ_GLBL_0__SLC_MASK                                                                                   0x00020000L
2743 #define SQ_GLBL_0__OP_MASK                                                                                    0x01FC0000L
2744 #define SQ_GLBL_0__ENCODING_MASK                                                                              0xFC000000L
2745 //SQ_GLBL_1
2746 #define SQ_GLBL_1__ADDR__SHIFT                                                                                0x0
2747 #define SQ_GLBL_1__DATA__SHIFT                                                                                0x8
2748 #define SQ_GLBL_1__SADDR__SHIFT                                                                               0x10
2749 #define SQ_GLBL_1__NV__SHIFT                                                                                  0x17
2750 #define SQ_GLBL_1__VDST__SHIFT                                                                                0x18
2751 #define SQ_GLBL_1__ADDR_MASK                                                                                  0x000000FFL
2752 #define SQ_GLBL_1__DATA_MASK                                                                                  0x0000FF00L
2753 #define SQ_GLBL_1__SADDR_MASK                                                                                 0x007F0000L
2754 #define SQ_GLBL_1__NV_MASK                                                                                    0x00800000L
2755 #define SQ_GLBL_1__VDST_MASK                                                                                  0xFF000000L
2756 //SQ_INST
2757 #define SQ_INST__ENCODING__SHIFT                                                                              0x0
2758 #define SQ_INST__ENCODING_MASK                                                                                0xFFFFFFFFL
2759 //SQ_MIMG_0
2760 #define SQ_MIMG_0__OPM__SHIFT                                                                                 0x0
2761 #define SQ_MIMG_0__DMASK__SHIFT                                                                               0x8
2762 #define SQ_MIMG_0__UNORM__SHIFT                                                                               0xc
2763 #define SQ_MIMG_0__GLC__SHIFT                                                                                 0xd
2764 #define SQ_MIMG_0__DA__SHIFT                                                                                  0xe
2765 #define SQ_MIMG_0__A16__SHIFT                                                                                 0xf
2766 #define SQ_MIMG_0__TFE__SHIFT                                                                                 0x10
2767 #define SQ_MIMG_0__LWE__SHIFT                                                                                 0x11
2768 #define SQ_MIMG_0__OP__SHIFT                                                                                  0x12
2769 #define SQ_MIMG_0__SLC__SHIFT                                                                                 0x19
2770 #define SQ_MIMG_0__ENCODING__SHIFT                                                                            0x1a
2771 #define SQ_MIMG_0__OPM_MASK                                                                                   0x00000001L
2772 #define SQ_MIMG_0__DMASK_MASK                                                                                 0x00000F00L
2773 #define SQ_MIMG_0__UNORM_MASK                                                                                 0x00001000L
2774 #define SQ_MIMG_0__GLC_MASK                                                                                   0x00002000L
2775 #define SQ_MIMG_0__DA_MASK                                                                                    0x00004000L
2776 #define SQ_MIMG_0__A16_MASK                                                                                   0x00008000L
2777 #define SQ_MIMG_0__TFE_MASK                                                                                   0x00010000L
2778 #define SQ_MIMG_0__LWE_MASK                                                                                   0x00020000L
2779 #define SQ_MIMG_0__OP_MASK                                                                                    0x01FC0000L
2780 #define SQ_MIMG_0__SLC_MASK                                                                                   0x02000000L
2781 #define SQ_MIMG_0__ENCODING_MASK                                                                              0xFC000000L
2782 //SQ_MIMG_1
2783 #define SQ_MIMG_1__VADDR__SHIFT                                                                               0x0
2784 #define SQ_MIMG_1__VDATA__SHIFT                                                                               0x8
2785 #define SQ_MIMG_1__SRSRC__SHIFT                                                                               0x10
2786 #define SQ_MIMG_1__SSAMP__SHIFT                                                                               0x15
2787 #define SQ_MIMG_1__D16__SHIFT                                                                                 0x1f
2788 #define SQ_MIMG_1__VADDR_MASK                                                                                 0x000000FFL
2789 #define SQ_MIMG_1__VDATA_MASK                                                                                 0x0000FF00L
2790 #define SQ_MIMG_1__SRSRC_MASK                                                                                 0x001F0000L
2791 #define SQ_MIMG_1__SSAMP_MASK                                                                                 0x03E00000L
2792 #define SQ_MIMG_1__D16_MASK                                                                                   0x80000000L
2793 //SQ_MTBUF_0
2794 #define SQ_MTBUF_0__OFFSET__SHIFT                                                                             0x0
2795 #define SQ_MTBUF_0__OFFEN__SHIFT                                                                              0xc
2796 #define SQ_MTBUF_0__IDXEN__SHIFT                                                                              0xd
2797 #define SQ_MTBUF_0__GLC__SHIFT                                                                                0xe
2798 #define SQ_MTBUF_0__OP__SHIFT                                                                                 0xf
2799 #define SQ_MTBUF_0__DFMT__SHIFT                                                                               0x13
2800 #define SQ_MTBUF_0__NFMT__SHIFT                                                                               0x17
2801 #define SQ_MTBUF_0__ENCODING__SHIFT                                                                           0x1a
2802 #define SQ_MTBUF_0__OFFSET_MASK                                                                               0x00000FFFL
2803 #define SQ_MTBUF_0__OFFEN_MASK                                                                                0x00001000L
2804 #define SQ_MTBUF_0__IDXEN_MASK                                                                                0x00002000L
2805 #define SQ_MTBUF_0__GLC_MASK                                                                                  0x00004000L
2806 #define SQ_MTBUF_0__OP_MASK                                                                                   0x00078000L
2807 #define SQ_MTBUF_0__DFMT_MASK                                                                                 0x00780000L
2808 #define SQ_MTBUF_0__NFMT_MASK                                                                                 0x03800000L
2809 #define SQ_MTBUF_0__ENCODING_MASK                                                                             0xFC000000L
2810 //SQ_MTBUF_1
2811 #define SQ_MTBUF_1__VADDR__SHIFT                                                                              0x0
2812 #define SQ_MTBUF_1__VDATA__SHIFT                                                                              0x8
2813 #define SQ_MTBUF_1__SRSRC__SHIFT                                                                              0x10
2814 #define SQ_MTBUF_1__SLC__SHIFT                                                                                0x16
2815 #define SQ_MTBUF_1__TFE__SHIFT                                                                                0x17
2816 #define SQ_MTBUF_1__SOFFSET__SHIFT                                                                            0x18
2817 #define SQ_MTBUF_1__VADDR_MASK                                                                                0x000000FFL
2818 #define SQ_MTBUF_1__VDATA_MASK                                                                                0x0000FF00L
2819 #define SQ_MTBUF_1__SRSRC_MASK                                                                                0x001F0000L
2820 #define SQ_MTBUF_1__SLC_MASK                                                                                  0x00400000L
2821 #define SQ_MTBUF_1__TFE_MASK                                                                                  0x00800000L
2822 #define SQ_MTBUF_1__SOFFSET_MASK                                                                              0xFF000000L
2823 //SQ_MUBUF_0
2824 #define SQ_MUBUF_0__OFFSET__SHIFT                                                                             0x0
2825 #define SQ_MUBUF_0__OFFEN__SHIFT                                                                              0xc
2826 #define SQ_MUBUF_0__IDXEN__SHIFT                                                                              0xd
2827 #define SQ_MUBUF_0__GLC__SHIFT                                                                                0xe
2828 #define SQ_MUBUF_0__LDS__SHIFT                                                                                0x10
2829 #define SQ_MUBUF_0__SLC__SHIFT                                                                                0x11
2830 #define SQ_MUBUF_0__OP__SHIFT                                                                                 0x12
2831 #define SQ_MUBUF_0__ENCODING__SHIFT                                                                           0x1a
2832 #define SQ_MUBUF_0__OFFSET_MASK                                                                               0x00000FFFL
2833 #define SQ_MUBUF_0__OFFEN_MASK                                                                                0x00001000L
2834 #define SQ_MUBUF_0__IDXEN_MASK                                                                                0x00002000L
2835 #define SQ_MUBUF_0__GLC_MASK                                                                                  0x00004000L
2836 #define SQ_MUBUF_0__LDS_MASK                                                                                  0x00010000L
2837 #define SQ_MUBUF_0__SLC_MASK                                                                                  0x00020000L
2838 #define SQ_MUBUF_0__OP_MASK                                                                                   0x01FC0000L
2839 #define SQ_MUBUF_0__ENCODING_MASK                                                                             0xFC000000L
2840 //SQ_MUBUF_1
2841 #define SQ_MUBUF_1__VADDR__SHIFT                                                                              0x0
2842 #define SQ_MUBUF_1__VDATA__SHIFT                                                                              0x8
2843 #define SQ_MUBUF_1__SRSRC__SHIFT                                                                              0x10
2844 #define SQ_MUBUF_1__TFE__SHIFT                                                                                0x17
2845 #define SQ_MUBUF_1__SOFFSET__SHIFT                                                                            0x18
2846 #define SQ_MUBUF_1__VADDR_MASK                                                                                0x000000FFL
2847 #define SQ_MUBUF_1__VDATA_MASK                                                                                0x0000FF00L
2848 #define SQ_MUBUF_1__SRSRC_MASK                                                                                0x001F0000L
2849 #define SQ_MUBUF_1__TFE_MASK                                                                                  0x00800000L
2850 #define SQ_MUBUF_1__SOFFSET_MASK                                                                              0xFF000000L
2851 //SQ_SCRATCH_0
2852 #define SQ_SCRATCH_0__OFFSET__SHIFT                                                                           0x0
2853 #define SQ_SCRATCH_0__LDS__SHIFT                                                                              0xd
2854 #define SQ_SCRATCH_0__SEG__SHIFT                                                                              0xe
2855 #define SQ_SCRATCH_0__GLC__SHIFT                                                                              0x10
2856 #define SQ_SCRATCH_0__SLC__SHIFT                                                                              0x11
2857 #define SQ_SCRATCH_0__OP__SHIFT                                                                               0x12
2858 #define SQ_SCRATCH_0__ENCODING__SHIFT                                                                         0x1a
2859 #define SQ_SCRATCH_0__OFFSET_MASK                                                                             0x00001FFFL
2860 #define SQ_SCRATCH_0__LDS_MASK                                                                                0x00002000L
2861 #define SQ_SCRATCH_0__SEG_MASK                                                                                0x0000C000L
2862 #define SQ_SCRATCH_0__GLC_MASK                                                                                0x00010000L
2863 #define SQ_SCRATCH_0__SLC_MASK                                                                                0x00020000L
2864 #define SQ_SCRATCH_0__OP_MASK                                                                                 0x01FC0000L
2865 #define SQ_SCRATCH_0__ENCODING_MASK                                                                           0xFC000000L
2866 //SQ_SCRATCH_1
2867 #define SQ_SCRATCH_1__ADDR__SHIFT                                                                             0x0
2868 #define SQ_SCRATCH_1__DATA__SHIFT                                                                             0x8
2869 #define SQ_SCRATCH_1__SADDR__SHIFT                                                                            0x10
2870 #define SQ_SCRATCH_1__NV__SHIFT                                                                               0x17
2871 #define SQ_SCRATCH_1__VDST__SHIFT                                                                             0x18
2872 #define SQ_SCRATCH_1__ADDR_MASK                                                                               0x000000FFL
2873 #define SQ_SCRATCH_1__DATA_MASK                                                                               0x0000FF00L
2874 #define SQ_SCRATCH_1__SADDR_MASK                                                                              0x007F0000L
2875 #define SQ_SCRATCH_1__NV_MASK                                                                                 0x00800000L
2876 #define SQ_SCRATCH_1__VDST_MASK                                                                               0xFF000000L
2877 //SQ_SMEM_0
2878 #define SQ_SMEM_0__SBASE__SHIFT                                                                               0x0
2879 #define SQ_SMEM_0__SDATA__SHIFT                                                                               0x6
2880 #define SQ_SMEM_0__SOFFSET_EN__SHIFT                                                                          0xe
2881 #define SQ_SMEM_0__NV__SHIFT                                                                                  0xf
2882 #define SQ_SMEM_0__GLC__SHIFT                                                                                 0x10
2883 #define SQ_SMEM_0__IMM__SHIFT                                                                                 0x11
2884 #define SQ_SMEM_0__OP__SHIFT                                                                                  0x12
2885 #define SQ_SMEM_0__ENCODING__SHIFT                                                                            0x1a
2886 #define SQ_SMEM_0__SBASE_MASK                                                                                 0x0000003FL
2887 #define SQ_SMEM_0__SDATA_MASK                                                                                 0x00001FC0L
2888 #define SQ_SMEM_0__SOFFSET_EN_MASK                                                                            0x00004000L
2889 #define SQ_SMEM_0__NV_MASK                                                                                    0x00008000L
2890 #define SQ_SMEM_0__GLC_MASK                                                                                   0x00010000L
2891 #define SQ_SMEM_0__IMM_MASK                                                                                   0x00020000L
2892 #define SQ_SMEM_0__OP_MASK                                                                                    0x03FC0000L
2893 #define SQ_SMEM_0__ENCODING_MASK                                                                              0xFC000000L
2894 //SQ_SMEM_1
2895 #define SQ_SMEM_1__OFFSET__SHIFT                                                                              0x0
2896 #define SQ_SMEM_1__SOFFSET__SHIFT                                                                             0x19
2897 #define SQ_SMEM_1__OFFSET_MASK                                                                                0x001FFFFFL
2898 #define SQ_SMEM_1__SOFFSET_MASK                                                                               0xFE000000L
2899 //SQ_SOP1
2900 #define SQ_SOP1__SSRC0__SHIFT                                                                                 0x0
2901 #define SQ_SOP1__OP__SHIFT                                                                                    0x8
2902 #define SQ_SOP1__SDST__SHIFT                                                                                  0x10
2903 #define SQ_SOP1__ENCODING__SHIFT                                                                              0x17
2904 #define SQ_SOP1__SSRC0_MASK                                                                                   0x000000FFL
2905 #define SQ_SOP1__OP_MASK                                                                                      0x0000FF00L
2906 #define SQ_SOP1__SDST_MASK                                                                                    0x007F0000L
2907 #define SQ_SOP1__ENCODING_MASK                                                                                0xFF800000L
2908 //SQ_SOP2
2909 #define SQ_SOP2__SSRC0__SHIFT                                                                                 0x0
2910 #define SQ_SOP2__SSRC1__SHIFT                                                                                 0x8
2911 #define SQ_SOP2__SDST__SHIFT                                                                                  0x10
2912 #define SQ_SOP2__OP__SHIFT                                                                                    0x17
2913 #define SQ_SOP2__ENCODING__SHIFT                                                                              0x1e
2914 #define SQ_SOP2__SSRC0_MASK                                                                                   0x000000FFL
2915 #define SQ_SOP2__SSRC1_MASK                                                                                   0x0000FF00L
2916 #define SQ_SOP2__SDST_MASK                                                                                    0x007F0000L
2917 #define SQ_SOP2__OP_MASK                                                                                      0x3F800000L
2918 #define SQ_SOP2__ENCODING_MASK                                                                                0xC0000000L
2919 //SQ_SOPC
2920 #define SQ_SOPC__SSRC0__SHIFT                                                                                 0x0
2921 #define SQ_SOPC__SSRC1__SHIFT                                                                                 0x8
2922 #define SQ_SOPC__OP__SHIFT                                                                                    0x10
2923 #define SQ_SOPC__ENCODING__SHIFT                                                                              0x17
2924 #define SQ_SOPC__SSRC0_MASK                                                                                   0x000000FFL
2925 #define SQ_SOPC__SSRC1_MASK                                                                                   0x0000FF00L
2926 #define SQ_SOPC__OP_MASK                                                                                      0x007F0000L
2927 #define SQ_SOPC__ENCODING_MASK                                                                                0xFF800000L
2928 //SQ_SOPK
2929 #define SQ_SOPK__SIMM16__SHIFT                                                                                0x0
2930 #define SQ_SOPK__SDST__SHIFT                                                                                  0x10
2931 #define SQ_SOPK__OP__SHIFT                                                                                    0x17
2932 #define SQ_SOPK__ENCODING__SHIFT                                                                              0x1c
2933 #define SQ_SOPK__SIMM16_MASK                                                                                  0x0000FFFFL
2934 #define SQ_SOPK__SDST_MASK                                                                                    0x007F0000L
2935 #define SQ_SOPK__OP_MASK                                                                                      0x0F800000L
2936 #define SQ_SOPK__ENCODING_MASK                                                                                0xF0000000L
2937 //SQ_SOPP
2938 #define SQ_SOPP__SIMM16__SHIFT                                                                                0x0
2939 #define SQ_SOPP__OP__SHIFT                                                                                    0x10
2940 #define SQ_SOPP__ENCODING__SHIFT                                                                              0x17
2941 #define SQ_SOPP__SIMM16_MASK                                                                                  0x0000FFFFL
2942 #define SQ_SOPP__OP_MASK                                                                                      0x007F0000L
2943 #define SQ_SOPP__ENCODING_MASK                                                                                0xFF800000L
2944 //SQ_VINTRP
2945 #define SQ_VINTRP__VSRC__SHIFT                                                                                0x0
2946 #define SQ_VINTRP__ATTRCHAN__SHIFT                                                                            0x8
2947 #define SQ_VINTRP__ATTR__SHIFT                                                                                0xa
2948 #define SQ_VINTRP__OP__SHIFT                                                                                  0x10
2949 #define SQ_VINTRP__VDST__SHIFT                                                                                0x12
2950 #define SQ_VINTRP__ENCODING__SHIFT                                                                            0x1a
2951 #define SQ_VINTRP__VSRC_MASK                                                                                  0x000000FFL
2952 #define SQ_VINTRP__ATTRCHAN_MASK                                                                              0x00000300L
2953 #define SQ_VINTRP__ATTR_MASK                                                                                  0x0000FC00L
2954 #define SQ_VINTRP__OP_MASK                                                                                    0x00030000L
2955 #define SQ_VINTRP__VDST_MASK                                                                                  0x03FC0000L
2956 #define SQ_VINTRP__ENCODING_MASK                                                                              0xFC000000L
2957 //SQ_VOP1
2958 #define SQ_VOP1__SRC0__SHIFT                                                                                  0x0
2959 #define SQ_VOP1__OP__SHIFT                                                                                    0x9
2960 #define SQ_VOP1__VDST__SHIFT                                                                                  0x11
2961 #define SQ_VOP1__ENCODING__SHIFT                                                                              0x19
2962 #define SQ_VOP1__SRC0_MASK                                                                                    0x000001FFL
2963 #define SQ_VOP1__OP_MASK                                                                                      0x0001FE00L
2964 #define SQ_VOP1__VDST_MASK                                                                                    0x01FE0000L
2965 #define SQ_VOP1__ENCODING_MASK                                                                                0xFE000000L
2966 //SQ_VOP2
2967 #define SQ_VOP2__SRC0__SHIFT                                                                                  0x0
2968 #define SQ_VOP2__VSRC1__SHIFT                                                                                 0x9
2969 #define SQ_VOP2__VDST__SHIFT                                                                                  0x11
2970 #define SQ_VOP2__OP__SHIFT                                                                                    0x19
2971 #define SQ_VOP2__ENCODING__SHIFT                                                                              0x1f
2972 #define SQ_VOP2__SRC0_MASK                                                                                    0x000001FFL
2973 #define SQ_VOP2__VSRC1_MASK                                                                                   0x0001FE00L
2974 #define SQ_VOP2__VDST_MASK                                                                                    0x01FE0000L
2975 #define SQ_VOP2__OP_MASK                                                                                      0x7E000000L
2976 #define SQ_VOP2__ENCODING_MASK                                                                                0x80000000L
2977 //SQ_VOP3P_0
2978 #define SQ_VOP3P_0__VDST__SHIFT                                                                               0x0
2979 #define SQ_VOP3P_0__NEG_HI__SHIFT                                                                             0x8
2980 #define SQ_VOP3P_0__OP_SEL__SHIFT                                                                             0xb
2981 #define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT                                                                        0xe
2982 #define SQ_VOP3P_0__CLAMP__SHIFT                                                                              0xf
2983 #define SQ_VOP3P_0__OP__SHIFT                                                                                 0x10
2984 #define SQ_VOP3P_0__ENCODING__SHIFT                                                                           0x17
2985 #define SQ_VOP3P_0__VDST_MASK                                                                                 0x000000FFL
2986 #define SQ_VOP3P_0__NEG_HI_MASK                                                                               0x00000700L
2987 #define SQ_VOP3P_0__OP_SEL_MASK                                                                               0x00003800L
2988 #define SQ_VOP3P_0__OP_SEL_HI_2_MASK                                                                          0x00004000L
2989 #define SQ_VOP3P_0__CLAMP_MASK                                                                                0x00008000L
2990 #define SQ_VOP3P_0__OP_MASK                                                                                   0x007F0000L
2991 #define SQ_VOP3P_0__ENCODING_MASK                                                                             0xFF800000L
2992 //SQ_VOP3P_1
2993 #define SQ_VOP3P_1__SRC0__SHIFT                                                                               0x0
2994 #define SQ_VOP3P_1__SRC1__SHIFT                                                                               0x9
2995 #define SQ_VOP3P_1__SRC2__SHIFT                                                                               0x12
2996 #define SQ_VOP3P_1__OP_SEL_HI__SHIFT                                                                          0x1b
2997 #define SQ_VOP3P_1__NEG__SHIFT                                                                                0x1d
2998 #define SQ_VOP3P_1__SRC0_MASK                                                                                 0x000001FFL
2999 #define SQ_VOP3P_1__SRC1_MASK                                                                                 0x0003FE00L
3000 #define SQ_VOP3P_1__SRC2_MASK                                                                                 0x07FC0000L
3001 #define SQ_VOP3P_1__OP_SEL_HI_MASK                                                                            0x18000000L
3002 #define SQ_VOP3P_1__NEG_MASK                                                                                  0xE0000000L
3003 //SQ_VOP3_0
3004 #define SQ_VOP3_0__VDST__SHIFT                                                                                0x0
3005 #define SQ_VOP3_0__ABS__SHIFT                                                                                 0x8
3006 #define SQ_VOP3_0__OP_SEL__SHIFT                                                                              0xb
3007 #define SQ_VOP3_0__CLAMP__SHIFT                                                                               0xf
3008 #define SQ_VOP3_0__OP__SHIFT                                                                                  0x10
3009 #define SQ_VOP3_0__ENCODING__SHIFT                                                                            0x1a
3010 #define SQ_VOP3_0__VDST_MASK                                                                                  0x000000FFL
3011 #define SQ_VOP3_0__ABS_MASK                                                                                   0x00000700L
3012 #define SQ_VOP3_0__OP_SEL_MASK                                                                                0x00007800L
3013 #define SQ_VOP3_0__CLAMP_MASK                                                                                 0x00008000L
3014 #define SQ_VOP3_0__OP_MASK                                                                                    0x03FF0000L
3015 #define SQ_VOP3_0__ENCODING_MASK                                                                              0xFC000000L
3016 //SQ_VOP3_0_SDST_ENC
3017 #define SQ_VOP3_0_SDST_ENC__VDST__SHIFT                                                                       0x0
3018 #define SQ_VOP3_0_SDST_ENC__SDST__SHIFT                                                                       0x8
3019 #define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT                                                                      0xf
3020 #define SQ_VOP3_0_SDST_ENC__OP__SHIFT                                                                         0x10
3021 #define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT                                                                   0x1a
3022 #define SQ_VOP3_0_SDST_ENC__VDST_MASK                                                                         0x000000FFL
3023 #define SQ_VOP3_0_SDST_ENC__SDST_MASK                                                                         0x00007F00L
3024 #define SQ_VOP3_0_SDST_ENC__CLAMP_MASK                                                                        0x00008000L
3025 #define SQ_VOP3_0_SDST_ENC__OP_MASK                                                                           0x03FF0000L
3026 #define SQ_VOP3_0_SDST_ENC__ENCODING_MASK                                                                     0xFC000000L
3027 //SQ_VOP3_1
3028 #define SQ_VOP3_1__SRC0__SHIFT                                                                                0x0
3029 #define SQ_VOP3_1__SRC1__SHIFT                                                                                0x9
3030 #define SQ_VOP3_1__SRC2__SHIFT                                                                                0x12
3031 #define SQ_VOP3_1__OMOD__SHIFT                                                                                0x1b
3032 #define SQ_VOP3_1__NEG__SHIFT                                                                                 0x1d
3033 #define SQ_VOP3_1__SRC0_MASK                                                                                  0x000001FFL
3034 #define SQ_VOP3_1__SRC1_MASK                                                                                  0x0003FE00L
3035 #define SQ_VOP3_1__SRC2_MASK                                                                                  0x07FC0000L
3036 #define SQ_VOP3_1__OMOD_MASK                                                                                  0x18000000L
3037 #define SQ_VOP3_1__NEG_MASK                                                                                   0xE0000000L
3038 //SQ_VOPC
3039 #define SQ_VOPC__SRC0__SHIFT                                                                                  0x0
3040 #define SQ_VOPC__VSRC1__SHIFT                                                                                 0x9
3041 #define SQ_VOPC__OP__SHIFT                                                                                    0x11
3042 #define SQ_VOPC__ENCODING__SHIFT                                                                              0x19
3043 #define SQ_VOPC__SRC0_MASK                                                                                    0x000001FFL
3044 #define SQ_VOPC__VSRC1_MASK                                                                                   0x0001FE00L
3045 #define SQ_VOPC__OP_MASK                                                                                      0x01FE0000L
3046 #define SQ_VOPC__ENCODING_MASK                                                                                0xFE000000L
3047 //SQ_VOP_DPP
3048 #define SQ_VOP_DPP__SRC0__SHIFT                                                                               0x0
3049 #define SQ_VOP_DPP__DPP_CTRL__SHIFT                                                                           0x8
3050 #define SQ_VOP_DPP__BOUND_CTRL__SHIFT                                                                         0x13
3051 #define SQ_VOP_DPP__SRC0_NEG__SHIFT                                                                           0x14
3052 #define SQ_VOP_DPP__SRC0_ABS__SHIFT                                                                           0x15
3053 #define SQ_VOP_DPP__SRC1_NEG__SHIFT                                                                           0x16
3054 #define SQ_VOP_DPP__SRC1_ABS__SHIFT                                                                           0x17
3055 #define SQ_VOP_DPP__BANK_MASK__SHIFT                                                                          0x18
3056 #define SQ_VOP_DPP__ROW_MASK__SHIFT                                                                           0x1c
3057 #define SQ_VOP_DPP__SRC0_MASK                                                                                 0x000000FFL
3058 #define SQ_VOP_DPP__DPP_CTRL_MASK                                                                             0x0001FF00L
3059 #define SQ_VOP_DPP__BOUND_CTRL_MASK                                                                           0x00080000L
3060 #define SQ_VOP_DPP__SRC0_NEG_MASK                                                                             0x00100000L
3061 #define SQ_VOP_DPP__SRC0_ABS_MASK                                                                             0x00200000L
3062 #define SQ_VOP_DPP__SRC1_NEG_MASK                                                                             0x00400000L
3063 #define SQ_VOP_DPP__SRC1_ABS_MASK                                                                             0x00800000L
3064 #define SQ_VOP_DPP__BANK_MASK_MASK                                                                            0x0F000000L
3065 #define SQ_VOP_DPP__ROW_MASK_MASK                                                                             0xF0000000L
3066 //SQ_VOP_SDWA
3067 #define SQ_VOP_SDWA__SRC0__SHIFT                                                                              0x0
3068 #define SQ_VOP_SDWA__DST_SEL__SHIFT                                                                           0x8
3069 #define SQ_VOP_SDWA__DST_UNUSED__SHIFT                                                                        0xb
3070 #define SQ_VOP_SDWA__CLAMP__SHIFT                                                                             0xd
3071 #define SQ_VOP_SDWA__OMOD__SHIFT                                                                              0xe
3072 #define SQ_VOP_SDWA__SRC0_SEL__SHIFT                                                                          0x10
3073 #define SQ_VOP_SDWA__SRC0_SEXT__SHIFT                                                                         0x13
3074 #define SQ_VOP_SDWA__SRC0_NEG__SHIFT                                                                          0x14
3075 #define SQ_VOP_SDWA__SRC0_ABS__SHIFT                                                                          0x15
3076 #define SQ_VOP_SDWA__S0__SHIFT                                                                                0x17
3077 #define SQ_VOP_SDWA__SRC1_SEL__SHIFT                                                                          0x18
3078 #define SQ_VOP_SDWA__SRC1_SEXT__SHIFT                                                                         0x1b
3079 #define SQ_VOP_SDWA__SRC1_NEG__SHIFT                                                                          0x1c
3080 #define SQ_VOP_SDWA__SRC1_ABS__SHIFT                                                                          0x1d
3081 #define SQ_VOP_SDWA__S1__SHIFT                                                                                0x1f
3082 #define SQ_VOP_SDWA__SRC0_MASK                                                                                0x000000FFL
3083 #define SQ_VOP_SDWA__DST_SEL_MASK                                                                             0x00000700L
3084 #define SQ_VOP_SDWA__DST_UNUSED_MASK                                                                          0x00001800L
3085 #define SQ_VOP_SDWA__CLAMP_MASK                                                                               0x00002000L
3086 #define SQ_VOP_SDWA__OMOD_MASK                                                                                0x0000C000L
3087 #define SQ_VOP_SDWA__SRC0_SEL_MASK                                                                            0x00070000L
3088 #define SQ_VOP_SDWA__SRC0_SEXT_MASK                                                                           0x00080000L
3089 #define SQ_VOP_SDWA__SRC0_NEG_MASK                                                                            0x00100000L
3090 #define SQ_VOP_SDWA__SRC0_ABS_MASK                                                                            0x00200000L
3091 #define SQ_VOP_SDWA__S0_MASK                                                                                  0x00800000L
3092 #define SQ_VOP_SDWA__SRC1_SEL_MASK                                                                            0x07000000L
3093 #define SQ_VOP_SDWA__SRC1_SEXT_MASK                                                                           0x08000000L
3094 #define SQ_VOP_SDWA__SRC1_NEG_MASK                                                                            0x10000000L
3095 #define SQ_VOP_SDWA__SRC1_ABS_MASK                                                                            0x20000000L
3096 #define SQ_VOP_SDWA__S1_MASK                                                                                  0x80000000L
3097 //SQ_VOP_SDWA_SDST_ENC
3098 #define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT                                                                     0x0
3099 #define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT                                                                     0x8
3100 #define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT                                                                       0xf
3101 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT                                                                 0x10
3102 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT                                                                0x13
3103 #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT                                                                 0x14
3104 #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT                                                                 0x15
3105 #define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT                                                                       0x17
3106 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT                                                                 0x18
3107 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT                                                                0x1b
3108 #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT                                                                 0x1c
3109 #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT                                                                 0x1d
3110 #define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT                                                                       0x1f
3111 #define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK                                                                       0x000000FFL
3112 #define SQ_VOP_SDWA_SDST_ENC__SDST_MASK                                                                       0x00007F00L
3113 #define SQ_VOP_SDWA_SDST_ENC__SD_MASK                                                                         0x00008000L
3114 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK                                                                   0x00070000L
3115 #define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK                                                                  0x00080000L
3116 #define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK                                                                   0x00100000L
3117 #define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK                                                                   0x00200000L
3118 #define SQ_VOP_SDWA_SDST_ENC__S0_MASK                                                                         0x00800000L
3119 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK                                                                   0x07000000L
3120 #define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK                                                                  0x08000000L
3121 #define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK                                                                   0x10000000L
3122 #define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK                                                                   0x20000000L
3123 #define SQ_VOP_SDWA_SDST_ENC__S1_MASK                                                                         0x80000000L
3124 //SQ_LB_CTR_CTRL
3125 #define SQ_LB_CTR_CTRL__START__SHIFT                                                                          0x0
3126 #define SQ_LB_CTR_CTRL__LOAD__SHIFT                                                                           0x1
3127 #define SQ_LB_CTR_CTRL__CLEAR__SHIFT                                                                          0x2
3128 #define SQ_LB_CTR_CTRL__START_MASK                                                                            0x00000001L
3129 #define SQ_LB_CTR_CTRL__LOAD_MASK                                                                             0x00000002L
3130 #define SQ_LB_CTR_CTRL__CLEAR_MASK                                                                            0x00000004L
3131 //SQ_LB_DATA0
3132 #define SQ_LB_DATA0__DATA__SHIFT                                                                              0x0
3133 #define SQ_LB_DATA0__DATA_MASK                                                                                0xFFFFFFFFL
3134 //SQ_LB_DATA1
3135 #define SQ_LB_DATA1__DATA__SHIFT                                                                              0x0
3136 #define SQ_LB_DATA1__DATA_MASK                                                                                0xFFFFFFFFL
3137 //SQ_LB_DATA2
3138 #define SQ_LB_DATA2__DATA__SHIFT                                                                              0x0
3139 #define SQ_LB_DATA2__DATA_MASK                                                                                0xFFFFFFFFL
3140 //SQ_LB_DATA3
3141 #define SQ_LB_DATA3__DATA__SHIFT                                                                              0x0
3142 #define SQ_LB_DATA3__DATA_MASK                                                                                0xFFFFFFFFL
3143 //SQ_LB_CTR_SEL
3144 #define SQ_LB_CTR_SEL__SEL0__SHIFT                                                                            0x0
3145 #define SQ_LB_CTR_SEL__SEL1__SHIFT                                                                            0x4
3146 #define SQ_LB_CTR_SEL__SEL2__SHIFT                                                                            0x8
3147 #define SQ_LB_CTR_SEL__SEL3__SHIFT                                                                            0xc
3148 #define SQ_LB_CTR_SEL__SEL0_MASK                                                                              0x0000000FL
3149 #define SQ_LB_CTR_SEL__SEL1_MASK                                                                              0x000000F0L
3150 #define SQ_LB_CTR_SEL__SEL2_MASK                                                                              0x00000F00L
3151 #define SQ_LB_CTR_SEL__SEL3_MASK                                                                              0x0000F000L
3152 //SQ_LB_CTR0_CU
3153 #define SQ_LB_CTR0_CU__SH0_MASK__SHIFT                                                                        0x0
3154 #define SQ_LB_CTR0_CU__SH1_MASK__SHIFT                                                                        0x10
3155 #define SQ_LB_CTR0_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3156 #define SQ_LB_CTR0_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3157 //SQ_LB_CTR1_CU
3158 #define SQ_LB_CTR1_CU__SH0_MASK__SHIFT                                                                        0x0
3159 #define SQ_LB_CTR1_CU__SH1_MASK__SHIFT                                                                        0x10
3160 #define SQ_LB_CTR1_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3161 #define SQ_LB_CTR1_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3162 //SQ_LB_CTR2_CU
3163 #define SQ_LB_CTR2_CU__SH0_MASK__SHIFT                                                                        0x0
3164 #define SQ_LB_CTR2_CU__SH1_MASK__SHIFT                                                                        0x10
3165 #define SQ_LB_CTR2_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3166 #define SQ_LB_CTR2_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3167 //SQ_LB_CTR3_CU
3168 #define SQ_LB_CTR3_CU__SH0_MASK__SHIFT                                                                        0x0
3169 #define SQ_LB_CTR3_CU__SH1_MASK__SHIFT                                                                        0x10
3170 #define SQ_LB_CTR3_CU__SH0_MASK_MASK                                                                          0x0000FFFFL
3171 #define SQ_LB_CTR3_CU__SH1_MASK_MASK                                                                          0xFFFF0000L
3172 //SQC_EDC_CNT
3173 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x0
3174 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x2
3175 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x4
3176 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x6
3177 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x8
3178 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0xa
3179 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0xc
3180 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0xe
3181 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x10
3182 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x12
3183 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x14
3184 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x16
3185 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT                                                 0x18
3186 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT                                                 0x1a
3187 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT                                                    0x1c
3188 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT                                                    0x1e
3189 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00000003L
3190 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x0000000CL
3191 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00000030L
3192 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x000000C0L
3193 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00000300L
3194 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x00000C00L
3195 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00003000L
3196 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x0000C000L
3197 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x00030000L
3198 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x000C0000L
3199 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x00300000L
3200 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK                                                      0x00C00000L
3201 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK                                                   0x03000000L
3202 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK                                                   0x0C000000L
3203 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK                                                      0x30000000L
3204 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK                                                      0xC0000000L
3205 //SQ_EDC_SEC_CNT
3206 #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT                                                                        0x0
3207 #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT                                                                       0x8
3208 #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT                                                                       0x10
3209 #define SQ_EDC_SEC_CNT__LDS_SEC_MASK                                                                          0x000000FFL
3210 #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK                                                                         0x0000FF00L
3211 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK                                                                         0x00FF0000L
3212 //SQ_EDC_DED_CNT
3213 #define SQ_EDC_DED_CNT__LDS_DED__SHIFT                                                                        0x0
3214 #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT                                                                       0x8
3215 #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT                                                                       0x10
3216 #define SQ_EDC_DED_CNT__LDS_DED_MASK                                                                          0x000000FFL
3217 #define SQ_EDC_DED_CNT__SGPR_DED_MASK                                                                         0x0000FF00L
3218 #define SQ_EDC_DED_CNT__VGPR_DED_MASK                                                                         0x00FF0000L
3219 //SQ_EDC_INFO
3220 #define SQ_EDC_INFO__WAVE_ID__SHIFT                                                                           0x0
3221 #define SQ_EDC_INFO__SIMD_ID__SHIFT                                                                           0x4
3222 #define SQ_EDC_INFO__SOURCE__SHIFT                                                                            0x6
3223 #define SQ_EDC_INFO__VM_ID__SHIFT                                                                             0x9
3224 #define SQ_EDC_INFO__WAVE_ID_MASK                                                                             0x0000000FL
3225 #define SQ_EDC_INFO__SIMD_ID_MASK                                                                             0x00000030L
3226 #define SQ_EDC_INFO__SOURCE_MASK                                                                              0x000001C0L
3227 #define SQ_EDC_INFO__VM_ID_MASK                                                                               0x00001E00L
3228 //SQ_EDC_CNT
3229 #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT                                                                    0x0
3230 #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT                                                                    0x2
3231 #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT                                                                    0x4
3232 #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT                                                                    0x6
3233 #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT                                                                     0x8
3234 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT                                                                     0xa
3235 #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT                                                                    0xc
3236 #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT                                                                    0xe
3237 #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT                                                                    0x10
3238 #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT                                                                    0x12
3239 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT                                                                    0x14
3240 #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT                                                                    0x16
3241 #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT                                                                    0x18
3242 #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT                                                                    0x1a
3243 #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK                                                                      0x00000003L
3244 #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK                                                                      0x0000000CL
3245 #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK                                                                      0x00000030L
3246 #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK                                                                      0x000000C0L
3247 #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK                                                                       0x00000300L
3248 #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK                                                                       0x00000C00L
3249 #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK                                                                      0x00003000L
3250 #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK                                                                      0x0000C000L
3251 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK                                                                      0x00030000L
3252 #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK                                                                      0x000C0000L
3253 #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK                                                                      0x00300000L
3254 #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK                                                                      0x00C00000L
3255 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK                                                                      0x03000000L
3256 #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK                                                                      0x0C000000L
3257 //SQ_EDC_FUE_CNTL
3258 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT                                                               0x0
3259 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT                                                         0x10
3260 #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK                                                                 0x0000FFFFL
3261 #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK                                                           0xFFFF0000L
3262 //SQ_THREAD_TRACE_WORD_CMN
3263 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT                                                           0x0
3264 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT                                                           0x4
3265 #define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK                                                             0x000FL
3266 #define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK                                                             0x0010L
3267 //SQ_THREAD_TRACE_WORD_EVENT
3268 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT                                                         0x0
3269 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT                                                         0x4
3270 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT                                                              0x5
3271 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT                                                              0x6
3272 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT                                                         0xa
3273 #define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK                                                           0x000FL
3274 #define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK                                                           0x0010L
3275 #define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK                                                                0x0020L
3276 #define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK                                                                0x01C0L
3277 #define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK                                                           0xFC00L
3278 //SQ_THREAD_TRACE_WORD_INST
3279 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT                                                          0x0
3280 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT                                                          0x4
3281 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT                                                             0x5
3282 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT                                                             0x9
3283 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT                                                           0xb
3284 #define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK                                                            0x000FL
3285 #define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK                                                            0x0010L
3286 #define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK                                                               0x01E0L
3287 #define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK                                                               0x0600L
3288 #define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK                                                             0xF800L
3289 //SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
3290 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT                                                0x0
3291 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT                                                0x4
3292 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT                                                   0x5
3293 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT                                                   0x9
3294 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT                                                0xf
3295 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT                                                     0x10
3296 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK                                                  0x0000000FL
3297 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK                                                  0x00000010L
3298 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK                                                     0x000001E0L
3299 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK                                                     0x00000600L
3300 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK                                                  0x00008000L
3301 #define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK                                                       0xFFFF0000L
3302 //SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
3303 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT                                          0x0
3304 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT                                          0x4
3305 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT                                               0x5
3306 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT                                               0x6
3307 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT                                             0xa
3308 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT                                             0xe
3309 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT                                             0x10
3310 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK                                            0x0000000FL
3311 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK                                            0x00000010L
3312 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK                                                 0x00000020L
3313 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK                                                 0x000003C0L
3314 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK                                               0x00003C00L
3315 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK                                               0x0000C000L
3316 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK                                               0xFFFF0000L
3317 //SQ_THREAD_TRACE_WORD_ISSUE
3318 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT                                                         0x0
3319 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT                                                         0x4
3320 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT                                                            0x5
3321 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT                                                              0x8
3322 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT                                                              0xa
3323 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT                                                              0xc
3324 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT                                                              0xe
3325 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT                                                              0x10
3326 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT                                                              0x12
3327 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT                                                              0x14
3328 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT                                                              0x16
3329 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT                                                              0x18
3330 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT                                                              0x1a
3331 #define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK                                                           0x0000000FL
3332 #define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK                                                           0x00000010L
3333 #define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK                                                              0x00000060L
3334 #define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK                                                                0x00000300L
3335 #define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK                                                                0x00000C00L
3336 #define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK                                                                0x00003000L
3337 #define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK                                                                0x0000C000L
3338 #define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK                                                                0x00030000L
3339 #define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK                                                                0x000C0000L
3340 #define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK                                                                0x00300000L
3341 #define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK                                                                0x00C00000L
3342 #define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK                                                                0x03000000L
3343 #define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK                                                                0x0C000000L
3344 //SQ_THREAD_TRACE_WORD_MISC
3345 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT                                                          0x0
3346 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT                                                          0x4
3347 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT                                                               0xc
3348 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT                                                     0xd
3349 #define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK                                                            0x000FL
3350 #define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK                                                            0x0FF0L
3351 #define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK                                                                 0x1000L
3352 #define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK                                                       0xE000L
3353 //SQ_THREAD_TRACE_WORD_PERF_1_OF_2
3354 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT                                                   0x0
3355 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT                                                   0x4
3356 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT                                                        0x5
3357 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT                                                        0x6
3358 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT                                                    0xa
3359 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT                                                        0xc
3360 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT                                                     0x19
3361 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK                                                     0x0000000FL
3362 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK                                                     0x00000010L
3363 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK                                                          0x00000020L
3364 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK                                                          0x000003C0L
3365 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK                                                      0x00000C00L
3366 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK                                                          0x01FFF000L
3367 #define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK                                                       0xFE000000L
3368 //SQ_THREAD_TRACE_WORD_REG_1_OF_2
3369 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT                                                    0x0
3370 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT                                                    0x4
3371 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT                                                       0x5
3372 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT                                                         0x7
3373 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT                                              0x9
3374 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT                                                      0xa
3375 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT                                                      0xe
3376 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT                                                        0xf
3377 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT                                                      0x10
3378 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK                                                      0x0000000FL
3379 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK                                                      0x00000010L
3380 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK                                                         0x00000060L
3381 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK                                                           0x00000180L
3382 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK                                                0x00000200L
3383 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK                                                        0x00001C00L
3384 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK                                                        0x00004000L
3385 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK                                                          0x00008000L
3386 #define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK                                                        0xFFFF0000L
3387 //SQ_THREAD_TRACE_WORD_REG_2_OF_2
3388 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT                                                          0x0
3389 #define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK                                                            0xFFFFFFFFL
3390 //SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
3391 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT                                                 0x0
3392 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT                                                 0x4
3393 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT                                                    0x5
3394 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT                                                      0x7
3395 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT                                                   0x9
3396 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT                                                    0x10
3397 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK                                                   0x0000000FL
3398 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK                                                   0x00000010L
3399 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK                                                      0x00000060L
3400 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK                                                        0x00000180L
3401 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK                                                     0x0000FE00L
3402 #define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK                                                      0xFFFF0000L
3403 //SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
3404 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT                                                    0x0
3405 #define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK                                                      0x0000FFFFL
3406 //SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
3407 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT                                              0x0
3408 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT                                                 0x10
3409 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK                                                0x0000000FL
3410 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK                                                   0xFFFF0000L
3411 //SQ_THREAD_TRACE_WORD_WAVE
3412 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT                                                          0x0
3413 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT                                                          0x4
3414 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT                                                               0x5
3415 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT                                                               0x6
3416 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT                                                             0xa
3417 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT                                                             0xe
3418 #define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK                                                            0x000FL
3419 #define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK                                                            0x0010L
3420 #define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK                                                                 0x0020L
3421 #define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK                                                                 0x03C0L
3422 #define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK                                                               0x3C00L
3423 #define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK                                                               0xC000L
3424 //SQ_THREAD_TRACE_WORD_WAVE_START
3425 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT                                                    0x0
3426 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT                                                    0x4
3427 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT                                                         0x5
3428 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT                                                         0x6
3429 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT                                                       0xa
3430 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT                                                       0xe
3431 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT                                                    0x10
3432 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT                                        0x15
3433 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT                                                         0x16
3434 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT                                                         0x1d
3435 #define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK                                                      0x0000000FL
3436 #define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK                                                      0x00000010L
3437 #define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK                                                           0x00000020L
3438 #define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK                                                           0x000003C0L
3439 #define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK                                                         0x00003C00L
3440 #define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK                                                         0x0000C000L
3441 #define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK                                                      0x001F0000L
3442 #define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK                                          0x00200000L
3443 #define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK                                                           0x1FC00000L
3444 #define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK                                                           0xE0000000L
3445 //SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
3446 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT                                                     0x0
3447 #define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK                                                       0x00FFFFFFL
3448 //SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
3449 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT                                             0x0
3450 #define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK                                               0xFFFFL
3451 //SQ_THREAD_TRACE_WORD_PERF_2_OF_2
3452 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT                                                     0x0
3453 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT                                                        0x6
3454 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT                                                        0x13
3455 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK                                                       0x0000003FL
3456 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK                                                          0x0007FFC0L
3457 #define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK                                                          0xFFF80000L
3458 //SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
3459 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT                                                 0x0
3460 #define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK                                                   0xFFFFFFFFL
3461 //SQ_WREXEC_EXEC_HI
3462 #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT                                                                     0x0
3463 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT                                                                  0x1a
3464 #define SQ_WREXEC_EXEC_HI__ATC__SHIFT                                                                         0x1b
3465 #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT                                                                       0x1c
3466 #define SQ_WREXEC_EXEC_HI__MSB__SHIFT                                                                         0x1f
3467 #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK                                                                       0x0000FFFFL
3468 #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK                                                                    0x04000000L
3469 #define SQ_WREXEC_EXEC_HI__ATC_MASK                                                                           0x08000000L
3470 #define SQ_WREXEC_EXEC_HI__MTYPE_MASK                                                                         0x70000000L
3471 #define SQ_WREXEC_EXEC_HI__MSB_MASK                                                                           0x80000000L
3472 //SQ_WREXEC_EXEC_LO
3473 #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT                                                                     0x0
3474 #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK                                                                       0xFFFFFFFFL
3475 //SQ_BUF_RSRC_WORD0
3476 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT                                                                0x0
3477 #define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK                                                                  0xFFFFFFFFL
3478 //SQ_BUF_RSRC_WORD1
3479 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
3480 #define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT                                                                      0x10
3481 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT                                                               0x1e
3482 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT                                                              0x1f
3483 #define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK                                                               0x0000FFFFL
3484 #define SQ_BUF_RSRC_WORD1__STRIDE_MASK                                                                        0x3FFF0000L
3485 #define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK                                                                 0x40000000L
3486 #define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK                                                                0x80000000L
3487 //SQ_BUF_RSRC_WORD2
3488 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT                                                                 0x0
3489 #define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK                                                                   0xFFFFFFFFL
3490 //SQ_BUF_RSRC_WORD3
3491 #define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT                                                                   0x0
3492 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT                                                                   0x3
3493 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT                                                                   0x6
3494 #define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT                                                                   0x9
3495 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT                                                                  0xc
3496 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT                                                                 0xf
3497 #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT                                                              0x13
3498 #define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT                                                                0x14
3499 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT                                                                0x15
3500 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT                                                              0x17
3501 #define SQ_BUF_RSRC_WORD3__NV__SHIFT                                                                          0x1b
3502 #define SQ_BUF_RSRC_WORD3__TYPE__SHIFT                                                                        0x1e
3503 #define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK                                                                     0x00000007L
3504 #define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK                                                                     0x00000038L
3505 #define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK                                                                     0x000001C0L
3506 #define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK                                                                     0x00000E00L
3507 #define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK                                                                    0x00007000L
3508 #define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK                                                                   0x00078000L
3509 #define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK                                                                0x00080000L
3510 #define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK                                                                  0x00100000L
3511 #define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK                                                                  0x00600000L
3512 #define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK                                                                0x00800000L
3513 #define SQ_BUF_RSRC_WORD3__NV_MASK                                                                            0x08000000L
3514 #define SQ_BUF_RSRC_WORD3__TYPE_MASK                                                                          0xC0000000L
3515 //SQ_IMG_RSRC_WORD0
3516 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT                                                                0x0
3517 #define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK                                                                  0xFFFFFFFFL
3518 //SQ_IMG_RSRC_WORD1
3519 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT                                                             0x0
3520 #define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT                                                                     0x8
3521 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT                                                                 0x14
3522 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT                                                                  0x1a
3523 #define SQ_IMG_RSRC_WORD1__NV__SHIFT                                                                          0x1e
3524 #define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT                                                                 0x1f
3525 #define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK                                                               0x000000FFL
3526 #define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK                                                                       0x000FFF00L
3527 #define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK                                                                   0x03F00000L
3528 #define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK                                                                    0x3C000000L
3529 #define SQ_IMG_RSRC_WORD1__NV_MASK                                                                            0x40000000L
3530 #define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK                                                                   0x80000000L
3531 //SQ_IMG_RSRC_WORD2
3532 #define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT                                                                       0x0
3533 #define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT                                                                      0xe
3534 #define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT                                                                    0x1c
3535 #define SQ_IMG_RSRC_WORD2__WIDTH_MASK                                                                         0x00003FFFL
3536 #define SQ_IMG_RSRC_WORD2__HEIGHT_MASK                                                                        0x0FFFC000L
3537 #define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK                                                                      0x70000000L
3538 //SQ_IMG_RSRC_WORD3
3539 #define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT                                                                   0x0
3540 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT                                                                   0x3
3541 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT                                                                   0x6
3542 #define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT                                                                   0x9
3543 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT                                                                  0xc
3544 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT                                                                  0x10
3545 #define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT                                                                     0x14
3546 #define SQ_IMG_RSRC_WORD3__TYPE__SHIFT                                                                        0x1c
3547 #define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK                                                                     0x00000007L
3548 #define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK                                                                     0x00000038L
3549 #define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK                                                                     0x000001C0L
3550 #define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK                                                                     0x00000E00L
3551 #define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK                                                                    0x0000F000L
3552 #define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK                                                                    0x000F0000L
3553 #define SQ_IMG_RSRC_WORD3__SW_MODE_MASK                                                                       0x01F00000L
3554 #define SQ_IMG_RSRC_WORD3__TYPE_MASK                                                                          0xF0000000L
3555 //SQ_IMG_RSRC_WORD4
3556 #define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT                                                                       0x0
3557 #define SQ_IMG_RSRC_WORD4__PITCH__SHIFT                                                                       0xd
3558 #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT                                                                  0x1d
3559 #define SQ_IMG_RSRC_WORD4__DEPTH_MASK                                                                         0x00001FFFL
3560 #define SQ_IMG_RSRC_WORD4__PITCH_MASK                                                                         0x1FFFE000L
3561 #define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK                                                                    0xE0000000L
3562 //SQ_IMG_RSRC_WORD5
3563 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT                                                                  0x0
3564 #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT                                                                 0xd
3565 #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT                                                           0x11
3566 #define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT                                                                 0x19
3567 #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT                                                           0x1a
3568 #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT                                                             0x1b
3569 #define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT                                                                     0x1c
3570 #define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK                                                                    0x00001FFFL
3571 #define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK                                                                   0x0001E000L
3572 #define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK                                                             0x01FE0000L
3573 #define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK                                                                   0x02000000L
3574 #define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK                                                             0x04000000L
3575 #define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK                                                               0x08000000L
3576 #define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK                                                                       0xF0000000L
3577 //SQ_IMG_RSRC_WORD6
3578 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT                                                                0x0
3579 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT                                                             0xc
3580 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT                                                              0x14
3581 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT                                                              0x15
3582 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT                                                             0x16
3583 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT                                                             0x17
3584 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT                                                             0x18
3585 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT                                                             0x1c
3586 #define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK                                                                  0x00000FFFL
3587 #define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK                                                               0x000FF000L
3588 #define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK                                                                0x00100000L
3589 #define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK                                                                0x00200000L
3590 #define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK                                                               0x00400000L
3591 #define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK                                                               0x00800000L
3592 #define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK                                                               0x0F000000L
3593 #define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK                                                               0xF0000000L
3594 //SQ_IMG_RSRC_WORD7
3595 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT                                                           0x0
3596 #define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK                                                             0xFFFFFFFFL
3597 //SQ_IMG_SAMP_WORD0
3598 #define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT                                                                     0x0
3599 #define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT                                                                     0x3
3600 #define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT                                                                     0x6
3601 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT                                                             0x9
3602 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT                                                          0xc
3603 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT                                                          0xf
3604 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT                                                             0x10
3605 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT                                                              0x13
3606 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT                                                               0x14
3607 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT                                                                  0x15
3608 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT                                                                 0x1b
3609 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT                                                           0x1c
3610 #define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT                                                                 0x1d
3611 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT                                                                 0x1f
3612 #define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK                                                                       0x00000007L
3613 #define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK                                                                       0x00000038L
3614 #define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK                                                                       0x000001C0L
3615 #define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK                                                               0x00000E00L
3616 #define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK                                                            0x00007000L
3617 #define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK                                                            0x00008000L
3618 #define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK                                                               0x00070000L
3619 #define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK                                                                0x00080000L
3620 #define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK                                                                 0x00100000L
3621 #define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK                                                                    0x07E00000L
3622 #define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK                                                                   0x08000000L
3623 #define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK                                                             0x10000000L
3624 #define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK                                                                   0x60000000L
3625 #define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK                                                                   0x80000000L
3626 //SQ_IMG_SAMP_WORD1
3627 #define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT                                                                     0x0
3628 #define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT                                                                     0xc
3629 #define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT                                                                    0x18
3630 #define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT                                                                      0x1c
3631 #define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK                                                                       0x00000FFFL
3632 #define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK                                                                       0x00FFF000L
3633 #define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK                                                                      0x0F000000L
3634 #define SQ_IMG_SAMP_WORD1__PERF_Z_MASK                                                                        0xF0000000L
3635 //SQ_IMG_SAMP_WORD2
3636 #define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT                                                                    0x0
3637 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT                                                                0xe
3638 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT                                                               0x14
3639 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT                                                               0x16
3640 #define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT                                                                    0x18
3641 #define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT                                                                  0x1a
3642 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT                                                          0x1c
3643 #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT                                                              0x1d
3644 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT                                                             0x1e
3645 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT                                                              0x1f
3646 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK                                                                      0x00003FFFL
3647 #define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK                                                                  0x000FC000L
3648 #define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK                                                                 0x00300000L
3649 #define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK                                                                 0x00C00000L
3650 #define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK                                                                      0x03000000L
3651 #define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK                                                                    0x0C000000L
3652 #define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK                                                            0x10000000L
3653 #define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK                                                                0x20000000L
3654 #define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK                                                               0x40000000L
3655 #define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK                                                                0x80000000L
3656 //SQ_IMG_SAMP_WORD3
3657 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT                                                            0x0
3658 #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT                                                                0xc
3659 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT                                                           0x1e
3660 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK                                                              0x00000FFFL
3661 #define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK                                                                  0x00001000L
3662 #define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK                                                             0xC0000000L
3663 //SQ_FLAT_SCRATCH_WORD0
3664 #define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT                                                                    0x0
3665 #define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK                                                                      0x0007FFFFL
3666 //SQ_FLAT_SCRATCH_WORD1
3667 #define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT                                                                  0x0
3668 #define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK                                                                    0x00FFFFFFL
3669 //SQ_M0_GPR_IDX_WORD
3670 #define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT                                                                      0x0
3671 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT                                                                  0xc
3672 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT                                                                  0xd
3673 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT                                                                  0xe
3674 #define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT                                                                   0xf
3675 #define SQ_M0_GPR_IDX_WORD__INDEX_MASK                                                                        0x000000FFL
3676 #define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK                                                                    0x00001000L
3677 #define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK                                                                    0x00002000L
3678 #define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK                                                                    0x00004000L
3679 #define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK                                                                     0x00008000L
3680 //SQC_ICACHE_UTCL1_CNTL1
3681 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
3682 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
3683 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
3684 #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT                                                              0x3
3685 #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
3686 #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT                                                               0x7
3687 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
3688 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
3689 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                    0x13
3690 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                0x17
3691 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                  0x18
3692 #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
3693 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
3694 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
3695 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
3696 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
3697 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
3698 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
3699 #define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
3700 #define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK                                                                0x00000018L
3701 #define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
3702 #define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
3703 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
3704 #define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
3705 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                      0x00780000L
3706 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                  0x00800000L
3707 #define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                    0x01000000L
3708 #define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
3709 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
3710 #define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
3711 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
3712 #define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
3713 //SQC_ICACHE_UTCL1_CNTL2
3714 #define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT                                                                  0x0
3715 #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
3716 #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
3717 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT                                                             0xa
3718 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                0xb
3719 #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
3720 #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
3721 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
3722 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
3723 #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
3724 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
3725 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
3726 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
3727 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
3728 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
3729 #define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK                                                                    0x000000FFL
3730 #define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
3731 #define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
3732 #define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK                                                               0x00000400L
3733 #define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
3734 #define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
3735 #define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
3736 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
3737 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
3738 #define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
3739 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
3740 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
3741 #define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
3742 #define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
3743 #define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
3744 //SQC_DCACHE_UTCL1_CNTL1
3745 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                       0x0
3746 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                          0x1
3747 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                        0x2
3748 #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT                                                              0x3
3749 #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                        0x5
3750 #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT                                                               0x7
3751 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                      0x11
3752 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                   0x12
3753 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT                                                    0x13
3754 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT                                                0x17
3755 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT                                                  0x18
3756 #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                             0x19
3757 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                             0x1a
3758 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                         0x1b
3759 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                 0x1c
3760 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                 0x1e
3761 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                         0x00000001L
3762 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                            0x00000002L
3763 #define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                          0x00000004L
3764 #define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK                                                                0x00000018L
3765 #define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                          0x00000060L
3766 #define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK                                                                 0x0000FF80L
3767 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                        0x00020000L
3768 #define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                     0x00040000L
3769 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK                                                      0x00780000L
3770 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK                                                  0x00800000L
3771 #define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK                                                    0x01000000L
3772 #define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                               0x02000000L
3773 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK                                                               0x04000000L
3774 #define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                           0x08000000L
3775 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                   0x30000000L
3776 #define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                   0xC0000000L
3777 //SQC_DCACHE_UTCL1_CNTL2
3778 #define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT                                                                  0x0
3779 #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT                                                     0x8
3780 #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                         0x9
3781 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT                                                             0xa
3782 #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                0xb
3783 #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                         0xc
3784 #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                          0xd
3785 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                            0xe
3786 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                    0xf
3787 #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT                                                         0x10
3788 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT                                                0x12
3789 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT                                                       0x13
3790 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT                                                 0x14
3791 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT                                                        0x15
3792 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                   0x1a
3793 #define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK                                                                    0x000000FFL
3794 #define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK                                                       0x00000100L
3795 #define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                           0x00000200L
3796 #define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK                                                               0x00000400L
3797 #define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK                                                                  0x00000800L
3798 #define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                           0x00001000L
3799 #define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                            0x00002000L
3800 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                              0x00004000L
3801 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                      0x00008000L
3802 #define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK                                                           0x00030000L
3803 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK                                                  0x00040000L
3804 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK                                                         0x00080000L
3805 #define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK                                                   0x00100000L
3806 #define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK                                                          0x01E00000L
3807 #define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                     0x04000000L
3808 //SQC_ICACHE_UTCL1_STATUS
3809 #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
3810 #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
3811 #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                          0x2
3812 #define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
3813 #define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
3814 #define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
3815 //SQC_DCACHE_UTCL1_STATUS
3816 #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                        0x0
3817 #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                        0x1
3818 #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                          0x2
3819 #define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK                                                          0x00000001L
3820 #define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK                                                          0x00000002L
3821 #define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK                                                            0x00000004L
3822 
3823 
3824 // addressBlock: gc_shsdec
3825 //SX_DEBUG_BUSY
3826 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT                                                              0x0
3827 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT                                                              0x1
3828 #define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT                                                                      0x2
3829 #define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT                                                                   0x3
3830 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT                                                              0x4
3831 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT                                                              0x5
3832 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT                                                              0x6
3833 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT                                                              0x7
3834 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT                                                              0x8
3835 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT                                                              0x9
3836 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT                                                              0xa
3837 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT                                                              0xb
3838 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT                                                              0xc
3839 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT                                                              0xd
3840 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT                                                              0xe
3841 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT                                                              0xf
3842 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT                                                              0x10
3843 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT                                                              0x11
3844 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT                                                              0x12
3845 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT                                                              0x13
3846 #define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT                                                                 0x14
3847 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT                                                                 0x15
3848 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT                                                                 0x16
3849 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT                                                                 0x17
3850 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT                                                                 0x18
3851 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT                                                                 0x19
3852 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT                                                                 0x1a
3853 #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT                                                                     0x1b
3854 #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT                                                                    0x1c
3855 #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT                                                                    0x1d
3856 #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT                                                                   0x1e
3857 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT                                                                  0x1f
3858 #define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK                                                                0x00000001L
3859 #define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK                                                                0x00000002L
3860 #define SX_DEBUG_BUSY__PA_SX_BUSY_MASK                                                                        0x00000004L
3861 #define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK                                                                     0x00000008L
3862 #define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK                                                                0x00000010L
3863 #define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK                                                                0x00000020L
3864 #define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK                                                                0x00000040L
3865 #define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK                                                                0x00000080L
3866 #define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK                                                                0x00000100L
3867 #define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK                                                                0x00000200L
3868 #define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK                                                                0x00000400L
3869 #define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK                                                                0x00000800L
3870 #define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK                                                                0x00001000L
3871 #define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK                                                                0x00002000L
3872 #define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK                                                                0x00004000L
3873 #define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK                                                                0x00008000L
3874 #define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK                                                                0x00010000L
3875 #define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK                                                                0x00020000L
3876 #define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK                                                                0x00040000L
3877 #define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK                                                                0x00080000L
3878 #define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK                                                                   0x00100000L
3879 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK                                                                   0x00200000L
3880 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK                                                                   0x00400000L
3881 #define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK                                                                   0x00800000L
3882 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK                                                                   0x01000000L
3883 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK                                                                   0x02000000L
3884 #define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK                                                                   0x04000000L
3885 #define SX_DEBUG_BUSY__PCCMD_VALID_MASK                                                                       0x08000000L
3886 #define SX_DEBUG_BUSY__VDATA1_VALID_MASK                                                                      0x10000000L
3887 #define SX_DEBUG_BUSY__VDATA0_VALID_MASK                                                                      0x20000000L
3888 #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK                                                                     0x40000000L
3889 #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK                                                                    0x80000000L
3890 //SX_DEBUG_BUSY_2
3891 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT                                                     0x0
3892 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT                                                     0x1
3893 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT                                                     0x2
3894 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT                                                     0x3
3895 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT                                                     0x4
3896 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT                                                     0x5
3897 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT                                                     0x6
3898 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT                                                     0x7
3899 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT                                                     0x8
3900 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT                                                     0x9
3901 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT                                                     0xa
3902 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT                                                     0xb
3903 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT                                                     0xc
3904 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT                                                     0xd
3905 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT                                                     0xe
3906 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT                                                     0xf
3907 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT                                                     0x10
3908 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT                                                     0x11
3909 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT                                                     0x12
3910 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT                                                     0x13
3911 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT                                                     0x14
3912 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT                                                     0x15
3913 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT                                                     0x16
3914 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT                                                     0x17
3915 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT                                                     0x18
3916 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT                                                     0x19
3917 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT                                                     0x1a
3918 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT                                                     0x1b
3919 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT                                                     0x1c
3920 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT                                                     0x1d
3921 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT                                                     0x1e
3922 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT                                                     0x1f
3923 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK                                                       0x00000001L
3924 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK                                                       0x00000002L
3925 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK                                                       0x00000004L
3926 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK                                                       0x00000008L
3927 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK                                                       0x00000010L
3928 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK                                                       0x00000020L
3929 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK                                                       0x00000040L
3930 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK                                                       0x00000080L
3931 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK                                                       0x00000100L
3932 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK                                                       0x00000200L
3933 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK                                                       0x00000400L
3934 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK                                                       0x00000800L
3935 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK                                                       0x00001000L
3936 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK                                                       0x00002000L
3937 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK                                                       0x00004000L
3938 #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK                                                       0x00008000L
3939 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK                                                       0x00010000L
3940 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK                                                       0x00020000L
3941 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK                                                       0x00040000L
3942 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK                                                       0x00080000L
3943 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK                                                       0x00100000L
3944 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK                                                       0x00200000L
3945 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK                                                       0x00400000L
3946 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK                                                       0x00800000L
3947 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK                                                       0x01000000L
3948 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK                                                       0x02000000L
3949 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK                                                       0x04000000L
3950 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK                                                       0x08000000L
3951 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK                                                       0x10000000L
3952 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK                                                       0x20000000L
3953 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK                                                       0x40000000L
3954 #define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK                                                       0x80000000L
3955 //SX_DEBUG_BUSY_3
3956 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT                                                     0x0
3957 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT                                                     0x1
3958 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT                                                     0x2
3959 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT                                                     0x3
3960 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT                                                     0x4
3961 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT                                                     0x5
3962 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT                                                     0x6
3963 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT                                                     0x7
3964 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT                                                     0x8
3965 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT                                                     0x9
3966 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT                                                     0xa
3967 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT                                                     0xb
3968 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT                                                     0xc
3969 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT                                                     0xd
3970 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT                                                     0xe
3971 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT                                                     0xf
3972 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT                                                     0x10
3973 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT                                                     0x11
3974 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT                                                     0x12
3975 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT                                                     0x13
3976 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT                                                     0x14
3977 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT                                                     0x15
3978 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT                                                     0x16
3979 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT                                                     0x17
3980 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT                                                     0x18
3981 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT                                                     0x19
3982 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT                                                     0x1a
3983 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT                                                     0x1b
3984 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT                                                     0x1c
3985 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT                                                     0x1d
3986 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT                                                     0x1e
3987 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT                                                     0x1f
3988 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK                                                       0x00000001L
3989 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK                                                       0x00000002L
3990 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK                                                       0x00000004L
3991 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK                                                       0x00000008L
3992 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK                                                       0x00000010L
3993 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK                                                       0x00000020L
3994 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK                                                       0x00000040L
3995 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK                                                       0x00000080L
3996 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK                                                       0x00000100L
3997 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK                                                       0x00000200L
3998 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK                                                       0x00000400L
3999 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK                                                       0x00000800L
4000 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK                                                       0x00001000L
4001 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK                                                       0x00002000L
4002 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK                                                       0x00004000L
4003 #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK                                                       0x00008000L
4004 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK                                                       0x00010000L
4005 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK                                                       0x00020000L
4006 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK                                                       0x00040000L
4007 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK                                                       0x00080000L
4008 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK                                                       0x00100000L
4009 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK                                                       0x00200000L
4010 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK                                                       0x00400000L
4011 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK                                                       0x00800000L
4012 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK                                                       0x01000000L
4013 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK                                                       0x02000000L
4014 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK                                                       0x04000000L
4015 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK                                                       0x08000000L
4016 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK                                                       0x10000000L
4017 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK                                                       0x20000000L
4018 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK                                                       0x40000000L
4019 #define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK                                                       0x80000000L
4020 //SX_DEBUG_BUSY_4
4021 #define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT                                                                 0x0
4022 #define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT                                                          0x1
4023 #define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT                                                                 0x2
4024 #define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT                                                                 0x3
4025 #define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT                                                          0x4
4026 #define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT                                                          0x5
4027 #define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT                                                                 0x6
4028 #define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT                                                                 0x7
4029 #define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT                                                          0x8
4030 #define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT                                                          0x9
4031 #define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT                                                                 0xa
4032 #define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT                                                                 0xb
4033 #define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT                                                          0xc
4034 #define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT                                                          0xd
4035 #define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT                                                                 0xe
4036 #define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT                                                                 0xf
4037 #define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT                                                          0x10
4038 #define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT                                                       0x11
4039 #define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT                                                           0x12
4040 #define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT                                                           0x13
4041 #define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT                                                       0x14
4042 #define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT                                                           0x15
4043 #define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT                                                           0x16
4044 #define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT                                                       0x17
4045 #define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT                                                           0x18
4046 #define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT                                                           0x19
4047 #define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT                                                       0x1a
4048 #define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT                                                           0x1b
4049 #define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT                                                           0x1c
4050 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT                                                       0x1d
4051 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT                                                   0x1e
4052 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT                                                       0x1f
4053 #define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK                                                                   0x00000001L
4054 #define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK                                                            0x00000002L
4055 #define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK                                                                   0x00000004L
4056 #define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK                                                                   0x00000008L
4057 #define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK                                                            0x00000010L
4058 #define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK                                                            0x00000020L
4059 #define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK                                                                   0x00000040L
4060 #define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK                                                                   0x00000080L
4061 #define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK                                                            0x00000100L
4062 #define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK                                                            0x00000200L
4063 #define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK                                                                   0x00000400L
4064 #define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK                                                                   0x00000800L
4065 #define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK                                                            0x00001000L
4066 #define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK                                                            0x00002000L
4067 #define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK                                                                   0x00004000L
4068 #define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK                                                                   0x00008000L
4069 #define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK                                                            0x00010000L
4070 #define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK                                                         0x00020000L
4071 #define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK                                                             0x00040000L
4072 #define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK                                                             0x00080000L
4073 #define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK                                                         0x00100000L
4074 #define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK                                                             0x00200000L
4075 #define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK                                                             0x00400000L
4076 #define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK                                                         0x00800000L
4077 #define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK                                                             0x01000000L
4078 #define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK                                                             0x02000000L
4079 #define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK                                                         0x04000000L
4080 #define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK                                                             0x08000000L
4081 #define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK                                                             0x10000000L
4082 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK                                                         0x20000000L
4083 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK                                                     0x40000000L
4084 #define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK                                                         0x80000000L
4085 //SX_DEBUG_BUSY_5
4086 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT                                                       0x0
4087 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT                                                       0x1
4088 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT                                                       0x2
4089 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT                                                       0x3
4090 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT                                                       0x4
4091 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT                                                   0x5
4092 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT                                                       0x6
4093 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT                                                       0x7
4094 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT                                                       0x8
4095 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT                                                       0x9
4096 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT                                                       0xa
4097 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT                                                       0xb
4098 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT                                                   0xc
4099 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT                                                       0xd
4100 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT                                                       0xe
4101 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT                                                       0xf
4102 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT                                                       0x10
4103 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT                                                       0x11
4104 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT                                                       0x12
4105 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT                                                   0x13
4106 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT                                                       0x14
4107 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT                                                       0x15
4108 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT                                                       0x16
4109 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT                                                       0x17
4110 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT                                                       0x18
4111 #define SX_DEBUG_BUSY_5__RESERVED__SHIFT                                                                      0x19
4112 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK                                                         0x00000001L
4113 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK                                                         0x00000002L
4114 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK                                                         0x00000004L
4115 #define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK                                                         0x00000008L
4116 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK                                                         0x00000010L
4117 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK                                                     0x00000020L
4118 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK                                                         0x00000040L
4119 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK                                                         0x00000080L
4120 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK                                                         0x00000100L
4121 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK                                                         0x00000200L
4122 #define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK                                                         0x00000400L
4123 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK                                                         0x00000800L
4124 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK                                                     0x00001000L
4125 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK                                                         0x00002000L
4126 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK                                                         0x00004000L
4127 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK                                                         0x00008000L
4128 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK                                                         0x00010000L
4129 #define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK                                                         0x00020000L
4130 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK                                                         0x00040000L
4131 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK                                                     0x00080000L
4132 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK                                                         0x00100000L
4133 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK                                                         0x00200000L
4134 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK                                                         0x00400000L
4135 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK                                                         0x00800000L
4136 #define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK                                                         0x01000000L
4137 #define SX_DEBUG_BUSY_5__RESERVED_MASK                                                                        0xFE000000L
4138 //SX_DEBUG_1
4139 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT                                                                  0x0
4140 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                      0x8
4141 #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                           0x9
4142 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                    0xa
4143 #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT                                                              0xb
4144 #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT                                                            0xc
4145 #define SX_DEBUG_1__PC_CFG__SHIFT                                                                             0xd
4146 #define SX_DEBUG_1__DEBUG_DATA__SHIFT                                                                         0xe
4147 #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK                                                                    0x0000007FL
4148 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                        0x00000100L
4149 #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK                                                             0x00000200L
4150 #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                      0x00000400L
4151 #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK                                                                0x00000800L
4152 #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK                                                              0x00001000L
4153 #define SX_DEBUG_1__PC_CFG_MASK                                                                               0x00002000L
4154 #define SX_DEBUG_1__DEBUG_DATA_MASK                                                                           0xFFFFC000L
4155 //SPI_PS_MAX_WAVE_ID
4156 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                                0x0
4157 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT                                                      0x10
4158 #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                                  0x00000FFFL
4159 #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK                                                        0x03FF0000L
4160 //SPI_START_PHASE
4161 #define SPI_START_PHASE__VGPR_START_PHASE__SHIFT                                                              0x0
4162 #define SPI_START_PHASE__SGPR_START_PHASE__SHIFT                                                              0x2
4163 #define SPI_START_PHASE__WAVE_START_PHASE__SHIFT                                                              0x4
4164 #define SPI_START_PHASE__VGPR_START_PHASE_MASK                                                                0x00000003L
4165 #define SPI_START_PHASE__SGPR_START_PHASE_MASK                                                                0x0000000CL
4166 #define SPI_START_PHASE__WAVE_START_PHASE_MASK                                                                0x00000030L
4167 //SPI_GFX_CNTL
4168 #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT                                                                     0x0
4169 #define SPI_GFX_CNTL__RESET_COUNTS_MASK                                                                       0x00000001L
4170 //SPI_DEBUG_READ
4171 #define SPI_DEBUG_READ__DATA__SHIFT                                                                           0x0
4172 #define SPI_DEBUG_READ__DATA_MASK                                                                             0xFFFFFFFFL
4173 //SPI_DSM_CNTL
4174 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT                                                    0x0
4175 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                   0x2
4176 #define SPI_DSM_CNTL__UNUSED__SHIFT                                                                           0x3
4177 #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK                                                      0x00000003L
4178 #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK                                                     0x00000004L
4179 #define SPI_DSM_CNTL__UNUSED_MASK                                                                             0xFFFFFFF8L
4180 //SPI_DSM_CNTL2
4181 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
4182 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT                                                  0x2
4183 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT                                                         0x4
4184 #define SPI_DSM_CNTL2__UNUSED__SHIFT                                                                          0xa
4185 #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
4186 #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
4187 #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK                                                           0x000003F0L
4188 #define SPI_DSM_CNTL2__UNUSED_MASK                                                                            0xFFFFFC00L
4189 //SPI_EDC_CNT
4190 #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT                                                              0x0
4191 #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK                                                                0x00000003L
4192 //SPI_DEBUG_BUSY
4193 #define SPI_DEBUG_BUSY__LS_BUSY__SHIFT                                                                        0x0
4194 #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT                                                                        0x1
4195 #define SPI_DEBUG_BUSY__ES_BUSY__SHIFT                                                                        0x2
4196 #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT                                                                        0x3
4197 #define SPI_DEBUG_BUSY__VS_BUSY__SHIFT                                                                        0x4
4198 #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT                                                                       0x5
4199 #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT                                                                       0x6
4200 #define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT                                                                       0x7
4201 #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT                                                                       0x8
4202 #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT                                                                       0x9
4203 #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT                                                                       0xa
4204 #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT                                                                       0xb
4205 #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT                                                                       0xc
4206 #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT                                                                       0xd
4207 #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT                                                                       0xe
4208 #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT                                                                       0xf
4209 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT                                                               0x10
4210 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT                                                               0x11
4211 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT                                                               0x12
4212 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT                                                               0x13
4213 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT                                                                0x14
4214 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT                                                               0x15
4215 #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT                                                                      0x16
4216 #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT                                                                      0x17
4217 #define SPI_DEBUG_BUSY__LS_BUSY_MASK                                                                          0x00000001L
4218 #define SPI_DEBUG_BUSY__HS_BUSY_MASK                                                                          0x00000002L
4219 #define SPI_DEBUG_BUSY__ES_BUSY_MASK                                                                          0x00000004L
4220 #define SPI_DEBUG_BUSY__GS_BUSY_MASK                                                                          0x00000008L
4221 #define SPI_DEBUG_BUSY__VS_BUSY_MASK                                                                          0x00000010L
4222 #define SPI_DEBUG_BUSY__PS0_BUSY_MASK                                                                         0x00000020L
4223 #define SPI_DEBUG_BUSY__PS1_BUSY_MASK                                                                         0x00000040L
4224 #define SPI_DEBUG_BUSY__CSG_BUSY_MASK                                                                         0x00000080L
4225 #define SPI_DEBUG_BUSY__CS0_BUSY_MASK                                                                         0x00000100L
4226 #define SPI_DEBUG_BUSY__CS1_BUSY_MASK                                                                         0x00000200L
4227 #define SPI_DEBUG_BUSY__CS2_BUSY_MASK                                                                         0x00000400L
4228 #define SPI_DEBUG_BUSY__CS3_BUSY_MASK                                                                         0x00000800L
4229 #define SPI_DEBUG_BUSY__CS4_BUSY_MASK                                                                         0x00001000L
4230 #define SPI_DEBUG_BUSY__CS5_BUSY_MASK                                                                         0x00002000L
4231 #define SPI_DEBUG_BUSY__CS6_BUSY_MASK                                                                         0x00004000L
4232 #define SPI_DEBUG_BUSY__CS7_BUSY_MASK                                                                         0x00008000L
4233 #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK                                                                 0x00010000L
4234 #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK                                                                 0x00020000L
4235 #define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK                                                                 0x00040000L
4236 #define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK                                                                 0x00080000L
4237 #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK                                                                  0x00100000L
4238 #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK                                                                 0x00200000L
4239 #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK                                                                        0x00400000L
4240 #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK                                                                        0x00800000L
4241 //SPI_CONFIG_PS_CU_EN
4242 #define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT                                                                    0x0
4243 #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT                                                                0x1
4244 #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT                                                                0x10
4245 #define SPI_CONFIG_PS_CU_EN__ENABLE_MASK                                                                      0x00000001L
4246 #define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK                                                                  0x0000FFFEL
4247 #define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK                                                                  0xFFFF0000L
4248 //SPI_WF_LIFETIME_CNTL
4249 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT                                                            0x0
4250 #define SPI_WF_LIFETIME_CNTL__EN__SHIFT                                                                       0x4
4251 #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK                                                              0x0000000FL
4252 #define SPI_WF_LIFETIME_CNTL__EN_MASK                                                                         0x00000010L
4253 //SPI_WF_LIFETIME_LIMIT_0
4254 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT                                                               0x0
4255 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT                                                               0x1f
4256 #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4257 #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK                                                                 0x80000000L
4258 //SPI_WF_LIFETIME_LIMIT_1
4259 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT                                                               0x0
4260 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT                                                               0x1f
4261 #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4262 #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK                                                                 0x80000000L
4263 //SPI_WF_LIFETIME_LIMIT_2
4264 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT                                                               0x0
4265 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT                                                               0x1f
4266 #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4267 #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK                                                                 0x80000000L
4268 //SPI_WF_LIFETIME_LIMIT_3
4269 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT                                                               0x0
4270 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT                                                               0x1f
4271 #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4272 #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK                                                                 0x80000000L
4273 //SPI_WF_LIFETIME_LIMIT_4
4274 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT                                                               0x0
4275 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT                                                               0x1f
4276 #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4277 #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK                                                                 0x80000000L
4278 //SPI_WF_LIFETIME_LIMIT_5
4279 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT                                                               0x0
4280 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT                                                               0x1f
4281 #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4282 #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK                                                                 0x80000000L
4283 //SPI_WF_LIFETIME_LIMIT_6
4284 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT                                                               0x0
4285 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT                                                               0x1f
4286 #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4287 #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK                                                                 0x80000000L
4288 //SPI_WF_LIFETIME_LIMIT_7
4289 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT                                                               0x0
4290 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT                                                               0x1f
4291 #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4292 #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK                                                                 0x80000000L
4293 //SPI_WF_LIFETIME_LIMIT_8
4294 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT                                                               0x0
4295 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT                                                               0x1f
4296 #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4297 #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK                                                                 0x80000000L
4298 //SPI_WF_LIFETIME_LIMIT_9
4299 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT                                                               0x0
4300 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT                                                               0x1f
4301 #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK                                                                 0x7FFFFFFFL
4302 #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK                                                                 0x80000000L
4303 //SPI_WF_LIFETIME_STATUS_0
4304 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT                                                              0x0
4305 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT                                                             0x1f
4306 #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK                                                                0x7FFFFFFFL
4307 #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK                                                               0x80000000L
4308 //SPI_WF_LIFETIME_STATUS_1
4309 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT                                                              0x0
4310 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT                                                             0x1f
4311 #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK                                                                0x7FFFFFFFL
4312 #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK                                                               0x80000000L
4313 //SPI_WF_LIFETIME_STATUS_2
4314 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT                                                              0x0
4315 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT                                                             0x1f
4316 #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK                                                                0x7FFFFFFFL
4317 #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK                                                               0x80000000L
4318 //SPI_WF_LIFETIME_STATUS_3
4319 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT                                                              0x0
4320 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT                                                             0x1f
4321 #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK                                                                0x7FFFFFFFL
4322 #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK                                                               0x80000000L
4323 //SPI_WF_LIFETIME_STATUS_4
4324 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT                                                              0x0
4325 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT                                                             0x1f
4326 #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK                                                                0x7FFFFFFFL
4327 #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK                                                               0x80000000L
4328 //SPI_WF_LIFETIME_STATUS_5
4329 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT                                                              0x0
4330 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT                                                             0x1f
4331 #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK                                                                0x7FFFFFFFL
4332 #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK                                                               0x80000000L
4333 //SPI_WF_LIFETIME_STATUS_6
4334 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT                                                              0x0
4335 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT                                                             0x1f
4336 #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK                                                                0x7FFFFFFFL
4337 #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK                                                               0x80000000L
4338 //SPI_WF_LIFETIME_STATUS_7
4339 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT                                                              0x0
4340 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT                                                             0x1f
4341 #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK                                                                0x7FFFFFFFL
4342 #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK                                                               0x80000000L
4343 //SPI_WF_LIFETIME_STATUS_8
4344 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT                                                              0x0
4345 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT                                                             0x1f
4346 #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK                                                                0x7FFFFFFFL
4347 #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK                                                               0x80000000L
4348 //SPI_WF_LIFETIME_STATUS_9
4349 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT                                                              0x0
4350 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT                                                             0x1f
4351 #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK                                                                0x7FFFFFFFL
4352 #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK                                                               0x80000000L
4353 //SPI_WF_LIFETIME_STATUS_10
4354 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT                                                             0x0
4355 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT                                                            0x1f
4356 #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK                                                               0x7FFFFFFFL
4357 #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK                                                              0x80000000L
4358 //SPI_WF_LIFETIME_STATUS_11
4359 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT                                                             0x0
4360 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT                                                            0x1f
4361 #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK                                                               0x7FFFFFFFL
4362 #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK                                                              0x80000000L
4363 //SPI_WF_LIFETIME_STATUS_12
4364 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT                                                             0x0
4365 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT                                                            0x1f
4366 #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK                                                               0x7FFFFFFFL
4367 #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK                                                              0x80000000L
4368 //SPI_WF_LIFETIME_STATUS_13
4369 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT                                                             0x0
4370 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT                                                            0x1f
4371 #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK                                                               0x7FFFFFFFL
4372 #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK                                                              0x80000000L
4373 //SPI_WF_LIFETIME_STATUS_14
4374 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT                                                             0x0
4375 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT                                                            0x1f
4376 #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK                                                               0x7FFFFFFFL
4377 #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK                                                              0x80000000L
4378 //SPI_WF_LIFETIME_STATUS_15
4379 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT                                                             0x0
4380 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT                                                            0x1f
4381 #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK                                                               0x7FFFFFFFL
4382 #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK                                                              0x80000000L
4383 //SPI_WF_LIFETIME_STATUS_16
4384 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT                                                             0x0
4385 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT                                                            0x1f
4386 #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK                                                               0x7FFFFFFFL
4387 #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK                                                              0x80000000L
4388 //SPI_WF_LIFETIME_STATUS_17
4389 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT                                                             0x0
4390 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT                                                            0x1f
4391 #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK                                                               0x7FFFFFFFL
4392 #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK                                                              0x80000000L
4393 //SPI_WF_LIFETIME_STATUS_18
4394 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT                                                             0x0
4395 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT                                                            0x1f
4396 #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK                                                               0x7FFFFFFFL
4397 #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK                                                              0x80000000L
4398 //SPI_WF_LIFETIME_STATUS_19
4399 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT                                                             0x0
4400 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT                                                            0x1f
4401 #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK                                                               0x7FFFFFFFL
4402 #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK                                                              0x80000000L
4403 //SPI_WF_LIFETIME_STATUS_20
4404 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT                                                             0x0
4405 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT                                                            0x1f
4406 #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK                                                               0x7FFFFFFFL
4407 #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK                                                              0x80000000L
4408 //SPI_WF_LIFETIME_DEBUG
4409 #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT                                                             0x0
4410 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT                                                             0x1f
4411 #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK                                                               0x7FFFFFFFL
4412 #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK                                                               0x80000000L
4413 //SPI_LB_CTR_CTRL
4414 #define SPI_LB_CTR_CTRL__LOAD__SHIFT                                                                          0x0
4415 #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT                                                                  0x1
4416 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT                                                                 0x3
4417 #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT                                                                  0x4
4418 #define SPI_LB_CTR_CTRL__LOAD_MASK                                                                            0x00000001L
4419 #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK                                                                    0x00000006L
4420 #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK                                                                   0x00000008L
4421 #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK                                                                    0x00000010L
4422 //SPI_LB_CU_MASK
4423 #define SPI_LB_CU_MASK__CU_MASK__SHIFT                                                                        0x0
4424 #define SPI_LB_CU_MASK__CU_MASK_MASK                                                                          0xFFFFL
4425 //SPI_LB_DATA_REG
4426 #define SPI_LB_DATA_REG__CNT_DATA__SHIFT                                                                      0x0
4427 #define SPI_LB_DATA_REG__CNT_DATA_MASK                                                                        0xFFFFFFFFL
4428 //SPI_PG_ENABLE_STATIC_CU_MASK
4429 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT                                                          0x0
4430 #define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK                                                            0xFFFFL
4431 //SPI_GDS_CREDITS
4432 #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT                                                               0x0
4433 #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT                                                                0x8
4434 #define SPI_GDS_CREDITS__UNUSED__SHIFT                                                                        0x10
4435 #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK                                                                 0x000000FFL
4436 #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK                                                                  0x0000FF00L
4437 #define SPI_GDS_CREDITS__UNUSED_MASK                                                                          0xFFFF0000L
4438 //SPI_SX_EXPORT_BUFFER_SIZES
4439 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT                                                  0x0
4440 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT                                               0x10
4441 #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK                                                    0x0000FFFFL
4442 #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK                                                 0xFFFF0000L
4443 //SPI_SX_SCOREBOARD_BUFFER_SIZES
4444 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT                                          0x0
4445 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT                                       0x10
4446 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK                                            0x0000FFFFL
4447 #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK                                         0xFFFF0000L
4448 //SPI_CSQ_WF_ACTIVE_STATUS
4449 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT                                                               0x0
4450 #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK                                                                 0xFFFFFFFFL
4451 //SPI_CSQ_WF_ACTIVE_COUNT_0
4452 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT                                                               0x0
4453 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT                                                              0x10
4454 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK                                                                 0x000007FFL
4455 #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK                                                                0x07FF0000L
4456 //SPI_CSQ_WF_ACTIVE_COUNT_1
4457 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT                                                               0x0
4458 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT                                                              0x10
4459 #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK                                                                 0x000007FFL
4460 #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK                                                                0x07FF0000L
4461 //SPI_CSQ_WF_ACTIVE_COUNT_2
4462 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT                                                               0x0
4463 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT                                                              0x10
4464 #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK                                                                 0x000007FFL
4465 #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK                                                                0x07FF0000L
4466 //SPI_CSQ_WF_ACTIVE_COUNT_3
4467 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT                                                               0x0
4468 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT                                                              0x10
4469 #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK                                                                 0x000007FFL
4470 #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK                                                                0x07FF0000L
4471 //SPI_CSQ_WF_ACTIVE_COUNT_4
4472 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT                                                               0x0
4473 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT                                                              0x10
4474 #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK                                                                 0x000007FFL
4475 #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK                                                                0x07FF0000L
4476 //SPI_CSQ_WF_ACTIVE_COUNT_5
4477 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT                                                               0x0
4478 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT                                                              0x10
4479 #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK                                                                 0x000007FFL
4480 #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK                                                                0x07FF0000L
4481 //SPI_CSQ_WF_ACTIVE_COUNT_6
4482 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT                                                               0x0
4483 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT                                                              0x10
4484 #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK                                                                 0x000007FFL
4485 #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK                                                                0x07FF0000L
4486 //SPI_CSQ_WF_ACTIVE_COUNT_7
4487 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT                                                               0x0
4488 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT                                                              0x10
4489 #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK                                                                 0x000007FFL
4490 #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK                                                                0x07FF0000L
4491 //SPI_LB_DATA_WAVES
4492 #define SPI_LB_DATA_WAVES__COUNT0__SHIFT                                                                      0x0
4493 #define SPI_LB_DATA_WAVES__COUNT1__SHIFT                                                                      0x10
4494 #define SPI_LB_DATA_WAVES__COUNT0_MASK                                                                        0x0000FFFFL
4495 #define SPI_LB_DATA_WAVES__COUNT1_MASK                                                                        0xFFFF0000L
4496 //SPI_LB_DATA_PERCU_WAVE_HSGS
4497 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT                                                        0x0
4498 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT                                                        0x10
4499 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK                                                          0x0000FFFFL
4500 #define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK                                                          0xFFFF0000L
4501 //SPI_LB_DATA_PERCU_WAVE_VSPS
4502 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT                                                        0x0
4503 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT                                                        0x10
4504 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK                                                          0x0000FFFFL
4505 #define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK                                                          0xFFFF0000L
4506 //SPI_LB_DATA_PERCU_WAVE_CS
4507 #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT                                                              0x0
4508 #define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK                                                                0xFFFFL
4509 //SPIS_DEBUG_READ
4510 #define SPIS_DEBUG_READ__DATA__SHIFT                                                                          0x0
4511 #define SPIS_DEBUG_READ__DATA_MASK                                                                            0xFFFFFFFFL
4512 //BCI_DEBUG_READ
4513 #define BCI_DEBUG_READ__DATA__SHIFT                                                                           0x0
4514 #define BCI_DEBUG_READ__DATA_MASK                                                                             0xFFFFFFL
4515 //SPI_P0_TRAP_SCREEN_PSBA_LO
4516 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
4517 #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4518 //SPI_P0_TRAP_SCREEN_PSBA_HI
4519 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
4520 #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
4521 //SPI_P0_TRAP_SCREEN_PSMA_LO
4522 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
4523 #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4524 //SPI_P0_TRAP_SCREEN_PSMA_HI
4525 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
4526 #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
4527 //SPI_P0_TRAP_SCREEN_GPR_MIN
4528 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
4529 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
4530 #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
4531 #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
4532 //SPI_P1_TRAP_SCREEN_PSBA_LO
4533 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT                                                           0x0
4534 #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4535 //SPI_P1_TRAP_SCREEN_PSBA_HI
4536 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT                                                           0x0
4537 #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK                                                             0xFFL
4538 //SPI_P1_TRAP_SCREEN_PSMA_LO
4539 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT                                                           0x0
4540 #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK                                                             0xFFFFFFFFL
4541 //SPI_P1_TRAP_SCREEN_PSMA_HI
4542 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT                                                           0x0
4543 #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK                                                             0xFFL
4544 //SPI_P1_TRAP_SCREEN_GPR_MIN
4545 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT                                                           0x0
4546 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT                                                           0x6
4547 #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK                                                             0x003FL
4548 #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK                                                             0x03C0L
4549 
4550 
4551 // addressBlock: gc_tpdec
4552 //TD_CNTL
4553 #define TD_CNTL__SYNC_PHASE_SH__SHIFT                                                                         0x0
4554 #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT                                                                     0x4
4555 #define TD_CNTL__PAD_STALL_EN__SHIFT                                                                          0x8
4556 #define TD_CNTL__EXTEND_LDS_STALL__SHIFT                                                                      0x9
4557 #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT                                                                0xb
4558 #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT                                                               0xf
4559 #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT                                                                    0x10
4560 #define TD_CNTL__LD_FLOAT_MODE__SHIFT                                                                         0x12
4561 #define TD_CNTL__GATHER4_DX9_MODE__SHIFT                                                                      0x13
4562 #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT                                                                0x14
4563 #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT                                                                  0x15
4564 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT                                                            0x17
4565 #define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT                                                        0x18
4566 #define TD_CNTL__SYNC_PHASE_SH_MASK                                                                           0x00000003L
4567 #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK                                                                       0x00000030L
4568 #define TD_CNTL__PAD_STALL_EN_MASK                                                                            0x00000100L
4569 #define TD_CNTL__EXTEND_LDS_STALL_MASK                                                                        0x00000600L
4570 #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK                                                                  0x00001800L
4571 #define TD_CNTL__PRECISION_COMPATIBILITY_MASK                                                                 0x00008000L
4572 #define TD_CNTL__GATHER4_FLOAT_MODE_MASK                                                                      0x00010000L
4573 #define TD_CNTL__LD_FLOAT_MODE_MASK                                                                           0x00040000L
4574 #define TD_CNTL__GATHER4_DX9_MODE_MASK                                                                        0x00080000L
4575 #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK                                                                  0x00100000L
4576 #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK                                                                    0x00200000L
4577 #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK                                                              0x00800000L
4578 #define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK                                                          0x01000000L
4579 //TD_STATUS
4580 #define TD_STATUS__BUSY__SHIFT                                                                                0x1f
4581 #define TD_STATUS__BUSY_MASK                                                                                  0x80000000L
4582 //TD_DSM_CNTL
4583 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT                                                  0x0
4584 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT                                                 0x2
4585 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT                                                  0x3
4586 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT                                                 0x5
4587 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT                                                     0x6
4588 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT                                                    0x8
4589 #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK                                                    0x00000003L
4590 #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK                                                   0x00000004L
4591 #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK                                                    0x00000018L
4592 #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK                                                   0x00000020L
4593 #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK                                                       0x000000C0L
4594 #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK                                                      0x00000100L
4595 //TD_DSM_CNTL2
4596 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT                                                0x0
4597 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT                                                0x2
4598 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT                                                0x3
4599 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT                                                0x5
4600 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x6
4601 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x8
4602 #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT                                                                  0x1a
4603 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK                                                  0x00000003L
4604 #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK                                                  0x00000004L
4605 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
4606 #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
4607 #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x000000C0L
4608 #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00000100L
4609 #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK                                                                    0xFC000000L
4610 //TD_SCRATCH
4611 #define TD_SCRATCH__SCRATCH__SHIFT                                                                            0x0
4612 #define TD_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
4613 //TA_CNTL
4614 #define TA_CNTL__FX_XNACK_CREDIT__SHIFT                                                                       0x0
4615 #define TA_CNTL__SQ_XNACK_CREDIT__SHIFT                                                                       0x9
4616 #define TA_CNTL__TC_DATA_CREDIT__SHIFT                                                                        0xd
4617 #define TA_CNTL__ALIGNER_CREDIT__SHIFT                                                                        0x10
4618 #define TA_CNTL__TD_FIFO_CREDIT__SHIFT                                                                        0x16
4619 #define TA_CNTL__FX_XNACK_CREDIT_MASK                                                                         0x0000007FL
4620 #define TA_CNTL__SQ_XNACK_CREDIT_MASK                                                                         0x00001E00L
4621 #define TA_CNTL__TC_DATA_CREDIT_MASK                                                                          0x0000E000L
4622 #define TA_CNTL__ALIGNER_CREDIT_MASK                                                                          0x001F0000L
4623 #define TA_CNTL__TD_FIFO_CREDIT_MASK                                                                          0xFFC00000L
4624 //TA_CNTL_AUX
4625 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT                                                                  0x0
4626 #define TA_CNTL_AUX__RESERVED__SHIFT                                                                          0x1
4627 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT                                                                0x5
4628 #define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT                                                                   0x6
4629 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT                                                        0x7
4630 #define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT                                                               0x9
4631 #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT                                                                 0xa
4632 #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT                                                              0xc
4633 #define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT                                                                  0xd
4634 #define TA_CNTL_AUX__ANISO_STEP__SHIFT                                                                        0xe
4635 #define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT                                                                     0xf
4636 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT                                                                 0x10
4637 #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT                                                                   0x11
4638 #define TA_CNTL_AUX__ANISO_TAP__SHIFT                                                                         0x12
4639 #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT                                                                0x13
4640 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT                                                      0x14
4641 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT                                                 0x15
4642 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT                                                          0x16
4643 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT                                                 0x17
4644 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT                                                  0x18
4645 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT                                               0x19
4646 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT                                                     0x1a
4647 #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT                                                         0x1b
4648 #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT                                                               0x1c
4649 #define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT                                                                   0x1d
4650 #define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT                                                                  0x1e
4651 #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK                                                                    0x00000001L
4652 #define TA_CNTL_AUX__RESERVED_MASK                                                                            0x0000000EL
4653 #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK                                                                  0x00000020L
4654 #define TA_CNTL_AUX__GATHERH_DST_SEL_MASK                                                                     0x00000040L
4655 #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK                                                          0x00000080L
4656 #define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK                                                                 0x00000200L
4657 #define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK                                                                   0x00000C00L
4658 #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK                                                                0x00001000L
4659 #define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK                                                                    0x00002000L
4660 #define TA_CNTL_AUX__ANISO_STEP_MASK                                                                          0x00004000L
4661 #define TA_CNTL_AUX__MINMAG_UNNORM_MASK                                                                       0x00008000L
4662 #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK                                                                   0x00010000L
4663 #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK                                                                     0x00020000L
4664 #define TA_CNTL_AUX__ANISO_TAP_MASK                                                                           0x00040000L
4665 #define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK                                                                  0x00080000L
4666 #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK                                                        0x00100000L
4667 #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK                                                   0x00200000L
4668 #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK                                                            0x00400000L
4669 #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK                                                   0x00800000L
4670 #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK                                                    0x01000000L
4671 #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK                                                 0x02000000L
4672 #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK                                                       0x04000000L
4673 #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK                                                           0x08000000L
4674 #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK                                                                 0x10000000L
4675 #define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK                                                                     0x20000000L
4676 #define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK                                                                    0xC0000000L
4677 //TA_RESERVED_010C
4678 #define TA_RESERVED_010C__Unused__SHIFT                                                                       0x0
4679 #define TA_RESERVED_010C__Unused_MASK                                                                         0xFFFFFFFFL
4680 //TA_STATUS
4681 #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT                                                                     0xc
4682 #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT                                                                     0xd
4683 #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT                                                                     0xe
4684 #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT                                                                     0x10
4685 #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT                                                                     0x11
4686 #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT                                                                     0x12
4687 #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT                                                                     0x14
4688 #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT                                                                     0x15
4689 #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT                                                                     0x16
4690 #define TA_STATUS__IN_BUSY__SHIFT                                                                             0x18
4691 #define TA_STATUS__FG_BUSY__SHIFT                                                                             0x19
4692 #define TA_STATUS__LA_BUSY__SHIFT                                                                             0x1a
4693 #define TA_STATUS__FL_BUSY__SHIFT                                                                             0x1b
4694 #define TA_STATUS__TA_BUSY__SHIFT                                                                             0x1c
4695 #define TA_STATUS__FA_BUSY__SHIFT                                                                             0x1d
4696 #define TA_STATUS__AL_BUSY__SHIFT                                                                             0x1e
4697 #define TA_STATUS__BUSY__SHIFT                                                                                0x1f
4698 #define TA_STATUS__FG_PFIFO_EMPTYB_MASK                                                                       0x00001000L
4699 #define TA_STATUS__FG_LFIFO_EMPTYB_MASK                                                                       0x00002000L
4700 #define TA_STATUS__FG_SFIFO_EMPTYB_MASK                                                                       0x00004000L
4701 #define TA_STATUS__FL_PFIFO_EMPTYB_MASK                                                                       0x00010000L
4702 #define TA_STATUS__FL_LFIFO_EMPTYB_MASK                                                                       0x00020000L
4703 #define TA_STATUS__FL_SFIFO_EMPTYB_MASK                                                                       0x00040000L
4704 #define TA_STATUS__FA_PFIFO_EMPTYB_MASK                                                                       0x00100000L
4705 #define TA_STATUS__FA_LFIFO_EMPTYB_MASK                                                                       0x00200000L
4706 #define TA_STATUS__FA_SFIFO_EMPTYB_MASK                                                                       0x00400000L
4707 #define TA_STATUS__IN_BUSY_MASK                                                                               0x01000000L
4708 #define TA_STATUS__FG_BUSY_MASK                                                                               0x02000000L
4709 #define TA_STATUS__LA_BUSY_MASK                                                                               0x04000000L
4710 #define TA_STATUS__FL_BUSY_MASK                                                                               0x08000000L
4711 #define TA_STATUS__TA_BUSY_MASK                                                                               0x10000000L
4712 #define TA_STATUS__FA_BUSY_MASK                                                                               0x20000000L
4713 #define TA_STATUS__AL_BUSY_MASK                                                                               0x40000000L
4714 #define TA_STATUS__BUSY_MASK                                                                                  0x80000000L
4715 //TA_SCRATCH
4716 #define TA_SCRATCH__SCRATCH__SHIFT                                                                            0x0
4717 #define TA_SCRATCH__SCRATCH_MASK                                                                              0xFFFFFFFFL
4718 
4719 
4720 // addressBlock: gc_gdsdec
4721 //GDS_CONFIG
4722 #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT                                                                  0x1
4723 #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT                                                                  0x3
4724 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT                                                                  0x5
4725 #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT                                                                  0x7
4726 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK                                                                    0x00000006L
4727 #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK                                                                    0x00000018L
4728 #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK                                                                    0x00000060L
4729 #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK                                                                    0x00000180L
4730 //GDS_CNTL_STATUS
4731 #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT                                                                      0x0
4732 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT                                                                0x1
4733 #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT                                                                  0x2
4734 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT                                                              0x3
4735 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT                                                              0x4
4736 #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT                                                                   0x5
4737 #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT                                                                   0x6
4738 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT                                                                0x7
4739 #define GDS_CNTL_STATUS__DS_BUSY__SHIFT                                                                       0x8
4740 #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT                                                                      0x9
4741 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT                                                                 0xa
4742 #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT                                                                  0xb
4743 #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT                                                                  0xc
4744 #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT                                                                  0xd
4745 #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT                                                                  0xe
4746 #define GDS_CNTL_STATUS__GDS_BUSY_MASK                                                                        0x00000001L
4747 #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK                                                                  0x00000002L
4748 #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK                                                                    0x00000004L
4749 #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK                                                                0x00000008L
4750 #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK                                                                0x00000010L
4751 #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK                                                                     0x00000020L
4752 #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK                                                                     0x00000040L
4753 #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK                                                                  0x00000080L
4754 #define GDS_CNTL_STATUS__DS_BUSY_MASK                                                                         0x00000100L
4755 #define GDS_CNTL_STATUS__GWS_BUSY_MASK                                                                        0x00000200L
4756 #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK                                                                   0x00000400L
4757 #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK                                                                    0x00000800L
4758 #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK                                                                    0x00001000L
4759 #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK                                                                    0x00002000L
4760 #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK                                                                    0x00004000L
4761 //GDS_ENHANCE2
4762 #define GDS_ENHANCE2__MISC__SHIFT                                                                             0x0
4763 #define GDS_ENHANCE2__UNUSED__SHIFT                                                                           0x10
4764 #define GDS_ENHANCE2__MISC_MASK                                                                               0x0000FFFFL
4765 #define GDS_ENHANCE2__UNUSED_MASK                                                                             0xFFFF0000L
4766 //GDS_PROTECTION_FAULT
4767 #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                                0x0
4768 #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                           0x1
4769 #define GDS_PROTECTION_FAULT__GRBM__SHIFT                                                                     0x2
4770 #define GDS_PROTECTION_FAULT__SH_ID__SHIFT                                                                    0x3
4771 #define GDS_PROTECTION_FAULT__CU_ID__SHIFT                                                                    0x6
4772 #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT                                                                  0xa
4773 #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT                                                                  0xc
4774 #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT                                                                  0x10
4775 #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK                                                                  0x00000001L
4776 #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                             0x00000002L
4777 #define GDS_PROTECTION_FAULT__GRBM_MASK                                                                       0x00000004L
4778 #define GDS_PROTECTION_FAULT__SH_ID_MASK                                                                      0x00000038L
4779 #define GDS_PROTECTION_FAULT__CU_ID_MASK                                                                      0x000003C0L
4780 #define GDS_PROTECTION_FAULT__SIMD_ID_MASK                                                                    0x00000C00L
4781 #define GDS_PROTECTION_FAULT__WAVE_ID_MASK                                                                    0x0000F000L
4782 #define GDS_PROTECTION_FAULT__ADDRESS_MASK                                                                    0xFFFF0000L
4783 //GDS_VM_PROTECTION_FAULT
4784 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT                                                             0x0
4785 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT                                                        0x1
4786 #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT                                                                   0x2
4787 #define GDS_VM_PROTECTION_FAULT__OA__SHIFT                                                                    0x3
4788 #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT                                                                  0x4
4789 #define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT                                                                   0x5
4790 #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT                                                                  0x8
4791 #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT                                                               0x10
4792 #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK                                                               0x00000001L
4793 #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK                                                          0x00000002L
4794 #define GDS_VM_PROTECTION_FAULT__GWS_MASK                                                                     0x00000004L
4795 #define GDS_VM_PROTECTION_FAULT__OA_MASK                                                                      0x00000008L
4796 #define GDS_VM_PROTECTION_FAULT__GRBM_MASK                                                                    0x00000010L
4797 #define GDS_VM_PROTECTION_FAULT__TMZ_MASK                                                                     0x00000020L
4798 #define GDS_VM_PROTECTION_FAULT__VMID_MASK                                                                    0x00000F00L
4799 #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK                                                                 0xFFFF0000L
4800 //GDS_EDC_CNT
4801 #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT                                                                       0x0
4802 #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT                                                               0x2
4803 #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT                                                                       0x4
4804 #define GDS_EDC_CNT__UNUSED__SHIFT                                                                            0x6
4805 #define GDS_EDC_CNT__GDS_MEM_DED_MASK                                                                         0x00000003L
4806 #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK                                                                 0x0000000CL
4807 #define GDS_EDC_CNT__GDS_MEM_SEC_MASK                                                                         0x00000030L
4808 #define GDS_EDC_CNT__UNUSED_MASK                                                                              0xFFFFFFC0L
4809 //GDS_EDC_GRBM_CNT
4810 #define GDS_EDC_GRBM_CNT__DED__SHIFT                                                                          0x0
4811 #define GDS_EDC_GRBM_CNT__SEC__SHIFT                                                                          0x2
4812 #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT                                                                       0x4
4813 #define GDS_EDC_GRBM_CNT__DED_MASK                                                                            0x00000003L
4814 #define GDS_EDC_GRBM_CNT__SEC_MASK                                                                            0x0000000CL
4815 #define GDS_EDC_GRBM_CNT__UNUSED_MASK                                                                         0xFFFFFFF0L
4816 //GDS_EDC_OA_DED
4817 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT                                                            0x0
4818 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT                                                            0x1
4819 #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT                                                                     0x2
4820 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT                                                             0x3
4821 #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT                                                                  0x4
4822 #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT                                                                  0x5
4823 #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT                                                                  0x6
4824 #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT                                                                  0x7
4825 #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT                                                                  0x8
4826 #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT                                                                  0x9
4827 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT                                                                  0xa
4828 #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT                                                                  0xb
4829 #define GDS_EDC_OA_DED__UNUSED1__SHIFT                                                                        0xc
4830 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK                                                              0x00000001L
4831 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK                                                              0x00000002L
4832 #define GDS_EDC_OA_DED__ME0_CS_DED_MASK                                                                       0x00000004L
4833 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK                                                               0x00000008L
4834 #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK                                                                    0x00000010L
4835 #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK                                                                    0x00000020L
4836 #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK                                                                    0x00000040L
4837 #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK                                                                    0x00000080L
4838 #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK                                                                    0x00000100L
4839 #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK                                                                    0x00000200L
4840 #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK                                                                    0x00000400L
4841 #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK                                                                    0x00000800L
4842 #define GDS_EDC_OA_DED__UNUSED1_MASK                                                                          0xFFFFF000L
4843 //GDS_DSM_CNTL
4844 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT                                                 0x0
4845 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT                                                 0x1
4846 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                      0x2
4847 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT                                         0x3
4848 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT                                         0x4
4849 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
4850 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT                                         0x6
4851 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT                                         0x7
4852 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT                                              0x8
4853 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT                                        0x9
4854 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT                                        0xa
4855 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT                                             0xb
4856 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT                                            0xc
4857 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT                                            0xd
4858 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT                                                 0xe
4859 #define GDS_DSM_CNTL__UNUSED__SHIFT                                                                           0xf
4860 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK                                                   0x00000001L
4861 #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK                                                   0x00000002L
4862 #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK                                                        0x00000004L
4863 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK                                           0x00000008L
4864 #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK                                           0x00000010L
4865 #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
4866 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK                                           0x00000040L
4867 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK                                           0x00000080L
4868 #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK                                                0x00000100L
4869 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK                                          0x00000200L
4870 #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK                                          0x00000400L
4871 #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK                                               0x00000800L
4872 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK                                              0x00001000L
4873 #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK                                              0x00002000L
4874 #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK                                                   0x00004000L
4875 #define GDS_DSM_CNTL__UNUSED_MASK                                                                             0xFFFF8000L
4876 //GDS_EDC_OA_PHY_CNT
4877 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT                                                        0x0
4878 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT                                                        0x2
4879 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT                                                        0x4
4880 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT                                                        0x6
4881 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT                                                       0x8
4882 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT                                                                    0xa
4883 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK                                                          0x00000003L
4884 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK                                                          0x0000000CL
4885 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK                                                          0x00000030L
4886 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK                                                          0x000000C0L
4887 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK                                                         0x00000300L
4888 #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK                                                                      0xFFFFFC00L
4889 //GDS_EDC_OA_PIPE_CNT
4890 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT                                                    0x0
4891 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT                                                    0x2
4892 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT                                                    0x4
4893 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT                                                    0x6
4894 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT                                                    0x8
4895 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT                                                    0xa
4896 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT                                                    0xc
4897 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT                                                    0xe
4898 #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT                                                                    0x10
4899 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK                                                      0x00000003L
4900 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK                                                      0x0000000CL
4901 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK                                                      0x00000030L
4902 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK                                                      0x000000C0L
4903 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK                                                      0x00000300L
4904 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK                                                      0x00000C00L
4905 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK                                                      0x00003000L
4906 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK                                                      0x0000C000L
4907 #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK                                                                      0xFFFF0000L
4908 //GDS_DSM_CNTL2
4909 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT                                                     0x0
4910 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT                                                     0x2
4911 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT                                             0x3
4912 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT                                             0x5
4913 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT                                             0x6
4914 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT                                             0x8
4915 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT                                            0x9
4916 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT                                            0xb
4917 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT                                                0xc
4918 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT                                                0xe
4919 #define GDS_DSM_CNTL2__UNUSED__SHIFT                                                                          0xf
4920 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT                                                                0x1a
4921 #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK                                                       0x00000003L
4922 #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK                                                       0x00000004L
4923 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
4924 #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK                                               0x00000020L
4925 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK                                               0x000000C0L
4926 #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK                                               0x00000100L
4927 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK                                              0x00000600L
4928 #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK                                              0x00000800L
4929 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK                                                  0x00003000L
4930 #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK                                                  0x00004000L
4931 #define GDS_DSM_CNTL2__UNUSED_MASK                                                                            0x03FF8000L
4932 #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK                                                                  0xFC000000L
4933 //GDS_WD_GDS_CSB
4934 #define GDS_WD_GDS_CSB__COUNTER__SHIFT                                                                        0x0
4935 #define GDS_WD_GDS_CSB__UNUSED__SHIFT                                                                         0xd
4936 #define GDS_WD_GDS_CSB__COUNTER_MASK                                                                          0x00001FFFL
4937 #define GDS_WD_GDS_CSB__UNUSED_MASK                                                                           0xFFFFE000L
4938 
4939 
4940 // addressBlock: gc_rbdec
4941 //DB_DEBUG
4942 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT                                                       0x0
4943 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT                                                         0x1
4944 #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT                                                                    0x2
4945 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT                                                              0x3
4946 #define DB_DEBUG__FORCE_Z_MODE__SHIFT                                                                         0x4
4947 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT                                                               0x6
4948 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT                                                             0x7
4949 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT                                                               0x8
4950 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT                                                              0xa
4951 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT                                                              0xc
4952 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT                                                                 0xe
4953 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT                                                           0xf
4954 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT                                                              0x10
4955 #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT                                                                  0x11
4956 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT                                                               0x12
4957 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT                                                             0x13
4958 #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT                                                                    0x15
4959 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT                                                0x16
4960 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT                                                    0x17
4961 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT                                                           0x18
4962 #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT                                                                   0x1c
4963 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT                                                           0x1d
4964 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT                                                           0x1e
4965 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT                                                           0x1f
4966 #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK                                                         0x00000001L
4967 #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK                                                           0x00000002L
4968 #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK                                                                      0x00000004L
4969 #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK                                                                0x00000008L
4970 #define DB_DEBUG__FORCE_Z_MODE_MASK                                                                           0x00000030L
4971 #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK                                                                 0x00000040L
4972 #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK                                                               0x00000080L
4973 #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK                                                                 0x00000300L
4974 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK                                                                0x00000C00L
4975 #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK                                                                0x00003000L
4976 #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK                                                                   0x00004000L
4977 #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK                                                             0x00008000L
4978 #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK                                                                0x00010000L
4979 #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK                                                                    0x00020000L
4980 #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK                                                                 0x00040000L
4981 #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK                                                               0x00180000L
4982 #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK                                                                      0x00200000L
4983 #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK                                                  0x00400000L
4984 #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK                                                      0x00800000L
4985 #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK                                                             0x0F000000L
4986 #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK                                                                     0x10000000L
4987 #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK                                                             0x20000000L
4988 #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK                                                             0x40000000L
4989 #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK                                                             0x80000000L
4990 //DB_DEBUG2
4991 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT                                                            0x0
4992 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT                                                          0x1
4993 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT                                                            0x2
4994 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT                                                                 0x3
4995 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT                                                        0x4
4996 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT                                                            0x5
4997 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT                                                        0x6
4998 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT                                                        0x7
4999 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT                                                     0x8
5000 #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT                                                                       0x9
5001 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT                                                    0xe
5002 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT                                                             0xf
5003 #define DB_DEBUG2__RESERVED__SHIFT                                                                            0x10
5004 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT                                                         0x11
5005 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT                                                         0x12
5006 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT                                                        0x13
5007 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT                                                             0x1c
5008 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT                                                        0x1d
5009 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT                                                    0x1e
5010 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT                                                0x1f
5011 #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK                                                              0x00000001L
5012 #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK                                                            0x00000002L
5013 #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK                                                              0x00000004L
5014 #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK                                                                   0x00000008L
5015 #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK                                                          0x00000010L
5016 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK                                                              0x00000020L
5017 #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK                                                          0x00000040L
5018 #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK                                                          0x00000080L
5019 #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK                                                       0x00000100L
5020 #define DB_DEBUG2__CLK_OFF_DELAY_MASK                                                                         0x00003E00L
5021 #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK                                                      0x00004000L
5022 #define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK                                                               0x00008000L
5023 #define DB_DEBUG2__RESERVED_MASK                                                                              0x00010000L
5024 #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK                                                           0x00020000L
5025 #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK                                                           0x00040000L
5026 #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK                                                          0x00080000L
5027 #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK                                                               0x10000000L
5028 #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK                                                          0x20000000L
5029 #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK                                                      0x40000000L
5030 #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK                                                  0x80000000L
5031 //DB_DEBUG3
5032 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT                                                     0x0
5033 #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT                                                             0x1
5034 #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT                                                                    0x2
5035 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT                                                     0x3
5036 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT                                                          0x4
5037 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT                                                             0x5
5038 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT                                                              0x6
5039 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT                                                              0x7
5040 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT                                                      0x8
5041 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT                                                 0x9
5042 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT                                            0xa
5043 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT                                                        0xb
5044 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT                                                        0xc
5045 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT                                                                0xd
5046 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT                                                         0xe
5047 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT                                                       0xf
5048 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT                                                             0x10
5049 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT                                                         0x11
5050 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT                                                        0x12
5051 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT                                                     0x13
5052 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT                                                         0x14
5053 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT                                                0x15
5054 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT                                                        0x16
5055 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT                                                  0x17
5056 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT                                                           0x18
5057 #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT                                                                 0x19
5058 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT                                                             0x1a
5059 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT                                                       0x1b
5060 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT                                                         0x1c
5061 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT                                                         0x1d
5062 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT                                                       0x1e
5063 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT                                                   0x1f
5064 #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK                                                       0x00000001L
5065 #define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK                                                               0x00000002L
5066 #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK                                                                      0x00000004L
5067 #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK                                                       0x00000008L
5068 #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK                                                            0x00000010L
5069 #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK                                                               0x00000020L
5070 #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK                                                                0x00000040L
5071 #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK                                                                0x00000080L
5072 #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK                                                        0x00000100L
5073 #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK                                                   0x00000200L
5074 #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK                                              0x00000400L
5075 #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK                                                          0x00000800L
5076 #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK                                                          0x00001000L
5077 #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK                                                                  0x00002000L
5078 #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK                                                           0x00004000L
5079 #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK                                                         0x00008000L
5080 #define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK                                                               0x00010000L
5081 #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK                                                           0x00020000L
5082 #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK                                                          0x00040000L
5083 #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK                                                       0x00080000L
5084 #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK                                                           0x00100000L
5085 #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK                                                  0x00200000L
5086 #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK                                                          0x00400000L
5087 #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK                                                    0x00800000L
5088 #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK                                                             0x01000000L
5089 #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK                                                                   0x02000000L
5090 #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK                                                               0x04000000L
5091 #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK                                                         0x08000000L
5092 #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK                                                           0x10000000L
5093 #define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK                                                           0x20000000L
5094 #define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK                                                         0x40000000L
5095 #define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK                                                     0x80000000L
5096 //DB_DEBUG4
5097 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT                                                         0x0
5098 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT                                                   0x1
5099 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT                                                    0x2
5100 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT                                             0x3
5101 #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT                                                          0x4
5102 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT                                                       0x5
5103 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT                                                    0x6
5104 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT                                                                0x7
5105 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT                                                  0x8
5106 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT                                                        0x9
5107 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT                                                        0xa
5108 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT                                                        0xb
5109 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT                                                           0xc
5110 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT                                                   0xd
5111 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT                                              0xe
5112 #define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT                                                                 0xf
5113 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT                                                0x10
5114 #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT                                                  0x11
5115 #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT                                                  0x12
5116 #define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT                                                                     0x13
5117 #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK                                                           0x00000001L
5118 #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK                                                     0x00000002L
5119 #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK                                                      0x00000004L
5120 #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK                                               0x00000008L
5121 #define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK                                                            0x00000010L
5122 #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK                                                         0x00000020L
5123 #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK                                                      0x00000040L
5124 #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK                                                                  0x00000080L
5125 #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK                                                    0x00000100L
5126 #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK                                                          0x00000200L
5127 #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK                                                          0x00000400L
5128 #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK                                                          0x00000800L
5129 #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK                                                             0x00001000L
5130 #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK                                                     0x00002000L
5131 #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK                                                0x00004000L
5132 #define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK                                                                   0x00008000L
5133 #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK                                                  0x00010000L
5134 #define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK                                                    0x00020000L
5135 #define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK                                                    0x00040000L
5136 #define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK                                                                       0xFFF80000L
5137 //DB_CREDIT_LIMIT
5138 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT                                                            0x0
5139 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT                                                            0x5
5140 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT                                                           0xa
5141 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT                                                            0x18
5142 #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK                                                              0x0000001FL
5143 #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK                                                              0x000003E0L
5144 #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK                                                             0x00001C00L
5145 #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK                                                              0x7F000000L
5146 //DB_WATERMARKS
5147 #define DB_WATERMARKS__DEPTH_FREE__SHIFT                                                                      0x0
5148 #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT                                                                     0x5
5149 #define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT                                                                 0xb
5150 #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT                                                              0xf
5151 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT                                                            0x14
5152 #define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT                                                                0x1e
5153 #define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT                                                                 0x1f
5154 #define DB_WATERMARKS__DEPTH_FREE_MASK                                                                        0x0000001FL
5155 #define DB_WATERMARKS__DEPTH_FLUSH_MASK                                                                       0x000007E0L
5156 #define DB_WATERMARKS__FORCE_SUMMARIZE_MASK                                                                   0x00007800L
5157 #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK                                                                0x000F8000L
5158 #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK                                                              0x0FF00000L
5159 #define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK                                                                  0x40000000L
5160 #define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK                                                                   0x80000000L
5161 //DB_SUBTILE_CONTROL
5162 #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT                                                                    0x0
5163 #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT                                                                    0x2
5164 #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT                                                                    0x4
5165 #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT                                                                    0x6
5166 #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT                                                                    0x8
5167 #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT                                                                    0xa
5168 #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT                                                                    0xc
5169 #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT                                                                    0xe
5170 #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT                                                                   0x10
5171 #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT                                                                   0x12
5172 #define DB_SUBTILE_CONTROL__MSAA1_X_MASK                                                                      0x00000003L
5173 #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK                                                                      0x0000000CL
5174 #define DB_SUBTILE_CONTROL__MSAA2_X_MASK                                                                      0x00000030L
5175 #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK                                                                      0x000000C0L
5176 #define DB_SUBTILE_CONTROL__MSAA4_X_MASK                                                                      0x00000300L
5177 #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK                                                                      0x00000C00L
5178 #define DB_SUBTILE_CONTROL__MSAA8_X_MASK                                                                      0x00003000L
5179 #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK                                                                      0x0000C000L
5180 #define DB_SUBTILE_CONTROL__MSAA16_X_MASK                                                                     0x00030000L
5181 #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK                                                                     0x000C0000L
5182 //DB_FREE_CACHELINES
5183 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT                                                           0x0
5184 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT                                                           0x7
5185 #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT                                                               0xe
5186 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT                                                           0x14
5187 #define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT                                                             0x18
5188 #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK                                                             0x0000007FL
5189 #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK                                                             0x00003F80L
5190 #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK                                                                 0x000FC000L
5191 #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK                                                             0x00F00000L
5192 #define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK                                                               0xFF000000L
5193 //DB_FIFO_DEPTH1
5194 #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT                                                           0x0
5195 #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT                                                           0x5
5196 #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT                                                                      0xa
5197 #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT                                                                       0x10
5198 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT                                                         0x15
5199 #define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK                                                             0x0000001FL
5200 #define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK                                                             0x000003E0L
5201 #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK                                                                        0x0000FC00L
5202 #define DB_FIFO_DEPTH1__QC_DEPTH_MASK                                                                         0x001F0000L
5203 #define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK                                                           0x1FE00000L
5204 //DB_FIFO_DEPTH2
5205 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT                                                               0x0
5206 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT                                                            0x8
5207 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT                                                               0xf
5208 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT                                                            0x19
5209 #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK                                                                 0x000000FFL
5210 #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK                                                              0x00007F00L
5211 #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK                                                                 0x01FF8000L
5212 #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK                                                              0xFE000000L
5213 //DB_EXCEPTION_CONTROL
5214 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT                                                    0x0
5215 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT                                                     0x1
5216 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT                                                       0x2
5217 #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK                                                      0x00000001L
5218 #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK                                                       0x00000002L
5219 #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK                                                         0x00000004L
5220 //DB_RING_CONTROL
5221 #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT                                                               0x0
5222 #define DB_RING_CONTROL__COUNTER_CONTROL_MASK                                                                 0x00000003L
5223 //DB_MEM_ARB_WATERMARKS
5224 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT                                                       0x0
5225 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT                                                       0x8
5226 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT                                                       0x10
5227 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT                                                       0x18
5228 #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK                                                         0x00000007L
5229 #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK                                                         0x00000700L
5230 #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK                                                         0x00070000L
5231 #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK                                                         0x07000000L
5232 //DB_RMI_CACHE_POLICY
5233 #define DB_RMI_CACHE_POLICY__Z_RD__SHIFT                                                                      0x0
5234 #define DB_RMI_CACHE_POLICY__S_RD__SHIFT                                                                      0x1
5235 #define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT                                                                  0x2
5236 #define DB_RMI_CACHE_POLICY__Z_WR__SHIFT                                                                      0x8
5237 #define DB_RMI_CACHE_POLICY__S_WR__SHIFT                                                                      0x9
5238 #define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT                                                                  0xa
5239 #define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT                                                                 0xb
5240 #define DB_RMI_CACHE_POLICY__CC_RD__SHIFT                                                                     0x10
5241 #define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT                                                                  0x11
5242 #define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT                                                                  0x12
5243 #define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT                                                                    0x13
5244 #define DB_RMI_CACHE_POLICY__CC_WR__SHIFT                                                                     0x18
5245 #define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT                                                                  0x19
5246 #define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT                                                                  0x1a
5247 #define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT                                                                    0x1b
5248 #define DB_RMI_CACHE_POLICY__Z_RD_MASK                                                                        0x00000001L
5249 #define DB_RMI_CACHE_POLICY__S_RD_MASK                                                                        0x00000002L
5250 #define DB_RMI_CACHE_POLICY__HTILE_RD_MASK                                                                    0x00000004L
5251 #define DB_RMI_CACHE_POLICY__Z_WR_MASK                                                                        0x00000100L
5252 #define DB_RMI_CACHE_POLICY__S_WR_MASK                                                                        0x00000200L
5253 #define DB_RMI_CACHE_POLICY__HTILE_WR_MASK                                                                    0x00000400L
5254 #define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK                                                                   0x00000800L
5255 #define DB_RMI_CACHE_POLICY__CC_RD_MASK                                                                       0x00010000L
5256 #define DB_RMI_CACHE_POLICY__FMASK_RD_MASK                                                                    0x00020000L
5257 #define DB_RMI_CACHE_POLICY__CMASK_RD_MASK                                                                    0x00040000L
5258 #define DB_RMI_CACHE_POLICY__DCC_RD_MASK                                                                      0x00080000L
5259 #define DB_RMI_CACHE_POLICY__CC_WR_MASK                                                                       0x01000000L
5260 #define DB_RMI_CACHE_POLICY__FMASK_WR_MASK                                                                    0x02000000L
5261 #define DB_RMI_CACHE_POLICY__CMASK_WR_MASK                                                                    0x04000000L
5262 #define DB_RMI_CACHE_POLICY__DCC_WR_MASK                                                                      0x08000000L
5263 //DB_DFSM_CONFIG
5264 #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT                                                                    0x0
5265 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT                                                               0x1
5266 #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT                                                                   0x2
5267 #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT                                                                    0x3
5268 #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT                                                          0x8
5269 #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK                                                                      0x00000001L
5270 #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK                                                                 0x00000002L
5271 #define DB_DFSM_CONFIG__DISABLE_POPS_MASK                                                                     0x00000004L
5272 #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK                                                                      0x00000008L
5273 #define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK                                                            0x00007F00L
5274 //DB_DFSM_WATERMARK
5275 #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT                                                         0x0
5276 #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT                                                         0x10
5277 #define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK                                                           0x0000FFFFL
5278 #define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK                                                           0xFFFF0000L
5279 //DB_DFSM_TILES_IN_FLIGHT
5280 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
5281 #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT                                                            0x10
5282 #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
5283 #define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK                                                              0xFFFF0000L
5284 //DB_DFSM_PRIMS_IN_FLIGHT
5285 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT                                                        0x0
5286 #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT                                                            0x10
5287 #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK                                                          0x0000FFFFL
5288 #define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK                                                              0xFFFF0000L
5289 //DB_DFSM_WATCHDOG
5290 #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT                                                                 0x0
5291 #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK                                                                   0xFFFFFFFFL
5292 //DB_DFSM_FLUSH_ENABLE
5293 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT                                                           0x0
5294 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT                                                       0x18
5295 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT                                                               0x1c
5296 #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK                                                             0x000003FFL
5297 #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK                                                         0x0F000000L
5298 #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK                                                                 0xF0000000L
5299 //DB_DFSM_FLUSH_AUX_EVENT
5300 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT                                                               0x0
5301 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT                                                               0x8
5302 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT                                                               0x10
5303 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT                                                               0x18
5304 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK                                                                 0x000000FFL
5305 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK                                                                 0x0000FF00L
5306 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK                                                                 0x00FF0000L
5307 #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK                                                                 0xFF000000L
5308 //CC_RB_REDUNDANCY
5309 #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                                   0x8
5310 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                               0xc
5311 #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                                   0x10
5312 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                               0x14
5313 #define CC_RB_REDUNDANCY__FAILED_RB0_MASK                                                                     0x00000F00L
5314 #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                                 0x00001000L
5315 #define CC_RB_REDUNDANCY__FAILED_RB1_MASK                                                                     0x000F0000L
5316 #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                                 0x00100000L
5317 //CC_RB_BACKEND_DISABLE
5318 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                         0x10
5319 #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                           0x00FF0000L
5320 //GB_ADDR_CONFIG
5321 #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                      0x0
5322 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                           0x3
5323 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                           0x6
5324 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                           0x8
5325 #define GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                      0xc
5326 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT                                                        0x10
5327 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                             0x13
5328 #define GB_ADDR_CONFIG__NUM_GPUS__SHIFT                                                                       0x15
5329 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT                                                            0x18
5330 #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                                  0x1a
5331 #define GB_ADDR_CONFIG__ROW_SIZE__SHIFT                                                                       0x1c
5332 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT                                                                0x1e
5333 #define GB_ADDR_CONFIG__SE_ENABLE__SHIFT                                                                      0x1f
5334 #define GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                        0x00000007L
5335 #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                             0x00000038L
5336 #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                             0x000000C0L
5337 #define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                             0x00000700L
5338 #define GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                        0x00007000L
5339 #define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK                                                          0x00070000L
5340 #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                               0x00180000L
5341 #define GB_ADDR_CONFIG__NUM_GPUS_MASK                                                                         0x00E00000L
5342 #define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK                                                              0x03000000L
5343 #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                                    0x0C000000L
5344 #define GB_ADDR_CONFIG__ROW_SIZE_MASK                                                                         0x30000000L
5345 #define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK                                                                  0x40000000L
5346 #define GB_ADDR_CONFIG__SE_ENABLE_MASK                                                                        0x80000000L
5347 //GB_BACKEND_MAP
5348 #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT                                                                    0x0
5349 #define GB_BACKEND_MAP__BACKEND_MAP_MASK                                                                      0xFFFFFFFFL
5350 //GB_GPU_ID
5351 #define GB_GPU_ID__GPU_ID__SHIFT                                                                              0x0
5352 #define GB_GPU_ID__GPU_ID_MASK                                                                                0x0000000FL
5353 //CC_RB_DAISY_CHAIN
5354 #define CC_RB_DAISY_CHAIN__RB_0__SHIFT                                                                        0x0
5355 #define CC_RB_DAISY_CHAIN__RB_1__SHIFT                                                                        0x4
5356 #define CC_RB_DAISY_CHAIN__RB_2__SHIFT                                                                        0x8
5357 #define CC_RB_DAISY_CHAIN__RB_3__SHIFT                                                                        0xc
5358 #define CC_RB_DAISY_CHAIN__RB_4__SHIFT                                                                        0x10
5359 #define CC_RB_DAISY_CHAIN__RB_5__SHIFT                                                                        0x14
5360 #define CC_RB_DAISY_CHAIN__RB_6__SHIFT                                                                        0x18
5361 #define CC_RB_DAISY_CHAIN__RB_7__SHIFT                                                                        0x1c
5362 #define CC_RB_DAISY_CHAIN__RB_0_MASK                                                                          0x0000000FL
5363 #define CC_RB_DAISY_CHAIN__RB_1_MASK                                                                          0x000000F0L
5364 #define CC_RB_DAISY_CHAIN__RB_2_MASK                                                                          0x00000F00L
5365 #define CC_RB_DAISY_CHAIN__RB_3_MASK                                                                          0x0000F000L
5366 #define CC_RB_DAISY_CHAIN__RB_4_MASK                                                                          0x000F0000L
5367 #define CC_RB_DAISY_CHAIN__RB_5_MASK                                                                          0x00F00000L
5368 #define CC_RB_DAISY_CHAIN__RB_6_MASK                                                                          0x0F000000L
5369 #define CC_RB_DAISY_CHAIN__RB_7_MASK                                                                          0xF0000000L
5370 //GB_ADDR_CONFIG_READ
5371 #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                                 0x0
5372 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                      0x3
5373 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT                                                      0x6
5374 #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                      0x8
5375 #define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                                 0xc
5376 #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT                                                   0x10
5377 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                        0x13
5378 #define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT                                                                  0x15
5379 #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT                                                       0x18
5380 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT                                                             0x1a
5381 #define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT                                                                  0x1c
5382 #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT                                                           0x1e
5383 #define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT                                                                 0x1f
5384 #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                                   0x00000007L
5385 #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                        0x00000038L
5386 #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK                                                        0x000000C0L
5387 #define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                        0x00000700L
5388 #define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                                   0x00007000L
5389 #define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK                                                     0x00070000L
5390 #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                          0x00180000L
5391 #define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK                                                                    0x00E00000L
5392 #define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK                                                         0x03000000L
5393 #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK                                                               0x0C000000L
5394 #define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK                                                                    0x30000000L
5395 #define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK                                                             0x40000000L
5396 #define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK                                                                   0x80000000L
5397 //GB_TILE_MODE0
5398 #define GB_TILE_MODE0__ARRAY_MODE__SHIFT                                                                      0x2
5399 #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT                                                                     0x6
5400 #define GB_TILE_MODE0__TILE_SPLIT__SHIFT                                                                      0xb
5401 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5402 #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT                                                                    0x19
5403 #define GB_TILE_MODE0__ARRAY_MODE_MASK                                                                        0x0000003CL
5404 #define GB_TILE_MODE0__PIPE_CONFIG_MASK                                                                       0x000007C0L
5405 #define GB_TILE_MODE0__TILE_SPLIT_MASK                                                                        0x00003800L
5406 #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5407 #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5408 //GB_TILE_MODE1
5409 #define GB_TILE_MODE1__ARRAY_MODE__SHIFT                                                                      0x2
5410 #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT                                                                     0x6
5411 #define GB_TILE_MODE1__TILE_SPLIT__SHIFT                                                                      0xb
5412 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5413 #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT                                                                    0x19
5414 #define GB_TILE_MODE1__ARRAY_MODE_MASK                                                                        0x0000003CL
5415 #define GB_TILE_MODE1__PIPE_CONFIG_MASK                                                                       0x000007C0L
5416 #define GB_TILE_MODE1__TILE_SPLIT_MASK                                                                        0x00003800L
5417 #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5418 #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5419 //GB_TILE_MODE2
5420 #define GB_TILE_MODE2__ARRAY_MODE__SHIFT                                                                      0x2
5421 #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT                                                                     0x6
5422 #define GB_TILE_MODE2__TILE_SPLIT__SHIFT                                                                      0xb
5423 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5424 #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT                                                                    0x19
5425 #define GB_TILE_MODE2__ARRAY_MODE_MASK                                                                        0x0000003CL
5426 #define GB_TILE_MODE2__PIPE_CONFIG_MASK                                                                       0x000007C0L
5427 #define GB_TILE_MODE2__TILE_SPLIT_MASK                                                                        0x00003800L
5428 #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5429 #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5430 //GB_TILE_MODE3
5431 #define GB_TILE_MODE3__ARRAY_MODE__SHIFT                                                                      0x2
5432 #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT                                                                     0x6
5433 #define GB_TILE_MODE3__TILE_SPLIT__SHIFT                                                                      0xb
5434 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5435 #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT                                                                    0x19
5436 #define GB_TILE_MODE3__ARRAY_MODE_MASK                                                                        0x0000003CL
5437 #define GB_TILE_MODE3__PIPE_CONFIG_MASK                                                                       0x000007C0L
5438 #define GB_TILE_MODE3__TILE_SPLIT_MASK                                                                        0x00003800L
5439 #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5440 #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5441 //GB_TILE_MODE4
5442 #define GB_TILE_MODE4__ARRAY_MODE__SHIFT                                                                      0x2
5443 #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT                                                                     0x6
5444 #define GB_TILE_MODE4__TILE_SPLIT__SHIFT                                                                      0xb
5445 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5446 #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT                                                                    0x19
5447 #define GB_TILE_MODE4__ARRAY_MODE_MASK                                                                        0x0000003CL
5448 #define GB_TILE_MODE4__PIPE_CONFIG_MASK                                                                       0x000007C0L
5449 #define GB_TILE_MODE4__TILE_SPLIT_MASK                                                                        0x00003800L
5450 #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5451 #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5452 //GB_TILE_MODE5
5453 #define GB_TILE_MODE5__ARRAY_MODE__SHIFT                                                                      0x2
5454 #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT                                                                     0x6
5455 #define GB_TILE_MODE5__TILE_SPLIT__SHIFT                                                                      0xb
5456 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5457 #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT                                                                    0x19
5458 #define GB_TILE_MODE5__ARRAY_MODE_MASK                                                                        0x0000003CL
5459 #define GB_TILE_MODE5__PIPE_CONFIG_MASK                                                                       0x000007C0L
5460 #define GB_TILE_MODE5__TILE_SPLIT_MASK                                                                        0x00003800L
5461 #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5462 #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5463 //GB_TILE_MODE6
5464 #define GB_TILE_MODE6__ARRAY_MODE__SHIFT                                                                      0x2
5465 #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT                                                                     0x6
5466 #define GB_TILE_MODE6__TILE_SPLIT__SHIFT                                                                      0xb
5467 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5468 #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT                                                                    0x19
5469 #define GB_TILE_MODE6__ARRAY_MODE_MASK                                                                        0x0000003CL
5470 #define GB_TILE_MODE6__PIPE_CONFIG_MASK                                                                       0x000007C0L
5471 #define GB_TILE_MODE6__TILE_SPLIT_MASK                                                                        0x00003800L
5472 #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5473 #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5474 //GB_TILE_MODE7
5475 #define GB_TILE_MODE7__ARRAY_MODE__SHIFT                                                                      0x2
5476 #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT                                                                     0x6
5477 #define GB_TILE_MODE7__TILE_SPLIT__SHIFT                                                                      0xb
5478 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5479 #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT                                                                    0x19
5480 #define GB_TILE_MODE7__ARRAY_MODE_MASK                                                                        0x0000003CL
5481 #define GB_TILE_MODE7__PIPE_CONFIG_MASK                                                                       0x000007C0L
5482 #define GB_TILE_MODE7__TILE_SPLIT_MASK                                                                        0x00003800L
5483 #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5484 #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5485 //GB_TILE_MODE8
5486 #define GB_TILE_MODE8__ARRAY_MODE__SHIFT                                                                      0x2
5487 #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT                                                                     0x6
5488 #define GB_TILE_MODE8__TILE_SPLIT__SHIFT                                                                      0xb
5489 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5490 #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT                                                                    0x19
5491 #define GB_TILE_MODE8__ARRAY_MODE_MASK                                                                        0x0000003CL
5492 #define GB_TILE_MODE8__PIPE_CONFIG_MASK                                                                       0x000007C0L
5493 #define GB_TILE_MODE8__TILE_SPLIT_MASK                                                                        0x00003800L
5494 #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5495 #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5496 //GB_TILE_MODE9
5497 #define GB_TILE_MODE9__ARRAY_MODE__SHIFT                                                                      0x2
5498 #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT                                                                     0x6
5499 #define GB_TILE_MODE9__TILE_SPLIT__SHIFT                                                                      0xb
5500 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT                                                             0x16
5501 #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT                                                                    0x19
5502 #define GB_TILE_MODE9__ARRAY_MODE_MASK                                                                        0x0000003CL
5503 #define GB_TILE_MODE9__PIPE_CONFIG_MASK                                                                       0x000007C0L
5504 #define GB_TILE_MODE9__TILE_SPLIT_MASK                                                                        0x00003800L
5505 #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK                                                               0x01C00000L
5506 #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK                                                                      0x06000000L
5507 //GB_TILE_MODE10
5508 #define GB_TILE_MODE10__ARRAY_MODE__SHIFT                                                                     0x2
5509 #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT                                                                    0x6
5510 #define GB_TILE_MODE10__TILE_SPLIT__SHIFT                                                                     0xb
5511 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5512 #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT                                                                   0x19
5513 #define GB_TILE_MODE10__ARRAY_MODE_MASK                                                                       0x0000003CL
5514 #define GB_TILE_MODE10__PIPE_CONFIG_MASK                                                                      0x000007C0L
5515 #define GB_TILE_MODE10__TILE_SPLIT_MASK                                                                       0x00003800L
5516 #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5517 #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5518 //GB_TILE_MODE11
5519 #define GB_TILE_MODE11__ARRAY_MODE__SHIFT                                                                     0x2
5520 #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT                                                                    0x6
5521 #define GB_TILE_MODE11__TILE_SPLIT__SHIFT                                                                     0xb
5522 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5523 #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT                                                                   0x19
5524 #define GB_TILE_MODE11__ARRAY_MODE_MASK                                                                       0x0000003CL
5525 #define GB_TILE_MODE11__PIPE_CONFIG_MASK                                                                      0x000007C0L
5526 #define GB_TILE_MODE11__TILE_SPLIT_MASK                                                                       0x00003800L
5527 #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5528 #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5529 //GB_TILE_MODE12
5530 #define GB_TILE_MODE12__ARRAY_MODE__SHIFT                                                                     0x2
5531 #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT                                                                    0x6
5532 #define GB_TILE_MODE12__TILE_SPLIT__SHIFT                                                                     0xb
5533 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5534 #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT                                                                   0x19
5535 #define GB_TILE_MODE12__ARRAY_MODE_MASK                                                                       0x0000003CL
5536 #define GB_TILE_MODE12__PIPE_CONFIG_MASK                                                                      0x000007C0L
5537 #define GB_TILE_MODE12__TILE_SPLIT_MASK                                                                       0x00003800L
5538 #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5539 #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5540 //GB_TILE_MODE13
5541 #define GB_TILE_MODE13__ARRAY_MODE__SHIFT                                                                     0x2
5542 #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT                                                                    0x6
5543 #define GB_TILE_MODE13__TILE_SPLIT__SHIFT                                                                     0xb
5544 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5545 #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT                                                                   0x19
5546 #define GB_TILE_MODE13__ARRAY_MODE_MASK                                                                       0x0000003CL
5547 #define GB_TILE_MODE13__PIPE_CONFIG_MASK                                                                      0x000007C0L
5548 #define GB_TILE_MODE13__TILE_SPLIT_MASK                                                                       0x00003800L
5549 #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5550 #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5551 //GB_TILE_MODE14
5552 #define GB_TILE_MODE14__ARRAY_MODE__SHIFT                                                                     0x2
5553 #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT                                                                    0x6
5554 #define GB_TILE_MODE14__TILE_SPLIT__SHIFT                                                                     0xb
5555 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5556 #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT                                                                   0x19
5557 #define GB_TILE_MODE14__ARRAY_MODE_MASK                                                                       0x0000003CL
5558 #define GB_TILE_MODE14__PIPE_CONFIG_MASK                                                                      0x000007C0L
5559 #define GB_TILE_MODE14__TILE_SPLIT_MASK                                                                       0x00003800L
5560 #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5561 #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5562 //GB_TILE_MODE15
5563 #define GB_TILE_MODE15__ARRAY_MODE__SHIFT                                                                     0x2
5564 #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT                                                                    0x6
5565 #define GB_TILE_MODE15__TILE_SPLIT__SHIFT                                                                     0xb
5566 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5567 #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT                                                                   0x19
5568 #define GB_TILE_MODE15__ARRAY_MODE_MASK                                                                       0x0000003CL
5569 #define GB_TILE_MODE15__PIPE_CONFIG_MASK                                                                      0x000007C0L
5570 #define GB_TILE_MODE15__TILE_SPLIT_MASK                                                                       0x00003800L
5571 #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5572 #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5573 //GB_TILE_MODE16
5574 #define GB_TILE_MODE16__ARRAY_MODE__SHIFT                                                                     0x2
5575 #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT                                                                    0x6
5576 #define GB_TILE_MODE16__TILE_SPLIT__SHIFT                                                                     0xb
5577 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5578 #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT                                                                   0x19
5579 #define GB_TILE_MODE16__ARRAY_MODE_MASK                                                                       0x0000003CL
5580 #define GB_TILE_MODE16__PIPE_CONFIG_MASK                                                                      0x000007C0L
5581 #define GB_TILE_MODE16__TILE_SPLIT_MASK                                                                       0x00003800L
5582 #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5583 #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5584 //GB_TILE_MODE17
5585 #define GB_TILE_MODE17__ARRAY_MODE__SHIFT                                                                     0x2
5586 #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT                                                                    0x6
5587 #define GB_TILE_MODE17__TILE_SPLIT__SHIFT                                                                     0xb
5588 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5589 #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT                                                                   0x19
5590 #define GB_TILE_MODE17__ARRAY_MODE_MASK                                                                       0x0000003CL
5591 #define GB_TILE_MODE17__PIPE_CONFIG_MASK                                                                      0x000007C0L
5592 #define GB_TILE_MODE17__TILE_SPLIT_MASK                                                                       0x00003800L
5593 #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5594 #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5595 //GB_TILE_MODE18
5596 #define GB_TILE_MODE18__ARRAY_MODE__SHIFT                                                                     0x2
5597 #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT                                                                    0x6
5598 #define GB_TILE_MODE18__TILE_SPLIT__SHIFT                                                                     0xb
5599 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5600 #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT                                                                   0x19
5601 #define GB_TILE_MODE18__ARRAY_MODE_MASK                                                                       0x0000003CL
5602 #define GB_TILE_MODE18__PIPE_CONFIG_MASK                                                                      0x000007C0L
5603 #define GB_TILE_MODE18__TILE_SPLIT_MASK                                                                       0x00003800L
5604 #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5605 #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5606 //GB_TILE_MODE19
5607 #define GB_TILE_MODE19__ARRAY_MODE__SHIFT                                                                     0x2
5608 #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT                                                                    0x6
5609 #define GB_TILE_MODE19__TILE_SPLIT__SHIFT                                                                     0xb
5610 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5611 #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT                                                                   0x19
5612 #define GB_TILE_MODE19__ARRAY_MODE_MASK                                                                       0x0000003CL
5613 #define GB_TILE_MODE19__PIPE_CONFIG_MASK                                                                      0x000007C0L
5614 #define GB_TILE_MODE19__TILE_SPLIT_MASK                                                                       0x00003800L
5615 #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5616 #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5617 //GB_TILE_MODE20
5618 #define GB_TILE_MODE20__ARRAY_MODE__SHIFT                                                                     0x2
5619 #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT                                                                    0x6
5620 #define GB_TILE_MODE20__TILE_SPLIT__SHIFT                                                                     0xb
5621 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5622 #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT                                                                   0x19
5623 #define GB_TILE_MODE20__ARRAY_MODE_MASK                                                                       0x0000003CL
5624 #define GB_TILE_MODE20__PIPE_CONFIG_MASK                                                                      0x000007C0L
5625 #define GB_TILE_MODE20__TILE_SPLIT_MASK                                                                       0x00003800L
5626 #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5627 #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5628 //GB_TILE_MODE21
5629 #define GB_TILE_MODE21__ARRAY_MODE__SHIFT                                                                     0x2
5630 #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT                                                                    0x6
5631 #define GB_TILE_MODE21__TILE_SPLIT__SHIFT                                                                     0xb
5632 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5633 #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT                                                                   0x19
5634 #define GB_TILE_MODE21__ARRAY_MODE_MASK                                                                       0x0000003CL
5635 #define GB_TILE_MODE21__PIPE_CONFIG_MASK                                                                      0x000007C0L
5636 #define GB_TILE_MODE21__TILE_SPLIT_MASK                                                                       0x00003800L
5637 #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5638 #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5639 //GB_TILE_MODE22
5640 #define GB_TILE_MODE22__ARRAY_MODE__SHIFT                                                                     0x2
5641 #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT                                                                    0x6
5642 #define GB_TILE_MODE22__TILE_SPLIT__SHIFT                                                                     0xb
5643 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5644 #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT                                                                   0x19
5645 #define GB_TILE_MODE22__ARRAY_MODE_MASK                                                                       0x0000003CL
5646 #define GB_TILE_MODE22__PIPE_CONFIG_MASK                                                                      0x000007C0L
5647 #define GB_TILE_MODE22__TILE_SPLIT_MASK                                                                       0x00003800L
5648 #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5649 #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5650 //GB_TILE_MODE23
5651 #define GB_TILE_MODE23__ARRAY_MODE__SHIFT                                                                     0x2
5652 #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT                                                                    0x6
5653 #define GB_TILE_MODE23__TILE_SPLIT__SHIFT                                                                     0xb
5654 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5655 #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT                                                                   0x19
5656 #define GB_TILE_MODE23__ARRAY_MODE_MASK                                                                       0x0000003CL
5657 #define GB_TILE_MODE23__PIPE_CONFIG_MASK                                                                      0x000007C0L
5658 #define GB_TILE_MODE23__TILE_SPLIT_MASK                                                                       0x00003800L
5659 #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5660 #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5661 //GB_TILE_MODE24
5662 #define GB_TILE_MODE24__ARRAY_MODE__SHIFT                                                                     0x2
5663 #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT                                                                    0x6
5664 #define GB_TILE_MODE24__TILE_SPLIT__SHIFT                                                                     0xb
5665 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5666 #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT                                                                   0x19
5667 #define GB_TILE_MODE24__ARRAY_MODE_MASK                                                                       0x0000003CL
5668 #define GB_TILE_MODE24__PIPE_CONFIG_MASK                                                                      0x000007C0L
5669 #define GB_TILE_MODE24__TILE_SPLIT_MASK                                                                       0x00003800L
5670 #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5671 #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5672 //GB_TILE_MODE25
5673 #define GB_TILE_MODE25__ARRAY_MODE__SHIFT                                                                     0x2
5674 #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT                                                                    0x6
5675 #define GB_TILE_MODE25__TILE_SPLIT__SHIFT                                                                     0xb
5676 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5677 #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT                                                                   0x19
5678 #define GB_TILE_MODE25__ARRAY_MODE_MASK                                                                       0x0000003CL
5679 #define GB_TILE_MODE25__PIPE_CONFIG_MASK                                                                      0x000007C0L
5680 #define GB_TILE_MODE25__TILE_SPLIT_MASK                                                                       0x00003800L
5681 #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5682 #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5683 //GB_TILE_MODE26
5684 #define GB_TILE_MODE26__ARRAY_MODE__SHIFT                                                                     0x2
5685 #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT                                                                    0x6
5686 #define GB_TILE_MODE26__TILE_SPLIT__SHIFT                                                                     0xb
5687 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5688 #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT                                                                   0x19
5689 #define GB_TILE_MODE26__ARRAY_MODE_MASK                                                                       0x0000003CL
5690 #define GB_TILE_MODE26__PIPE_CONFIG_MASK                                                                      0x000007C0L
5691 #define GB_TILE_MODE26__TILE_SPLIT_MASK                                                                       0x00003800L
5692 #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5693 #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5694 //GB_TILE_MODE27
5695 #define GB_TILE_MODE27__ARRAY_MODE__SHIFT                                                                     0x2
5696 #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT                                                                    0x6
5697 #define GB_TILE_MODE27__TILE_SPLIT__SHIFT                                                                     0xb
5698 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5699 #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT                                                                   0x19
5700 #define GB_TILE_MODE27__ARRAY_MODE_MASK                                                                       0x0000003CL
5701 #define GB_TILE_MODE27__PIPE_CONFIG_MASK                                                                      0x000007C0L
5702 #define GB_TILE_MODE27__TILE_SPLIT_MASK                                                                       0x00003800L
5703 #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5704 #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5705 //GB_TILE_MODE28
5706 #define GB_TILE_MODE28__ARRAY_MODE__SHIFT                                                                     0x2
5707 #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT                                                                    0x6
5708 #define GB_TILE_MODE28__TILE_SPLIT__SHIFT                                                                     0xb
5709 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5710 #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT                                                                   0x19
5711 #define GB_TILE_MODE28__ARRAY_MODE_MASK                                                                       0x0000003CL
5712 #define GB_TILE_MODE28__PIPE_CONFIG_MASK                                                                      0x000007C0L
5713 #define GB_TILE_MODE28__TILE_SPLIT_MASK                                                                       0x00003800L
5714 #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5715 #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5716 //GB_TILE_MODE29
5717 #define GB_TILE_MODE29__ARRAY_MODE__SHIFT                                                                     0x2
5718 #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT                                                                    0x6
5719 #define GB_TILE_MODE29__TILE_SPLIT__SHIFT                                                                     0xb
5720 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5721 #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT                                                                   0x19
5722 #define GB_TILE_MODE29__ARRAY_MODE_MASK                                                                       0x0000003CL
5723 #define GB_TILE_MODE29__PIPE_CONFIG_MASK                                                                      0x000007C0L
5724 #define GB_TILE_MODE29__TILE_SPLIT_MASK                                                                       0x00003800L
5725 #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5726 #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5727 //GB_TILE_MODE30
5728 #define GB_TILE_MODE30__ARRAY_MODE__SHIFT                                                                     0x2
5729 #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT                                                                    0x6
5730 #define GB_TILE_MODE30__TILE_SPLIT__SHIFT                                                                     0xb
5731 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5732 #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT                                                                   0x19
5733 #define GB_TILE_MODE30__ARRAY_MODE_MASK                                                                       0x0000003CL
5734 #define GB_TILE_MODE30__PIPE_CONFIG_MASK                                                                      0x000007C0L
5735 #define GB_TILE_MODE30__TILE_SPLIT_MASK                                                                       0x00003800L
5736 #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5737 #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5738 //GB_TILE_MODE31
5739 #define GB_TILE_MODE31__ARRAY_MODE__SHIFT                                                                     0x2
5740 #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT                                                                    0x6
5741 #define GB_TILE_MODE31__TILE_SPLIT__SHIFT                                                                     0xb
5742 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT                                                            0x16
5743 #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT                                                                   0x19
5744 #define GB_TILE_MODE31__ARRAY_MODE_MASK                                                                       0x0000003CL
5745 #define GB_TILE_MODE31__PIPE_CONFIG_MASK                                                                      0x000007C0L
5746 #define GB_TILE_MODE31__TILE_SPLIT_MASK                                                                       0x00003800L
5747 #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK                                                              0x01C00000L
5748 #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK                                                                     0x06000000L
5749 //GB_MACROTILE_MODE0
5750 #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT                                                                 0x0
5751 #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT                                                                0x2
5752 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5753 #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT                                                                  0x6
5754 #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK                                                                   0x00000003L
5755 #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK                                                                  0x0000000CL
5756 #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5757 #define GB_MACROTILE_MODE0__NUM_BANKS_MASK                                                                    0x000000C0L
5758 //GB_MACROTILE_MODE1
5759 #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT                                                                 0x0
5760 #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT                                                                0x2
5761 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5762 #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT                                                                  0x6
5763 #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK                                                                   0x00000003L
5764 #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK                                                                  0x0000000CL
5765 #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5766 #define GB_MACROTILE_MODE1__NUM_BANKS_MASK                                                                    0x000000C0L
5767 //GB_MACROTILE_MODE2
5768 #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT                                                                 0x0
5769 #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT                                                                0x2
5770 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5771 #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT                                                                  0x6
5772 #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK                                                                   0x00000003L
5773 #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK                                                                  0x0000000CL
5774 #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5775 #define GB_MACROTILE_MODE2__NUM_BANKS_MASK                                                                    0x000000C0L
5776 //GB_MACROTILE_MODE3
5777 #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT                                                                 0x0
5778 #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT                                                                0x2
5779 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5780 #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT                                                                  0x6
5781 #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK                                                                   0x00000003L
5782 #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK                                                                  0x0000000CL
5783 #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5784 #define GB_MACROTILE_MODE3__NUM_BANKS_MASK                                                                    0x000000C0L
5785 //GB_MACROTILE_MODE4
5786 #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT                                                                 0x0
5787 #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT                                                                0x2
5788 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5789 #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT                                                                  0x6
5790 #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK                                                                   0x00000003L
5791 #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK                                                                  0x0000000CL
5792 #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5793 #define GB_MACROTILE_MODE4__NUM_BANKS_MASK                                                                    0x000000C0L
5794 //GB_MACROTILE_MODE5
5795 #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT                                                                 0x0
5796 #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT                                                                0x2
5797 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5798 #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT                                                                  0x6
5799 #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK                                                                   0x00000003L
5800 #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK                                                                  0x0000000CL
5801 #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5802 #define GB_MACROTILE_MODE5__NUM_BANKS_MASK                                                                    0x000000C0L
5803 //GB_MACROTILE_MODE6
5804 #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT                                                                 0x0
5805 #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT                                                                0x2
5806 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5807 #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT                                                                  0x6
5808 #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK                                                                   0x00000003L
5809 #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK                                                                  0x0000000CL
5810 #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5811 #define GB_MACROTILE_MODE6__NUM_BANKS_MASK                                                                    0x000000C0L
5812 //GB_MACROTILE_MODE7
5813 #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT                                                                 0x0
5814 #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT                                                                0x2
5815 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5816 #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT                                                                  0x6
5817 #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK                                                                   0x00000003L
5818 #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK                                                                  0x0000000CL
5819 #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5820 #define GB_MACROTILE_MODE7__NUM_BANKS_MASK                                                                    0x000000C0L
5821 //GB_MACROTILE_MODE8
5822 #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT                                                                 0x0
5823 #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT                                                                0x2
5824 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5825 #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT                                                                  0x6
5826 #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK                                                                   0x00000003L
5827 #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK                                                                  0x0000000CL
5828 #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5829 #define GB_MACROTILE_MODE8__NUM_BANKS_MASK                                                                    0x000000C0L
5830 //GB_MACROTILE_MODE9
5831 #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT                                                                 0x0
5832 #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT                                                                0x2
5833 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT                                                          0x4
5834 #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT                                                                  0x6
5835 #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK                                                                   0x00000003L
5836 #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK                                                                  0x0000000CL
5837 #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK                                                            0x00000030L
5838 #define GB_MACROTILE_MODE9__NUM_BANKS_MASK                                                                    0x000000C0L
5839 //GB_MACROTILE_MODE10
5840 #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT                                                                0x0
5841 #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT                                                               0x2
5842 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5843 #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT                                                                 0x6
5844 #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK                                                                  0x00000003L
5845 #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK                                                                 0x0000000CL
5846 #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5847 #define GB_MACROTILE_MODE10__NUM_BANKS_MASK                                                                   0x000000C0L
5848 //GB_MACROTILE_MODE11
5849 #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT                                                                0x0
5850 #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT                                                               0x2
5851 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5852 #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT                                                                 0x6
5853 #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK                                                                  0x00000003L
5854 #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK                                                                 0x0000000CL
5855 #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5856 #define GB_MACROTILE_MODE11__NUM_BANKS_MASK                                                                   0x000000C0L
5857 //GB_MACROTILE_MODE12
5858 #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT                                                                0x0
5859 #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT                                                               0x2
5860 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5861 #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT                                                                 0x6
5862 #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK                                                                  0x00000003L
5863 #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK                                                                 0x0000000CL
5864 #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5865 #define GB_MACROTILE_MODE12__NUM_BANKS_MASK                                                                   0x000000C0L
5866 //GB_MACROTILE_MODE13
5867 #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT                                                                0x0
5868 #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT                                                               0x2
5869 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5870 #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT                                                                 0x6
5871 #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK                                                                  0x00000003L
5872 #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK                                                                 0x0000000CL
5873 #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5874 #define GB_MACROTILE_MODE13__NUM_BANKS_MASK                                                                   0x000000C0L
5875 //GB_MACROTILE_MODE14
5876 #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT                                                                0x0
5877 #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT                                                               0x2
5878 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5879 #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT                                                                 0x6
5880 #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK                                                                  0x00000003L
5881 #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK                                                                 0x0000000CL
5882 #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5883 #define GB_MACROTILE_MODE14__NUM_BANKS_MASK                                                                   0x000000C0L
5884 //GB_MACROTILE_MODE15
5885 #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT                                                                0x0
5886 #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT                                                               0x2
5887 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT                                                         0x4
5888 #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT                                                                 0x6
5889 #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK                                                                  0x00000003L
5890 #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK                                                                 0x0000000CL
5891 #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK                                                           0x00000030L
5892 #define GB_MACROTILE_MODE15__NUM_BANKS_MASK                                                                   0x000000C0L
5893 //CB_HW_CONTROL
5894 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT                                                            0x0
5895 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT                                                            0x6
5896 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT                                                            0xc
5897 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT                                                      0x10
5898 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT                                                0x12
5899 #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT                                                                 0x13
5900 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT                                                             0x14
5901 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT                                                0x15
5902 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT                                                         0x16
5903 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT                                             0x17
5904 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT                                                   0x18
5905 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT                                                        0x19
5906 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT                                                 0x1a
5907 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT                                0x1b
5908 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT                                   0x1c
5909 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT                                0x1d
5910 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT                                              0x1e
5911 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT                                    0x1f
5912 #define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK                                                              0x0000000FL
5913 #define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK                                                              0x000003C0L
5914 #define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK                                                              0x0000F000L
5915 #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK                                                        0x00010000L
5916 #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK                                                  0x00040000L
5917 #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK                                                                   0x00080000L
5918 #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK                                                               0x00100000L
5919 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK                                                  0x00200000L
5920 #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK                                                           0x00400000L
5921 #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK                                               0x00800000L
5922 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK                                                     0x01000000L
5923 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK                                                          0x02000000L
5924 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK                                                   0x04000000L
5925 #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK                                  0x08000000L
5926 #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK                                     0x10000000L
5927 #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK                                  0x20000000L
5928 #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK                                                0x40000000L
5929 #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK                                      0x80000000L
5930 //CB_HW_CONTROL_1
5931 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT                                                             0x0
5932 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT                                                             0x5
5933 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT                                                             0xb
5934 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT                                                            0x11
5935 #define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT                                                                   0x1a
5936 #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK                                                               0x0000001FL
5937 #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK                                                               0x000007E0L
5938 #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK                                                               0x0001F800L
5939 #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK                                                              0x03FE0000L
5940 #define CB_HW_CONTROL_1__RMI_CREDITS_MASK                                                                     0xFC000000L
5941 //CB_HW_CONTROL_2
5942 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT                                                        0x0
5943 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT                                                      0x8
5944 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT                                                      0xf
5945 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT                                                   0x18
5946 #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT                                                                  0x1c
5947 #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK                                                          0x000000FFL
5948 #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK                                                        0x00007F00L
5949 #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK                                                        0x007F8000L
5950 #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK                                                     0x0F000000L
5951 #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK                                                                    0xF0000000L
5952 //CB_HW_CONTROL_3
5953 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT                                        0x0
5954 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT                                              0x1
5955 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT                                                  0x2
5956 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT                                                 0x3
5957 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT                                            0x4
5958 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT                                            0x5
5959 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT                                                 0x6
5960 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT                                                 0x7
5961 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT                             0x8
5962 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT                                                 0x9
5963 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT                                                     0xa
5964 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT                                             0xb
5965 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT                                              0xc
5966 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT                                              0xd
5967 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT                                                0xe
5968 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT                                                           0xf
5969 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT                                                          0x10
5970 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT                                                       0x11
5971 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT                                                       0x12
5972 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT                                                       0x13
5973 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT                                                       0x14
5974 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT                                                    0x15
5975 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT                                                    0x16
5976 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT                                                    0x17
5977 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT                                                    0x18
5978 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT                                                  0x19
5979 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT                                                  0x1a
5980 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT                                            0x1b
5981 #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT                                                  0x1c
5982 #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK                                          0x00000001L
5983 #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK                                                0x00000002L
5984 #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK                                                    0x00000004L
5985 #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK                                                   0x00000008L
5986 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK                                              0x00000010L
5987 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK                                              0x00000020L
5988 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK                                                   0x00000040L
5989 #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK                                                   0x00000080L
5990 #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK                               0x00000100L
5991 #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK                                                   0x00000200L
5992 #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK                                                       0x00000400L
5993 #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK                                               0x00000800L
5994 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK                                                0x00001000L
5995 #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK                                                0x00002000L
5996 #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK                                                  0x00004000L
5997 #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK                                                             0x00008000L
5998 #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK                                                            0x00010000L
5999 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK                                                         0x00020000L
6000 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK                                                         0x00040000L
6001 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK                                                         0x00080000L
6002 #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK                                                         0x00100000L
6003 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK                                                      0x00200000L
6004 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK                                                      0x00400000L
6005 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK                                                      0x00800000L
6006 #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK                                                      0x01000000L
6007 #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK                                                    0x02000000L
6008 #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK                                                    0x04000000L
6009 #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK                                              0x08000000L
6010 #define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK                                                    0x30000000L
6011 //CB_HW_MEM_ARBITER_RD
6012 #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT                                                                     0x0
6013 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT                                                        0x2
6014 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT                                                          0x6
6015 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT                                                                0xa
6016 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT                                                                0xc
6017 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT                                                                0xe
6018 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT                                                                0x10
6019 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
6020 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
6021 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT                                                   0x16
6022 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT                                                                0x17
6023 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT                                                             0x1a
6024 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
6025 #define CB_HW_MEM_ARBITER_RD__MODE_MASK                                                                       0x00000003L
6026 #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
6027 #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
6028 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK                                                                  0x00000C00L
6029 #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK                                                                  0x00003000L
6030 #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK                                                                  0x0000C000L
6031 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK                                                                  0x00030000L
6032 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
6033 #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
6034 #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK                                                     0x00400000L
6035 #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK                                                                  0x03800000L
6036 #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK                                                               0x1C000000L
6037 #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
6038 //CB_HW_MEM_ARBITER_WR
6039 #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT                                                                     0x0
6040 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT                                                        0x2
6041 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT                                                          0x6
6042 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT                                                                0xa
6043 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT                                                                0xc
6044 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT                                                                0xe
6045 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT                                                                0x10
6046 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT                                                        0x12
6047 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT                                                      0x14
6048 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT                                                  0x16
6049 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT                                                                0x17
6050 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT                                                             0x1a
6051 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT                                                 0x1d
6052 #define CB_HW_MEM_ARBITER_WR__MODE_MASK                                                                       0x00000003L
6053 #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK                                                          0x0000003CL
6054 #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK                                                            0x000003C0L
6055 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK                                                                  0x00000C00L
6056 #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK                                                                  0x00003000L
6057 #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK                                                                  0x0000C000L
6058 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK                                                                  0x00030000L
6059 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK                                                          0x000C0000L
6060 #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK                                                        0x00300000L
6061 #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK                                                    0x00400000L
6062 #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK                                                                  0x03800000L
6063 #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK                                                               0x1C000000L
6064 #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK                                                   0x20000000L
6065 //CB_DCC_CONFIG
6066 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT                                                        0x0
6067 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT                                                      0x5
6068 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT                                               0x6
6069 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT                                                       0x8
6070 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT                                                     0x10
6071 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT                                                           0x18
6072 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT                                                              0x1c
6073 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK                                                          0x0000001FL
6074 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK                                                        0x00000020L
6075 #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK                                                 0x00000040L
6076 #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK                                                         0x0000FF00L
6077 #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK                                                       0x007F0000L
6078 #define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK                                                             0x0F000000L
6079 #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK                                                                0xF0000000L
6080 //GC_USER_RB_REDUNDANCY
6081 #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT                                                              0x8
6082 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT                                                          0xc
6083 #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT                                                              0x10
6084 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT                                                          0x14
6085 #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK                                                                0x00000F00L
6086 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK                                                            0x00001000L
6087 #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK                                                                0x000F0000L
6088 #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK                                                            0x00100000L
6089 //GC_USER_RB_BACKEND_DISABLE
6090 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT                                                    0x10
6091 #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK                                                      0x00FF0000L
6092 
6093 
6094 // addressBlock: gc_rmi_rmidec
6095 //RMI_GENERAL_CNTL
6096 #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT                                                                0x0
6097 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT                                                           0x1
6098 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT                                                              0x11
6099 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT                                                               0x13
6100 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT                                                               0x14
6101 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT                                                     0x15
6102 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT                                                       0x19
6103 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT                                              0x1a
6104 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1b
6105 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT                                              0x1c
6106 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT                                             0x1d
6107 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT                                       0x1e
6108 #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK                                                                  0x00000001L
6109 #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK                                                             0x0001FFFEL
6110 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK                                                                0x00060000L
6111 #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK                                                                 0x00080000L
6112 #define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK                                                                 0x00100000L
6113 #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK                                                       0x01E00000L
6114 #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK                                                         0x02000000L
6115 #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK                                                0x04000000L
6116 #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK                                               0x08000000L
6117 #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK                                                0x10000000L
6118 #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK                                               0x20000000L
6119 #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK                                         0x40000000L
6120 //RMI_GENERAL_CNTL1
6121 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT                                                0x0
6122 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT                                                     0x4
6123 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT                                                     0x6
6124 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT                                            0x8
6125 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT                                                       0x9
6126 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT                                                             0xa
6127 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT                                           0xb
6128 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT                                           0xc
6129 #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK                                                  0x0000000FL
6130 #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK                                                       0x00000030L
6131 #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK                                                       0x000000C0L
6132 #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK                                              0x00000100L
6133 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK                                                         0x00000200L
6134 #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK                                                               0x00000400L
6135 #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK                                             0x00000800L
6136 #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK                                             0x00001000L
6137 //RMI_GENERAL_STATUS
6138 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT                                                0x0
6139 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT                                                 0x1
6140 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT                                                0x2
6141 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT                                                 0x3
6142 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT                                                0x4
6143 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT                                                              0x5
6144 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT                                                             0x6
6145 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT                                                        0x7
6146 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT                                                        0x8
6147 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT                                                           0x9
6148 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT                                                       0xa
6149 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xb
6150 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT                                                 0xc
6151 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT                                                        0xd
6152 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT                                                           0xe
6153 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT                                                       0xf
6154 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x10
6155 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT                                                 0x11
6156 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT                                                            0x12
6157 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT                                                            0x13
6158 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT                                                             0x14
6159 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT                                                        0x15
6160 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT                                                           0x1d
6161 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT                                                            0x1e
6162 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT                                          0x1f
6163 #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK                                                  0x00000001L
6164 #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK                                                   0x00000002L
6165 #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK                                                  0x00000004L
6166 #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK                                                   0x00000008L
6167 #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK                                                  0x00000010L
6168 #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK                                                                0x00000020L
6169 #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK                                                               0x00000040L
6170 #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK                                                          0x00000080L
6171 #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK                                                          0x00000100L
6172 #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK                                                             0x00000200L
6173 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK                                                         0x00000400L
6174 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00000800L
6175 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK                                                   0x00001000L
6176 #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK                                                          0x00002000L
6177 #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK                                                             0x00004000L
6178 #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK                                                         0x00008000L
6179 #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00010000L
6180 #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK                                                   0x00020000L
6181 #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK                                                              0x00040000L
6182 #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK                                                              0x00080000L
6183 #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK                                                               0x00100000L
6184 #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK                                                          0x1FE00000L
6185 #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK                                                             0x20000000L
6186 #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK                                                              0x40000000L
6187 #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK                                            0x80000000L
6188 //RMI_SUBBLOCK_STATUS0
6189 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT                                     0x0
6190 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT                                         0x7
6191 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT                                        0x8
6192 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT                                     0x9
6193 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT                                         0x10
6194 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT                                        0x11
6195 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT                                                       0x12
6196 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK                                       0x0000007FL
6197 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK                                           0x00000080L
6198 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK                                          0x00000100L
6199 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK                                       0x0000FE00L
6200 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK                                           0x00010000L
6201 #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK                                          0x00020000L
6202 #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK                                                         0x0FFC0000L
6203 //RMI_SUBBLOCK_STATUS1
6204 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT                                                   0x0
6205 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT                                                   0xa
6206 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT                                                       0x14
6207 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK                                                     0x000003FFL
6208 #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK                                                     0x000FFC00L
6209 #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK                                                         0x3FF00000L
6210 //RMI_SUBBLOCK_STATUS2
6211 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT                                                      0x0
6212 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT                                                      0x9
6213 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK                                                        0x000001FFL
6214 #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK                                                        0x0003FE00L
6215 //RMI_SUBBLOCK_STATUS3
6216 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT                                             0x0
6217 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT                                             0xa
6218 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK                                               0x000003FFL
6219 #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK                                               0x000FFC00L
6220 //RMI_XBAR_CONFIG
6221 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT                                                      0x0
6222 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT                                             0x2
6223 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT                                                0x6
6224 #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT                                                                   0x7
6225 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT                                                                0x8
6226 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT                                                       0xc
6227 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT                                                                0xd
6228 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT                                                                0xe
6229 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK                                                        0x00000003L
6230 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK                                               0x0000003CL
6231 #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK                                                  0x00000040L
6232 #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK                                                                     0x00000080L
6233 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK                                                                  0x00000F00L
6234 #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK                                                         0x00001000L
6235 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK                                                                  0x00002000L
6236 #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK                                                                  0x00004000L
6237 //RMI_PROBE_POP_LOGIC_CNTL
6238 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT                                             0x0
6239 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT                                                    0x7
6240 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT                                      0x8
6241 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT                                             0xa
6242 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT                                                    0x11
6243 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK                                               0x0000007FL
6244 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK                                                      0x00000080L
6245 #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK                                        0x00000300L
6246 #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK                                               0x0001FC00L
6247 #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK                                                      0x00020000L
6248 //RMI_UTC_XNACK_N_MISC_CNTL
6249 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT                                              0x0
6250 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT                                         0x8
6251 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT                                                     0xc
6252 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT                                       0xd
6253 #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK                                                0x000000FFL
6254 #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK                                           0x00000F00L
6255 #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK                                                       0x00001000L
6256 #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK                                         0x00002000L
6257 //RMI_DEMUX_CNTL
6258 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT                                                               0x0
6259 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x1
6260 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                                0x4
6261 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT                                             0x6
6262 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT                                                                0xe
6263 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT                                                               0x10
6264 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                                 0x11
6265 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                                0x14
6266 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT                                             0x16
6267 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT                                                                0x1e
6268 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK                                                                 0x00000001L
6269 #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00000002L
6270 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK                                                  0x00000030L
6271 #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK                                               0x00003FC0L
6272 #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK                                                                  0x0000C000L
6273 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK                                                                 0x00010000L
6274 #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                                   0x00020000L
6275 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK                                                  0x00300000L
6276 #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK                                               0x3FC00000L
6277 #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK                                                                  0xC0000000L
6278 //RMI_UTCL1_CNTL1
6279 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
6280 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT                                                                 0x1
6281 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
6282 #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
6283 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
6284 #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
6285 #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT                                                                    0x10
6286 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT                                                             0x11
6287 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT                                                          0x12
6288 #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
6289 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
6290 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
6291 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
6292 #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
6293 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT                                                                0x1b
6294 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
6295 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
6296 #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
6297 #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK                                                                   0x00000002L
6298 #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
6299 #define RMI_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
6300 #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
6301 #define RMI_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
6302 #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK                                                                      0x00010000L
6303 #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK                                                               0x00020000L
6304 #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK                                                            0x00040000L
6305 #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
6306 #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
6307 #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
6308 #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
6309 #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
6310 #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK                                                                  0x08000000L
6311 #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
6312 #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
6313 //RMI_UTCL1_CNTL2
6314 #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
6315 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
6316 #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT                                                                    0xa
6317 #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT                                                                       0xb
6318 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
6319 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT                                                                 0xd
6320 #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
6321 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
6322 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT                                                          0x10
6323 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT                                                 0x12
6324 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT                                                        0x13
6325 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT                                                  0x14
6326 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT                                                         0x15
6327 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT                                                         0x19
6328 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT                                                    0x1a
6329 #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK                                                                       0x000000FFL
6330 #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
6331 #define RMI_UTCL1_CNTL2__LINE_VALID_MASK                                                                      0x00000400L
6332 #define RMI_UTCL1_CNTL2__DIS_EDC_MASK                                                                         0x00000800L
6333 #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
6334 #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK                                                                   0x00002000L
6335 #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
6336 #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
6337 #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK                                                            0x00030000L
6338 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK                                                   0x00040000L
6339 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK                                                          0x00080000L
6340 #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK                                                    0x00100000L
6341 #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK                                                           0x01E00000L
6342 #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK                                                           0x02000000L
6343 #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK                                                      0x04000000L
6344 //RMI_UTC_UNIT_CONFIG
6345 //RMI_TCIW_FORMATTER0_CNTL
6346 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT                                             0x0
6347 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT                                          0x1
6348 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
6349 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT                                         0x13
6350 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
6351 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT                                                  0x1c
6352 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT                                                  0x1d
6353 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
6354 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT                                                  0x1f
6355 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK                                               0x00000001L
6356 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK                                            0x000001FEL
6357 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
6358 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK                                           0x07F80000L
6359 #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
6360 #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK                                                    0x10000000L
6361 #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK                                                    0x20000000L
6362 #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
6363 #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK                                                    0x80000000L
6364 //RMI_TCIW_FORMATTER1_CNTL
6365 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT                                             0x0
6366 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT                                          0x1
6367 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT                                       0x9
6368 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT                                         0x13
6369 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT                                  0x1b
6370 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT                                                  0x1c
6371 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT                                                  0x1d
6372 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT                                     0x1e
6373 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT                                                  0x1f
6374 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK                                               0x00000001L
6375 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK                                            0x000001FEL
6376 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK                                         0x0007FE00L
6377 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK                                           0x07F80000L
6378 #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK                                    0x08000000L
6379 #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK                                                    0x10000000L
6380 #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK                                                    0x20000000L
6381 #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK                                       0x40000000L
6382 #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK                                                    0x80000000L
6383 //RMI_SCOREBOARD_CNTL
6384 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT                                                        0x0
6385 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT                                              0x1
6386 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT                                                        0x2
6387 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT                                              0x3
6388 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT                                                      0x4
6389 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT                                         0x5
6390 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT                                      0x6
6391 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT                                                      0x7
6392 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT                                                  0x8
6393 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT                                   0x9
6394 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK                                                          0x00000001L
6395 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK                                                0x00000002L
6396 #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK                                                          0x00000004L
6397 #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK                                                0x00000008L
6398 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK                                                        0x00000010L
6399 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK                                           0x00000020L
6400 #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK                                        0x00000040L
6401 #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK                                                        0x00000080L
6402 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK                                                    0x00000100L
6403 #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK                                     0x001FFE00L
6404 //RMI_SCOREBOARD_STATUS0
6405 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT                                                     0x0
6406 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT                                                    0x1
6407 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT                                                   0x2
6408 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT                                                   0x12
6409 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT                                                       0x13
6410 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT                                                 0x14
6411 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT                                                    0x15
6412 #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK                                                       0x00000001L
6413 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK                                                      0x00000002L
6414 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK                                                     0x0003FFFCL
6415 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK                                                     0x00040000L
6416 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK                                                         0x00080000L
6417 #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK                                                   0x00100000L
6418 #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK                                                      0x00200000L
6419 //RMI_SCOREBOARD_STATUS1
6420 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT                                                        0x0
6421 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT                                              0xc
6422 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT                                               0xd
6423 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT                                      0xe
6424 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT                                                        0xf
6425 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT                                              0x1b
6426 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT                                               0x1c
6427 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT                                                  0x1d
6428 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT                                                  0x1e
6429 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK                                                          0x00000FFFL
6430 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK                                                0x00001000L
6431 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK                                                 0x00002000L
6432 #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK                                        0x00004000L
6433 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK                                                          0x07FF8000L
6434 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK                                                0x08000000L
6435 #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK                                                 0x10000000L
6436 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK                                                    0x20000000L
6437 #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK                                                    0x40000000L
6438 //RMI_SCOREBOARD_STATUS2
6439 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT                                                       0x0
6440 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT                                             0xc
6441 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT                                                       0xd
6442 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT                                             0x19
6443 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT                                                     0x1a
6444 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT                                                     0x1b
6445 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT                                           0x1c
6446 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT                                           0x1d
6447 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT                                              0x1e
6448 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT                                              0x1f
6449 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK                                                         0x00000FFFL
6450 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK                                               0x00001000L
6451 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK                                                         0x01FFE000L
6452 #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK                                               0x02000000L
6453 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK                                                       0x04000000L
6454 #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK                                                       0x08000000L
6455 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK                                             0x10000000L
6456 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK                                             0x20000000L
6457 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK                                                0x40000000L
6458 #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK                                                0x80000000L
6459 //RMI_XBAR_ARBITER_CONFIG
6460 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT                                                        0x0
6461 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x2
6462 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT                                                       0x3
6463 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x4
6464 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT                                        0x6
6465 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT                                     0x8
6466 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT                                                        0x10
6467 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT                                     0x12
6468 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT                                                       0x13
6469 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT                                         0x14
6470 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT                                        0x16
6471 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT                                     0x18
6472 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK                                                          0x00000003L
6473 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00000004L
6474 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK                                                         0x00000008L
6475 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK                                           0x00000010L
6476 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK                                          0x000000C0L
6477 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK                                       0x0000FF00L
6478 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK                                                          0x00030000L
6479 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK                                       0x00040000L
6480 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK                                                         0x00080000L
6481 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK                                           0x00100000L
6482 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK                                          0x00C00000L
6483 #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK                                       0xFF000000L
6484 //RMI_XBAR_ARBITER_CONFIG_1
6485 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT                                  0x0
6486 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT                                  0x8
6487 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT                                  0x10
6488 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT                                  0x18
6489 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK                                    0x000000FFL
6490 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK                                    0x0000FF00L
6491 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK                                    0x00FF0000L
6492 #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK                                    0xFF000000L
6493 //RMI_CLOCK_CNTRL
6494 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT                                                         0x0
6495 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT                                                         0x5
6496 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT                                                       0xa
6497 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT                                                       0xf
6498 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT                                                         0x14
6499 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT                                                       0x19
6500 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK                                                           0x0000001FL
6501 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK                                                           0x000003E0L
6502 #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK                                                         0x00007C00L
6503 #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK                                                         0x000F8000L
6504 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK                                                           0x01F00000L
6505 #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK                                                         0x3E000000L
6506 //RMI_UTCL1_STATUS
6507 #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
6508 #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
6509 #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
6510 #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
6511 #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
6512 #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
6513 //RMI_XNACK_DEBUG
6514 #define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT                                                                0x0
6515 #define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK                                                                  0x0000FFFFL
6516 //RMI_SPARE
6517 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT                                     0x0
6518 #define RMI_SPARE__SPARE_BIT_1__SHIFT                                                                         0x1
6519 #define RMI_SPARE__SPARE_BIT_2__SHIFT                                                                         0x2
6520 #define RMI_SPARE__SPARE_BIT_3__SHIFT                                                                         0x3
6521 #define RMI_SPARE__SPARE_BIT_4__SHIFT                                                                         0x4
6522 #define RMI_SPARE__SPARE_BIT_5__SHIFT                                                                         0x5
6523 #define RMI_SPARE__SPARE_BIT_6__SHIFT                                                                         0x6
6524 #define RMI_SPARE__SPARE_BIT_7__SHIFT                                                                         0x7
6525 #define RMI_SPARE__SPARE_BIT_8_0__SHIFT                                                                       0x8
6526 #define RMI_SPARE__SPARE_BIT_16_0__SHIFT                                                                      0x10
6527 #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK                                       0x00000001L
6528 #define RMI_SPARE__SPARE_BIT_1_MASK                                                                           0x00000002L
6529 #define RMI_SPARE__SPARE_BIT_2_MASK                                                                           0x00000004L
6530 #define RMI_SPARE__SPARE_BIT_3_MASK                                                                           0x00000008L
6531 #define RMI_SPARE__SPARE_BIT_4_MASK                                                                           0x00000010L
6532 #define RMI_SPARE__SPARE_BIT_5_MASK                                                                           0x00000020L
6533 #define RMI_SPARE__SPARE_BIT_6_MASK                                                                           0x00000040L
6534 #define RMI_SPARE__SPARE_BIT_7_MASK                                                                           0x00000080L
6535 #define RMI_SPARE__SPARE_BIT_8_0_MASK                                                                         0x0000FF00L
6536 #define RMI_SPARE__SPARE_BIT_16_0_MASK                                                                        0xFFFF0000L
6537 //RMI_SPARE_1
6538 #define RMI_SPARE_1__SPARE_BIT_8__SHIFT                                                                       0x0
6539 #define RMI_SPARE_1__SPARE_BIT_9__SHIFT                                                                       0x1
6540 #define RMI_SPARE_1__SPARE_BIT_10__SHIFT                                                                      0x2
6541 #define RMI_SPARE_1__SPARE_BIT_11__SHIFT                                                                      0x3
6542 #define RMI_SPARE_1__SPARE_BIT_12__SHIFT                                                                      0x4
6543 #define RMI_SPARE_1__SPARE_BIT_13__SHIFT                                                                      0x5
6544 #define RMI_SPARE_1__SPARE_BIT_14__SHIFT                                                                      0x6
6545 #define RMI_SPARE_1__SPARE_BIT_15__SHIFT                                                                      0x7
6546 #define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT                                                                     0x8
6547 #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT                                                                    0x10
6548 #define RMI_SPARE_1__SPARE_BIT_8_MASK                                                                         0x00000001L
6549 #define RMI_SPARE_1__SPARE_BIT_9_MASK                                                                         0x00000002L
6550 #define RMI_SPARE_1__SPARE_BIT_10_MASK                                                                        0x00000004L
6551 #define RMI_SPARE_1__SPARE_BIT_11_MASK                                                                        0x00000008L
6552 #define RMI_SPARE_1__SPARE_BIT_12_MASK                                                                        0x00000010L
6553 #define RMI_SPARE_1__SPARE_BIT_13_MASK                                                                        0x00000020L
6554 #define RMI_SPARE_1__SPARE_BIT_14_MASK                                                                        0x00000040L
6555 #define RMI_SPARE_1__SPARE_BIT_15_MASK                                                                        0x00000080L
6556 #define RMI_SPARE_1__SPARE_BIT_8_1_MASK                                                                       0x0000FF00L
6557 #define RMI_SPARE_1__SPARE_BIT_16_1_MASK                                                                      0xFFFF0000L
6558 //RMI_SPARE_2
6559 #define RMI_SPARE_2__SPARE_BIT_16__SHIFT                                                                      0x0
6560 #define RMI_SPARE_2__SPARE_BIT_17__SHIFT                                                                      0x1
6561 #define RMI_SPARE_2__SPARE_BIT_18__SHIFT                                                                      0x2
6562 #define RMI_SPARE_2__SPARE_BIT_19__SHIFT                                                                      0x3
6563 #define RMI_SPARE_2__SPARE_BIT_20__SHIFT                                                                      0x4
6564 #define RMI_SPARE_2__SPARE_BIT_21__SHIFT                                                                      0x5
6565 #define RMI_SPARE_2__SPARE_BIT_22__SHIFT                                                                      0x6
6566 #define RMI_SPARE_2__SPARE_BIT_23__SHIFT                                                                      0x7
6567 #define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT                                                                     0x8
6568 #define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT                                                                     0xc
6569 #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT                                                                     0x10
6570 #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT                                                                     0x18
6571 #define RMI_SPARE_2__SPARE_BIT_16_MASK                                                                        0x00000001L
6572 #define RMI_SPARE_2__SPARE_BIT_17_MASK                                                                        0x00000002L
6573 #define RMI_SPARE_2__SPARE_BIT_18_MASK                                                                        0x00000004L
6574 #define RMI_SPARE_2__SPARE_BIT_19_MASK                                                                        0x00000008L
6575 #define RMI_SPARE_2__SPARE_BIT_20_MASK                                                                        0x00000010L
6576 #define RMI_SPARE_2__SPARE_BIT_21_MASK                                                                        0x00000020L
6577 #define RMI_SPARE_2__SPARE_BIT_22_MASK                                                                        0x00000040L
6578 #define RMI_SPARE_2__SPARE_BIT_23_MASK                                                                        0x00000080L
6579 #define RMI_SPARE_2__SPARE_BIT_4_0_MASK                                                                       0x00000F00L
6580 #define RMI_SPARE_2__SPARE_BIT_4_1_MASK                                                                       0x0000F000L
6581 #define RMI_SPARE_2__SPARE_BIT_8_2_MASK                                                                       0x00FF0000L
6582 #define RMI_SPARE_2__SPARE_BIT_8_3_MASK                                                                       0xFF000000L
6583 
6584 
6585 // addressBlock: gc_utcl2_atcl2dec
6586 //ATC_L2_CNTL
6587 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                               0x0
6588 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                              0x3
6589 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                   0x6
6590 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                                  0x7
6591 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                             0x8
6592 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                          0xb
6593 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                                 0x00000003L
6594 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                                0x00000018L
6595 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                     0x00000040L
6596 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                    0x00000080L
6597 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                               0x00000700L
6598 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                            0x00000800L
6599 //ATC_L2_CNTL2
6600 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                      0x0
6601 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                             0x6
6602 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                              0x8
6603 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                     0x9
6604 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                               0xc
6605 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                         0xf
6606 #define ATC_L2_CNTL2__BANK_SELECT_MASK                                                                        0x0000003FL
6607 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                               0x000000C0L
6608 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                                0x00000100L
6609 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                       0x00000E00L
6610 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                                 0x00007000L
6611 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                           0x001F8000L
6612 //ATC_L2_CACHE_DATA0
6613 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                        0x0
6614 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                          0x1
6615 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                          0x2
6616 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                                  0x17
6617 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                          0x00000001L
6618 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                            0x00000002L
6619 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                            0x007FFFFCL
6620 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                    0x07800000L
6621 //ATC_L2_CACHE_DATA1
6622 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                   0x0
6623 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                     0xFFFFFFFFL
6624 //ATC_L2_CACHE_DATA2
6625 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                      0x0
6626 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                        0xFFFFFFFFL
6627 //ATC_L2_CNTL3
6628 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                                  0x0
6629 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                        0x3
6630 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                    0x00000007L
6631 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                          0x000001F8L
6632 //ATC_L2_STATUS
6633 #define ATC_L2_STATUS__BUSY__SHIFT                                                                            0x0
6634 #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                               0x1
6635 #define ATC_L2_STATUS__BUSY_MASK                                                                              0x00000001L
6636 #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                                 0x3FFFFFFEL
6637 //ATC_L2_STATUS2
6638 #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                              0x0
6639 #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                                  0x8
6640 #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                                0x000000FFL
6641 #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                                    0x0000FF00L
6642 //ATC_L2_MISC_CG
6643 #define ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                         0x6
6644 #define ATC_L2_MISC_CG__ENABLE__SHIFT                                                                         0x12
6645 #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                                  0x13
6646 #define ATC_L2_MISC_CG__OFFDLY_MASK                                                                           0x00000FC0L
6647 #define ATC_L2_MISC_CG__ENABLE_MASK                                                                           0x00040000L
6648 #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                    0x00080000L
6649 //ATC_L2_MEM_POWER_LS
6650 #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                                  0x0
6651 #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                   0x6
6652 #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                    0x0000003FL
6653 #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                     0x00000FC0L
6654 //ATC_L2_CGTT_CLK_CTRL
6655 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
6656 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
6657 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                            0xf
6658 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                      0x10
6659 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                            0x18
6660 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
6661 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
6662 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                              0x00008000L
6663 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                        0x00FF0000L
6664 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                              0xFF000000L
6665 
6666 // addressBlock: gc_utcl2_vml2pfdec
6667 //VM_L2_CNTL
6668 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                    0x0
6669 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                      0x1
6670 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                      0x2
6671 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                      0x4
6672 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                  0x8
6673 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                            0x9
6674 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0xa
6675 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                           0xb
6676 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                           0xc
6677 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                            0xf
6678 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                           0x12
6679 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                      0x13
6680 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                        0x15
6681 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                             0x1a
6682 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                      0x00000001L
6683 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                        0x00000002L
6684 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                        0x0000000CL
6685 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                        0x00000030L
6686 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                    0x00000100L
6687 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                              0x00000200L
6688 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000400L
6689 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                             0x00000800L
6690 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                             0x00007000L
6691 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                              0x00038000L
6692 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                             0x00040000L
6693 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                        0x00180000L
6694 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                          0x03E00000L
6695 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                               0x0C000000L
6696 //VM_L2_CNTL2
6697 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                            0x0
6698 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                               0x1
6699 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                     0x15
6700 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                   0x16
6701 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                            0x17
6702 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                             0x1a
6703 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                          0x1c
6704 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                              0x00000001L
6705 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                                 0x00000002L
6706 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                       0x00200000L
6707 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                     0x00400000L
6708 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                              0x03800000L
6709 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                               0x0C000000L
6710 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                            0x70000000L
6711 //VM_L2_CNTL3
6712 #define VM_L2_CNTL3__BANK_SELECT__SHIFT                                                                       0x0
6713 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                              0x6
6714 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                          0x8
6715 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                       0xf
6716 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                       0x14
6717 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                        0x15
6718 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                      0x18
6719 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                            0x1c
6720 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                          0x1d
6721 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                              0x1e
6722 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                         0x1f
6723 #define VM_L2_CNTL3__BANK_SELECT_MASK                                                                         0x0000003FL
6724 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                                0x000000C0L
6725 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                            0x00001F00L
6726 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                         0x000F8000L
6727 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                         0x00100000L
6728 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                          0x00E00000L
6729 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                        0x0F000000L
6730 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                              0x10000000L
6731 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                            0x20000000L
6732 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                                0x40000000L
6733 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                           0x80000000L
6734 //VM_L2_STATUS
6735 #define VM_L2_STATUS__L2_BUSY__SHIFT                                                                          0x0
6736 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                              0x1
6737 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                                 0x11
6738 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x12
6739 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                   0x13
6740 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                   0x14
6741 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                   0x15
6742 #define VM_L2_STATUS__L2_BUSY_MASK                                                                            0x00000001L
6743 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                                0x0001FFFEL
6744 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                   0x00020000L
6745 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00040000L
6746 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                     0x00080000L
6747 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                     0x00100000L
6748 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                     0x00200000L
6749 //VM_DUMMY_PAGE_FAULT_CNTL
6750 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                              0x0
6751 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                           0x1
6752 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                              0x2
6753 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                                0x00000001L
6754 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                             0x00000002L
6755 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                                0x000000FCL
6756 //VM_DUMMY_PAGE_FAULT_ADDR_LO32
6757 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                            0x0
6758 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                              0xFFFFFFFFL
6759 //VM_DUMMY_PAGE_FAULT_ADDR_HI32
6760 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                             0x0
6761 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                               0x0000000FL
6762 //VM_L2_PROTECTION_FAULT_CNTL
6763 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                0x0
6764 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT             0x1
6765 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x2
6766 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x3
6767 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x4
6768 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x5
6769 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                 0x6
6770 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x7
6771 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                        0x8
6772 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x9
6773 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0xa
6774 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0xb
6775 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
6776 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                                0xd
6777 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                          0x1d
6778 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                           0x1e
6779 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                              0x1f
6780 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                  0x00000001L
6781 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK               0x00000002L
6782 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000004L
6783 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000008L
6784 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000010L
6785 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000020L
6786 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                   0x00000040L
6787 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000080L
6788 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                          0x00000100L
6789 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000200L
6790 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00000400L
6791 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00000800L
6792 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
6793 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                  0x1FFFE000L
6794 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                            0x20000000L
6795 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                             0x40000000L
6796 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                                0x80000000L
6797 //VM_L2_PROTECTION_FAULT_CNTL2
6798 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                    0x0
6799 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                              0x10
6800 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                        0x11
6801 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                             0x12
6802 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                     0x13
6803 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                      0x0000FFFFL
6804 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                0x00010000L
6805 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                          0x00020000L
6806 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                               0x00040000L
6807 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                       0x00080000L
6808 //VM_L2_PROTECTION_FAULT_MM_CNTL3
6809 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x0
6810 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0xFFFFFFFFL
6811 //VM_L2_PROTECTION_FAULT_MM_CNTL4
6812 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                 0x0
6813 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                   0xFFFFFFFFL
6814 //VM_L2_PROTECTION_FAULT_STATUS
6815 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                     0x0
6816 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                    0x1
6817 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                               0x4
6818 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                   0x8
6819 #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                             0x9
6820 #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                              0x12
6821 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                          0x13
6822 #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                            0x14
6823 #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                              0x18
6824 #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                            0x19
6825 #define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT                                                             0x1d
6826 #define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT                                                             0x1e
6827 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                       0x00000001L
6828 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                      0x0000000EL
6829 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                                 0x000000F0L
6830 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                     0x00000100L
6831 #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                               0x0003FE00L
6832 #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                                0x00040000L
6833 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                            0x00080000L
6834 #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                              0x00F00000L
6835 #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                                0x01000000L
6836 #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                              0x1E000000L
6837 #define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK                                                               0x20000000L
6838 #define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK                                                               0x40000000L
6839 //VM_L2_PROTECTION_FAULT_ADDR_LO32
6840 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                       0x0
6841 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                         0xFFFFFFFFL
6842 //VM_L2_PROTECTION_FAULT_ADDR_HI32
6843 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                        0x0
6844 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                          0x0000000FL
6845 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
6846 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                              0x0
6847 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                                0xFFFFFFFFL
6848 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
6849 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                               0x0
6850 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                                 0x0000000FL
6851 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
6852 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
6853 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
6854 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
6855 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
6856 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
6857 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
6858 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
6859 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
6860 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
6861 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
6862 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
6863 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
6864 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                         0x0
6865 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                           0xFFFFFFFFL
6866 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
6867 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                          0x0
6868 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                            0x0000000FL
6869 //VM_L2_CNTL4
6870 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                       0x0
6871 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                      0x6
6872 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                      0x7
6873 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                           0x8
6874 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                          0x12
6875 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                               0x1c
6876 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                         0x0000003FL
6877 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                        0x00000040L
6878 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                        0x00000080L
6879 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                             0x0003FF00L
6880 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                            0x0FFC0000L
6881 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                                 0x10000000L
6882 //VM_L2_MM_GROUP_RT_CLASSES
6883 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                    0x0
6884 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                    0x1
6885 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                    0x2
6886 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                    0x3
6887 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                    0x4
6888 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                    0x5
6889 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                    0x6
6890 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                    0x7
6891 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                    0x8
6892 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                    0x9
6893 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                   0xa
6894 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                   0xb
6895 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                   0xc
6896 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                   0xd
6897 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                   0xe
6898 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                   0xf
6899 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                   0x10
6900 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                   0x11
6901 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                   0x12
6902 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                   0x13
6903 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                   0x14
6904 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                   0x15
6905 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                   0x16
6906 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                   0x17
6907 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                   0x18
6908 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                   0x19
6909 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                   0x1a
6910 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                   0x1b
6911 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                   0x1c
6912 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                   0x1d
6913 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                   0x1e
6914 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                   0x1f
6915 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                      0x00000001L
6916 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                      0x00000002L
6917 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                      0x00000004L
6918 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                      0x00000008L
6919 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                      0x00000010L
6920 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                      0x00000020L
6921 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                      0x00000040L
6922 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                      0x00000080L
6923 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                      0x00000100L
6924 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                      0x00000200L
6925 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                     0x00000400L
6926 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                     0x00000800L
6927 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                     0x00001000L
6928 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                     0x00002000L
6929 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                     0x00004000L
6930 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                     0x00008000L
6931 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                     0x00010000L
6932 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                     0x00020000L
6933 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                     0x00040000L
6934 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                     0x00080000L
6935 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                     0x00100000L
6936 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                     0x00200000L
6937 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                     0x00400000L
6938 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                     0x00800000L
6939 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                     0x01000000L
6940 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                     0x02000000L
6941 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                     0x04000000L
6942 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                     0x08000000L
6943 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                     0x10000000L
6944 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                     0x20000000L
6945 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                     0x40000000L
6946 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                     0x80000000L
6947 //VM_L2_BANK_SELECT_RESERVED_CID
6948 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                        0x0
6949 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                       0xa
6950 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                         0x14
6951 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                               0x18
6952 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                            0x19
6953 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                          0x000001FFL
6954 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                         0x0007FC00L
6955 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                           0x00100000L
6956 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                                 0x01000000L
6957 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                              0x02000000L
6958 //VM_L2_BANK_SELECT_RESERVED_CID2
6959 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                       0x0
6960 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                      0xa
6961 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                        0x14
6962 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                              0x18
6963 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                           0x19
6964 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                         0x000001FFL
6965 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                        0x0007FC00L
6966 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                          0x00100000L
6967 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                                0x01000000L
6968 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                             0x02000000L
6969 //VM_L2_CACHE_PARITY_CNTL
6970 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                                 0x0
6971 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                               0x1
6972 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                    0x2
6973 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                                 0x3
6974 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                               0x4
6975 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                    0x5
6976 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                      0x6
6977 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                    0x9
6978 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                     0xc
6979 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                   0x00000001L
6980 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                                 0x00000002L
6981 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                      0x00000004L
6982 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                   0x00000008L
6983 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                                 0x00000010L
6984 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                      0x00000020L
6985 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                        0x000001C0L
6986 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                      0x00000E00L
6987 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                       0x0000F000L
6988 //VM_L2_CGTT_CLK_CTRL
6989 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
6990 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
6991 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
6992 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
6993 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
6994 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
6995 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
6996 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
6997 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
6998 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
6999 //VM_L2_MEM_ECC_INDEX
7000 #define VM_L2_MEM_ECC_INDEX__INDEX__SHIFT                                                                     0x0
7001 #define VM_L2_MEM_ECC_INDEX__INDEX_MASK                                                                       0x000000FFL
7002 //VM_L2_WALKER_MEM_ECC_INDEX
7003 #define VM_L2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT                                                              0x0
7004 #define VM_L2_WALKER_MEM_ECC_INDEX__INDEX_MASK                                                                0x000000FFL
7005 //VM_L2_MEM_ECC_CNT
7006 #define VM_L2_MEM_ECC_CNT__SEC_COUNT__SHIFT                                                                   0xc
7007 #define VM_L2_MEM_ECC_CNT__DED_COUNT__SHIFT                                                                   0xe
7008 #define VM_L2_MEM_ECC_CNT__SEC_COUNT_MASK                                                                     0x00003000L
7009 #define VM_L2_MEM_ECC_CNT__DED_COUNT_MASK                                                                     0x0000C000L
7010 //VM_L2_WALKER_MEM_ECC_CNT
7011 #define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT__SHIFT                                                            0xc
7012 #define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT__SHIFT                                                            0xe
7013 #define VM_L2_WALKER_MEM_ECC_CNT__SEC_COUNT_MASK                                                              0x00003000L
7014 #define VM_L2_WALKER_MEM_ECC_CNT__DED_COUNT_MASK                                                              0x0000C000L
7015 
7016 // addressBlock: gc_utcl2_vml2vcdec
7017 //VM_CONTEXT0_CNTL
7018 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7019 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7020 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7021 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7022 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7023 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7024 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7025 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7026 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7027 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7028 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7029 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7030 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7031 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7032 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7033 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7034 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7035 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7036 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7037 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7038 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7039 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7040 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7041 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7042 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7043 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7044 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7045 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7046 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7047 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7048 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7049 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7050 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7051 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7052 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7053 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7054 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7055 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7056 //VM_CONTEXT1_CNTL
7057 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7058 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7059 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7060 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7061 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7062 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7063 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7064 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7065 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7066 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7067 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7068 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7069 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7070 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7071 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7072 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7073 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7074 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7075 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7076 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7077 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7078 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7079 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7080 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7081 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7082 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7083 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7084 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7085 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7086 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7087 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7088 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7089 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7090 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7091 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7092 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7093 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7094 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7095 //VM_CONTEXT2_CNTL
7096 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7097 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7098 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7099 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7100 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7101 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7102 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7103 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7104 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7105 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7106 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7107 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7108 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7109 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7110 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7111 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7112 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7113 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7114 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7115 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7116 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7117 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7118 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7119 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7120 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7121 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7122 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7123 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7124 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7125 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7126 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7127 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7128 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7129 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7130 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7131 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7132 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7133 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7134 //VM_CONTEXT3_CNTL
7135 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7136 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7137 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7138 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7139 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7140 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7141 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7142 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7143 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7144 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7145 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7146 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7147 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7148 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7149 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7150 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7151 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7152 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7153 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7154 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7155 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7156 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7157 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7158 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7159 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7160 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7161 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7162 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7163 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7164 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7165 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7166 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7167 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7168 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7169 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7170 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7171 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7172 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7173 //VM_CONTEXT4_CNTL
7174 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7175 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7176 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7177 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7178 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7179 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7180 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7181 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7182 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7183 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7184 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7185 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7186 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7187 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7188 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7189 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7190 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7191 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7192 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7193 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7194 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7195 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7196 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7197 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7198 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7199 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7200 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7201 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7202 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7203 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7204 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7205 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7206 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7207 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7208 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7209 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7210 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7211 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7212 //VM_CONTEXT5_CNTL
7213 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7214 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7215 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7216 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7217 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7218 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7219 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7220 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7221 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7222 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7223 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7224 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7225 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7226 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7227 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7228 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7229 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7230 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7231 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7232 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7233 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7234 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7235 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7236 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7237 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7238 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7239 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7240 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7241 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7242 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7243 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7244 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7245 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7246 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7247 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7248 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7249 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7250 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7251 //VM_CONTEXT6_CNTL
7252 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7253 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7254 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7255 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7256 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7257 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7258 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7259 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7260 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7261 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7262 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7263 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7264 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7265 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7266 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7267 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7268 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7269 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7270 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7271 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7272 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7273 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7274 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7275 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7276 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7277 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7278 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7279 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7280 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7281 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7282 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7283 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7284 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7285 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7286 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7287 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7288 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7289 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7290 //VM_CONTEXT7_CNTL
7291 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7292 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7293 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7294 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7295 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7296 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7297 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7298 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7299 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7300 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7301 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7302 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7303 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7304 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7305 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7306 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7307 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7308 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7309 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7310 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7311 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7312 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7313 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7314 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7315 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7316 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7317 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7318 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7319 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7320 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7321 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7322 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7323 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7324 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7325 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7326 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7327 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7328 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7329 //VM_CONTEXT8_CNTL
7330 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7331 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7332 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7333 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7334 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7335 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7336 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7337 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7338 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7339 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7340 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7341 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7342 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7343 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7344 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7345 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7346 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7347 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7348 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7349 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7350 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7351 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7352 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7353 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7354 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7355 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7356 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7357 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7358 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7359 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7360 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7361 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7362 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7363 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7364 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7365 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7366 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7367 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7368 //VM_CONTEXT9_CNTL
7369 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                               0x0
7370 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                             0x1
7371 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                        0x3
7372 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                       0x7
7373 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                            0x8
7374 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x9
7375 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xa
7376 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0xb
7377 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0xc
7378 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0xd
7379 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0xe
7380 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xf
7381 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x10
7382 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                       0x11
7383 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                         0x12
7384 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x13
7385 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x14
7386 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x15
7387 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x16
7388 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                                 0x00000001L
7389 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                               0x00000006L
7390 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                          0x00000078L
7391 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                         0x00000080L
7392 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                              0x00000100L
7393 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00000200L
7394 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00000400L
7395 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00000800L
7396 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00001000L
7397 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00002000L
7398 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00004000L
7399 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00008000L
7400 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00010000L
7401 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                         0x00020000L
7402 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                           0x00040000L
7403 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00080000L
7404 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00100000L
7405 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00200000L
7406 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00400000L
7407 //VM_CONTEXT10_CNTL
7408 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7409 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7410 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7411 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7412 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7413 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7414 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7415 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7416 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7417 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7418 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7419 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7420 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7421 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7422 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7423 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7424 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7425 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7426 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7427 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7428 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7429 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7430 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7431 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7432 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7433 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7434 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7435 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7436 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7437 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7438 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7439 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7440 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7441 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7442 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7443 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7444 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7445 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7446 //VM_CONTEXT11_CNTL
7447 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7448 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7449 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7450 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7451 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7452 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7453 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7454 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7455 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7456 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7457 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7458 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7459 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7460 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7461 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7462 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7463 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7464 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7465 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7466 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7467 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7468 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7469 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7470 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7471 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7472 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7473 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7474 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7475 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7476 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7477 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7478 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7479 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7480 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7481 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7482 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7483 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7484 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7485 //VM_CONTEXT12_CNTL
7486 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7487 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7488 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7489 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7490 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7491 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7492 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7493 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7494 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7495 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7496 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7497 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7498 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7499 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7500 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7501 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7502 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7503 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7504 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7505 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7506 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7507 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7508 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7509 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7510 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7511 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7512 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7513 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7514 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7515 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7516 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7517 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7518 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7519 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7520 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7521 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7522 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7523 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7524 //VM_CONTEXT13_CNTL
7525 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7526 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7527 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7528 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7529 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7530 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7531 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7532 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7533 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7534 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7535 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7536 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7537 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7538 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7539 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7540 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7541 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7542 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7543 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7544 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7545 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7546 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7547 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7548 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7549 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7550 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7551 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7552 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7553 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7554 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7555 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7556 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7557 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7558 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7559 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7560 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7561 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7562 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7563 //VM_CONTEXT14_CNTL
7564 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7565 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7566 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7567 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7568 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7569 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7570 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7571 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7572 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7573 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7574 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7575 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7576 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7577 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7578 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7579 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7580 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7581 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7582 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7583 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7584 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7585 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7586 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7587 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7588 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7589 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7590 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7591 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7592 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7593 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7594 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7595 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7596 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7597 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7598 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7599 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7600 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7601 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7602 //VM_CONTEXT15_CNTL
7603 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                              0x0
7604 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                            0x1
7605 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                       0x3
7606 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                      0x7
7607 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                           0x8
7608 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x9
7609 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xa
7610 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                0xb
7611 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                  0xc
7612 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0xd
7613 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0xe
7614 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xf
7615 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x10
7616 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                      0x11
7617 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                        0x12
7618 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x13
7619 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x14
7620 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x15
7621 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x16
7622 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                                0x00000001L
7623 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                              0x00000006L
7624 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                         0x00000078L
7625 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                        0x00000080L
7626 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                             0x00000100L
7627 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00000200L
7628 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00000400L
7629 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                  0x00000800L
7630 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                    0x00001000L
7631 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00002000L
7632 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00004000L
7633 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00008000L
7634 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00010000L
7635 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                        0x00020000L
7636 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                          0x00040000L
7637 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00080000L
7638 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00100000L
7639 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00200000L
7640 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00400000L
7641 //VM_CONTEXTS_DISABLE
7642 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                         0x0
7643 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                         0x1
7644 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                         0x2
7645 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                         0x3
7646 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                         0x4
7647 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                         0x5
7648 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                         0x6
7649 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                         0x7
7650 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                         0x8
7651 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                         0x9
7652 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                        0xa
7653 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                        0xb
7654 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                        0xc
7655 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                        0xd
7656 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                        0xe
7657 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                        0xf
7658 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                           0x00000001L
7659 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                           0x00000002L
7660 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                           0x00000004L
7661 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                           0x00000008L
7662 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                           0x00000010L
7663 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                           0x00000020L
7664 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                           0x00000040L
7665 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                           0x00000080L
7666 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                           0x00000100L
7667 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                           0x00000200L
7668 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                          0x00000400L
7669 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                          0x00000800L
7670 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                          0x00001000L
7671 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                          0x00002000L
7672 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                          0x00004000L
7673 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                          0x00008000L
7674 //VM_INVALIDATE_ENG0_SEM
7675 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                              0x0
7676 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                                0x00000001L
7677 //VM_INVALIDATE_ENG1_SEM
7678 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                              0x0
7679 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                                0x00000001L
7680 //VM_INVALIDATE_ENG2_SEM
7681 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                              0x0
7682 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                                0x00000001L
7683 //VM_INVALIDATE_ENG3_SEM
7684 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                              0x0
7685 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                                0x00000001L
7686 //VM_INVALIDATE_ENG4_SEM
7687 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                              0x0
7688 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                                0x00000001L
7689 //VM_INVALIDATE_ENG5_SEM
7690 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                              0x0
7691 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                                0x00000001L
7692 //VM_INVALIDATE_ENG6_SEM
7693 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                              0x0
7694 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                                0x00000001L
7695 //VM_INVALIDATE_ENG7_SEM
7696 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                              0x0
7697 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                                0x00000001L
7698 //VM_INVALIDATE_ENG8_SEM
7699 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                              0x0
7700 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                                0x00000001L
7701 //VM_INVALIDATE_ENG9_SEM
7702 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                              0x0
7703 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                                0x00000001L
7704 //VM_INVALIDATE_ENG10_SEM
7705 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                             0x0
7706 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                               0x00000001L
7707 //VM_INVALIDATE_ENG11_SEM
7708 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                             0x0
7709 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                               0x00000001L
7710 //VM_INVALIDATE_ENG12_SEM
7711 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                             0x0
7712 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                               0x00000001L
7713 //VM_INVALIDATE_ENG13_SEM
7714 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                             0x0
7715 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                               0x00000001L
7716 //VM_INVALIDATE_ENG14_SEM
7717 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                             0x0
7718 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                               0x00000001L
7719 //VM_INVALIDATE_ENG15_SEM
7720 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                             0x0
7721 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                               0x00000001L
7722 //VM_INVALIDATE_ENG16_SEM
7723 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                             0x0
7724 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                               0x00000001L
7725 //VM_INVALIDATE_ENG17_SEM
7726 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                             0x0
7727 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                               0x00000001L
7728 //VM_INVALIDATE_ENG0_REQ
7729 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7730 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7731 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7732 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7733 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7734 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7735 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7736 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7737 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7738 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7739 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7740 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7741 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7742 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7743 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7744 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7745 //VM_INVALIDATE_ENG1_REQ
7746 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7747 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7748 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7749 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7750 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7751 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7752 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7753 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7754 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7755 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7756 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7757 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7758 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7759 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7760 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7761 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7762 //VM_INVALIDATE_ENG2_REQ
7763 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7764 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7765 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7766 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7767 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7768 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7769 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7770 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7771 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7772 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7773 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7774 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7775 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7776 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7777 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7778 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7779 //VM_INVALIDATE_ENG3_REQ
7780 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7781 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7782 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7783 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7784 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7785 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7786 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7787 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7788 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7789 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7790 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7791 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7792 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7793 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7794 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7795 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7796 //VM_INVALIDATE_ENG4_REQ
7797 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7798 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7799 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7800 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7801 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7802 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7803 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7804 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7805 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7806 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7807 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7808 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7809 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7810 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7811 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7812 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7813 //VM_INVALIDATE_ENG5_REQ
7814 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7815 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7816 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7817 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7818 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7819 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7820 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7821 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7822 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7823 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7824 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7825 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7826 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7827 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7828 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7829 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7830 //VM_INVALIDATE_ENG6_REQ
7831 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7832 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7833 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7834 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7835 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7836 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7837 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7838 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7839 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7840 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7841 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7842 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7843 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7844 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7845 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7846 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7847 //VM_INVALIDATE_ENG7_REQ
7848 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7849 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7850 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7851 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7852 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7853 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7854 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7855 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7856 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7857 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7858 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7859 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7860 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7861 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7862 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7863 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7864 //VM_INVALIDATE_ENG8_REQ
7865 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7866 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7867 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7868 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7869 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7870 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7871 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7872 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7873 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7874 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7875 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7876 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7877 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7878 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7879 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7880 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7881 //VM_INVALIDATE_ENG9_REQ
7882 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                                0x0
7883 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                             0x10
7884 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                     0x12
7885 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                     0x13
7886 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                     0x14
7887 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                     0x15
7888 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                     0x16
7889 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                     0x17
7890 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                  0x0000FFFFL
7891 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                               0x00030000L
7892 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                       0x00040000L
7893 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                       0x00080000L
7894 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                       0x00100000L
7895 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                       0x00200000L
7896 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                       0x00400000L
7897 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                       0x00800000L
7898 //VM_INVALIDATE_ENG10_REQ
7899 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7900 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7901 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7902 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7903 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7904 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7905 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7906 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7907 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7908 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7909 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7910 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7911 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7912 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7913 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7914 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7915 //VM_INVALIDATE_ENG11_REQ
7916 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7917 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7918 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7919 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7920 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7921 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7922 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7923 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7924 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7925 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7926 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7927 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7928 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7929 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7930 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7931 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7932 //VM_INVALIDATE_ENG12_REQ
7933 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7934 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7935 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7936 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7937 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7938 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7939 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7940 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7941 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7942 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7943 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7944 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7945 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7946 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7947 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7948 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7949 //VM_INVALIDATE_ENG13_REQ
7950 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7951 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7952 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7953 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7954 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7955 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7956 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7957 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7958 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7959 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7960 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7961 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7962 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7963 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7964 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7965 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7966 //VM_INVALIDATE_ENG14_REQ
7967 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7968 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7969 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7970 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7971 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7972 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7973 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7974 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7975 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7976 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7977 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7978 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7979 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7980 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7981 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7982 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
7983 //VM_INVALIDATE_ENG15_REQ
7984 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
7985 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                            0x10
7986 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
7987 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
7988 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
7989 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
7990 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
7991 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
7992 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
7993 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
7994 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
7995 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
7996 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
7997 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
7998 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
7999 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
8000 //VM_INVALIDATE_ENG16_REQ
8001 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
8002 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                            0x10
8003 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
8004 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
8005 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
8006 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
8007 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
8008 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
8009 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
8010 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
8011 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
8012 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
8013 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
8014 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
8015 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
8016 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
8017 //VM_INVALIDATE_ENG17_REQ
8018 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                               0x0
8019 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                            0x10
8020 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                    0x12
8021 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                    0x13
8022 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                    0x14
8023 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                    0x15
8024 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                    0x16
8025 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x17
8026 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                 0x0000FFFFL
8027 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                              0x00030000L
8028 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                      0x00040000L
8029 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                      0x00080000L
8030 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                      0x00100000L
8031 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                      0x00200000L
8032 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                      0x00400000L
8033 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00800000L
8034 //VM_INVALIDATE_ENG0_ACK
8035 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8036 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                              0x10
8037 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8038 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                                0x00010000L
8039 //VM_INVALIDATE_ENG1_ACK
8040 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8041 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                              0x10
8042 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8043 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                                0x00010000L
8044 //VM_INVALIDATE_ENG2_ACK
8045 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8046 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                              0x10
8047 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8048 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                                0x00010000L
8049 //VM_INVALIDATE_ENG3_ACK
8050 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8051 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                              0x10
8052 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8053 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                                0x00010000L
8054 //VM_INVALIDATE_ENG4_ACK
8055 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8056 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                              0x10
8057 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8058 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                                0x00010000L
8059 //VM_INVALIDATE_ENG5_ACK
8060 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8061 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                              0x10
8062 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8063 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                                0x00010000L
8064 //VM_INVALIDATE_ENG6_ACK
8065 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8066 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                              0x10
8067 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8068 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                                0x00010000L
8069 //VM_INVALIDATE_ENG7_ACK
8070 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8071 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                              0x10
8072 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8073 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                                0x00010000L
8074 //VM_INVALIDATE_ENG8_ACK
8075 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8076 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                              0x10
8077 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8078 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                                0x00010000L
8079 //VM_INVALIDATE_ENG9_ACK
8080 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                                0x0
8081 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                              0x10
8082 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                  0x0000FFFFL
8083 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                                0x00010000L
8084 //VM_INVALIDATE_ENG10_ACK
8085 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8086 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                             0x10
8087 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8088 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                               0x00010000L
8089 //VM_INVALIDATE_ENG11_ACK
8090 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8091 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                             0x10
8092 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8093 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                               0x00010000L
8094 //VM_INVALIDATE_ENG12_ACK
8095 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8096 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                             0x10
8097 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8098 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                               0x00010000L
8099 //VM_INVALIDATE_ENG13_ACK
8100 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8101 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                             0x10
8102 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8103 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                               0x00010000L
8104 //VM_INVALIDATE_ENG14_ACK
8105 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8106 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                             0x10
8107 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8108 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                               0x00010000L
8109 //VM_INVALIDATE_ENG15_ACK
8110 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8111 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                             0x10
8112 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8113 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                               0x00010000L
8114 //VM_INVALIDATE_ENG16_ACK
8115 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8116 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                             0x10
8117 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8118 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                               0x00010000L
8119 //VM_INVALIDATE_ENG17_ACK
8120 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                               0x0
8121 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                             0x10
8122 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                 0x0000FFFFL
8123 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                               0x00010000L
8124 //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
8125 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8126 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8127 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8128 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8129 //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
8130 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8131 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8132 //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
8133 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8134 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8135 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8136 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8137 //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
8138 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8139 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8140 //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
8141 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8142 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8143 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8144 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8145 //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
8146 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8147 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8148 //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
8149 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8150 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8151 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8152 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8153 //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
8154 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8155 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8156 //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
8157 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8158 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8159 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8160 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8161 //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
8162 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8163 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8164 //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
8165 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8166 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8167 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8168 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8169 //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
8170 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8171 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8172 //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
8173 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8174 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8175 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8176 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8177 //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
8178 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8179 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8180 //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
8181 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8182 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8183 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8184 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8185 //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
8186 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8187 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8188 //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
8189 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8190 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8191 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8192 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8193 //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
8194 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8195 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8196 //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
8197 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                      0x0
8198 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                  0x1
8199 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                        0x00000001L
8200 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                    0xFFFFFFFEL
8201 //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
8202 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                   0x0
8203 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                     0x0000001FL
8204 //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
8205 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8206 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8207 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8208 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8209 //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
8210 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8211 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8212 //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
8213 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8214 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8215 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8216 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8217 //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
8218 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8219 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8220 //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
8221 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8222 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8223 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8224 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8225 //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
8226 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8227 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8228 //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
8229 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8230 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8231 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8232 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8233 //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
8234 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8235 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8236 //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
8237 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8238 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8239 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8240 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8241 //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
8242 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8243 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8244 //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
8245 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8246 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8247 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8248 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8249 //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
8250 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8251 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8252 //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
8253 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8254 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8255 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8256 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8257 //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
8258 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8259 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8260 //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
8261 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                     0x0
8262 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                 0x1
8263 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                       0x00000001L
8264 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                   0xFFFFFFFEL
8265 //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
8266 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                  0x0
8267 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                    0x0000001FL
8268 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
8269 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8270 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8271 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
8272 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8273 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8274 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
8275 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8276 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8277 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
8278 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8279 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8280 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
8281 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8282 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8283 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
8284 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8285 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8286 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
8287 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8288 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8289 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
8290 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8291 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8292 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
8293 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8294 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8295 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
8296 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8297 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8298 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
8299 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8300 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8301 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
8302 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8303 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8304 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
8305 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8306 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8307 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
8308 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8309 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8310 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
8311 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8312 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8313 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
8314 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8315 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8316 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
8317 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8318 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8319 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
8320 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8321 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8322 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
8323 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                               0x0
8324 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                 0xFFFFFFFFL
8325 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
8326 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                               0x0
8327 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                 0xFFFFFFFFL
8328 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
8329 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8330 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8331 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
8332 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8333 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8334 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
8335 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8336 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8337 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
8338 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8339 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8340 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
8341 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8342 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8343 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
8344 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8345 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8346 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
8347 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8348 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8349 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
8350 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8351 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8352 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
8353 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8354 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8355 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
8356 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8357 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8358 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
8359 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                              0x0
8360 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                                0xFFFFFFFFL
8361 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
8362 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                              0x0
8363 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                                0xFFFFFFFFL
8364 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
8365 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8366 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8367 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
8368 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8369 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8370 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
8371 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8372 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8373 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
8374 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8375 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8376 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
8377 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8378 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8379 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
8380 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8381 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8382 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
8383 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8384 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8385 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
8386 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8387 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8388 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
8389 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8390 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8391 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
8392 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8393 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8394 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
8395 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8396 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8397 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
8398 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8399 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8400 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
8401 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8402 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8403 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
8404 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8405 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8406 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
8407 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8408 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8409 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
8410 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8411 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8412 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
8413 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8414 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8415 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
8416 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8417 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8418 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
8419 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
8420 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
8421 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
8422 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
8423 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
8424 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
8425 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8426 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8427 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
8428 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8429 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8430 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
8431 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8432 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8433 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
8434 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8435 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8436 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
8437 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8438 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8439 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
8440 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8441 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8442 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
8443 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8444 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8445 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
8446 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8447 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8448 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
8449 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8450 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8451 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
8452 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8453 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8454 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
8455 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
8456 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
8457 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
8458 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
8459 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
8460 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
8461 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8462 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8463 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
8464 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8465 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8466 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
8467 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8468 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8469 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
8470 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8471 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8472 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
8473 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8474 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8475 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
8476 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8477 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8478 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
8479 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8480 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8481 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
8482 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8483 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8484 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
8485 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8486 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8487 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
8488 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8489 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8490 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
8491 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8492 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8493 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
8494 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8495 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8496 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
8497 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8498 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8499 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
8500 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8501 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8502 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
8503 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8504 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8505 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
8506 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8507 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8508 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
8509 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8510 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8511 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
8512 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8513 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8514 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
8515 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                 0x0
8516 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                   0xFFFFFFFFL
8517 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
8518 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                  0x0
8519 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                    0x0000000FL
8520 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
8521 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8522 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8523 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
8524 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8525 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8526 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
8527 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8528 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8529 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
8530 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8531 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8532 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
8533 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8534 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8535 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
8536 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8537 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8538 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
8539 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8540 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8541 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
8542 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8543 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8544 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
8545 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8546 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8547 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
8548 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8549 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8550 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
8551 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                                0x0
8552 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                  0xFFFFFFFFL
8553 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
8554 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                 0x0
8555 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                   0x0000000FL
8556 
8557 
8558 // addressBlock: gc_utcl2_vmsharedpfdec
8559 //MC_VM_NB_MMIOBASE
8560 #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                    0x0
8561 #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                      0xFFFFFFFFL
8562 //MC_VM_NB_MMIOLIMIT
8563 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                  0x0
8564 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                    0xFFFFFFFFL
8565 //MC_VM_NB_PCI_CTRL
8566 #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                  0x17
8567 #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                    0x00800000L
8568 //MC_VM_NB_PCI_ARB
8569 #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                     0x3
8570 #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                       0x00000008L
8571 //MC_VM_NB_TOP_OF_DRAM_SLOT1
8572 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                        0x17
8573 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                          0xFF800000L
8574 //MC_VM_NB_LOWER_TOP_OF_DRAM2
8575 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                            0x0
8576 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                        0x17
8577 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                              0x00000001L
8578 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                          0xFF800000L
8579 //MC_VM_NB_UPPER_TOP_OF_DRAM2
8580 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                        0x0
8581 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                          0x00000FFFL
8582 //MC_VM_FB_OFFSET
8583 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                     0x0
8584 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                       0x00FFFFFFL
8585 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
8586 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                               0x0
8587 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                                 0xFFFFFFFFL
8588 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
8589 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                               0x0
8590 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                                 0x0000000FL
8591 //MC_VM_STEERING
8592 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                               0x0
8593 #define MC_VM_STEERING__DEFAULT_STEERING_MASK                                                                 0x00000003L
8594 //MC_SHARED_VIRT_RESET_REQ
8595 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                   0x0
8596 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                   0x1f
8597 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                     0x0000FFFFL
8598 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                     0x80000000L
8599 //MC_MEM_POWER_LS
8600 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                      0x0
8601 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                       0x6
8602 #define MC_MEM_POWER_LS__LS_SETUP_MASK                                                                        0x0000003FL
8603 #define MC_MEM_POWER_LS__LS_HOLD_MASK                                                                         0x00000FC0L
8604 //MC_VM_CACHEABLE_DRAM_ADDRESS_START
8605 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                    0x0
8606 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                      0x000FFFFFL
8607 //MC_VM_CACHEABLE_DRAM_ADDRESS_END
8608 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                      0x0
8609 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                        0x000FFFFFL
8610 //MC_VM_APT_CNTL
8611 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                                 0x0
8612 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                               0x1
8613 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                   0x00000001L
8614 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                                 0x00000002L
8615 //MC_VM_LOCAL_HBM_ADDRESS_START
8616 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                                         0x0
8617 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                                           0x000FFFFFL
8618 //MC_VM_LOCAL_HBM_ADDRESS_END
8619 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                                           0x0
8620 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                             0x000FFFFFL
8621 //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
8622 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                        0x0
8623 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                          0x00000001L
8624 
8625 
8626 // addressBlock: gc_utcl2_vmsharedvcdec
8627 //MC_VM_FB_LOCATION_BASE
8628 #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                                0x0
8629 #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                  0x00FFFFFFL
8630 //MC_VM_FB_LOCATION_TOP
8631 #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                  0x0
8632 #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                    0x00FFFFFFL
8633 //MC_VM_AGP_TOP
8634 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                         0x0
8635 #define MC_VM_AGP_TOP__AGP_TOP_MASK                                                                           0x00FFFFFFL
8636 //MC_VM_AGP_BOT
8637 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                         0x0
8638 #define MC_VM_AGP_BOT__AGP_BOT_MASK                                                                           0x00FFFFFFL
8639 //MC_VM_AGP_BASE
8640 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                       0x0
8641 #define MC_VM_AGP_BASE__AGP_BASE_MASK                                                                         0x00FFFFFFL
8642 //MC_VM_SYSTEM_APERTURE_LOW_ADDR
8643 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                   0x0
8644 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                     0x3FFFFFFFL
8645 //MC_VM_SYSTEM_APERTURE_HIGH_ADDR
8646 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                  0x0
8647 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                    0x3FFFFFFFL
8648 //MC_VM_MX_L1_TLB_CNTL
8649 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                            0x0
8650 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                       0x3
8651 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                          0x5
8652 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                             0x6
8653 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                                 0x7
8654 #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                    0xb
8655 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                                   0xd
8656 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                              0x00000001L
8657 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                         0x00000018L
8658 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                            0x00000020L
8659 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                               0x00000040L
8660 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                   0x00000780L
8661 #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                      0x00001800L
8662 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                                     0x00002000L
8663 
8664 
8665 // addressBlock: gc_tcdec
8666 //TCP_INVALIDATE
8667 #define TCP_INVALIDATE__START__SHIFT                                                                          0x0
8668 #define TCP_INVALIDATE__START_MASK                                                                            0x00000001L
8669 //TCP_STATUS
8670 #define TCP_STATUS__TCP_BUSY__SHIFT                                                                           0x0
8671 #define TCP_STATUS__INPUT_BUSY__SHIFT                                                                         0x1
8672 #define TCP_STATUS__ADRS_BUSY__SHIFT                                                                          0x2
8673 #define TCP_STATUS__TAGRAMS_BUSY__SHIFT                                                                       0x3
8674 #define TCP_STATUS__CNTRL_BUSY__SHIFT                                                                         0x4
8675 #define TCP_STATUS__LFIFO_BUSY__SHIFT                                                                         0x5
8676 #define TCP_STATUS__READ_BUSY__SHIFT                                                                          0x6
8677 #define TCP_STATUS__FORMAT_BUSY__SHIFT                                                                        0x7
8678 #define TCP_STATUS__VM_BUSY__SHIFT                                                                            0x8
8679 #define TCP_STATUS__TCP_BUSY_MASK                                                                             0x00000001L
8680 #define TCP_STATUS__INPUT_BUSY_MASK                                                                           0x00000002L
8681 #define TCP_STATUS__ADRS_BUSY_MASK                                                                            0x00000004L
8682 #define TCP_STATUS__TAGRAMS_BUSY_MASK                                                                         0x00000008L
8683 #define TCP_STATUS__CNTRL_BUSY_MASK                                                                           0x00000010L
8684 #define TCP_STATUS__LFIFO_BUSY_MASK                                                                           0x00000020L
8685 #define TCP_STATUS__READ_BUSY_MASK                                                                            0x00000040L
8686 #define TCP_STATUS__FORMAT_BUSY_MASK                                                                          0x00000080L
8687 #define TCP_STATUS__VM_BUSY_MASK                                                                              0x00000100L
8688 //TCP_CNTL
8689 #define TCP_CNTL__FORCE_HIT__SHIFT                                                                            0x0
8690 #define TCP_CNTL__FORCE_MISS__SHIFT                                                                           0x1
8691 #define TCP_CNTL__L1_SIZE__SHIFT                                                                              0x2
8692 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT                                                                 0x4
8693 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT                                                               0x5
8694 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT                                                                  0xf
8695 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT                                                                 0x16
8696 #define TCP_CNTL__DISABLE_Z_MAP__SHIFT                                                                        0x1c
8697 #define TCP_CNTL__INV_ALL_VMIDS__SHIFT                                                                        0x1d
8698 #define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT                                                                 0x1e
8699 #define TCP_CNTL__FORCE_HIT_MASK                                                                              0x00000001L
8700 #define TCP_CNTL__FORCE_MISS_MASK                                                                             0x00000002L
8701 #define TCP_CNTL__L1_SIZE_MASK                                                                                0x0000000CL
8702 #define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK                                                                   0x00000010L
8703 #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK                                                                 0x00000020L
8704 #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK                                                                    0x001F8000L
8705 #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK                                                                   0x0FC00000L
8706 #define TCP_CNTL__DISABLE_Z_MAP_MASK                                                                          0x10000000L
8707 #define TCP_CNTL__INV_ALL_VMIDS_MASK                                                                          0x20000000L
8708 #define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK                                                                   0x40000000L
8709 //TCP_CHAN_STEER_LO
8710 #define TCP_CHAN_STEER_LO__CHAN0__SHIFT                                                                       0x0
8711 #define TCP_CHAN_STEER_LO__CHAN1__SHIFT                                                                       0x4
8712 #define TCP_CHAN_STEER_LO__CHAN2__SHIFT                                                                       0x8
8713 #define TCP_CHAN_STEER_LO__CHAN3__SHIFT                                                                       0xc
8714 #define TCP_CHAN_STEER_LO__CHAN4__SHIFT                                                                       0x10
8715 #define TCP_CHAN_STEER_LO__CHAN5__SHIFT                                                                       0x14
8716 #define TCP_CHAN_STEER_LO__CHAN6__SHIFT                                                                       0x18
8717 #define TCP_CHAN_STEER_LO__CHAN7__SHIFT                                                                       0x1c
8718 #define TCP_CHAN_STEER_LO__CHAN0_MASK                                                                         0x0000000FL
8719 #define TCP_CHAN_STEER_LO__CHAN1_MASK                                                                         0x000000F0L
8720 #define TCP_CHAN_STEER_LO__CHAN2_MASK                                                                         0x00000F00L
8721 #define TCP_CHAN_STEER_LO__CHAN3_MASK                                                                         0x0000F000L
8722 #define TCP_CHAN_STEER_LO__CHAN4_MASK                                                                         0x000F0000L
8723 #define TCP_CHAN_STEER_LO__CHAN5_MASK                                                                         0x00F00000L
8724 #define TCP_CHAN_STEER_LO__CHAN6_MASK                                                                         0x0F000000L
8725 #define TCP_CHAN_STEER_LO__CHAN7_MASK                                                                         0xF0000000L
8726 //TCP_CHAN_STEER_HI
8727 #define TCP_CHAN_STEER_HI__CHAN8__SHIFT                                                                       0x0
8728 #define TCP_CHAN_STEER_HI__CHAN9__SHIFT                                                                       0x4
8729 #define TCP_CHAN_STEER_HI__CHANA__SHIFT                                                                       0x8
8730 #define TCP_CHAN_STEER_HI__CHANB__SHIFT                                                                       0xc
8731 #define TCP_CHAN_STEER_HI__CHANC__SHIFT                                                                       0x10
8732 #define TCP_CHAN_STEER_HI__CHAND__SHIFT                                                                       0x14
8733 #define TCP_CHAN_STEER_HI__CHANE__SHIFT                                                                       0x18
8734 #define TCP_CHAN_STEER_HI__CHANF__SHIFT                                                                       0x1c
8735 #define TCP_CHAN_STEER_HI__CHAN8_MASK                                                                         0x0000000FL
8736 #define TCP_CHAN_STEER_HI__CHAN9_MASK                                                                         0x000000F0L
8737 #define TCP_CHAN_STEER_HI__CHANA_MASK                                                                         0x00000F00L
8738 #define TCP_CHAN_STEER_HI__CHANB_MASK                                                                         0x0000F000L
8739 #define TCP_CHAN_STEER_HI__CHANC_MASK                                                                         0x000F0000L
8740 #define TCP_CHAN_STEER_HI__CHAND_MASK                                                                         0x00F00000L
8741 #define TCP_CHAN_STEER_HI__CHANE_MASK                                                                         0x0F000000L
8742 #define TCP_CHAN_STEER_HI__CHANF_MASK                                                                         0xF0000000L
8743 //TCP_ADDR_CONFIG
8744 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT                                                                 0x0
8745 #define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                     0x4
8746 #define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT                                                                   0x6
8747 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT                                                                0x9
8748 #define TCP_ADDR_CONFIG__ENABLE64KHASH__SHIFT                                                                 0xb
8749 #define TCP_ADDR_CONFIG__ENABLE2MHASH__SHIFT                                                                  0xc
8750 #define TCP_ADDR_CONFIG__ENABLE1GHASH__SHIFT                                                                  0xd
8751 #define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK                                                                   0x0000000FL
8752 #define TCP_ADDR_CONFIG__NUM_BANKS_MASK                                                                       0x00000030L
8753 #define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK                                                                     0x000001C0L
8754 #define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK                                                                  0x00000200L
8755 #define TCP_ADDR_CONFIG__ENABLE64KHASH_MASK                                                                   0x00000800L
8756 #define TCP_ADDR_CONFIG__ENABLE2MHASH_MASK                                                                    0x00001000L
8757 #define TCP_ADDR_CONFIG__ENABLE1GHASH_MASK                                                                    0x00002000L
8758 //TCP_CREDIT
8759 #define TCP_CREDIT__LFIFO_CREDIT__SHIFT                                                                       0x0
8760 #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT                                                                    0x10
8761 #define TCP_CREDIT__TD_CREDIT__SHIFT                                                                          0x1d
8762 #define TCP_CREDIT__LFIFO_CREDIT_MASK                                                                         0x000003FFL
8763 #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK                                                                      0x007F0000L
8764 #define TCP_CREDIT__TD_CREDIT_MASK                                                                            0xE0000000L
8765 //TCP_BUFFER_ADDR_HASH_CNTL
8766 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT                                                        0x0
8767 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT                                                           0x8
8768 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT                                                   0x10
8769 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT                                                      0x18
8770 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK                                                          0x00000007L
8771 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK                                                             0x00000700L
8772 #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK                                                     0x00070000L
8773 #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK                                                        0x07000000L
8774 //TCP_EDC_CNT
8775 #define TCP_EDC_CNT__SEC_COUNT__SHIFT                                                                         0x0
8776 #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT                                                                   0x8
8777 #define TCP_EDC_CNT__DED_COUNT__SHIFT                                                                         0x10
8778 #define TCP_EDC_CNT__SEC_COUNT_MASK                                                                           0x000000FFL
8779 #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK                                                                     0x0000FF00L
8780 #define TCP_EDC_CNT__DED_COUNT_MASK                                                                           0x00FF0000L
8781 //TC_CFG_L1_LOAD_POLICY0
8782 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT                                                               0x0
8783 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT                                                               0x2
8784 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT                                                               0x4
8785 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT                                                               0x6
8786 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT                                                               0x8
8787 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT                                                               0xa
8788 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT                                                               0xc
8789 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT                                                               0xe
8790 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT                                                               0x10
8791 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT                                                               0x12
8792 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT                                                              0x14
8793 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT                                                              0x16
8794 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT                                                              0x18
8795 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT                                                              0x1a
8796 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT                                                              0x1c
8797 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT                                                              0x1e
8798 #define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK                                                                 0x00000003L
8799 #define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK                                                                 0x0000000CL
8800 #define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK                                                                 0x00000030L
8801 #define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK                                                                 0x000000C0L
8802 #define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK                                                                 0x00000300L
8803 #define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK                                                                 0x00000C00L
8804 #define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK                                                                 0x00003000L
8805 #define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK                                                                 0x0000C000L
8806 #define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK                                                                 0x00030000L
8807 #define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK                                                                 0x000C0000L
8808 #define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK                                                                0x00300000L
8809 #define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK                                                                0x00C00000L
8810 #define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK                                                                0x03000000L
8811 #define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK                                                                0x0C000000L
8812 #define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK                                                                0x30000000L
8813 #define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK                                                                0xC0000000L
8814 //TC_CFG_L1_LOAD_POLICY1
8815 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT                                                              0x0
8816 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT                                                              0x2
8817 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT                                                              0x4
8818 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT                                                              0x6
8819 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT                                                              0x8
8820 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT                                                              0xa
8821 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT                                                              0xc
8822 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT                                                              0xe
8823 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT                                                              0x10
8824 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT                                                              0x12
8825 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT                                                              0x14
8826 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT                                                              0x16
8827 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT                                                              0x18
8828 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT                                                              0x1a
8829 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT                                                              0x1c
8830 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT                                                              0x1e
8831 #define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK                                                                0x00000003L
8832 #define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK                                                                0x0000000CL
8833 #define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK                                                                0x00000030L
8834 #define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK                                                                0x000000C0L
8835 #define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK                                                                0x00000300L
8836 #define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK                                                                0x00000C00L
8837 #define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK                                                                0x00003000L
8838 #define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK                                                                0x0000C000L
8839 #define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK                                                                0x00030000L
8840 #define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK                                                                0x000C0000L
8841 #define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK                                                                0x00300000L
8842 #define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK                                                                0x00C00000L
8843 #define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK                                                                0x03000000L
8844 #define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK                                                                0x0C000000L
8845 #define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK                                                                0x30000000L
8846 #define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK                                                                0xC0000000L
8847 //TC_CFG_L1_STORE_POLICY
8848 #define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT                                                               0x0
8849 #define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT                                                               0x1
8850 #define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT                                                               0x2
8851 #define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT                                                               0x3
8852 #define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT                                                               0x4
8853 #define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT                                                               0x5
8854 #define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT                                                               0x6
8855 #define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT                                                               0x7
8856 #define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT                                                               0x8
8857 #define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT                                                               0x9
8858 #define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT                                                              0xa
8859 #define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT                                                              0xb
8860 #define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT                                                              0xc
8861 #define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT                                                              0xd
8862 #define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT                                                              0xe
8863 #define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT                                                              0xf
8864 #define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT                                                              0x10
8865 #define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT                                                              0x11
8866 #define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT                                                              0x12
8867 #define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT                                                              0x13
8868 #define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT                                                              0x14
8869 #define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT                                                              0x15
8870 #define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT                                                              0x16
8871 #define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT                                                              0x17
8872 #define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT                                                              0x18
8873 #define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT                                                              0x19
8874 #define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT                                                              0x1a
8875 #define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT                                                              0x1b
8876 #define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT                                                              0x1c
8877 #define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT                                                              0x1d
8878 #define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT                                                              0x1e
8879 #define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT                                                              0x1f
8880 #define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK                                                                 0x00000001L
8881 #define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK                                                                 0x00000002L
8882 #define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK                                                                 0x00000004L
8883 #define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK                                                                 0x00000008L
8884 #define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK                                                                 0x00000010L
8885 #define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK                                                                 0x00000020L
8886 #define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK                                                                 0x00000040L
8887 #define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK                                                                 0x00000080L
8888 #define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK                                                                 0x00000100L
8889 #define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK                                                                 0x00000200L
8890 #define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK                                                                0x00000400L
8891 #define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK                                                                0x00000800L
8892 #define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK                                                                0x00001000L
8893 #define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK                                                                0x00002000L
8894 #define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK                                                                0x00004000L
8895 #define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK                                                                0x00008000L
8896 #define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK                                                                0x00010000L
8897 #define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK                                                                0x00020000L
8898 #define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK                                                                0x00040000L
8899 #define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK                                                                0x00080000L
8900 #define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK                                                                0x00100000L
8901 #define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK                                                                0x00200000L
8902 #define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK                                                                0x00400000L
8903 #define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK                                                                0x00800000L
8904 #define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK                                                                0x01000000L
8905 #define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK                                                                0x02000000L
8906 #define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK                                                                0x04000000L
8907 #define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK                                                                0x08000000L
8908 #define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK                                                                0x10000000L
8909 #define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK                                                                0x20000000L
8910 #define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK                                                                0x40000000L
8911 #define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK                                                                0x80000000L
8912 //TC_CFG_L2_LOAD_POLICY0
8913 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT                                                               0x0
8914 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT                                                               0x2
8915 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT                                                               0x4
8916 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT                                                               0x6
8917 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT                                                               0x8
8918 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT                                                               0xa
8919 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT                                                               0xc
8920 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT                                                               0xe
8921 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT                                                               0x10
8922 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT                                                               0x12
8923 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT                                                              0x14
8924 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT                                                              0x16
8925 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT                                                              0x18
8926 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT                                                              0x1a
8927 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT                                                              0x1c
8928 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT                                                              0x1e
8929 #define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK                                                                 0x00000003L
8930 #define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK                                                                 0x0000000CL
8931 #define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK                                                                 0x00000030L
8932 #define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK                                                                 0x000000C0L
8933 #define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK                                                                 0x00000300L
8934 #define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK                                                                 0x00000C00L
8935 #define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK                                                                 0x00003000L
8936 #define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK                                                                 0x0000C000L
8937 #define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK                                                                 0x00030000L
8938 #define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK                                                                 0x000C0000L
8939 #define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK                                                                0x00300000L
8940 #define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK                                                                0x00C00000L
8941 #define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK                                                                0x03000000L
8942 #define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK                                                                0x0C000000L
8943 #define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK                                                                0x30000000L
8944 #define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK                                                                0xC0000000L
8945 //TC_CFG_L2_LOAD_POLICY1
8946 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT                                                              0x0
8947 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT                                                              0x2
8948 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT                                                              0x4
8949 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT                                                              0x6
8950 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT                                                              0x8
8951 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT                                                              0xa
8952 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT                                                              0xc
8953 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT                                                              0xe
8954 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT                                                              0x10
8955 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT                                                              0x12
8956 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT                                                              0x14
8957 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT                                                              0x16
8958 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT                                                              0x18
8959 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT                                                              0x1a
8960 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT                                                              0x1c
8961 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT                                                              0x1e
8962 #define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK                                                                0x00000003L
8963 #define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK                                                                0x0000000CL
8964 #define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK                                                                0x00000030L
8965 #define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK                                                                0x000000C0L
8966 #define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK                                                                0x00000300L
8967 #define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK                                                                0x00000C00L
8968 #define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK                                                                0x00003000L
8969 #define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK                                                                0x0000C000L
8970 #define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK                                                                0x00030000L
8971 #define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK                                                                0x000C0000L
8972 #define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK                                                                0x00300000L
8973 #define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK                                                                0x00C00000L
8974 #define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK                                                                0x03000000L
8975 #define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK                                                                0x0C000000L
8976 #define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK                                                                0x30000000L
8977 #define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK                                                                0xC0000000L
8978 //TC_CFG_L2_STORE_POLICY0
8979 #define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT                                                              0x0
8980 #define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT                                                              0x2
8981 #define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT                                                              0x4
8982 #define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT                                                              0x6
8983 #define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT                                                              0x8
8984 #define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT                                                              0xa
8985 #define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT                                                              0xc
8986 #define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT                                                              0xe
8987 #define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT                                                              0x10
8988 #define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT                                                              0x12
8989 #define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT                                                             0x14
8990 #define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT                                                             0x16
8991 #define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT                                                             0x18
8992 #define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT                                                             0x1a
8993 #define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT                                                             0x1c
8994 #define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT                                                             0x1e
8995 #define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK                                                                0x00000003L
8996 #define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK                                                                0x0000000CL
8997 #define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK                                                                0x00000030L
8998 #define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK                                                                0x000000C0L
8999 #define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK                                                                0x00000300L
9000 #define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK                                                                0x00000C00L
9001 #define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK                                                                0x00003000L
9002 #define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK                                                                0x0000C000L
9003 #define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK                                                                0x00030000L
9004 #define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK                                                                0x000C0000L
9005 #define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK                                                               0x00300000L
9006 #define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK                                                               0x00C00000L
9007 #define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK                                                               0x03000000L
9008 #define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK                                                               0x0C000000L
9009 #define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK                                                               0x30000000L
9010 #define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK                                                               0xC0000000L
9011 //TC_CFG_L2_STORE_POLICY1
9012 #define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT                                                             0x0
9013 #define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT                                                             0x2
9014 #define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT                                                             0x4
9015 #define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT                                                             0x6
9016 #define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT                                                             0x8
9017 #define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT                                                             0xa
9018 #define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT                                                             0xc
9019 #define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT                                                             0xe
9020 #define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT                                                             0x10
9021 #define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT                                                             0x12
9022 #define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT                                                             0x14
9023 #define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT                                                             0x16
9024 #define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT                                                             0x18
9025 #define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT                                                             0x1a
9026 #define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT                                                             0x1c
9027 #define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT                                                             0x1e
9028 #define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK                                                               0x00000003L
9029 #define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK                                                               0x0000000CL
9030 #define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK                                                               0x00000030L
9031 #define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK                                                               0x000000C0L
9032 #define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK                                                               0x00000300L
9033 #define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK                                                               0x00000C00L
9034 #define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK                                                               0x00003000L
9035 #define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK                                                               0x0000C000L
9036 #define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK                                                               0x00030000L
9037 #define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK                                                               0x000C0000L
9038 #define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK                                                               0x00300000L
9039 #define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK                                                               0x00C00000L
9040 #define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK                                                               0x03000000L
9041 #define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK                                                               0x0C000000L
9042 #define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK                                                               0x30000000L
9043 #define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK                                                               0xC0000000L
9044 //TC_CFG_L2_ATOMIC_POLICY
9045 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT                                                              0x0
9046 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT                                                              0x2
9047 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT                                                              0x4
9048 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT                                                              0x6
9049 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT                                                              0x8
9050 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT                                                              0xa
9051 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT                                                              0xc
9052 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT                                                              0xe
9053 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT                                                              0x10
9054 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT                                                              0x12
9055 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT                                                             0x14
9056 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT                                                             0x16
9057 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT                                                             0x18
9058 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT                                                             0x1a
9059 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT                                                             0x1c
9060 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT                                                             0x1e
9061 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK                                                                0x00000003L
9062 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK                                                                0x0000000CL
9063 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK                                                                0x00000030L
9064 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK                                                                0x000000C0L
9065 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK                                                                0x00000300L
9066 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK                                                                0x00000C00L
9067 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK                                                                0x00003000L
9068 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK                                                                0x0000C000L
9069 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK                                                                0x00030000L
9070 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK                                                                0x000C0000L
9071 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK                                                               0x00300000L
9072 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK                                                               0x00C00000L
9073 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK                                                               0x03000000L
9074 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK                                                               0x0C000000L
9075 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK                                                               0x30000000L
9076 #define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK                                                               0xC0000000L
9077 //TC_CFG_L1_VOLATILE
9078 #define TC_CFG_L1_VOLATILE__VOL__SHIFT                                                                        0x0
9079 #define TC_CFG_L1_VOLATILE__VOL_MASK                                                                          0x0000000FL
9080 //TC_CFG_L2_VOLATILE
9081 #define TC_CFG_L2_VOLATILE__VOL__SHIFT                                                                        0x0
9082 #define TC_CFG_L2_VOLATILE__VOL_MASK                                                                          0x0000000FL
9083 //TCI_STATUS
9084 #define TCI_STATUS__TCI_BUSY__SHIFT                                                                           0x0
9085 #define TCI_STATUS__TCI_BUSY_MASK                                                                             0x00000001L
9086 //TCI_CNTL_1
9087 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT                                                                 0x0
9088 #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT                                                                     0x10
9089 #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT                                                                    0x18
9090 #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK                                                                   0x0000FFFFL
9091 #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK                                                                       0x00FF0000L
9092 #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK                                                                      0xFF000000L
9093 //TCI_CNTL_2
9094 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT                                                                0x0
9095 #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT                                                                     0x1
9096 #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK                                                                  0x00000001L
9097 #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK                                                                       0x000001FEL
9098 //TCC_CTRL
9099 #define TCC_CTRL__CACHE_SIZE__SHIFT                                                                           0x0
9100 #define TCC_CTRL__RATE__SHIFT                                                                                 0x2
9101 #define TCC_CTRL__WRITEBACK_MARGIN__SHIFT                                                                     0x4
9102 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT                                                           0x8
9103 #define TCC_CTRL__SRC_FIFO_SIZE__SHIFT                                                                        0xc
9104 #define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT                                                                    0x10
9105 #define TCC_CTRL__LINEAR_SET_HASH__SHIFT                                                                      0x15
9106 #define TCC_CTRL__MDC_SIZE__SHIFT                                                                             0x18
9107 #define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT                                                                      0x1a
9108 #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT                                                               0x1c
9109 #define TCC_CTRL__CACHE_SIZE_MASK                                                                             0x00000003L
9110 #define TCC_CTRL__RATE_MASK                                                                                   0x0000000CL
9111 #define TCC_CTRL__WRITEBACK_MARGIN_MASK                                                                       0x000000F0L
9112 #define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK                                                             0x00000F00L
9113 #define TCC_CTRL__SRC_FIFO_SIZE_MASK                                                                          0x0000F000L
9114 #define TCC_CTRL__LATENCY_FIFO_SIZE_MASK                                                                      0x000F0000L
9115 #define TCC_CTRL__LINEAR_SET_HASH_MASK                                                                        0x00200000L
9116 #define TCC_CTRL__MDC_SIZE_MASK                                                                               0x03000000L
9117 #define TCC_CTRL__MDC_SECTOR_SIZE_MASK                                                                        0x0C000000L
9118 #define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK                                                                 0xF0000000L
9119 //TCC_CTRL2
9120 #define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT                                                                     0x0
9121 #define TCC_CTRL2__PROBE_FIFO_SIZE_MASK                                                                       0x0000000FL
9122 //TCC_EDC_CNT
9123 #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT                                                              0x0
9124 #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT                                                              0x2
9125 #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT                                                             0x4
9126 #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT                                                             0x6
9127 #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT                                                           0x8
9128 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT                                                           0xa
9129 #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT                                                            0xc
9130 #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT                                                            0xe
9131 #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT                                                                0x10
9132 #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT                                                                0x12
9133 #define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT                                                              0x14
9134 #define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT                                                         0x16
9135 #define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT                                                            0x18
9136 #define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT                                                             0x1a
9137 #define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT                                                          0x1c
9138 #define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT                                                          0x1e
9139 #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK                                                                0x00000003L
9140 #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK                                                                0x0000000CL
9141 #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK                                                               0x00000030L
9142 #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK                                                               0x000000C0L
9143 #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK                                                             0x00000300L
9144 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK                                                             0x00000C00L
9145 #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK                                                              0x00003000L
9146 #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK                                                              0x0000C000L
9147 #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK                                                                  0x00030000L
9148 #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK                                                                  0x000C0000L
9149 #define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK                                                                0x00300000L
9150 #define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK                                                           0x00C00000L
9151 #define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK                                                              0x03000000L
9152 #define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK                                                               0x0C000000L
9153 #define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK                                                            0x30000000L
9154 #define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK                                                            0xC0000000L
9155 //TCC_EDC_CNT2
9156 #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT                                                           0x0
9157 #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT                                                       0x2
9158 #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                      0x4
9159 #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                  0x6
9160 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT                                                   0x8
9161 #define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT                                                 0xa
9162 #define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT                                                   0xc
9163 #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK                                                             0x00000003L
9164 #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK                                                         0x0000000CL
9165 #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK                                                        0x00000030L
9166 #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK                                                    0x000000C0L
9167 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK                                                     0x00000300L
9168 #define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK                                                   0x00000C00L
9169 #define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK                                                     0x00003000L
9170 //TCC_REDUNDANCY
9171 #define TCC_REDUNDANCY__MC_SEL0__SHIFT                                                                        0x0
9172 #define TCC_REDUNDANCY__MC_SEL1__SHIFT                                                                        0x1
9173 #define TCC_REDUNDANCY__MC_SEL0_MASK                                                                          0x00000001L
9174 #define TCC_REDUNDANCY__MC_SEL1_MASK                                                                          0x00000002L
9175 //TCC_EXE_DISABLE
9176 #define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT                                                                   0x1
9177 #define TCC_EXE_DISABLE__EXE_DISABLE_MASK                                                                     0x00000002L
9178 //TCC_DSM_CNTL
9179 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT                                                    0x0
9180 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT                                                0x2
9181 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT                                           0x3
9182 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x5
9183 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT                                           0x6
9184 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT                                       0x8
9185 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT                                           0x9
9186 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT                                       0xb
9187 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT                                            0xc
9188 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT                                        0xe
9189 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT                                            0xf
9190 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT                                        0x11
9191 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT                                                 0x12
9192 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x14
9193 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT                                                  0x15
9194 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x17
9195 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT                                                    0x18
9196 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT                                                0x1a
9197 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT                                               0x1b
9198 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x1d
9199 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK                                                      0x00000003L
9200 #define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK                                                  0x00000004L
9201 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK                                             0x00000018L
9202 #define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000020L
9203 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK                                             0x000000C0L
9204 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000100L
9205 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK                                             0x00000600L
9206 #define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK                                         0x00000800L
9207 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK                                              0x00003000L
9208 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK                                          0x00004000L
9209 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK                                              0x00018000L
9210 #define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK                                          0x00020000L
9211 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK                                                   0x000C0000L
9212 #define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK                                               0x00100000L
9213 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK                                                    0x00600000L
9214 #define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK                                                0x00800000L
9215 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK                                                      0x03000000L
9216 #define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK                                                  0x04000000L
9217 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK                                                 0x18000000L
9218 #define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK                                             0x20000000L
9219 //TCC_DSM_CNTLA
9220 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                     0x0
9221 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                                 0x2
9222 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT                                               0x3
9223 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x5
9224 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT                                                 0x6
9225 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x8
9226 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT                                             0x9
9227 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT                                         0xb
9228 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT                                            0xc
9229 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                        0xe
9230 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT                                        0xf
9231 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT                                    0x11
9232 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT                                         0x12
9233 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                     0x14
9234 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT                                                 0x15
9235 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x17
9236 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT                                                  0x18
9237 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x1a
9238 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT                                               0x1b
9239 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT                                           0x1d
9240 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK                                                       0x00000003L
9241 #define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                                   0x00000004L
9242 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK                                                 0x00000018L
9243 #define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                             0x00000020L
9244 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK                                                   0x000000C0L
9245 #define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK                                               0x00000100L
9246 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK                                               0x00000600L
9247 #define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK                                           0x00000800L
9248 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK                                              0x00003000L
9249 #define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK                                          0x00004000L
9250 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK                                          0x00018000L
9251 #define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK                                      0x00020000L
9252 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK                                           0x000C0000L
9253 #define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                       0x00100000L
9254 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK                                                   0x00600000L
9255 #define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK                                               0x00800000L
9256 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK                                                    0x03000000L
9257 #define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK                                                0x04000000L
9258 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK                                                 0x18000000L
9259 #define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK                                             0x20000000L
9260 //TCC_DSM_CNTL2
9261 #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT                                                  0x0
9262 #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT                                                  0x2
9263 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT                                         0x3
9264 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT                                         0x5
9265 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT                                         0x6
9266 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT                                         0x8
9267 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT                                         0x9
9268 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT                                         0xb
9269 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT                                          0xc
9270 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT                                          0xe
9271 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT                                          0xf
9272 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT                                          0x11
9273 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT                                               0x12
9274 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT                                               0x14
9275 #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT                                                0x15
9276 #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT                                                0x17
9277 #define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
9278 #define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK                                                    0x00000003L
9279 #define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK                                                    0x00000004L
9280 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK                                           0x00000018L
9281 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK                                           0x00000020L
9282 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK                                           0x000000C0L
9283 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK                                           0x00000100L
9284 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK                                           0x00000600L
9285 #define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK                                           0x00000800L
9286 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK                                            0x00003000L
9287 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK                                            0x00004000L
9288 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK                                            0x00018000L
9289 #define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK                                            0x00020000L
9290 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK                                                 0x000C0000L
9291 #define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK                                                 0x00100000L
9292 #define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK                                                  0x00600000L
9293 #define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK                                                  0x00800000L
9294 #define TCC_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
9295 //TCC_DSM_CNTL2A
9296 #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT                                                 0x0
9297 #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT                                                 0x2
9298 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT                                            0x3
9299 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT                                            0x5
9300 #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT                                                0x6
9301 #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT                                                0x8
9302 #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT                                             0x9
9303 #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT                                             0xb
9304 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT                                             0xc
9305 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT                                             0xe
9306 #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT                                               0xf
9307 #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT                                               0x11
9308 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT                                           0x12
9309 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT                                           0x14
9310 #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT                                                   0x15
9311 #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT                                                   0x17
9312 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT                                          0x18
9313 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT                                          0x1a
9314 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT                                       0x1b
9315 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT                                       0x1d
9316 #define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK                                                   0x00000003L
9317 #define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK                                                   0x00000004L
9318 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK                                              0x00000018L
9319 #define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK                                              0x00000020L
9320 #define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK                                                  0x000000C0L
9321 #define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK                                                  0x00000100L
9322 #define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK                                               0x00000600L
9323 #define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK                                               0x00000800L
9324 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
9325 #define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK                                               0x00004000L
9326 #define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK                                                 0x00018000L
9327 #define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK                                                 0x00020000L
9328 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK                                             0x000C0000L
9329 #define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK                                             0x00100000L
9330 #define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK                                                     0x00600000L
9331 #define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK                                                     0x00800000L
9332 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK                                            0x03000000L
9333 #define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK                                            0x04000000L
9334 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK                                         0x18000000L
9335 #define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK                                         0x20000000L
9336 //TCC_DSM_CNTL2B
9337 #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT                                               0x0
9338 #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT                                               0x2
9339 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT                                      0x3
9340 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT                                      0x5
9341 #define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
9342 #define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
9343 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK                                        0x00000018L
9344 #define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK                                        0x00000020L
9345 //TCC_WBINVL2
9346 #define TCC_WBINVL2__DONE__SHIFT                                                                              0x4
9347 #define TCC_WBINVL2__DONE_MASK                                                                                0x00000010L
9348 //TCC_SOFT_RESET
9349 #define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT                                                                 0x0
9350 #define TCC_SOFT_RESET__HALT_FOR_RESET_MASK                                                                   0x00000001L
9351 //TCA_CTRL
9352 #define TCA_CTRL__HOLE_TIMEOUT__SHIFT                                                                         0x0
9353 #define TCA_CTRL__RB_STILL_4_PHASE__SHIFT                                                                     0x4
9354 #define TCA_CTRL__RB_AS_TCI__SHIFT                                                                            0x5
9355 #define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT                                                               0x6
9356 #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT                                                          0x7
9357 #define TCA_CTRL__HOLE_TIMEOUT_MASK                                                                           0x0000000FL
9358 #define TCA_CTRL__RB_STILL_4_PHASE_MASK                                                                       0x00000010L
9359 #define TCA_CTRL__RB_AS_TCI_MASK                                                                              0x00000020L
9360 #define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK                                                                 0x00000040L
9361 #define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK                                                            0x00000080L
9362 //TCA_BURST_MASK
9363 #define TCA_BURST_MASK__ADDR_MASK__SHIFT                                                                      0x0
9364 #define TCA_BURST_MASK__ADDR_MASK_MASK                                                                        0xFFFFFFFFL
9365 //TCA_BURST_CTRL
9366 #define TCA_BURST_CTRL__MAX_BURST__SHIFT                                                                      0x0
9367 #define TCA_BURST_CTRL__RB_DISABLE__SHIFT                                                                     0x3
9368 #define TCA_BURST_CTRL__TCP_DISABLE__SHIFT                                                                    0x4
9369 #define TCA_BURST_CTRL__SQC_DISABLE__SHIFT                                                                    0x5
9370 #define TCA_BURST_CTRL__CPF_DISABLE__SHIFT                                                                    0x6
9371 #define TCA_BURST_CTRL__CPG_DISABLE__SHIFT                                                                    0x7
9372 #define TCA_BURST_CTRL__IA_DISABLE__SHIFT                                                                     0x8
9373 #define TCA_BURST_CTRL__WD_DISABLE__SHIFT                                                                     0x9
9374 #define TCA_BURST_CTRL__SQG_DISABLE__SHIFT                                                                    0xa
9375 #define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT                                                                  0xb
9376 #define TCA_BURST_CTRL__TPI_DISABLE__SHIFT                                                                    0xc
9377 #define TCA_BURST_CTRL__RLC_DISABLE__SHIFT                                                                    0xd
9378 #define TCA_BURST_CTRL__PA_DISABLE__SHIFT                                                                     0xe
9379 #define TCA_BURST_CTRL__MAX_BURST_MASK                                                                        0x00000007L
9380 #define TCA_BURST_CTRL__RB_DISABLE_MASK                                                                       0x00000008L
9381 #define TCA_BURST_CTRL__TCP_DISABLE_MASK                                                                      0x00000010L
9382 #define TCA_BURST_CTRL__SQC_DISABLE_MASK                                                                      0x00000020L
9383 #define TCA_BURST_CTRL__CPF_DISABLE_MASK                                                                      0x00000040L
9384 #define TCA_BURST_CTRL__CPG_DISABLE_MASK                                                                      0x00000080L
9385 #define TCA_BURST_CTRL__IA_DISABLE_MASK                                                                       0x00000100L
9386 #define TCA_BURST_CTRL__WD_DISABLE_MASK                                                                       0x00000200L
9387 #define TCA_BURST_CTRL__SQG_DISABLE_MASK                                                                      0x00000400L
9388 #define TCA_BURST_CTRL__UTCL2_DISABLE_MASK                                                                    0x00000800L
9389 #define TCA_BURST_CTRL__TPI_DISABLE_MASK                                                                      0x00001000L
9390 #define TCA_BURST_CTRL__RLC_DISABLE_MASK                                                                      0x00002000L
9391 #define TCA_BURST_CTRL__PA_DISABLE_MASK                                                                       0x00004000L
9392 //TCA_DSM_CNTL
9393 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT                                                 0x0
9394 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT                                             0x2
9395 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT                                                  0x3
9396 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT                                              0x5
9397 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK                                                   0x00000003L
9398 #define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK                                               0x00000004L
9399 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK                                                    0x00000018L
9400 #define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK                                                0x00000020L
9401 //TCA_DSM_CNTL2
9402 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT                                               0x0
9403 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT                                               0x2
9404 #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT                                                0x3
9405 #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT                                                0x5
9406 #define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                    0x1a
9407 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK                                                 0x00000003L
9408 #define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK                                                 0x00000004L
9409 #define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK                                                  0x00000018L
9410 #define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK                                                  0x00000020L
9411 #define TCA_DSM_CNTL2__INJECT_DELAY_MASK                                                                      0xFC000000L
9412 //TCA_EDC_CNT
9413 #define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT                                                               0x0
9414 #define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT                                                                0x2
9415 #define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK                                                                 0x00000003L
9416 #define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK                                                                  0x0000000CL
9417 
9418 
9419 // addressBlock: gc_shdec
9420 //SPI_SHADER_PGM_RSRC3_PS
9421 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT                                                                 0x0
9422 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT                                                            0x10
9423 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
9424 #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT                                                          0x1a
9425 #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK                                                                   0x0000FFFFL
9426 #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK                                                              0x003F0000L
9427 #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
9428 #define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK                                                            0x3C000000L
9429 //SPI_SHADER_PGM_LO_PS
9430 #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT                                                                 0x0
9431 #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9432 //SPI_SHADER_PGM_HI_PS
9433 #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT                                                                 0x0
9434 #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK                                                                   0xFFL
9435 //SPI_SHADER_PGM_RSRC1_PS
9436 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT                                                                 0x0
9437 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT                                                                 0x6
9438 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT                                                              0xa
9439 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT                                                            0xc
9440 #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT                                                                  0x14
9441 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT                                                            0x15
9442 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT                                                            0x16
9443 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT                                                             0x17
9444 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT                                                      0x18
9445 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT                                                             0x1c
9446 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT                                                             0x1d
9447 #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK                                                                   0x0000003FL
9448 #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK                                                                   0x000003C0L
9449 #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK                                                                0x00000C00L
9450 #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK                                                              0x000FF000L
9451 #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK                                                                    0x00100000L
9452 #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK                                                              0x00200000L
9453 #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK                                                              0x00400000L
9454 #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK                                                               0x00800000L
9455 #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK                                                        0x01000000L
9456 #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK                                                               0x10000000L
9457 #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK                                                               0x20000000L
9458 //SPI_SHADER_PGM_RSRC2_PS
9459 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT                                                            0x0
9460 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT                                                             0x1
9461 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT                                                          0x6
9462 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT                                                           0x7
9463 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT                                                        0x8
9464 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT                                                               0x10
9465 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT                                                 0x19
9466 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT                                              0x1a
9467 #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT                                                           0x1b
9468 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT                                                         0x1c
9469 #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK                                                              0x00000001L
9470 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK                                                               0x0000003EL
9471 #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK                                                            0x00000040L
9472 #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK                                                             0x00000080L
9473 #define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK                                                          0x0000FF00L
9474 #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK                                                                 0x01FF0000L
9475 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK                                                   0x02000000L
9476 #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK                                                0x04000000L
9477 #define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK                                                             0x08000000L
9478 #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK                                                           0x10000000L
9479 //SPI_SHADER_USER_DATA_PS_0
9480 #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT                                                                0x0
9481 #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK                                                                  0xFFFFFFFFL
9482 //SPI_SHADER_USER_DATA_PS_1
9483 #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT                                                                0x0
9484 #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK                                                                  0xFFFFFFFFL
9485 //SPI_SHADER_USER_DATA_PS_2
9486 #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT                                                                0x0
9487 #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK                                                                  0xFFFFFFFFL
9488 //SPI_SHADER_USER_DATA_PS_3
9489 #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT                                                                0x0
9490 #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK                                                                  0xFFFFFFFFL
9491 //SPI_SHADER_USER_DATA_PS_4
9492 #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT                                                                0x0
9493 #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK                                                                  0xFFFFFFFFL
9494 //SPI_SHADER_USER_DATA_PS_5
9495 #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT                                                                0x0
9496 #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK                                                                  0xFFFFFFFFL
9497 //SPI_SHADER_USER_DATA_PS_6
9498 #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT                                                                0x0
9499 #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK                                                                  0xFFFFFFFFL
9500 //SPI_SHADER_USER_DATA_PS_7
9501 #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT                                                                0x0
9502 #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK                                                                  0xFFFFFFFFL
9503 //SPI_SHADER_USER_DATA_PS_8
9504 #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT                                                                0x0
9505 #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK                                                                  0xFFFFFFFFL
9506 //SPI_SHADER_USER_DATA_PS_9
9507 #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT                                                                0x0
9508 #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK                                                                  0xFFFFFFFFL
9509 //SPI_SHADER_USER_DATA_PS_10
9510 #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT                                                               0x0
9511 #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK                                                                 0xFFFFFFFFL
9512 //SPI_SHADER_USER_DATA_PS_11
9513 #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT                                                               0x0
9514 #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK                                                                 0xFFFFFFFFL
9515 //SPI_SHADER_USER_DATA_PS_12
9516 #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT                                                               0x0
9517 #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK                                                                 0xFFFFFFFFL
9518 //SPI_SHADER_USER_DATA_PS_13
9519 #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT                                                               0x0
9520 #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK                                                                 0xFFFFFFFFL
9521 //SPI_SHADER_USER_DATA_PS_14
9522 #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT                                                               0x0
9523 #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK                                                                 0xFFFFFFFFL
9524 //SPI_SHADER_USER_DATA_PS_15
9525 #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT                                                               0x0
9526 #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK                                                                 0xFFFFFFFFL
9527 //SPI_SHADER_USER_DATA_PS_16
9528 #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT                                                               0x0
9529 #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK                                                                 0xFFFFFFFFL
9530 //SPI_SHADER_USER_DATA_PS_17
9531 #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT                                                               0x0
9532 #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK                                                                 0xFFFFFFFFL
9533 //SPI_SHADER_USER_DATA_PS_18
9534 #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT                                                               0x0
9535 #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK                                                                 0xFFFFFFFFL
9536 //SPI_SHADER_USER_DATA_PS_19
9537 #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT                                                               0x0
9538 #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK                                                                 0xFFFFFFFFL
9539 //SPI_SHADER_USER_DATA_PS_20
9540 #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT                                                               0x0
9541 #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK                                                                 0xFFFFFFFFL
9542 //SPI_SHADER_USER_DATA_PS_21
9543 #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT                                                               0x0
9544 #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK                                                                 0xFFFFFFFFL
9545 //SPI_SHADER_USER_DATA_PS_22
9546 #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT                                                               0x0
9547 #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK                                                                 0xFFFFFFFFL
9548 //SPI_SHADER_USER_DATA_PS_23
9549 #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT                                                               0x0
9550 #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK                                                                 0xFFFFFFFFL
9551 //SPI_SHADER_USER_DATA_PS_24
9552 #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT                                                               0x0
9553 #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK                                                                 0xFFFFFFFFL
9554 //SPI_SHADER_USER_DATA_PS_25
9555 #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT                                                               0x0
9556 #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK                                                                 0xFFFFFFFFL
9557 //SPI_SHADER_USER_DATA_PS_26
9558 #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT                                                               0x0
9559 #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK                                                                 0xFFFFFFFFL
9560 //SPI_SHADER_USER_DATA_PS_27
9561 #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT                                                               0x0
9562 #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK                                                                 0xFFFFFFFFL
9563 //SPI_SHADER_USER_DATA_PS_28
9564 #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT                                                               0x0
9565 #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK                                                                 0xFFFFFFFFL
9566 //SPI_SHADER_USER_DATA_PS_29
9567 #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT                                                               0x0
9568 #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK                                                                 0xFFFFFFFFL
9569 //SPI_SHADER_USER_DATA_PS_30
9570 #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT                                                               0x0
9571 #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK                                                                 0xFFFFFFFFL
9572 //SPI_SHADER_USER_DATA_PS_31
9573 #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT                                                               0x0
9574 #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK                                                                 0xFFFFFFFFL
9575 //SPI_SHADER_PGM_RSRC3_VS
9576 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT                                                                 0x0
9577 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT                                                            0x10
9578 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
9579 #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT                                                          0x1a
9580 #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK                                                                   0x0000FFFFL
9581 #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK                                                              0x003F0000L
9582 #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
9583 #define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK                                                            0x3C000000L
9584 //SPI_SHADER_LATE_ALLOC_VS
9585 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT                                                                0x0
9586 #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK                                                                  0x0000003FL
9587 //SPI_SHADER_PGM_LO_VS
9588 #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT                                                                 0x0
9589 #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9590 //SPI_SHADER_PGM_HI_VS
9591 #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT                                                                 0x0
9592 #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK                                                                   0xFFL
9593 //SPI_SHADER_PGM_RSRC1_VS
9594 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT                                                                 0x0
9595 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT                                                                 0x6
9596 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT                                                              0xa
9597 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT                                                            0xc
9598 #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT                                                                  0x14
9599 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT                                                            0x15
9600 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT                                                            0x16
9601 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT                                                             0x17
9602 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT                                                         0x18
9603 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT                                                       0x1a
9604 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT                                                             0x1e
9605 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT                                                             0x1f
9606 #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK                                                                   0x0000003FL
9607 #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK                                                                   0x000003C0L
9608 #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK                                                                0x00000C00L
9609 #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK                                                              0x000FF000L
9610 #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK                                                                    0x00100000L
9611 #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK                                                              0x00200000L
9612 #define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK                                                              0x00400000L
9613 #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK                                                               0x00800000L
9614 #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK                                                           0x03000000L
9615 #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK                                                         0x04000000L
9616 #define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK                                                               0x40000000L
9617 #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK                                                               0x80000000L
9618 //SPI_SHADER_PGM_RSRC2_VS
9619 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT                                                            0x0
9620 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT                                                             0x1
9621 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT                                                          0x6
9622 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT                                                             0x7
9623 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT                                                           0x8
9624 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT                                                           0x9
9625 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT                                                           0xa
9626 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT                                                           0xb
9627 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT                                                                 0xc
9628 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT                                                               0xd
9629 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT                                                            0x16
9630 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT                                                      0x18
9631 #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT                                                           0x1b
9632 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT                                                         0x1c
9633 #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK                                                              0x00000001L
9634 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK                                                               0x0000003EL
9635 #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK                                                            0x00000040L
9636 #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK                                                               0x00000080L
9637 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK                                                             0x00000100L
9638 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK                                                             0x00000200L
9639 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK                                                             0x00000400L
9640 #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK                                                             0x00000800L
9641 #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK                                                                   0x00001000L
9642 #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK                                                                 0x003FE000L
9643 #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK                                                              0x00400000L
9644 #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK                                                        0x01000000L
9645 #define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK                                                             0x08000000L
9646 #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK                                                           0x10000000L
9647 //SPI_SHADER_USER_DATA_VS_0
9648 #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT                                                                0x0
9649 #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK                                                                  0xFFFFFFFFL
9650 //SPI_SHADER_USER_DATA_VS_1
9651 #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT                                                                0x0
9652 #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK                                                                  0xFFFFFFFFL
9653 //SPI_SHADER_USER_DATA_VS_2
9654 #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT                                                                0x0
9655 #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK                                                                  0xFFFFFFFFL
9656 //SPI_SHADER_USER_DATA_VS_3
9657 #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT                                                                0x0
9658 #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK                                                                  0xFFFFFFFFL
9659 //SPI_SHADER_USER_DATA_VS_4
9660 #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT                                                                0x0
9661 #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK                                                                  0xFFFFFFFFL
9662 //SPI_SHADER_USER_DATA_VS_5
9663 #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT                                                                0x0
9664 #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK                                                                  0xFFFFFFFFL
9665 //SPI_SHADER_USER_DATA_VS_6
9666 #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT                                                                0x0
9667 #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK                                                                  0xFFFFFFFFL
9668 //SPI_SHADER_USER_DATA_VS_7
9669 #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT                                                                0x0
9670 #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK                                                                  0xFFFFFFFFL
9671 //SPI_SHADER_USER_DATA_VS_8
9672 #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT                                                                0x0
9673 #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK                                                                  0xFFFFFFFFL
9674 //SPI_SHADER_USER_DATA_VS_9
9675 #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT                                                                0x0
9676 #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK                                                                  0xFFFFFFFFL
9677 //SPI_SHADER_USER_DATA_VS_10
9678 #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT                                                               0x0
9679 #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK                                                                 0xFFFFFFFFL
9680 //SPI_SHADER_USER_DATA_VS_11
9681 #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT                                                               0x0
9682 #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK                                                                 0xFFFFFFFFL
9683 //SPI_SHADER_USER_DATA_VS_12
9684 #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT                                                               0x0
9685 #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK                                                                 0xFFFFFFFFL
9686 //SPI_SHADER_USER_DATA_VS_13
9687 #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT                                                               0x0
9688 #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK                                                                 0xFFFFFFFFL
9689 //SPI_SHADER_USER_DATA_VS_14
9690 #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT                                                               0x0
9691 #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK                                                                 0xFFFFFFFFL
9692 //SPI_SHADER_USER_DATA_VS_15
9693 #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT                                                               0x0
9694 #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK                                                                 0xFFFFFFFFL
9695 //SPI_SHADER_USER_DATA_VS_16
9696 #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT                                                               0x0
9697 #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK                                                                 0xFFFFFFFFL
9698 //SPI_SHADER_USER_DATA_VS_17
9699 #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT                                                               0x0
9700 #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK                                                                 0xFFFFFFFFL
9701 //SPI_SHADER_USER_DATA_VS_18
9702 #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT                                                               0x0
9703 #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK                                                                 0xFFFFFFFFL
9704 //SPI_SHADER_USER_DATA_VS_19
9705 #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT                                                               0x0
9706 #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK                                                                 0xFFFFFFFFL
9707 //SPI_SHADER_USER_DATA_VS_20
9708 #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT                                                               0x0
9709 #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK                                                                 0xFFFFFFFFL
9710 //SPI_SHADER_USER_DATA_VS_21
9711 #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT                                                               0x0
9712 #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK                                                                 0xFFFFFFFFL
9713 //SPI_SHADER_USER_DATA_VS_22
9714 #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT                                                               0x0
9715 #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK                                                                 0xFFFFFFFFL
9716 //SPI_SHADER_USER_DATA_VS_23
9717 #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT                                                               0x0
9718 #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK                                                                 0xFFFFFFFFL
9719 //SPI_SHADER_USER_DATA_VS_24
9720 #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT                                                               0x0
9721 #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK                                                                 0xFFFFFFFFL
9722 //SPI_SHADER_USER_DATA_VS_25
9723 #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT                                                               0x0
9724 #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK                                                                 0xFFFFFFFFL
9725 //SPI_SHADER_USER_DATA_VS_26
9726 #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT                                                               0x0
9727 #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK                                                                 0xFFFFFFFFL
9728 //SPI_SHADER_USER_DATA_VS_27
9729 #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT                                                               0x0
9730 #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK                                                                 0xFFFFFFFFL
9731 //SPI_SHADER_USER_DATA_VS_28
9732 #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT                                                               0x0
9733 #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK                                                                 0xFFFFFFFFL
9734 //SPI_SHADER_USER_DATA_VS_29
9735 #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT                                                               0x0
9736 #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK                                                                 0xFFFFFFFFL
9737 //SPI_SHADER_USER_DATA_VS_30
9738 #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT                                                               0x0
9739 #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK                                                                 0xFFFFFFFFL
9740 //SPI_SHADER_USER_DATA_VS_31
9741 #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT                                                               0x0
9742 #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK                                                                 0xFFFFFFFFL
9743 //SPI_SHADER_PGM_RSRC2_GS_VS
9744 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT                                                         0x0
9745 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT                                                          0x1
9746 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT                                                       0x6
9747 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT                                                            0x7
9748 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT                                                      0x10
9749 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT                                                          0x12
9750 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT                                                           0x13
9751 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT                                                        0x1b
9752 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT                                                      0x1c
9753 #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK                                                           0x00000001L
9754 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK                                                            0x0000003EL
9755 #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK                                                         0x00000040L
9756 #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK                                                              0x0000FF80L
9757 #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK                                                        0x00030000L
9758 #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK                                                            0x00040000L
9759 #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK                                                             0x07F80000L
9760 #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK                                                          0x08000000L
9761 #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK                                                        0x10000000L
9762 //SPI_SHADER_PGM_RSRC4_GS
9763 #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT                                                      0x0
9764 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT                                              0x7
9765 #define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK                                                        0x0000007FL
9766 #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK                                                0x00003F80L
9767 //SPI_SHADER_USER_DATA_ADDR_LO_GS
9768 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT                                                      0x0
9769 #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9770 //SPI_SHADER_USER_DATA_ADDR_HI_GS
9771 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT                                                      0x0
9772 #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9773 //SPI_SHADER_PGM_LO_ES
9774 #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT                                                                 0x0
9775 #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9776 //SPI_SHADER_PGM_HI_ES
9777 #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT                                                                 0x0
9778 #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK                                                                   0xFFL
9779 //SPI_SHADER_PGM_RSRC3_GS
9780 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT                                                                 0x0
9781 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT                                                            0x10
9782 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x16
9783 #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT                                                          0x1a
9784 #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK                                                                   0x0000FFFFL
9785 #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK                                                              0x003F0000L
9786 #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK                                                      0x03C00000L
9787 #define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK                                                            0x3C000000L
9788 //SPI_SHADER_PGM_LO_GS
9789 #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT                                                                 0x0
9790 #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9791 //SPI_SHADER_PGM_HI_GS
9792 #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT                                                                 0x0
9793 #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK                                                                   0xFFL
9794 //SPI_SHADER_PGM_RSRC1_GS
9795 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT                                                                 0x0
9796 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT                                                                 0x6
9797 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT                                                              0xa
9798 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT                                                            0xc
9799 #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT                                                                  0x14
9800 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT                                                            0x15
9801 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT                                                            0x16
9802 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT                                                             0x17
9803 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT                                                       0x18
9804 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT                                                             0x1c
9805 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT                                                      0x1d
9806 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT                                                             0x1f
9807 #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK                                                                   0x0000003FL
9808 #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK                                                                   0x000003C0L
9809 #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK                                                                0x00000C00L
9810 #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK                                                              0x000FF000L
9811 #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK                                                                    0x00100000L
9812 #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK                                                              0x00200000L
9813 #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK                                                              0x00400000L
9814 #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK                                                               0x00800000L
9815 #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK                                                         0x01000000L
9816 #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK                                                               0x10000000L
9817 #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK                                                        0x60000000L
9818 #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK                                                               0x80000000L
9819 //SPI_SHADER_PGM_RSRC2_GS
9820 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT                                                            0x0
9821 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT                                                             0x1
9822 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT                                                          0x6
9823 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT                                                               0x7
9824 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT                                                      0x10
9825 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT                                                             0x12
9826 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT                                                              0x13
9827 #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT                                                           0x1b
9828 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT                                                         0x1c
9829 #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK                                                              0x00000001L
9830 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK                                                               0x0000003EL
9831 #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK                                                            0x00000040L
9832 #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK                                                                 0x0000FF80L
9833 #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK                                                        0x00030000L
9834 #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK                                                               0x00040000L
9835 #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK                                                                0x07F80000L
9836 #define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK                                                             0x08000000L
9837 #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK                                                           0x10000000L
9838 //SPI_SHADER_USER_DATA_ES_0
9839 #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT                                                                0x0
9840 #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK                                                                  0xFFFFFFFFL
9841 //SPI_SHADER_USER_DATA_ES_1
9842 #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT                                                                0x0
9843 #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK                                                                  0xFFFFFFFFL
9844 //SPI_SHADER_USER_DATA_ES_2
9845 #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT                                                                0x0
9846 #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK                                                                  0xFFFFFFFFL
9847 //SPI_SHADER_USER_DATA_ES_3
9848 #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT                                                                0x0
9849 #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK                                                                  0xFFFFFFFFL
9850 //SPI_SHADER_USER_DATA_ES_4
9851 #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT                                                                0x0
9852 #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK                                                                  0xFFFFFFFFL
9853 //SPI_SHADER_USER_DATA_ES_5
9854 #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT                                                                0x0
9855 #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK                                                                  0xFFFFFFFFL
9856 //SPI_SHADER_USER_DATA_ES_6
9857 #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT                                                                0x0
9858 #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK                                                                  0xFFFFFFFFL
9859 //SPI_SHADER_USER_DATA_ES_7
9860 #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT                                                                0x0
9861 #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK                                                                  0xFFFFFFFFL
9862 //SPI_SHADER_USER_DATA_ES_8
9863 #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT                                                                0x0
9864 #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK                                                                  0xFFFFFFFFL
9865 //SPI_SHADER_USER_DATA_ES_9
9866 #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT                                                                0x0
9867 #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK                                                                  0xFFFFFFFFL
9868 //SPI_SHADER_USER_DATA_ES_10
9869 #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT                                                               0x0
9870 #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK                                                                 0xFFFFFFFFL
9871 //SPI_SHADER_USER_DATA_ES_11
9872 #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT                                                               0x0
9873 #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK                                                                 0xFFFFFFFFL
9874 //SPI_SHADER_USER_DATA_ES_12
9875 #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT                                                               0x0
9876 #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK                                                                 0xFFFFFFFFL
9877 //SPI_SHADER_USER_DATA_ES_13
9878 #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT                                                               0x0
9879 #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK                                                                 0xFFFFFFFFL
9880 //SPI_SHADER_USER_DATA_ES_14
9881 #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT                                                               0x0
9882 #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK                                                                 0xFFFFFFFFL
9883 //SPI_SHADER_USER_DATA_ES_15
9884 #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT                                                               0x0
9885 #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK                                                                 0xFFFFFFFFL
9886 //SPI_SHADER_USER_DATA_ES_16
9887 #define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT                                                               0x0
9888 #define SPI_SHADER_USER_DATA_ES_16__DATA_MASK                                                                 0xFFFFFFFFL
9889 //SPI_SHADER_USER_DATA_ES_17
9890 #define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT                                                               0x0
9891 #define SPI_SHADER_USER_DATA_ES_17__DATA_MASK                                                                 0xFFFFFFFFL
9892 //SPI_SHADER_USER_DATA_ES_18
9893 #define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT                                                               0x0
9894 #define SPI_SHADER_USER_DATA_ES_18__DATA_MASK                                                                 0xFFFFFFFFL
9895 //SPI_SHADER_USER_DATA_ES_19
9896 #define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT                                                               0x0
9897 #define SPI_SHADER_USER_DATA_ES_19__DATA_MASK                                                                 0xFFFFFFFFL
9898 //SPI_SHADER_USER_DATA_ES_20
9899 #define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT                                                               0x0
9900 #define SPI_SHADER_USER_DATA_ES_20__DATA_MASK                                                                 0xFFFFFFFFL
9901 //SPI_SHADER_USER_DATA_ES_21
9902 #define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT                                                               0x0
9903 #define SPI_SHADER_USER_DATA_ES_21__DATA_MASK                                                                 0xFFFFFFFFL
9904 //SPI_SHADER_USER_DATA_ES_22
9905 #define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT                                                               0x0
9906 #define SPI_SHADER_USER_DATA_ES_22__DATA_MASK                                                                 0xFFFFFFFFL
9907 //SPI_SHADER_USER_DATA_ES_23
9908 #define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT                                                               0x0
9909 #define SPI_SHADER_USER_DATA_ES_23__DATA_MASK                                                                 0xFFFFFFFFL
9910 //SPI_SHADER_USER_DATA_ES_24
9911 #define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT                                                               0x0
9912 #define SPI_SHADER_USER_DATA_ES_24__DATA_MASK                                                                 0xFFFFFFFFL
9913 //SPI_SHADER_USER_DATA_ES_25
9914 #define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT                                                               0x0
9915 #define SPI_SHADER_USER_DATA_ES_25__DATA_MASK                                                                 0xFFFFFFFFL
9916 //SPI_SHADER_USER_DATA_ES_26
9917 #define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT                                                               0x0
9918 #define SPI_SHADER_USER_DATA_ES_26__DATA_MASK                                                                 0xFFFFFFFFL
9919 //SPI_SHADER_USER_DATA_ES_27
9920 #define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT                                                               0x0
9921 #define SPI_SHADER_USER_DATA_ES_27__DATA_MASK                                                                 0xFFFFFFFFL
9922 //SPI_SHADER_USER_DATA_ES_28
9923 #define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT                                                               0x0
9924 #define SPI_SHADER_USER_DATA_ES_28__DATA_MASK                                                                 0xFFFFFFFFL
9925 //SPI_SHADER_USER_DATA_ES_29
9926 #define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT                                                               0x0
9927 #define SPI_SHADER_USER_DATA_ES_29__DATA_MASK                                                                 0xFFFFFFFFL
9928 //SPI_SHADER_USER_DATA_ES_30
9929 #define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT                                                               0x0
9930 #define SPI_SHADER_USER_DATA_ES_30__DATA_MASK                                                                 0xFFFFFFFFL
9931 //SPI_SHADER_USER_DATA_ES_31
9932 #define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT                                                               0x0
9933 #define SPI_SHADER_USER_DATA_ES_31__DATA_MASK                                                                 0xFFFFFFFFL
9934 //SPI_SHADER_PGM_RSRC4_HS
9935 #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT                                                      0x0
9936 #define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK                                                        0x0000007FL
9937 //SPI_SHADER_USER_DATA_ADDR_LO_HS
9938 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT                                                      0x0
9939 #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9940 //SPI_SHADER_USER_DATA_ADDR_HI_HS
9941 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT                                                      0x0
9942 #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK                                                        0xFFFFFFFFL
9943 //SPI_SHADER_PGM_LO_LS
9944 #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT                                                                 0x0
9945 #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9946 //SPI_SHADER_PGM_HI_LS
9947 #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT                                                                 0x0
9948 #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK                                                                   0xFFL
9949 //SPI_SHADER_PGM_RSRC3_HS
9950 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT                                                            0x0
9951 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT                                                    0x6
9952 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT                                                          0xa
9953 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT                                                                 0x10
9954 #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK                                                              0x0000003FL
9955 #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK                                                      0x000003C0L
9956 #define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK                                                            0x00003C00L
9957 #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK                                                                   0xFFFF0000L
9958 //SPI_SHADER_PGM_LO_HS
9959 #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT                                                                 0x0
9960 #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK                                                                   0xFFFFFFFFL
9961 //SPI_SHADER_PGM_HI_HS
9962 #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT                                                                 0x0
9963 #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK                                                                   0xFFL
9964 //SPI_SHADER_PGM_RSRC1_HS
9965 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT                                                                 0x0
9966 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT                                                                 0x6
9967 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT                                                              0xa
9968 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT                                                            0xc
9969 #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT                                                                  0x14
9970 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT                                                            0x15
9971 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT                                                            0x16
9972 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT                                                             0x17
9973 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT                                                             0x1b
9974 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT                                                      0x1c
9975 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT                                                             0x1e
9976 #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK                                                                   0x0000003FL
9977 #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK                                                                   0x000003C0L
9978 #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK                                                                0x00000C00L
9979 #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK                                                              0x000FF000L
9980 #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK                                                                    0x00100000L
9981 #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK                                                              0x00200000L
9982 #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK                                                              0x00400000L
9983 #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK                                                               0x00800000L
9984 #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK                                                               0x08000000L
9985 #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK                                                        0x30000000L
9986 #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK                                                               0x40000000L
9987 //SPI_SHADER_PGM_RSRC2_HS
9988 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT                                                            0x0
9989 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT                                                             0x1
9990 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT                                                          0x6
9991 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT                                                               0x7
9992 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT                                                              0x10
9993 #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT                                                           0x1b
9994 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT                                                         0x1c
9995 #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK                                                              0x00000001L
9996 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK                                                               0x0000003EL
9997 #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK                                                            0x00000040L
9998 #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK                                                                 0x0000FF80L
9999 #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK                                                                0x01FF0000L
10000 #define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK                                                             0x08000000L
10001 #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK                                                           0x10000000L
10002 //SPI_SHADER_USER_DATA_LS_0
10003 #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT                                                                0x0
10004 #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK                                                                  0xFFFFFFFFL
10005 //SPI_SHADER_USER_DATA_LS_1
10006 #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT                                                                0x0
10007 #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK                                                                  0xFFFFFFFFL
10008 //SPI_SHADER_USER_DATA_LS_2
10009 #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT                                                                0x0
10010 #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK                                                                  0xFFFFFFFFL
10011 //SPI_SHADER_USER_DATA_LS_3
10012 #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT                                                                0x0
10013 #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK                                                                  0xFFFFFFFFL
10014 //SPI_SHADER_USER_DATA_LS_4
10015 #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT                                                                0x0
10016 #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK                                                                  0xFFFFFFFFL
10017 //SPI_SHADER_USER_DATA_LS_5
10018 #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT                                                                0x0
10019 #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK                                                                  0xFFFFFFFFL
10020 //SPI_SHADER_USER_DATA_LS_6
10021 #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT                                                                0x0
10022 #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK                                                                  0xFFFFFFFFL
10023 //SPI_SHADER_USER_DATA_LS_7
10024 #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT                                                                0x0
10025 #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK                                                                  0xFFFFFFFFL
10026 //SPI_SHADER_USER_DATA_LS_8
10027 #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT                                                                0x0
10028 #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK                                                                  0xFFFFFFFFL
10029 //SPI_SHADER_USER_DATA_LS_9
10030 #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT                                                                0x0
10031 #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK                                                                  0xFFFFFFFFL
10032 //SPI_SHADER_USER_DATA_LS_10
10033 #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT                                                               0x0
10034 #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK                                                                 0xFFFFFFFFL
10035 //SPI_SHADER_USER_DATA_LS_11
10036 #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT                                                               0x0
10037 #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK                                                                 0xFFFFFFFFL
10038 //SPI_SHADER_USER_DATA_LS_12
10039 #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT                                                               0x0
10040 #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK                                                                 0xFFFFFFFFL
10041 //SPI_SHADER_USER_DATA_LS_13
10042 #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT                                                               0x0
10043 #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK                                                                 0xFFFFFFFFL
10044 //SPI_SHADER_USER_DATA_LS_14
10045 #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT                                                               0x0
10046 #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK                                                                 0xFFFFFFFFL
10047 //SPI_SHADER_USER_DATA_LS_15
10048 #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT                                                               0x0
10049 #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK                                                                 0xFFFFFFFFL
10050 //SPI_SHADER_USER_DATA_LS_16
10051 #define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT                                                               0x0
10052 #define SPI_SHADER_USER_DATA_LS_16__DATA_MASK                                                                 0xFFFFFFFFL
10053 //SPI_SHADER_USER_DATA_LS_17
10054 #define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT                                                               0x0
10055 #define SPI_SHADER_USER_DATA_LS_17__DATA_MASK                                                                 0xFFFFFFFFL
10056 //SPI_SHADER_USER_DATA_LS_18
10057 #define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT                                                               0x0
10058 #define SPI_SHADER_USER_DATA_LS_18__DATA_MASK                                                                 0xFFFFFFFFL
10059 //SPI_SHADER_USER_DATA_LS_19
10060 #define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT                                                               0x0
10061 #define SPI_SHADER_USER_DATA_LS_19__DATA_MASK                                                                 0xFFFFFFFFL
10062 //SPI_SHADER_USER_DATA_LS_20
10063 #define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT                                                               0x0
10064 #define SPI_SHADER_USER_DATA_LS_20__DATA_MASK                                                                 0xFFFFFFFFL
10065 //SPI_SHADER_USER_DATA_LS_21
10066 #define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT                                                               0x0
10067 #define SPI_SHADER_USER_DATA_LS_21__DATA_MASK                                                                 0xFFFFFFFFL
10068 //SPI_SHADER_USER_DATA_LS_22
10069 #define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT                                                               0x0
10070 #define SPI_SHADER_USER_DATA_LS_22__DATA_MASK                                                                 0xFFFFFFFFL
10071 //SPI_SHADER_USER_DATA_LS_23
10072 #define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT                                                               0x0
10073 #define SPI_SHADER_USER_DATA_LS_23__DATA_MASK                                                                 0xFFFFFFFFL
10074 //SPI_SHADER_USER_DATA_LS_24
10075 #define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT                                                               0x0
10076 #define SPI_SHADER_USER_DATA_LS_24__DATA_MASK                                                                 0xFFFFFFFFL
10077 //SPI_SHADER_USER_DATA_LS_25
10078 #define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT                                                               0x0
10079 #define SPI_SHADER_USER_DATA_LS_25__DATA_MASK                                                                 0xFFFFFFFFL
10080 //SPI_SHADER_USER_DATA_LS_26
10081 #define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT                                                               0x0
10082 #define SPI_SHADER_USER_DATA_LS_26__DATA_MASK                                                                 0xFFFFFFFFL
10083 //SPI_SHADER_USER_DATA_LS_27
10084 #define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT                                                               0x0
10085 #define SPI_SHADER_USER_DATA_LS_27__DATA_MASK                                                                 0xFFFFFFFFL
10086 //SPI_SHADER_USER_DATA_LS_28
10087 #define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT                                                               0x0
10088 #define SPI_SHADER_USER_DATA_LS_28__DATA_MASK                                                                 0xFFFFFFFFL
10089 //SPI_SHADER_USER_DATA_LS_29
10090 #define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT                                                               0x0
10091 #define SPI_SHADER_USER_DATA_LS_29__DATA_MASK                                                                 0xFFFFFFFFL
10092 //SPI_SHADER_USER_DATA_LS_30
10093 #define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT                                                               0x0
10094 #define SPI_SHADER_USER_DATA_LS_30__DATA_MASK                                                                 0xFFFFFFFFL
10095 //SPI_SHADER_USER_DATA_LS_31
10096 #define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT                                                               0x0
10097 #define SPI_SHADER_USER_DATA_LS_31__DATA_MASK                                                                 0xFFFFFFFFL
10098 //SPI_SHADER_USER_DATA_COMMON_0
10099 #define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT                                                            0x0
10100 #define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK                                                              0xFFFFFFFFL
10101 //SPI_SHADER_USER_DATA_COMMON_1
10102 #define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT                                                            0x0
10103 #define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK                                                              0xFFFFFFFFL
10104 //SPI_SHADER_USER_DATA_COMMON_2
10105 #define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT                                                            0x0
10106 #define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK                                                              0xFFFFFFFFL
10107 //SPI_SHADER_USER_DATA_COMMON_3
10108 #define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT                                                            0x0
10109 #define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK                                                              0xFFFFFFFFL
10110 //SPI_SHADER_USER_DATA_COMMON_4
10111 #define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT                                                            0x0
10112 #define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK                                                              0xFFFFFFFFL
10113 //SPI_SHADER_USER_DATA_COMMON_5
10114 #define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT                                                            0x0
10115 #define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK                                                              0xFFFFFFFFL
10116 //SPI_SHADER_USER_DATA_COMMON_6
10117 #define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT                                                            0x0
10118 #define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK                                                              0xFFFFFFFFL
10119 //SPI_SHADER_USER_DATA_COMMON_7
10120 #define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT                                                            0x0
10121 #define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK                                                              0xFFFFFFFFL
10122 //SPI_SHADER_USER_DATA_COMMON_8
10123 #define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT                                                            0x0
10124 #define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK                                                              0xFFFFFFFFL
10125 //SPI_SHADER_USER_DATA_COMMON_9
10126 #define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT                                                            0x0
10127 #define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK                                                              0xFFFFFFFFL
10128 //SPI_SHADER_USER_DATA_COMMON_10
10129 #define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT                                                           0x0
10130 #define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK                                                             0xFFFFFFFFL
10131 //SPI_SHADER_USER_DATA_COMMON_11
10132 #define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT                                                           0x0
10133 #define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK                                                             0xFFFFFFFFL
10134 //SPI_SHADER_USER_DATA_COMMON_12
10135 #define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT                                                           0x0
10136 #define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK                                                             0xFFFFFFFFL
10137 //SPI_SHADER_USER_DATA_COMMON_13
10138 #define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT                                                           0x0
10139 #define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK                                                             0xFFFFFFFFL
10140 //SPI_SHADER_USER_DATA_COMMON_14
10141 #define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT                                                           0x0
10142 #define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK                                                             0xFFFFFFFFL
10143 //SPI_SHADER_USER_DATA_COMMON_15
10144 #define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT                                                           0x0
10145 #define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK                                                             0xFFFFFFFFL
10146 //SPI_SHADER_USER_DATA_COMMON_16
10147 #define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT                                                           0x0
10148 #define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK                                                             0xFFFFFFFFL
10149 //SPI_SHADER_USER_DATA_COMMON_17
10150 #define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT                                                           0x0
10151 #define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK                                                             0xFFFFFFFFL
10152 //SPI_SHADER_USER_DATA_COMMON_18
10153 #define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT                                                           0x0
10154 #define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK                                                             0xFFFFFFFFL
10155 //SPI_SHADER_USER_DATA_COMMON_19
10156 #define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT                                                           0x0
10157 #define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK                                                             0xFFFFFFFFL
10158 //SPI_SHADER_USER_DATA_COMMON_20
10159 #define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT                                                           0x0
10160 #define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK                                                             0xFFFFFFFFL
10161 //SPI_SHADER_USER_DATA_COMMON_21
10162 #define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT                                                           0x0
10163 #define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK                                                             0xFFFFFFFFL
10164 //SPI_SHADER_USER_DATA_COMMON_22
10165 #define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT                                                           0x0
10166 #define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK                                                             0xFFFFFFFFL
10167 //SPI_SHADER_USER_DATA_COMMON_23
10168 #define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT                                                           0x0
10169 #define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK                                                             0xFFFFFFFFL
10170 //SPI_SHADER_USER_DATA_COMMON_24
10171 #define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT                                                           0x0
10172 #define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK                                                             0xFFFFFFFFL
10173 //SPI_SHADER_USER_DATA_COMMON_25
10174 #define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT                                                           0x0
10175 #define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK                                                             0xFFFFFFFFL
10176 //SPI_SHADER_USER_DATA_COMMON_26
10177 #define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT                                                           0x0
10178 #define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK                                                             0xFFFFFFFFL
10179 //SPI_SHADER_USER_DATA_COMMON_27
10180 #define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT                                                           0x0
10181 #define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK                                                             0xFFFFFFFFL
10182 //SPI_SHADER_USER_DATA_COMMON_28
10183 #define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT                                                           0x0
10184 #define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK                                                             0xFFFFFFFFL
10185 //SPI_SHADER_USER_DATA_COMMON_29
10186 #define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT                                                           0x0
10187 #define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK                                                             0xFFFFFFFFL
10188 //SPI_SHADER_USER_DATA_COMMON_30
10189 #define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT                                                           0x0
10190 #define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK                                                             0xFFFFFFFFL
10191 //SPI_SHADER_USER_DATA_COMMON_31
10192 #define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT                                                           0x0
10193 #define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK                                                             0xFFFFFFFFL
10194 //COMPUTE_DISPATCH_INITIATOR
10195 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT                                                  0x0
10196 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT                                                      0x1
10197 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT                                                 0x2
10198 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT                                                0x3
10199 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT                                                0x4
10200 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT                                              0x5
10201 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT                                                         0x6
10202 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT                                                  0xa
10203 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT                                                  0xb
10204 #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT                                                           0xc
10205 #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT                                                            0xe
10206 #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK                                                    0x00000001L
10207 #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK                                                        0x00000002L
10208 #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK                                                   0x00000004L
10209 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK                                                  0x00000008L
10210 #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK                                                  0x00000010L
10211 #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK                                                0x00000020L
10212 #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK                                                           0x00000040L
10213 #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK                                                    0x00000400L
10214 #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK                                                    0x00000800L
10215 #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK                                                             0x00001000L
10216 #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK                                                              0x00004000L
10217 //COMPUTE_DIM_X
10218 #define COMPUTE_DIM_X__SIZE__SHIFT                                                                            0x0
10219 #define COMPUTE_DIM_X__SIZE_MASK                                                                              0xFFFFFFFFL
10220 //COMPUTE_DIM_Y
10221 #define COMPUTE_DIM_Y__SIZE__SHIFT                                                                            0x0
10222 #define COMPUTE_DIM_Y__SIZE_MASK                                                                              0xFFFFFFFFL
10223 //COMPUTE_DIM_Z
10224 #define COMPUTE_DIM_Z__SIZE__SHIFT                                                                            0x0
10225 #define COMPUTE_DIM_Z__SIZE_MASK                                                                              0xFFFFFFFFL
10226 //COMPUTE_START_X
10227 #define COMPUTE_START_X__START__SHIFT                                                                         0x0
10228 #define COMPUTE_START_X__START_MASK                                                                           0xFFFFFFFFL
10229 //COMPUTE_START_Y
10230 #define COMPUTE_START_Y__START__SHIFT                                                                         0x0
10231 #define COMPUTE_START_Y__START_MASK                                                                           0xFFFFFFFFL
10232 //COMPUTE_START_Z
10233 #define COMPUTE_START_Z__START__SHIFT                                                                         0x0
10234 #define COMPUTE_START_Z__START_MASK                                                                           0xFFFFFFFFL
10235 //COMPUTE_NUM_THREAD_X
10236 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT                                                          0x0
10237 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
10238 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
10239 #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
10240 //COMPUTE_NUM_THREAD_Y
10241 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT                                                          0x0
10242 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
10243 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
10244 #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
10245 //COMPUTE_NUM_THREAD_Z
10246 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT                                                          0x0
10247 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT                                                       0x10
10248 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK                                                            0x0000FFFFL
10249 #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK                                                         0xFFFF0000L
10250 //COMPUTE_PIPELINESTAT_ENABLE
10251 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT                                               0x0
10252 #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK                                                 0x00000001L
10253 //COMPUTE_PERFCOUNT_ENABLE
10254 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT                                                     0x0
10255 #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK                                                       0x00000001L
10256 //COMPUTE_PGM_LO
10257 #define COMPUTE_PGM_LO__DATA__SHIFT                                                                           0x0
10258 #define COMPUTE_PGM_LO__DATA_MASK                                                                             0xFFFFFFFFL
10259 //COMPUTE_PGM_HI
10260 #define COMPUTE_PGM_HI__DATA__SHIFT                                                                           0x0
10261 #define COMPUTE_PGM_HI__DATA_MASK                                                                             0x000000FFL
10262 //COMPUTE_DISPATCH_PKT_ADDR_LO
10263 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT                                                             0x0
10264 #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK                                                               0xFFFFFFFFL
10265 //COMPUTE_DISPATCH_PKT_ADDR_HI
10266 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT                                                             0x0
10267 #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK                                                               0x000000FFL
10268 //COMPUTE_DISPATCH_SCRATCH_BASE_LO
10269 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT                                                         0x0
10270 #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK                                                           0xFFFFFFFFL
10271 //COMPUTE_DISPATCH_SCRATCH_BASE_HI
10272 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT                                                         0x0
10273 #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK                                                           0x000000FFL
10274 //COMPUTE_PGM_RSRC1
10275 #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT                                                                       0x0
10276 #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT                                                                       0x6
10277 #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT                                                                    0xa
10278 #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT                                                                  0xc
10279 #define COMPUTE_PGM_RSRC1__PRIV__SHIFT                                                                        0x14
10280 #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT                                                                  0x15
10281 #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT                                                                  0x16
10282 #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT                                                                   0x17
10283 #define COMPUTE_PGM_RSRC1__BULKY__SHIFT                                                                       0x18
10284 #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT                                                                   0x19
10285 #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT                                                                   0x1a
10286 #define COMPUTE_PGM_RSRC1__VGPRS_MASK                                                                         0x0000003FL
10287 #define COMPUTE_PGM_RSRC1__SGPRS_MASK                                                                         0x000003C0L
10288 #define COMPUTE_PGM_RSRC1__PRIORITY_MASK                                                                      0x00000C00L
10289 #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK                                                                    0x000FF000L
10290 #define COMPUTE_PGM_RSRC1__PRIV_MASK                                                                          0x00100000L
10291 #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK                                                                    0x00200000L
10292 #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK                                                                    0x00400000L
10293 #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK                                                                     0x00800000L
10294 #define COMPUTE_PGM_RSRC1__BULKY_MASK                                                                         0x01000000L
10295 #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK                                                                     0x02000000L
10296 #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK                                                                     0x04000000L
10297 //COMPUTE_PGM_RSRC2
10298 #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT                                                                  0x0
10299 #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT                                                                   0x1
10300 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT                                                                0x6
10301 #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT                                                                   0x7
10302 #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT                                                                   0x8
10303 #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT                                                                   0x9
10304 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT                                                                  0xa
10305 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT                                                              0xb
10306 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT                                                                 0xd
10307 #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT                                                                    0xf
10308 #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT                                                                     0x18
10309 #define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT                                                                 0x1f
10310 #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK                                                                    0x00000001L
10311 #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK                                                                     0x0000003EL
10312 #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK                                                                  0x00000040L
10313 #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK                                                                     0x00000080L
10314 #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK                                                                     0x00000100L
10315 #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK                                                                     0x00000200L
10316 #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK                                                                    0x00000400L
10317 #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK                                                                0x00001800L
10318 #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK                                                                   0x00006000L
10319 #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK                                                                      0x00FF8000L
10320 #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK                                                                       0x7F000000L
10321 #define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK                                                                   0x80000000L
10322 //COMPUTE_VMID
10323 #define COMPUTE_VMID__DATA__SHIFT                                                                             0x0
10324 #define COMPUTE_VMID__DATA_MASK                                                                               0x0000000FL
10325 //COMPUTE_RESOURCE_LIMITS
10326 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT                                                          0x0
10327 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT                                                             0xc
10328 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT                                                        0x10
10329 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT                                                        0x16
10330 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT                                                       0x17
10331 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT                                                        0x18
10332 #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT                                                          0x1b
10333 #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK                                                            0x000003FFL
10334 #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK                                                               0x0000F000L
10335 #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK                                                          0x003F0000L
10336 #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK                                                          0x00400000L
10337 #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK                                                         0x00800000L
10338 #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK                                                          0x07000000L
10339 #define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK                                                            0x78000000L
10340 //COMPUTE_STATIC_THREAD_MGMT_SE0
10341 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT                                                      0x0
10342 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT                                                      0x10
10343 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK                                                        0x0000FFFFL
10344 #define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK                                                        0xFFFF0000L
10345 //COMPUTE_STATIC_THREAD_MGMT_SE1
10346 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT                                                      0x0
10347 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT                                                      0x10
10348 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK                                                        0x0000FFFFL
10349 #define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK                                                        0xFFFF0000L
10350 //COMPUTE_TMPRING_SIZE
10351 #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT                                                                    0x0
10352 #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT                                                                 0xc
10353 #define COMPUTE_TMPRING_SIZE__WAVES_MASK                                                                      0x00000FFFL
10354 #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK                                                                   0x01FFF000L
10355 //COMPUTE_STATIC_THREAD_MGMT_SE2
10356 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT                                                      0x0
10357 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT                                                      0x10
10358 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK                                                        0x0000FFFFL
10359 #define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK                                                        0xFFFF0000L
10360 //COMPUTE_STATIC_THREAD_MGMT_SE3
10361 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT                                                      0x0
10362 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT                                                      0x10
10363 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK                                                        0x0000FFFFL
10364 #define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK                                                        0xFFFF0000L
10365 //COMPUTE_RESTART_X
10366 #define COMPUTE_RESTART_X__RESTART__SHIFT                                                                     0x0
10367 #define COMPUTE_RESTART_X__RESTART_MASK                                                                       0xFFFFFFFFL
10368 //COMPUTE_RESTART_Y
10369 #define COMPUTE_RESTART_Y__RESTART__SHIFT                                                                     0x0
10370 #define COMPUTE_RESTART_Y__RESTART_MASK                                                                       0xFFFFFFFFL
10371 //COMPUTE_RESTART_Z
10372 #define COMPUTE_RESTART_Z__RESTART__SHIFT                                                                     0x0
10373 #define COMPUTE_RESTART_Z__RESTART_MASK                                                                       0xFFFFFFFFL
10374 //COMPUTE_THREAD_TRACE_ENABLE
10375 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT                                               0x0
10376 #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK                                                 0x00000001L
10377 //COMPUTE_MISC_RESERVED
10378 #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT                                                               0x0
10379 #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT                                                               0x2
10380 #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT                                                               0x3
10381 #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT                                                               0x4
10382 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT                                                            0x5
10383 #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK                                                                 0x00000003L
10384 #define COMPUTE_MISC_RESERVED__RESERVED2_MASK                                                                 0x00000004L
10385 #define COMPUTE_MISC_RESERVED__RESERVED3_MASK                                                                 0x00000008L
10386 #define COMPUTE_MISC_RESERVED__RESERVED4_MASK                                                                 0x00000010L
10387 #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK                                                              0x0001FFE0L
10388 //COMPUTE_DISPATCH_ID
10389 #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT                                                               0x0
10390 #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK                                                                 0xFFFFFFFFL
10391 //COMPUTE_THREADGROUP_ID
10392 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT                                                         0x0
10393 #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK                                                           0xFFFFFFFFL
10394 //COMPUTE_RELAUNCH
10395 #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT                                                                      0x0
10396 #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT                                                                     0x1e
10397 #define COMPUTE_RELAUNCH__IS_STATE__SHIFT                                                                     0x1f
10398 #define COMPUTE_RELAUNCH__PAYLOAD_MASK                                                                        0x3FFFFFFFL
10399 #define COMPUTE_RELAUNCH__IS_EVENT_MASK                                                                       0x40000000L
10400 #define COMPUTE_RELAUNCH__IS_STATE_MASK                                                                       0x80000000L
10401 //COMPUTE_WAVE_RESTORE_ADDR_LO
10402 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT                                                             0x0
10403 #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK                                                               0xFFFFFFFFL
10404 //COMPUTE_WAVE_RESTORE_ADDR_HI
10405 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT                                                             0x0
10406 #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK                                                               0xFFFFL
10407 //COMPUTE_USER_DATA_0
10408 #define COMPUTE_USER_DATA_0__DATA__SHIFT                                                                      0x0
10409 #define COMPUTE_USER_DATA_0__DATA_MASK                                                                        0xFFFFFFFFL
10410 //COMPUTE_USER_DATA_1
10411 #define COMPUTE_USER_DATA_1__DATA__SHIFT                                                                      0x0
10412 #define COMPUTE_USER_DATA_1__DATA_MASK                                                                        0xFFFFFFFFL
10413 //COMPUTE_USER_DATA_2
10414 #define COMPUTE_USER_DATA_2__DATA__SHIFT                                                                      0x0
10415 #define COMPUTE_USER_DATA_2__DATA_MASK                                                                        0xFFFFFFFFL
10416 //COMPUTE_USER_DATA_3
10417 #define COMPUTE_USER_DATA_3__DATA__SHIFT                                                                      0x0
10418 #define COMPUTE_USER_DATA_3__DATA_MASK                                                                        0xFFFFFFFFL
10419 //COMPUTE_USER_DATA_4
10420 #define COMPUTE_USER_DATA_4__DATA__SHIFT                                                                      0x0
10421 #define COMPUTE_USER_DATA_4__DATA_MASK                                                                        0xFFFFFFFFL
10422 //COMPUTE_USER_DATA_5
10423 #define COMPUTE_USER_DATA_5__DATA__SHIFT                                                                      0x0
10424 #define COMPUTE_USER_DATA_5__DATA_MASK                                                                        0xFFFFFFFFL
10425 //COMPUTE_USER_DATA_6
10426 #define COMPUTE_USER_DATA_6__DATA__SHIFT                                                                      0x0
10427 #define COMPUTE_USER_DATA_6__DATA_MASK                                                                        0xFFFFFFFFL
10428 //COMPUTE_USER_DATA_7
10429 #define COMPUTE_USER_DATA_7__DATA__SHIFT                                                                      0x0
10430 #define COMPUTE_USER_DATA_7__DATA_MASK                                                                        0xFFFFFFFFL
10431 //COMPUTE_USER_DATA_8
10432 #define COMPUTE_USER_DATA_8__DATA__SHIFT                                                                      0x0
10433 #define COMPUTE_USER_DATA_8__DATA_MASK                                                                        0xFFFFFFFFL
10434 //COMPUTE_USER_DATA_9
10435 #define COMPUTE_USER_DATA_9__DATA__SHIFT                                                                      0x0
10436 #define COMPUTE_USER_DATA_9__DATA_MASK                                                                        0xFFFFFFFFL
10437 //COMPUTE_USER_DATA_10
10438 #define COMPUTE_USER_DATA_10__DATA__SHIFT                                                                     0x0
10439 #define COMPUTE_USER_DATA_10__DATA_MASK                                                                       0xFFFFFFFFL
10440 //COMPUTE_USER_DATA_11
10441 #define COMPUTE_USER_DATA_11__DATA__SHIFT                                                                     0x0
10442 #define COMPUTE_USER_DATA_11__DATA_MASK                                                                       0xFFFFFFFFL
10443 //COMPUTE_USER_DATA_12
10444 #define COMPUTE_USER_DATA_12__DATA__SHIFT                                                                     0x0
10445 #define COMPUTE_USER_DATA_12__DATA_MASK                                                                       0xFFFFFFFFL
10446 //COMPUTE_USER_DATA_13
10447 #define COMPUTE_USER_DATA_13__DATA__SHIFT                                                                     0x0
10448 #define COMPUTE_USER_DATA_13__DATA_MASK                                                                       0xFFFFFFFFL
10449 //COMPUTE_USER_DATA_14
10450 #define COMPUTE_USER_DATA_14__DATA__SHIFT                                                                     0x0
10451 #define COMPUTE_USER_DATA_14__DATA_MASK                                                                       0xFFFFFFFFL
10452 //COMPUTE_USER_DATA_15
10453 #define COMPUTE_USER_DATA_15__DATA__SHIFT                                                                     0x0
10454 #define COMPUTE_USER_DATA_15__DATA_MASK                                                                       0xFFFFFFFFL
10455 //COMPUTE_NOWHERE
10456 #define COMPUTE_NOWHERE__DATA__SHIFT                                                                          0x0
10457 #define COMPUTE_NOWHERE__DATA_MASK                                                                            0xFFFFFFFFL
10458 
10459 
10460 // addressBlock: gc_cppdec
10461 //CP_DFY_CNTL
10462 #define CP_DFY_CNTL__POLICY__SHIFT                                                                            0x0
10463 #define CP_DFY_CNTL__MTYPE__SHIFT                                                                             0x2
10464 #define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT                                                                       0x1a
10465 #define CP_DFY_CNTL__LFSR_RESET__SHIFT                                                                        0x1c
10466 #define CP_DFY_CNTL__MODE__SHIFT                                                                              0x1d
10467 #define CP_DFY_CNTL__ENABLE__SHIFT                                                                            0x1f
10468 #define CP_DFY_CNTL__POLICY_MASK                                                                              0x00000001L
10469 #define CP_DFY_CNTL__MTYPE_MASK                                                                               0x0000000CL
10470 #define CP_DFY_CNTL__TPI_SDP_SEL_MASK                                                                         0x04000000L
10471 #define CP_DFY_CNTL__LFSR_RESET_MASK                                                                          0x10000000L
10472 #define CP_DFY_CNTL__MODE_MASK                                                                                0x60000000L
10473 #define CP_DFY_CNTL__ENABLE_MASK                                                                              0x80000000L
10474 //CP_DFY_STAT
10475 #define CP_DFY_STAT__BURST_COUNT__SHIFT                                                                       0x0
10476 #define CP_DFY_STAT__TAGS_PENDING__SHIFT                                                                      0x10
10477 #define CP_DFY_STAT__BUSY__SHIFT                                                                              0x1f
10478 #define CP_DFY_STAT__BURST_COUNT_MASK                                                                         0x0000FFFFL
10479 #define CP_DFY_STAT__TAGS_PENDING_MASK                                                                        0x07FF0000L
10480 #define CP_DFY_STAT__BUSY_MASK                                                                                0x80000000L
10481 //CP_DFY_ADDR_HI
10482 #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT                                                                        0x0
10483 #define CP_DFY_ADDR_HI__ADDR_HI_MASK                                                                          0xFFFFFFFFL
10484 //CP_DFY_ADDR_LO
10485 #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT                                                                        0x5
10486 #define CP_DFY_ADDR_LO__ADDR_LO_MASK                                                                          0xFFFFFFE0L
10487 //CP_DFY_DATA_0
10488 #define CP_DFY_DATA_0__DATA__SHIFT                                                                            0x0
10489 #define CP_DFY_DATA_0__DATA_MASK                                                                              0xFFFFFFFFL
10490 //CP_DFY_DATA_1
10491 #define CP_DFY_DATA_1__DATA__SHIFT                                                                            0x0
10492 #define CP_DFY_DATA_1__DATA_MASK                                                                              0xFFFFFFFFL
10493 //CP_DFY_DATA_2
10494 #define CP_DFY_DATA_2__DATA__SHIFT                                                                            0x0
10495 #define CP_DFY_DATA_2__DATA_MASK                                                                              0xFFFFFFFFL
10496 //CP_DFY_DATA_3
10497 #define CP_DFY_DATA_3__DATA__SHIFT                                                                            0x0
10498 #define CP_DFY_DATA_3__DATA_MASK                                                                              0xFFFFFFFFL
10499 //CP_DFY_DATA_4
10500 #define CP_DFY_DATA_4__DATA__SHIFT                                                                            0x0
10501 #define CP_DFY_DATA_4__DATA_MASK                                                                              0xFFFFFFFFL
10502 //CP_DFY_DATA_5
10503 #define CP_DFY_DATA_5__DATA__SHIFT                                                                            0x0
10504 #define CP_DFY_DATA_5__DATA_MASK                                                                              0xFFFFFFFFL
10505 //CP_DFY_DATA_6
10506 #define CP_DFY_DATA_6__DATA__SHIFT                                                                            0x0
10507 #define CP_DFY_DATA_6__DATA_MASK                                                                              0xFFFFFFFFL
10508 //CP_DFY_DATA_7
10509 #define CP_DFY_DATA_7__DATA__SHIFT                                                                            0x0
10510 #define CP_DFY_DATA_7__DATA_MASK                                                                              0xFFFFFFFFL
10511 //CP_DFY_DATA_8
10512 #define CP_DFY_DATA_8__DATA__SHIFT                                                                            0x0
10513 #define CP_DFY_DATA_8__DATA_MASK                                                                              0xFFFFFFFFL
10514 //CP_DFY_DATA_9
10515 #define CP_DFY_DATA_9__DATA__SHIFT                                                                            0x0
10516 #define CP_DFY_DATA_9__DATA_MASK                                                                              0xFFFFFFFFL
10517 //CP_DFY_DATA_10
10518 #define CP_DFY_DATA_10__DATA__SHIFT                                                                           0x0
10519 #define CP_DFY_DATA_10__DATA_MASK                                                                             0xFFFFFFFFL
10520 //CP_DFY_DATA_11
10521 #define CP_DFY_DATA_11__DATA__SHIFT                                                                           0x0
10522 #define CP_DFY_DATA_11__DATA_MASK                                                                             0xFFFFFFFFL
10523 //CP_DFY_DATA_12
10524 #define CP_DFY_DATA_12__DATA__SHIFT                                                                           0x0
10525 #define CP_DFY_DATA_12__DATA_MASK                                                                             0xFFFFFFFFL
10526 //CP_DFY_DATA_13
10527 #define CP_DFY_DATA_13__DATA__SHIFT                                                                           0x0
10528 #define CP_DFY_DATA_13__DATA_MASK                                                                             0xFFFFFFFFL
10529 //CP_DFY_DATA_14
10530 #define CP_DFY_DATA_14__DATA__SHIFT                                                                           0x0
10531 #define CP_DFY_DATA_14__DATA_MASK                                                                             0xFFFFFFFFL
10532 //CP_DFY_DATA_15
10533 #define CP_DFY_DATA_15__DATA__SHIFT                                                                           0x0
10534 #define CP_DFY_DATA_15__DATA_MASK                                                                             0xFFFFFFFFL
10535 //CP_DFY_CMD
10536 #define CP_DFY_CMD__OFFSET__SHIFT                                                                             0x0
10537 #define CP_DFY_CMD__SIZE__SHIFT                                                                               0x10
10538 #define CP_DFY_CMD__OFFSET_MASK                                                                               0x000001FFL
10539 #define CP_DFY_CMD__SIZE_MASK                                                                                 0xFFFF0000L
10540 //CP_EOPQ_WAIT_TIME
10541 #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT                                                                   0x0
10542 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT                                                                 0xa
10543 #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK                                                                     0x000003FFL
10544 #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK                                                                   0x0003FC00L
10545 //CP_CPC_MGCG_SYNC_CNTL
10546 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT                                                         0x0
10547 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT                                                           0x8
10548 #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK                                                           0x000000FFL
10549 #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK                                                             0x0000FF00L
10550 //CPC_INT_INFO
10551 #define CPC_INT_INFO__ADDR_HI__SHIFT                                                                          0x0
10552 #define CPC_INT_INFO__TYPE__SHIFT                                                                             0x10
10553 #define CPC_INT_INFO__VMID__SHIFT                                                                             0x14
10554 #define CPC_INT_INFO__QUEUE_ID__SHIFT                                                                         0x1c
10555 #define CPC_INT_INFO__ADDR_HI_MASK                                                                            0x0000FFFFL
10556 #define CPC_INT_INFO__TYPE_MASK                                                                               0x00010000L
10557 #define CPC_INT_INFO__VMID_MASK                                                                               0x00F00000L
10558 #define CPC_INT_INFO__QUEUE_ID_MASK                                                                           0x70000000L
10559 //CP_VIRT_STATUS
10560 #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT                                                                    0x0
10561 #define CP_VIRT_STATUS__VIRT_STATUS_MASK                                                                      0xFFFFFFFFL
10562 //CPC_INT_ADDR
10563 #define CPC_INT_ADDR__ADDR__SHIFT                                                                             0x0
10564 #define CPC_INT_ADDR__ADDR_MASK                                                                               0xFFFFFFFFL
10565 //CPC_INT_PASID
10566 #define CPC_INT_PASID__PASID__SHIFT                                                                           0x0
10567 #define CPC_INT_PASID__PASID_MASK                                                                             0x0000FFFFL
10568 //CP_GFX_ERROR
10569 #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
10570 #define CP_GFX_ERROR__SUA_ERROR__SHIFT                                                                        0x4
10571 #define CP_GFX_ERROR__RSVD1_ERROR__SHIFT                                                                      0x5
10572 #define CP_GFX_ERROR__RSVD2_ERROR__SHIFT                                                                      0x6
10573 #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0x7
10574 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT                                                              0x8
10575 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT                                                               0x9
10576 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT                                                              0xa
10577 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT                                                              0xb
10578 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT                                                           0xc
10579 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT                                                           0xd
10580 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT                                                               0xe
10581 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT                                                               0xf
10582 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT                                                               0x10
10583 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT                                                           0x11
10584 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0x12
10585 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x13
10586 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT                                                               0x14
10587 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT                                                                0x15
10588 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT                                                                0x16
10589 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT                                                              0x17
10590 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT                                                            0x18
10591 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT                                                           0x19
10592 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1a
10593 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1b
10594 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1c
10595 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1d
10596 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT                                                           0x1e
10597 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT                                                              0x1f
10598 #define CP_GFX_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
10599 #define CP_GFX_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
10600 #define CP_GFX_ERROR__RSVD1_ERROR_MASK                                                                        0x00000020L
10601 #define CP_GFX_ERROR__RSVD2_ERROR_MASK                                                                        0x00000040L
10602 #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00000080L
10603 #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK                                                                0x00000100L
10604 #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK                                                                 0x00000200L
10605 #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK                                                                0x00000400L
10606 #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK                                                                0x00000800L
10607 #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK                                                             0x00001000L
10608 #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK                                                             0x00002000L
10609 #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK                                                                 0x00004000L
10610 #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK                                                                 0x00008000L
10611 #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK                                                                 0x00010000L
10612 #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK                                                             0x00020000L
10613 #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00040000L
10614 #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00080000L
10615 #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK                                                                 0x00100000L
10616 #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK                                                                  0x00200000L
10617 #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK                                                                  0x00400000L
10618 #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK                                                                0x00800000L
10619 #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK                                                              0x01000000L
10620 #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK                                                             0x02000000L
10621 #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK                                                             0x04000000L
10622 #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK                                                             0x08000000L
10623 #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK                                                             0x10000000L
10624 #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK                                                             0x20000000L
10625 #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK                                                             0x40000000L
10626 #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK                                                                0x80000000L
10627 //CPG_UTCL1_CNTL
10628 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
10629 #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
10630 #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
10631 #define CPG_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
10632 #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
10633 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
10634 #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
10635 #define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                            0x1d
10636 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
10637 #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
10638 #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
10639 #define CPG_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
10640 #define CPG_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
10641 #define CPG_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
10642 #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
10643 #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
10644 #define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                              0x20000000L
10645 #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
10646 //CPC_UTCL1_CNTL
10647 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
10648 #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
10649 #define CPC_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
10650 #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
10651 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
10652 #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
10653 #define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                            0x1d
10654 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
10655 #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
10656 #define CPC_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
10657 #define CPC_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
10658 #define CPC_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
10659 #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
10660 #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
10661 #define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                              0x20000000L
10662 #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
10663 //CPF_UTCL1_CNTL
10664 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                           0x0
10665 #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT                                                                0x17
10666 #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT                                                                      0x18
10667 #define CPF_UTCL1_CNTL__BYPASS__SHIFT                                                                         0x19
10668 #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT                                                                     0x1a
10669 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                                0x1b
10670 #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                    0x1c
10671 #define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                            0x1d
10672 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x1e
10673 #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT                                                                   0x1f
10674 #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                             0x000FFFFFL
10675 #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK                                                                  0x00800000L
10676 #define CPF_UTCL1_CNTL__DROP_MODE_MASK                                                                        0x01000000L
10677 #define CPF_UTCL1_CNTL__BYPASS_MASK                                                                           0x02000000L
10678 #define CPF_UTCL1_CNTL__INVALIDATE_MASK                                                                       0x04000000L
10679 #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                                  0x08000000L
10680 #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                      0x10000000L
10681 #define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                              0x20000000L
10682 #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x40000000L
10683 #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK                                                                     0x80000000L
10684 //CP_AQL_SMM_STATUS
10685 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT                                                               0x0
10686 #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK                                                                 0xFFFFFFFFL
10687 //CP_RB0_BASE
10688 #define CP_RB0_BASE__RB_BASE__SHIFT                                                                           0x0
10689 #define CP_RB0_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
10690 //CP_RB_BASE
10691 #define CP_RB_BASE__RB_BASE__SHIFT                                                                            0x0
10692 #define CP_RB_BASE__RB_BASE_MASK                                                                              0xFFFFFFFFL
10693 //CP_RB0_CNTL
10694 #define CP_RB0_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
10695 #define CP_RB0_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
10696 #define CP_RB0_CNTL__BUF_SWAP__SHIFT                                                                          0x11
10697 #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
10698 #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
10699 #define CP_RB0_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
10700 #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
10701 #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
10702 #define CP_RB0_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
10703 #define CP_RB0_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
10704 #define CP_RB0_CNTL__BUF_SWAP_MASK                                                                            0x00060000L
10705 #define CP_RB0_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
10706 #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
10707 #define CP_RB0_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
10708 #define CP_RB0_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
10709 #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
10710 //CP_RB_CNTL
10711 #define CP_RB_CNTL__RB_BUFSZ__SHIFT                                                                           0x0
10712 #define CP_RB_CNTL__RB_BLKSZ__SHIFT                                                                           0x8
10713 #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT                                                                        0x14
10714 #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                     0x16
10715 #define CP_RB_CNTL__CACHE_POLICY__SHIFT                                                                       0x18
10716 #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                       0x1b
10717 #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                     0x1f
10718 #define CP_RB_CNTL__RB_BUFSZ_MASK                                                                             0x0000003FL
10719 #define CP_RB_CNTL__RB_BLKSZ_MASK                                                                             0x00003F00L
10720 #define CP_RB_CNTL__MIN_AVAILSZ_MASK                                                                          0x00300000L
10721 #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK                                                                       0x00C00000L
10722 #define CP_RB_CNTL__CACHE_POLICY_MASK                                                                         0x01000000L
10723 #define CP_RB_CNTL__RB_NO_UPDATE_MASK                                                                         0x08000000L
10724 #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK                                                                       0x80000000L
10725 //CP_RB_RPTR_WR
10726 #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT                                                                      0x0
10727 #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK                                                                        0x000FFFFFL
10728 //CP_RB0_RPTR_ADDR
10729 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
10730 #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
10731 //CP_RB_RPTR_ADDR
10732 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                  0x2
10733 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                    0xFFFFFFFCL
10734 //CP_RB0_RPTR_ADDR_HI
10735 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
10736 #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
10737 //CP_RB_RPTR_ADDR_HI
10738 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                            0x0
10739 #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                              0x0000FFFFL
10740 //CP_RB0_BUFSZ_MASK
10741 #define CP_RB0_BUFSZ_MASK__DATA__SHIFT                                                                        0x0
10742 #define CP_RB0_BUFSZ_MASK__DATA_MASK                                                                          0x000FFFFFL
10743 //CP_RB_BUFSZ_MASK
10744 #define CP_RB_BUFSZ_MASK__DATA__SHIFT                                                                         0x0
10745 #define CP_RB_BUFSZ_MASK__DATA_MASK                                                                           0x000FFFFFL
10746 //CP_RB_WPTR_POLL_ADDR_LO
10747 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT                                                  0x2
10748 #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK                                                    0xFFFFFFFCL
10749 //CP_RB_WPTR_POLL_ADDR_HI
10750 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT                                                  0x0
10751 #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK                                                    0x0000FFFFL
10752 //GC_PRIV_MODE
10753 //CP_INT_CNTL
10754 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                      0xb
10755 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                           0xe
10756 #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                    0x10
10757 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                       0x11
10758 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT                                                               0x12
10759 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT                                                              0x13
10760 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT                                                             0x14
10761 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT                                                               0x15
10762 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT                                                             0x16
10763 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                               0x17
10764 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                           0x18
10765 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                             0x1a
10766 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                     0x1b
10767 #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                               0x1d
10768 #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                               0x1e
10769 #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                               0x1f
10770 #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                        0x00000800L
10771 #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                             0x00004000L
10772 #define CP_INT_CNTL__GPF_INT_ENABLE_MASK                                                                      0x00010000L
10773 #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                         0x00020000L
10774 #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK                                                                 0x00040000L
10775 #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK                                                                0x00080000L
10776 #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK                                                               0x00100000L
10777 #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK                                                                 0x00200000L
10778 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK                                                               0x00400000L
10779 #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                 0x00800000L
10780 #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                             0x01000000L
10781 #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                               0x04000000L
10782 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                       0x08000000L
10783 #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                 0x20000000L
10784 #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                 0x40000000L
10785 #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                 0x80000000L
10786 //CP_INT_STATUS
10787 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                      0xb
10788 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT                                                           0xe
10789 #define CP_INT_STATUS__GPF_INT_STAT__SHIFT                                                                    0x10
10790 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                       0x11
10791 #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT                                                               0x12
10792 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT                                                              0x13
10793 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT                                                             0x14
10794 #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT                                                               0x15
10795 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT                                                             0x16
10796 #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT                                                               0x17
10797 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT                                                           0x18
10798 #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT                                                             0x1a
10799 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                                     0x1b
10800 #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT                                                               0x1d
10801 #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT                                                               0x1e
10802 #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT                                                               0x1f
10803 #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                        0x00000800L
10804 #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK                                                             0x00004000L
10805 #define CP_INT_STATUS__GPF_INT_STAT_MASK                                                                      0x00010000L
10806 #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                         0x00020000L
10807 #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK                                                                 0x00040000L
10808 #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK                                                                0x00080000L
10809 #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK                                                               0x00100000L
10810 #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK                                                                 0x00200000L
10811 #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK                                                               0x00400000L
10812 #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK                                                                 0x00800000L
10813 #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK                                                             0x01000000L
10814 #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK                                                               0x04000000L
10815 #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK                                                       0x08000000L
10816 #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK                                                                 0x20000000L
10817 #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK                                                                 0x40000000L
10818 #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK                                                                 0x80000000L
10819 //CP_DEVICE_ID
10820 #define CP_DEVICE_ID__DEVICE_ID__SHIFT                                                                        0x0
10821 #define CP_DEVICE_ID__DEVICE_ID_MASK                                                                          0x000000FFL
10822 //CP_ME0_PIPE_PRIORITY_CNTS
10823 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
10824 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
10825 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
10826 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
10827 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
10828 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
10829 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
10830 #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
10831 //CP_RING_PRIORITY_CNTS
10832 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                           0x0
10833 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                          0x8
10834 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                          0x10
10835 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                           0x18
10836 #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                             0x000000FFL
10837 #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                            0x0000FF00L
10838 #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                            0x00FF0000L
10839 #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                             0xFF000000L
10840 //CP_ME0_PIPE0_PRIORITY
10841 #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
10842 #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
10843 //CP_RING0_PRIORITY
10844 #define CP_RING0_PRIORITY__PRIORITY__SHIFT                                                                    0x0
10845 #define CP_RING0_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
10846 //CP_ME0_PIPE1_PRIORITY
10847 #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
10848 #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
10849 //CP_RING1_PRIORITY
10850 #define CP_RING1_PRIORITY__PRIORITY__SHIFT                                                                    0x0
10851 #define CP_RING1_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
10852 //CP_ME0_PIPE2_PRIORITY
10853 #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
10854 #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
10855 //CP_RING2_PRIORITY
10856 #define CP_RING2_PRIORITY__PRIORITY__SHIFT                                                                    0x0
10857 #define CP_RING2_PRIORITY__PRIORITY_MASK                                                                      0x00000003L
10858 //CP_FATAL_ERROR
10859 #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT                                                                0x0
10860 #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT                                                                0x1
10861 #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT                                                                  0x2
10862 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT                                                            0x3
10863 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT                                                         0x4
10864 #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK                                                                  0x00000001L
10865 #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK                                                                  0x00000002L
10866 #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK                                                                    0x00000004L
10867 #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK                                                              0x00000008L
10868 #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK                                                           0x00000010L
10869 //CP_RB_VMID
10870 #define CP_RB_VMID__RB0_VMID__SHIFT                                                                           0x0
10871 #define CP_RB_VMID__RB1_VMID__SHIFT                                                                           0x8
10872 #define CP_RB_VMID__RB2_VMID__SHIFT                                                                           0x10
10873 #define CP_RB_VMID__RB0_VMID_MASK                                                                             0x0000000FL
10874 #define CP_RB_VMID__RB1_VMID_MASK                                                                             0x00000F00L
10875 #define CP_RB_VMID__RB2_VMID_MASK                                                                             0x000F0000L
10876 //CP_ME0_PIPE0_VMID
10877 #define CP_ME0_PIPE0_VMID__VMID__SHIFT                                                                        0x0
10878 #define CP_ME0_PIPE0_VMID__VMID_MASK                                                                          0x0000000FL
10879 //CP_ME0_PIPE1_VMID
10880 #define CP_ME0_PIPE1_VMID__VMID__SHIFT                                                                        0x0
10881 #define CP_ME0_PIPE1_VMID__VMID_MASK                                                                          0x0000000FL
10882 //CP_RB0_WPTR
10883 #define CP_RB0_WPTR__RB_WPTR__SHIFT                                                                           0x0
10884 #define CP_RB0_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
10885 //CP_RB_WPTR
10886 #define CP_RB_WPTR__RB_WPTR__SHIFT                                                                            0x0
10887 #define CP_RB_WPTR__RB_WPTR_MASK                                                                              0xFFFFFFFFL
10888 //CP_RB0_WPTR_HI
10889 #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
10890 #define CP_RB0_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
10891 //CP_RB_WPTR_HI
10892 #define CP_RB_WPTR_HI__RB_WPTR__SHIFT                                                                         0x0
10893 #define CP_RB_WPTR_HI__RB_WPTR_MASK                                                                           0xFFFFFFFFL
10894 //CP_RB1_WPTR
10895 #define CP_RB1_WPTR__RB_WPTR__SHIFT                                                                           0x0
10896 #define CP_RB1_WPTR__RB_WPTR_MASK                                                                             0xFFFFFFFFL
10897 //CP_RB1_WPTR_HI
10898 #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT                                                                        0x0
10899 #define CP_RB1_WPTR_HI__RB_WPTR_MASK                                                                          0xFFFFFFFFL
10900 //CP_RB2_WPTR
10901 #define CP_RB2_WPTR__RB_WPTR__SHIFT                                                                           0x0
10902 #define CP_RB2_WPTR__RB_WPTR_MASK                                                                             0x000FFFFFL
10903 //CP_RB_DOORBELL_CONTROL
10904 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                      0x1
10905 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                        0x2
10906 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                            0x1e
10907 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                           0x1f
10908 #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                        0x00000002L
10909 #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                          0x0FFFFFFCL
10910 #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                              0x40000000L
10911 #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                             0x80000000L
10912 //CP_RB_DOORBELL_RANGE_LOWER
10913 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                               0x2
10914 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                 0x0FFFFFFCL
10915 //CP_RB_DOORBELL_RANGE_UPPER
10916 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                               0x2
10917 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                 0x0FFFFFFCL
10918 //CP_MEC_DOORBELL_RANGE_LOWER
10919 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT                                              0x2
10920 #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK                                                0x0FFFFFFCL
10921 //CP_MEC_DOORBELL_RANGE_UPPER
10922 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT                                              0x2
10923 #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK                                                0x0FFFFFFCL
10924 //CPG_UTCL1_ERROR
10925 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
10926 #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
10927 //CPC_UTCL1_ERROR
10928 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT                                                           0x0
10929 #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK                                                             0x00000001L
10930 //CP_RB1_BASE
10931 #define CP_RB1_BASE__RB_BASE__SHIFT                                                                           0x0
10932 #define CP_RB1_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
10933 //CP_RB1_CNTL
10934 #define CP_RB1_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
10935 #define CP_RB1_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
10936 #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
10937 #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
10938 #define CP_RB1_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
10939 #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
10940 #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
10941 #define CP_RB1_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
10942 #define CP_RB1_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
10943 #define CP_RB1_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
10944 #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
10945 #define CP_RB1_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
10946 #define CP_RB1_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
10947 #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
10948 //CP_RB1_RPTR_ADDR
10949 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
10950 #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
10951 //CP_RB1_RPTR_ADDR_HI
10952 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
10953 #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
10954 //CP_RB2_BASE
10955 #define CP_RB2_BASE__RB_BASE__SHIFT                                                                           0x0
10956 #define CP_RB2_BASE__RB_BASE_MASK                                                                             0xFFFFFFFFL
10957 //CP_RB2_CNTL
10958 #define CP_RB2_CNTL__RB_BUFSZ__SHIFT                                                                          0x0
10959 #define CP_RB2_CNTL__RB_BLKSZ__SHIFT                                                                          0x8
10960 #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x14
10961 #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT                                                                    0x16
10962 #define CP_RB2_CNTL__CACHE_POLICY__SHIFT                                                                      0x18
10963 #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT                                                                      0x1b
10964 #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT                                                                    0x1f
10965 #define CP_RB2_CNTL__RB_BUFSZ_MASK                                                                            0x0000003FL
10966 #define CP_RB2_CNTL__RB_BLKSZ_MASK                                                                            0x00003F00L
10967 #define CP_RB2_CNTL__MIN_AVAILSZ_MASK                                                                         0x00300000L
10968 #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK                                                                      0x00C00000L
10969 #define CP_RB2_CNTL__CACHE_POLICY_MASK                                                                        0x01000000L
10970 #define CP_RB2_CNTL__RB_NO_UPDATE_MASK                                                                        0x08000000L
10971 #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK                                                                      0x80000000L
10972 //CP_RB2_RPTR_ADDR
10973 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                                 0x2
10974 #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                                   0xFFFFFFFCL
10975 //CP_RB2_RPTR_ADDR_HI
10976 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT                                                           0x0
10977 #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK                                                             0x0000FFFFL
10978 //CP_RB0_ACTIVE
10979 #define CP_RB0_ACTIVE__ACTIVE__SHIFT                                                                          0x0
10980 #define CP_RB0_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
10981 //CP_RB_ACTIVE
10982 #define CP_RB_ACTIVE__ACTIVE__SHIFT                                                                           0x0
10983 #define CP_RB_ACTIVE__ACTIVE_MASK                                                                             0x00000001L
10984 //CP_INT_CNTL_RING0
10985 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
10986 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
10987 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT                                                              0x10
10988 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
10989 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
10990 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
10991 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
10992 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
10993 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
10994 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
10995 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
10996 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
10997 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
10998 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
10999 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
11000 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
11001 #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
11002 #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
11003 #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK                                                                0x00010000L
11004 #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
11005 #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
11006 #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
11007 #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
11008 #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
11009 #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
11010 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
11011 #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
11012 #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
11013 #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
11014 #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
11015 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
11016 #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
11017 //CP_INT_CNTL_RING1
11018 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
11019 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
11020 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT                                                              0x10
11021 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
11022 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
11023 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
11024 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
11025 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
11026 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
11027 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
11028 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
11029 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
11030 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
11031 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
11032 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
11033 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
11034 #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
11035 #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
11036 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK                                                                0x00010000L
11037 #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
11038 #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
11039 #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
11040 #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
11041 #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
11042 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
11043 #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
11044 #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
11045 #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
11046 #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
11047 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
11048 #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
11049 #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
11050 //CP_INT_CNTL_RING2
11051 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT                                                0xb
11052 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                     0xe
11053 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT                                                              0x10
11054 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                 0x11
11055 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT                                                         0x12
11056 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT                                                        0x13
11057 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT                                                       0x14
11058 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT                                                         0x15
11059 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT                                                       0x16
11060 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT                                                         0x17
11061 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT                                                     0x18
11062 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT                                                       0x1a
11063 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                               0x1b
11064 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT                                                         0x1d
11065 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT                                                         0x1e
11066 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT                                                         0x1f
11067 #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK                                                  0x00000800L
11068 #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK                                                       0x00004000L
11069 #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK                                                                0x00010000L
11070 #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                   0x00020000L
11071 #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK                                                           0x00040000L
11072 #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK                                                          0x00080000L
11073 #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK                                                         0x00100000L
11074 #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK                                                           0x00200000L
11075 #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK                                                         0x00400000L
11076 #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK                                                           0x00800000L
11077 #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK                                                       0x01000000L
11078 #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK                                                         0x04000000L
11079 #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                 0x08000000L
11080 #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK                                                           0x20000000L
11081 #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK                                                           0x40000000L
11082 #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK                                                           0x80000000L
11083 //CP_INT_STATUS_RING0
11084 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
11085 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
11086 #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT                                                              0x10
11087 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
11088 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
11089 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT                                                       0x13
11090 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
11091 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
11092 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
11093 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT                                                         0x17
11094 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
11095 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
11096 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
11097 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT                                                         0x1d
11098 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT                                                         0x1e
11099 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT                                                         0x1f
11100 #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
11101 #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
11102 #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK                                                                0x00010000L
11103 #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
11104 #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
11105 #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK                                                         0x00080000L
11106 #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
11107 #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
11108 #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
11109 #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
11110 #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
11111 #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
11112 #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
11113 #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK                                                           0x20000000L
11114 #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK                                                           0x40000000L
11115 #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK                                                           0x80000000L
11116 //CP_INT_STATUS_RING1
11117 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
11118 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
11119 #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT                                                              0x10
11120 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
11121 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
11122 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
11123 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
11124 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
11125 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
11126 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT                                                         0x17
11127 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
11128 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
11129 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
11130 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT                                                         0x1d
11131 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT                                                         0x1e
11132 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT                                                         0x1f
11133 #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
11134 #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
11135 #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK                                                                0x00010000L
11136 #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
11137 #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
11138 #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
11139 #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
11140 #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
11141 #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
11142 #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
11143 #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
11144 #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
11145 #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
11146 #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK                                                           0x20000000L
11147 #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK                                                           0x40000000L
11148 #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK                                                           0x80000000L
11149 //CP_INT_STATUS_RING2
11150 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT                                                0xb
11151 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT                                                     0xe
11152 #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT                                                              0x10
11153 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT                                                 0x11
11154 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT                                                         0x12
11155 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT                                                        0x13
11156 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT                                                       0x14
11157 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT                                                         0x15
11158 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT                                                       0x16
11159 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT                                                         0x17
11160 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT                                                     0x18
11161 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT                                                       0x1a
11162 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT                                               0x1b
11163 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT                                                         0x1d
11164 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT                                                         0x1e
11165 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT                                                         0x1f
11166 #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK                                                  0x00000800L
11167 #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK                                                       0x00004000L
11168 #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK                                                                0x00010000L
11169 #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK                                                   0x00020000L
11170 #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK                                                           0x00040000L
11171 #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK                                                          0x00080000L
11172 #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK                                                         0x00100000L
11173 #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK                                                           0x00200000L
11174 #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK                                                         0x00400000L
11175 #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK                                                           0x00800000L
11176 #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK                                                       0x01000000L
11177 #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK                                                         0x04000000L
11178 #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK                                                 0x08000000L
11179 #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK                                                           0x20000000L
11180 #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK                                                           0x40000000L
11181 #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK                                                           0x80000000L
11182 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                             0x1
11183 #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK                                                               0x00000002L
11184 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
11185 #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
11186 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT                                                            0x1
11187 #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK                                                              0x00000002L
11188 //CP_PWR_CNTL
11189 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT                                                            0x0
11190 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT                                                            0x1
11191 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT                                                            0x8
11192 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT                                                            0x9
11193 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT                                                            0xa
11194 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT                                                            0xb
11195 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT                                                            0x10
11196 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT                                                            0x11
11197 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT                                                            0x12
11198 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT                                                            0x13
11199 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK                                                              0x00000001L
11200 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK                                                              0x00000002L
11201 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK                                                              0x00000100L
11202 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK                                                              0x00000200L
11203 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK                                                              0x00000400L
11204 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK                                                              0x00000800L
11205 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK                                                              0x00010000L
11206 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK                                                              0x00020000L
11207 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK                                                              0x00040000L
11208 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK                                                              0x00080000L
11209 //CP_MEM_SLP_CNTL
11210 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT                                                                  0x0
11211 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT                                                                  0x1
11212 #define CP_MEM_SLP_CNTL__RESERVED__SHIFT                                                                      0x2
11213 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT                                                        0x7
11214 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT                                                            0x8
11215 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT                                                           0x10
11216 #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                     0x18
11217 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK                                                                    0x00000001L
11218 #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK                                                                    0x00000002L
11219 #define CP_MEM_SLP_CNTL__RESERVED_MASK                                                                        0x0000007CL
11220 #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK                                                          0x00000080L
11221 #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK                                                              0x0000FF00L
11222 #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK                                                             0x00FF0000L
11223 #define CP_MEM_SLP_CNTL__RESERVED1_MASK                                                                       0xFF000000L
11224 //CP_ECC_FIRSTOCCURRENCE
11225 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT                                                              0x0
11226 #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT                                                                 0x4
11227 #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT                                                                     0x8
11228 #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT                                                                   0xa
11229 #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT                                                                  0xc
11230 #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT                                                                   0x10
11231 #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK                                                                0x00000003L
11232 #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK                                                                   0x000000F0L
11233 #define CP_ECC_FIRSTOCCURRENCE__ME_MASK                                                                       0x00000300L
11234 #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK                                                                     0x00000C00L
11235 #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK                                                                    0x00007000L
11236 #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK                                                                     0x000F0000L
11237 //CP_ECC_FIRSTOCCURRENCE_RING0
11238 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT                                                         0x0
11239 #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK                                                           0xFFFFFFFFL
11240 //CP_ECC_FIRSTOCCURRENCE_RING1
11241 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT                                                         0x0
11242 #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK                                                           0xFFFFFFFFL
11243 //CP_ECC_FIRSTOCCURRENCE_RING2
11244 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT                                                         0x0
11245 #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK                                                           0xFFFFFFFFL
11246 //GB_EDC_MODE
11247 #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT                                                                  0xf
11248 #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                     0x10
11249 #define GB_EDC_MODE__GATE_FUE__SHIFT                                                                          0x11
11250 #define GB_EDC_MODE__DED_MODE__SHIFT                                                                          0x14
11251 #define GB_EDC_MODE__PROP_FED__SHIFT                                                                          0x1d
11252 #define GB_EDC_MODE__BYPASS__SHIFT                                                                            0x1f
11253 #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK                                                                    0x00008000L
11254 #define GB_EDC_MODE__COUNT_FED_OUT_MASK                                                                       0x00010000L
11255 #define GB_EDC_MODE__GATE_FUE_MASK                                                                            0x00020000L
11256 #define GB_EDC_MODE__DED_MODE_MASK                                                                            0x00300000L
11257 #define GB_EDC_MODE__PROP_FED_MASK                                                                            0x20000000L
11258 #define GB_EDC_MODE__BYPASS_MASK                                                                              0x80000000L
11259 //CP_CPF_DEBUG
11260 //CP_PQ_WPTR_POLL_CNTL
11261 #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT                                                                   0x0
11262 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT                                                0x1d
11263 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT                                                              0x1e
11264 #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT                                                                       0x1f
11265 #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK                                                                     0x000000FFL
11266 #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK                                                  0x20000000L
11267 #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK                                                                0x40000000L
11268 #define CP_PQ_WPTR_POLL_CNTL__EN_MASK                                                                         0x80000000L
11269 //CP_PQ_WPTR_POLL_CNTL1
11270 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT                                                              0x0
11271 #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK                                                                0xFFFFFFFFL
11272 //CP_ME1_PIPE0_INT_CNTL
11273 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11274 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11275 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11276 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11277 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11278 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11279 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11280 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11281 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11282 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11283 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11284 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11285 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11286 #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11287 #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11288 #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11289 #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11290 #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11291 #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11292 #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11293 #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11294 #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11295 #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11296 #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11297 #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11298 #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11299 //CP_ME1_PIPE1_INT_CNTL
11300 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11301 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11302 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11303 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11304 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11305 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11306 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11307 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11308 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11309 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11310 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11311 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11312 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11313 #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11314 #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11315 #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11316 #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11317 #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11318 #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11319 #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11320 #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11321 #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11322 #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11323 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11324 #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11325 #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11326 //CP_ME1_PIPE2_INT_CNTL
11327 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11328 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11329 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11330 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11331 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11332 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11333 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11334 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11335 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11336 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11337 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11338 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11339 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11340 #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11341 #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11342 #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11343 #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11344 #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11345 #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11346 #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11347 #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11348 #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11349 #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11350 #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11351 #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11352 #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11353 //CP_ME1_PIPE3_INT_CNTL
11354 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11355 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11356 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11357 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11358 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11359 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11360 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11361 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11362 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11363 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11364 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11365 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11366 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11367 #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11368 #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11369 #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11370 #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11371 #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11372 #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11373 #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11374 #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11375 #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11376 #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11377 #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11378 #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11379 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11380 //CP_ME2_PIPE0_INT_CNTL
11381 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11382 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11383 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11384 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11385 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11386 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11387 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11388 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11389 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11390 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11391 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11392 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11393 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11394 #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11395 #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11396 #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11397 #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11398 #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11399 #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11400 #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11401 #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11402 #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11403 #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11404 #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11405 #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11406 #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11407 //CP_ME2_PIPE1_INT_CNTL
11408 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11409 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11410 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11411 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11412 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11413 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11414 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11415 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11416 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11417 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11418 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11419 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11420 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11421 #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11422 #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11423 #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11424 #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11425 #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11426 #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11427 #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11428 #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11429 #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11430 #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11431 #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11432 #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11433 #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11434 //CP_ME2_PIPE2_INT_CNTL
11435 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11436 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11437 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11438 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11439 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11440 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11441 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11442 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11443 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11444 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11445 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11446 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11447 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11448 #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11449 #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11450 #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11451 #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11452 #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11453 #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11454 #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11455 #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11456 #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11457 #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11458 #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11459 #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11460 #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11461 //CP_ME2_PIPE3_INT_CNTL
11462 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                             0xc
11463 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                              0xd
11464 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                 0xe
11465 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                0xf
11466 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                          0x10
11467 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                             0x11
11468 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                     0x17
11469 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                 0x18
11470 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                   0x1a
11471 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                           0x1b
11472 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                     0x1d
11473 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                     0x1e
11474 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                     0x1f
11475 #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                               0x00001000L
11476 #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                0x00002000L
11477 #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                   0x00004000L
11478 #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                  0x00008000L
11479 #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK                                                            0x00010000L
11480 #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                               0x00020000L
11481 #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                       0x00800000L
11482 #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                   0x01000000L
11483 #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                     0x04000000L
11484 #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                             0x08000000L
11485 #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                       0x20000000L
11486 #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                       0x40000000L
11487 #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                       0x80000000L
11488 //CP_ME1_PIPE0_INT_STATUS
11489 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11490 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11491 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11492 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11493 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11494 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11495 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11496 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11497 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11498 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11499 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11500 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11501 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11502 #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11503 #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11504 #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11505 #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11506 #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11507 #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11508 #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11509 #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11510 #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11511 #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11512 #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11513 #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11514 #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11515 //CP_ME1_PIPE1_INT_STATUS
11516 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11517 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11518 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11519 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11520 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11521 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11522 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11523 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11524 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11525 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11526 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11527 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11528 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11529 #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11530 #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11531 #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11532 #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11533 #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11534 #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11535 #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11536 #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11537 #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11538 #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11539 #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11540 #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11541 #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11542 //CP_ME1_PIPE2_INT_STATUS
11543 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11544 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11545 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11546 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11547 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11548 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11549 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11550 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11551 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11552 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11553 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11554 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11555 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11556 #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11557 #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11558 #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11559 #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11560 #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11561 #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11562 #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11563 #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11564 #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11565 #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11566 #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11567 #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11568 #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11569 //CP_ME1_PIPE3_INT_STATUS
11570 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11571 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11572 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11573 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11574 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11575 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11576 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11577 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11578 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11579 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11580 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11581 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11582 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11583 #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11584 #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11585 #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11586 #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11587 #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11588 #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11589 #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11590 #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11591 #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11592 #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11593 #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11594 #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11595 #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11596 //CP_ME2_PIPE0_INT_STATUS
11597 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11598 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11599 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11600 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11601 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11602 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11603 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11604 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11605 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11606 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11607 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11608 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11609 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11610 #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11611 #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11612 #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11613 #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11614 #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11615 #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11616 #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11617 #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11618 #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11619 #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11620 #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11621 #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11622 #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11623 //CP_ME2_PIPE1_INT_STATUS
11624 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11625 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11626 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11627 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11628 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11629 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11630 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11631 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11632 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11633 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11634 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11635 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11636 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11637 #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11638 #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11639 #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11640 #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11641 #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11642 #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11643 #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11644 #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11645 #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11646 #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11647 #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11648 #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11649 #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11650 //CP_ME2_PIPE2_INT_STATUS
11651 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11652 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11653 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11654 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11655 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11656 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11657 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11658 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11659 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11660 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11661 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11662 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11663 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11664 #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11665 #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11666 #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11667 #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11668 #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11669 #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11670 #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11671 #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11672 #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11673 #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11674 #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11675 #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11676 #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11677 //CP_ME2_PIPE3_INT_STATUS
11678 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                           0xc
11679 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                            0xd
11680 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                               0xe
11681 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                              0xf
11682 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT                                                        0x10
11683 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                           0x11
11684 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                   0x17
11685 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                               0x18
11686 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                 0x1a
11687 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                         0x1b
11688 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                   0x1d
11689 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                   0x1e
11690 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                   0x1f
11691 #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                             0x00001000L
11692 #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                              0x00002000L
11693 #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                 0x00004000L
11694 #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                0x00008000L
11695 #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK                                                          0x00010000L
11696 #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                             0x00020000L
11697 #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                     0x00800000L
11698 #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                 0x01000000L
11699 #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                   0x04000000L
11700 #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                           0x08000000L
11701 #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                     0x20000000L
11702 #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                     0x40000000L
11703 #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                     0x80000000L
11704 //CP_ME1_INT_STAT_DEBUG
11705 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT                                           0xc
11706 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT                                            0xd
11707 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                               0xe
11708 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT                                                0xf
11709 #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                        0x10
11710 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                           0x11
11711 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
11712 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                               0x18
11713 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                 0x1a
11714 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                         0x1b
11715 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                   0x1d
11716 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                   0x1e
11717 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                   0x1f
11718 #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK                                             0x00001000L
11719 #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK                                              0x00002000L
11720 #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                 0x00004000L
11721 #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK                                                  0x00008000L
11722 #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                          0x00010000L
11723 #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                             0x00020000L
11724 #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
11725 #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                 0x01000000L
11726 #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                   0x04000000L
11727 #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                           0x08000000L
11728 #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                     0x20000000L
11729 #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                     0x40000000L
11730 #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                     0x80000000L
11731 //CP_ME2_INT_STAT_DEBUG
11732 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT                                           0xc
11733 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT                                            0xd
11734 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT                                               0xe
11735 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT                                                0xf
11736 #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT                                                        0x10
11737 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT                                           0x11
11738 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT                                                   0x17
11739 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT                                               0x18
11740 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT                                                 0x1a
11741 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT                                         0x1b
11742 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT                                                   0x1d
11743 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT                                                   0x1e
11744 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT                                                   0x1f
11745 #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK                                             0x00001000L
11746 #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK                                              0x00002000L
11747 #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK                                                 0x00004000L
11748 #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK                                                  0x00008000L
11749 #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK                                                          0x00010000L
11750 #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK                                             0x00020000L
11751 #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK                                                     0x00800000L
11752 #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK                                                 0x01000000L
11753 #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK                                                   0x04000000L
11754 #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK                                           0x08000000L
11755 #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK                                                     0x20000000L
11756 #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK                                                     0x40000000L
11757 #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK                                                     0x80000000L
11758 //CC_GC_EDC_CONFIG
11759 #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
11760 #define CC_GC_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
11761 //CP_ME1_PIPE_PRIORITY_CNTS
11762 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
11763 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
11764 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
11765 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
11766 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
11767 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
11768 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
11769 #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
11770 //CP_ME1_PIPE0_PRIORITY
11771 #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
11772 #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11773 //CP_ME1_PIPE1_PRIORITY
11774 #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
11775 #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11776 //CP_ME1_PIPE2_PRIORITY
11777 #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
11778 #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11779 //CP_ME1_PIPE3_PRIORITY
11780 #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
11781 #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11782 //CP_ME2_PIPE_PRIORITY_CNTS
11783 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT                                                       0x0
11784 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT                                                      0x8
11785 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT                                                      0x10
11786 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT                                                       0x18
11787 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK                                                         0x000000FFL
11788 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK                                                        0x0000FF00L
11789 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK                                                        0x00FF0000L
11790 #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK                                                         0xFF000000L
11791 //CP_ME2_PIPE0_PRIORITY
11792 #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT                                                                0x0
11793 #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11794 //CP_ME2_PIPE1_PRIORITY
11795 #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT                                                                0x0
11796 #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11797 //CP_ME2_PIPE2_PRIORITY
11798 #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT                                                                0x0
11799 #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11800 //CP_ME2_PIPE3_PRIORITY
11801 #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT                                                                0x0
11802 #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK                                                                  0x00000003L
11803 //CP_CE_PRGRM_CNTR_START
11804 #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
11805 #define CP_CE_PRGRM_CNTR_START__IP_START_MASK                                                                 0x000007FFL
11806 //CP_PFP_PRGRM_CNTR_START
11807 #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT                                                              0x0
11808 #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK                                                                0x00001FFFL
11809 //CP_ME_PRGRM_CNTR_START
11810 #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT                                                               0x0
11811 #define CP_ME_PRGRM_CNTR_START__IP_START_MASK                                                                 0x00000FFFL
11812 //CP_MEC1_PRGRM_CNTR_START
11813 #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
11814 #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK                                                               0x0000FFFFL
11815 //CP_MEC2_PRGRM_CNTR_START
11816 #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT                                                             0x0
11817 #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK                                                               0x0000FFFFL
11818 //CP_CE_INTR_ROUTINE_START
11819 #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
11820 #define CP_CE_INTR_ROUTINE_START__IR_START_MASK                                                               0x000007FFL
11821 //CP_PFP_INTR_ROUTINE_START
11822 #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT                                                            0x0
11823 #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK                                                              0x00001FFFL
11824 //CP_ME_INTR_ROUTINE_START
11825 #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT                                                             0x0
11826 #define CP_ME_INTR_ROUTINE_START__IR_START_MASK                                                               0x00000FFFL
11827 //CP_MEC1_INTR_ROUTINE_START
11828 #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
11829 #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK                                                             0x0000FFFFL
11830 //CP_MEC2_INTR_ROUTINE_START
11831 #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT                                                           0x0
11832 #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK                                                             0x0000FFFFL
11833 //CP_CONTEXT_CNTL
11834 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT                                                          0x0
11835 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT                                                        0x4
11836 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT                                                          0x10
11837 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT                                                        0x14
11838 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK                                                            0x00000007L
11839 #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK                                                          0x00000070L
11840 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK                                                            0x00070000L
11841 #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK                                                          0x00700000L
11842 //CP_MAX_CONTEXT
11843 #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT                                                                    0x0
11844 #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK                                                                      0x00000007L
11845 //CP_IQ_WAIT_TIME1
11846 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT                                                                   0x0
11847 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT                                                               0x8
11848 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT                                                                  0x10
11849 #define CP_IQ_WAIT_TIME1__GWS__SHIFT                                                                          0x18
11850 #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK                                                                     0x000000FFL
11851 #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK                                                                 0x0000FF00L
11852 #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK                                                                    0x00FF0000L
11853 #define CP_IQ_WAIT_TIME1__GWS_MASK                                                                            0xFF000000L
11854 //CP_IQ_WAIT_TIME2
11855 #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT                                                                    0x0
11856 #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT                                                                     0x8
11857 #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT                                                                    0x10
11858 #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT                                                                    0x18
11859 #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK                                                                      0x000000FFL
11860 #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK                                                                       0x0000FF00L
11861 #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK                                                                      0x00FF0000L
11862 #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK                                                                      0xFF000000L
11863 //CP_RB0_BASE_HI
11864 #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
11865 #define CP_RB0_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
11866 //CP_RB1_BASE_HI
11867 #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
11868 #define CP_RB1_BASE_HI__RB_BASE_HI_MASK                                                                       0x000000FFL
11869 //CP_VMID_RESET
11870 #define CP_VMID_RESET__RESET_REQUEST__SHIFT                                                                   0x0
11871 #define CP_VMID_RESET__RESET_REQUEST_MASK                                                                     0x0000FFFFL
11872 //CPC_INT_CNTL
11873 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT                                                      0xc
11874 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT                                                       0xd
11875 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT                                                          0xe
11876 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT                                                         0xf
11877 #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT                                                                   0x10
11878 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT                                                      0x11
11879 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT                                                              0x17
11880 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT                                                          0x18
11881 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT                                                            0x1a
11882 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT                                                    0x1b
11883 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT                                                              0x1d
11884 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT                                                              0x1e
11885 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT                                                              0x1f
11886 #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK                                                        0x00001000L
11887 #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK                                                         0x00002000L
11888 #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK                                                            0x00004000L
11889 #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK                                                           0x00008000L
11890 #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK                                                                     0x00010000L
11891 #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK                                                        0x00020000L
11892 #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK                                                                0x00800000L
11893 #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK                                                            0x01000000L
11894 #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK                                                              0x04000000L
11895 #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK                                                      0x08000000L
11896 #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK                                                                0x20000000L
11897 #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK                                                                0x40000000L
11898 #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK                                                                0x80000000L
11899 //CPC_INT_STATUS
11900 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT                                                    0xc
11901 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT                                                     0xd
11902 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT                                                        0xe
11903 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT                                                       0xf
11904 #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT                                                                 0x10
11905 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT                                                    0x11
11906 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT                                                            0x17
11907 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT                                                        0x18
11908 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT                                                          0x1a
11909 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT                                                  0x1b
11910 #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT                                                            0x1d
11911 #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT                                                            0x1e
11912 #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT                                                            0x1f
11913 #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK                                                      0x00001000L
11914 #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK                                                       0x00002000L
11915 #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK                                                          0x00004000L
11916 #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK                                                         0x00008000L
11917 #define CPC_INT_STATUS__GPF_INT_STATUS_MASK                                                                   0x00010000L
11918 #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK                                                      0x00020000L
11919 #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK                                                              0x00800000L
11920 #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK                                                          0x01000000L
11921 #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK                                                            0x04000000L
11922 #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK                                                    0x08000000L
11923 #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK                                                              0x20000000L
11924 #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK                                                              0x40000000L
11925 #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK                                                              0x80000000L
11926 //CP_VMID_PREEMPT
11927 #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT                                                               0x0
11928 #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT                                                                  0x10
11929 #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK                                                                 0x0000FFFFL
11930 #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK                                                                    0x000F0000L
11931 //CPC_INT_CNTX_ID
11932 #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT                                                                       0x0
11933 #define CPC_INT_CNTX_ID__CNTX_ID_MASK                                                                         0xFFFFFFFFL
11934 //CP_PQ_STATUS
11935 #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
11936 #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
11937 #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
11938 #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
11939 //CP_CPC_IC_BASE_LO
11940 #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT                                                                  0xc
11941 #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK                                                                    0xFFFFF000L
11942 //CP_CPC_IC_BASE_HI
11943 #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT                                                                  0x0
11944 #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK                                                                    0x0000FFFFL
11945 //CP_CPC_IC_BASE_CNTL
11946 #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT                                                                      0x0
11947 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT                                                              0x18
11948 #define CP_CPC_IC_BASE_CNTL__VMID_MASK                                                                        0x0000000FL
11949 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK                                                                0x01000000L
11950 //CP_CPC_IC_OP_CNTL
11951 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT                                                            0x0
11952 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT                                                                0x4
11953 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT                                                               0x5
11954 #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK                                                              0x00000001L
11955 #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK                                                                  0x00000010L
11956 #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK                                                                 0x00000020L
11957 //CP_MEC1_F32_INT_DIS
11958 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
11959 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
11960 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
11961 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
11962 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
11963 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
11964 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
11965 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
11966 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
11967 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
11968 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
11969 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
11970 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
11971 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
11972 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
11973 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
11974 #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
11975 #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
11976 #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
11977 #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
11978 #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
11979 #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
11980 #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
11981 #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
11982 #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
11983 #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
11984 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
11985 #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
11986 #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
11987 #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
11988 #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
11989 #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
11990 //CP_MEC2_F32_INT_DIS
11991 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT                                                           0x0
11992 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT                                                              0x1
11993 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT                                                      0x2
11994 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT                                                            0x3
11995 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT                                                           0x4
11996 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT                                                       0x5
11997 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT                                                          0x6
11998 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT                                                         0x7
11999 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT                                                           0x8
12000 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT                                                              0x9
12001 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT                                                               0xa
12002 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT                                                               0xb
12003 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT                                                               0xc
12004 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT                                                        0xd
12005 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT                                                         0xe
12006 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT                                                       0xf
12007 #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK                                                             0x00000001L
12008 #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK                                                                0x00000002L
12009 #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK                                                        0x00000004L
12010 #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK                                                              0x00000008L
12011 #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK                                                             0x00000010L
12012 #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK                                                         0x00000020L
12013 #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK                                                            0x00000040L
12014 #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK                                                           0x00000080L
12015 #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK                                                             0x00000100L
12016 #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK                                                                0x00000200L
12017 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK                                                                 0x00000400L
12018 #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK                                                                 0x00000800L
12019 #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK                                                                 0x00001000L
12020 #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK                                                          0x00002000L
12021 #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK                                                           0x00004000L
12022 #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK                                                         0x00008000L
12023 //CP_VMID_STATUS
12024 #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT                                                              0x0
12025 #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT                                                              0x10
12026 #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK                                                                0x0000FFFFL
12027 #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK                                                                0xFFFF0000L
12028 
12029 
12030 // addressBlock: gc_cppdec2
12031 //CP_RB_DOORBELL_CONTROL_SCH_0
12032 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT                                                  0x2
12033 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT                                                      0x1e
12034 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT                                                     0x1f
12035 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12036 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK                                                        0x40000000L
12037 #define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK                                                       0x80000000L
12038 //CP_RB_DOORBELL_CONTROL_SCH_1
12039 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT                                                  0x2
12040 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT                                                      0x1e
12041 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT                                                     0x1f
12042 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12043 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK                                                        0x40000000L
12044 #define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK                                                       0x80000000L
12045 //CP_RB_DOORBELL_CONTROL_SCH_2
12046 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT                                                  0x2
12047 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT                                                      0x1e
12048 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT                                                     0x1f
12049 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12050 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK                                                        0x40000000L
12051 #define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK                                                       0x80000000L
12052 //CP_RB_DOORBELL_CONTROL_SCH_3
12053 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT                                                  0x2
12054 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT                                                      0x1e
12055 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT                                                     0x1f
12056 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12057 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK                                                        0x40000000L
12058 #define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK                                                       0x80000000L
12059 //CP_RB_DOORBELL_CONTROL_SCH_4
12060 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT                                                  0x2
12061 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT                                                      0x1e
12062 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT                                                     0x1f
12063 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12064 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK                                                        0x40000000L
12065 #define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK                                                       0x80000000L
12066 //CP_RB_DOORBELL_CONTROL_SCH_5
12067 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT                                                  0x2
12068 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT                                                      0x1e
12069 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT                                                     0x1f
12070 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12071 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK                                                        0x40000000L
12072 #define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK                                                       0x80000000L
12073 //CP_RB_DOORBELL_CONTROL_SCH_6
12074 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT                                                  0x2
12075 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT                                                      0x1e
12076 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT                                                     0x1f
12077 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12078 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK                                                        0x40000000L
12079 #define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK                                                       0x80000000L
12080 //CP_RB_DOORBELL_CONTROL_SCH_7
12081 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT                                                  0x2
12082 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT                                                      0x1e
12083 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT                                                     0x1f
12084 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK                                                    0x0FFFFFFCL
12085 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK                                                        0x40000000L
12086 #define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK                                                       0x80000000L
12087 //CP_RB_DOORBELL_CLEAR
12088 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT                                                             0x0
12089 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT                                             0x8
12090 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT                                            0x9
12091 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT                                                 0xa
12092 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT                                                0xb
12093 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT                                                 0xc
12094 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT                                                0xd
12095 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK                                                               0x00000007L
12096 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK                                               0x00000100L
12097 #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK                                              0x00000200L
12098 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK                                                   0x00000400L
12099 #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK                                                  0x00000800L
12100 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK                                                   0x00001000L
12101 #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK                                                  0x00002000L
12102 //CP_GFX_MQD_CONTROL
12103 #define CP_GFX_MQD_CONTROL__VMID__SHIFT                                                                       0x0
12104 #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
12105 #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
12106 #define CP_GFX_MQD_CONTROL__VMID_MASK                                                                         0x0000000FL
12107 #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
12108 #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK                                                                 0x01000000L
12109 //CP_GFX_MQD_BASE_ADDR
12110 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x2
12111 #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFCL
12112 //CP_GFX_MQD_BASE_ADDR_HI
12113 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
12114 #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x0000FFFFL
12115 //CP_RB_STATUS
12116 #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT                                                                 0x0
12117 #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT                                                                  0x1
12118 #define CP_RB_STATUS__DOORBELL_UPDATED_MASK                                                                   0x00000001L
12119 #define CP_RB_STATUS__DOORBELL_ENABLE_MASK                                                                    0x00000002L
12120 //CPG_UTCL1_STATUS
12121 #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
12122 #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
12123 #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
12124 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
12125 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
12126 #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
12127 #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
12128 #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
12129 #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
12130 #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
12131 #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
12132 #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
12133 //CPC_UTCL1_STATUS
12134 #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
12135 #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
12136 #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
12137 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
12138 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
12139 #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
12140 #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
12141 #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
12142 #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
12143 #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
12144 #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
12145 #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
12146 //CPF_UTCL1_STATUS
12147 #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
12148 #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
12149 #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
12150 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
12151 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
12152 #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
12153 #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
12154 #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
12155 #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
12156 #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
12157 #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
12158 #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
12159 //CP_SD_CNTL
12160 #define CP_SD_CNTL__CPF_EN__SHIFT                                                                             0x0
12161 #define CP_SD_CNTL__CPG_EN__SHIFT                                                                             0x1
12162 #define CP_SD_CNTL__CPC_EN__SHIFT                                                                             0x2
12163 #define CP_SD_CNTL__RLC_EN__SHIFT                                                                             0x3
12164 #define CP_SD_CNTL__SPI_EN__SHIFT                                                                             0x4
12165 #define CP_SD_CNTL__WD_EN__SHIFT                                                                              0x5
12166 #define CP_SD_CNTL__IA_EN__SHIFT                                                                              0x6
12167 #define CP_SD_CNTL__PA_EN__SHIFT                                                                              0x7
12168 #define CP_SD_CNTL__RMI_EN__SHIFT                                                                             0x8
12169 #define CP_SD_CNTL__EA_EN__SHIFT                                                                              0x9
12170 #define CP_SD_CNTL__CPF_EN_MASK                                                                               0x00000001L
12171 #define CP_SD_CNTL__CPG_EN_MASK                                                                               0x00000002L
12172 #define CP_SD_CNTL__CPC_EN_MASK                                                                               0x00000004L
12173 #define CP_SD_CNTL__RLC_EN_MASK                                                                               0x00000008L
12174 #define CP_SD_CNTL__SPI_EN_MASK                                                                               0x00000010L
12175 #define CP_SD_CNTL__WD_EN_MASK                                                                                0x00000020L
12176 #define CP_SD_CNTL__IA_EN_MASK                                                                                0x00000040L
12177 #define CP_SD_CNTL__PA_EN_MASK                                                                                0x00000080L
12178 #define CP_SD_CNTL__RMI_EN_MASK                                                                               0x00000100L
12179 #define CP_SD_CNTL__EA_EN_MASK                                                                                0x00000200L
12180 //CP_SOFT_RESET_CNTL
12181 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT                                                        0x0
12182 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT                                                        0x1
12183 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT                                                          0x2
12184 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT                                                         0x3
12185 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT                                               0x4
12186 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT                                                      0x5
12187 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT                                                         0x6
12188 #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK                                                          0x00000001L
12189 #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK                                                          0x00000002L
12190 #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK                                                            0x00000004L
12191 #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK                                                           0x00000008L
12192 #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK                                                 0x00000010L
12193 #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK                                                        0x00000020L
12194 #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK                                                           0x00000040L
12195 //CP_CPC_GFX_CNTL
12196 #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT                                                                       0x0
12197 #define CP_CPC_GFX_CNTL__PIPEID__SHIFT                                                                        0x3
12198 #define CP_CPC_GFX_CNTL__MEID__SHIFT                                                                          0x5
12199 #define CP_CPC_GFX_CNTL__VALID__SHIFT                                                                         0x7
12200 #define CP_CPC_GFX_CNTL__QUEUEID_MASK                                                                         0x00000007L
12201 #define CP_CPC_GFX_CNTL__PIPEID_MASK                                                                          0x00000018L
12202 #define CP_CPC_GFX_CNTL__MEID_MASK                                                                            0x00000060L
12203 #define CP_CPC_GFX_CNTL__VALID_MASK                                                                           0x00000080L
12204 
12205 
12206 // addressBlock: gc_spipdec
12207 //SPI_ARB_PRIORITY
12208 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT                                                               0x0
12209 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT                                                               0x3
12210 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT                                                               0x6
12211 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT                                                               0x9
12212 #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT                                                                 0xc
12213 #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT                                                                 0xe
12214 #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT                                                                 0x10
12215 #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT                                                                 0x12
12216 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK                                                                 0x00000007L
12217 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK                                                                 0x00000038L
12218 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK                                                                 0x000001C0L
12219 #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK                                                                 0x00000E00L
12220 #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK                                                                   0x00003000L
12221 #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK                                                                   0x0000C000L
12222 #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK                                                                   0x00030000L
12223 #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK                                                                   0x000C0000L
12224 //SPI_ARB_CYCLES_0
12225 #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT                                                                 0x0
12226 #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT                                                                 0x10
12227 #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK                                                                   0x0000FFFFL
12228 #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK                                                                   0xFFFF0000L
12229 //SPI_ARB_CYCLES_1
12230 #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT                                                                 0x0
12231 #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT                                                                 0x10
12232 #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK                                                                   0x0000FFFFL
12233 #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK                                                                   0xFFFF0000L
12234 //SPI_CDBG_SYS_GFX
12235 #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT                                                                        0x0
12236 #define SPI_CDBG_SYS_GFX__VS_EN__SHIFT                                                                        0x1
12237 #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT                                                                        0x2
12238 #define SPI_CDBG_SYS_GFX__ES_EN__SHIFT                                                                        0x3
12239 #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT                                                                        0x4
12240 #define SPI_CDBG_SYS_GFX__LS_EN__SHIFT                                                                        0x5
12241 #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT                                                                        0x6
12242 #define SPI_CDBG_SYS_GFX__PS_EN_MASK                                                                          0x0001L
12243 #define SPI_CDBG_SYS_GFX__VS_EN_MASK                                                                          0x0002L
12244 #define SPI_CDBG_SYS_GFX__GS_EN_MASK                                                                          0x0004L
12245 #define SPI_CDBG_SYS_GFX__ES_EN_MASK                                                                          0x0008L
12246 #define SPI_CDBG_SYS_GFX__HS_EN_MASK                                                                          0x0010L
12247 #define SPI_CDBG_SYS_GFX__LS_EN_MASK                                                                          0x0020L
12248 #define SPI_CDBG_SYS_GFX__CS_EN_MASK                                                                          0x0040L
12249 //SPI_CDBG_SYS_HP3D
12250 #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT                                                                       0x0
12251 #define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT                                                                       0x1
12252 #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT                                                                       0x2
12253 #define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT                                                                       0x3
12254 #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT                                                                       0x4
12255 #define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT                                                                       0x5
12256 #define SPI_CDBG_SYS_HP3D__PS_EN_MASK                                                                         0x0001L
12257 #define SPI_CDBG_SYS_HP3D__VS_EN_MASK                                                                         0x0002L
12258 #define SPI_CDBG_SYS_HP3D__GS_EN_MASK                                                                         0x0004L
12259 #define SPI_CDBG_SYS_HP3D__ES_EN_MASK                                                                         0x0008L
12260 #define SPI_CDBG_SYS_HP3D__HS_EN_MASK                                                                         0x0010L
12261 #define SPI_CDBG_SYS_HP3D__LS_EN_MASK                                                                         0x0020L
12262 //SPI_CDBG_SYS_CS0
12263 #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT                                                                        0x0
12264 #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT                                                                        0x8
12265 #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT                                                                        0x10
12266 #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT                                                                        0x18
12267 #define SPI_CDBG_SYS_CS0__PIPE0_MASK                                                                          0x000000FFL
12268 #define SPI_CDBG_SYS_CS0__PIPE1_MASK                                                                          0x0000FF00L
12269 #define SPI_CDBG_SYS_CS0__PIPE2_MASK                                                                          0x00FF0000L
12270 #define SPI_CDBG_SYS_CS0__PIPE3_MASK                                                                          0xFF000000L
12271 //SPI_CDBG_SYS_CS1
12272 #define SPI_CDBG_SYS_CS1__PIPE0__SHIFT                                                                        0x0
12273 #define SPI_CDBG_SYS_CS1__PIPE1__SHIFT                                                                        0x8
12274 #define SPI_CDBG_SYS_CS1__PIPE2__SHIFT                                                                        0x10
12275 #define SPI_CDBG_SYS_CS1__PIPE3__SHIFT                                                                        0x18
12276 #define SPI_CDBG_SYS_CS1__PIPE0_MASK                                                                          0x000000FFL
12277 #define SPI_CDBG_SYS_CS1__PIPE1_MASK                                                                          0x0000FF00L
12278 #define SPI_CDBG_SYS_CS1__PIPE2_MASK                                                                          0x00FF0000L
12279 #define SPI_CDBG_SYS_CS1__PIPE3_MASK                                                                          0xFF000000L
12280 //SPI_WCL_PIPE_PERCENT_GFX
12281 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT                                                                0x0
12282 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT                                                         0x7
12283 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT                                                         0xc
12284 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT                                                         0x11
12285 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT                                                         0x16
12286 #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK                                                                  0x0000007FL
12287 #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK                                                           0x00000F80L
12288 #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK                                                           0x0001F000L
12289 #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK                                                           0x003E0000L
12290 #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK                                                           0x07C00000L
12291 //SPI_WCL_PIPE_PERCENT_HP3D
12292 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT                                                               0x0
12293 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT                                                        0xc
12294 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT                                                        0x16
12295 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK                                                                 0x0000007FL
12296 #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK                                                          0x0001F000L
12297 #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK                                                          0x07C00000L
12298 //SPI_WCL_PIPE_PERCENT_CS0
12299 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT                                                                0x0
12300 #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK                                                                  0x7FL
12301 //SPI_WCL_PIPE_PERCENT_CS1
12302 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT                                                                0x0
12303 #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK                                                                  0x7FL
12304 //SPI_WCL_PIPE_PERCENT_CS2
12305 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT                                                                0x0
12306 #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK                                                                  0x7FL
12307 //SPI_WCL_PIPE_PERCENT_CS3
12308 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT                                                                0x0
12309 #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK                                                                  0x7FL
12310 //SPI_WCL_PIPE_PERCENT_CS4
12311 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT                                                                0x0
12312 #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK                                                                  0x7FL
12313 //SPI_WCL_PIPE_PERCENT_CS5
12314 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT                                                                0x0
12315 #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK                                                                  0x7FL
12316 //SPI_WCL_PIPE_PERCENT_CS6
12317 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT                                                                0x0
12318 #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK                                                                  0x7FL
12319 //SPI_WCL_PIPE_PERCENT_CS7
12320 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT                                                                0x0
12321 #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK                                                                  0x7FL
12322 //SPI_GDBG_WAVE_CNTL
12323 #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT                                                                   0x0
12324 #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT                                                                 0x1
12325 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK                                                                     0x00000001L
12326 #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK                                                                   0x0001FFFEL
12327 //SPI_GDBG_TRAP_CONFIG
12328 #define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT                                                                   0x0
12329 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT                                                                 0x2
12330 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT                                                                0x4
12331 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT                                                                 0x7
12332 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT                                                               0x8
12333 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT                                                              0x9
12334 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT                                                                  0xf
12335 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT                                                                 0x10
12336 #define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK                                                                     0x00000003L
12337 #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK                                                                   0x0000000CL
12338 #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK                                                                  0x00000070L
12339 #define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK                                                                   0x00000080L
12340 #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK                                                                 0x00000100L
12341 #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK                                                                0x00000200L
12342 #define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK                                                                    0x00008000L
12343 #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK                                                                   0xFFFF0000L
12344 //SPI_GDBG_TRAP_MASK
12345 #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT                                                                    0x0
12346 #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT                                                                    0x9
12347 #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK                                                                      0x01FFL
12348 #define SPI_GDBG_TRAP_MASK__REPLACE_MASK                                                                      0x0200L
12349 //SPI_GDBG_WAVE_CNTL2
12350 #define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT                                                                 0x0
12351 #define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT                                                                      0x10
12352 #define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK                                                                   0x0000FFFFL
12353 #define SPI_GDBG_WAVE_CNTL2__MODE_MASK                                                                        0x00030000L
12354 //SPI_GDBG_WAVE_CNTL3
12355 #define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT                                                                  0x0
12356 #define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT                                                                  0x1
12357 #define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT                                                                  0x2
12358 #define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT                                                                  0x3
12359 #define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT                                                                 0x4
12360 #define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT                                                                 0x5
12361 #define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT                                                                 0x6
12362 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT                                                                 0x7
12363 #define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT                                                                 0x8
12364 #define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT                                                                 0x9
12365 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT                                                                 0xa
12366 #define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT                                                                 0xb
12367 #define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT                                                                 0xc
12368 #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT                                                            0xd
12369 #define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT                                                                0x1c
12370 #define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK                                                                    0x00000001L
12371 #define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK                                                                    0x00000002L
12372 #define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK                                                                    0x00000004L
12373 #define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK                                                                    0x00000008L
12374 #define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK                                                                   0x00000010L
12375 #define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK                                                                   0x00000020L
12376 #define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK                                                                   0x00000040L
12377 #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK                                                                   0x00000080L
12378 #define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK                                                                   0x00000100L
12379 #define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK                                                                   0x00000200L
12380 #define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK                                                                   0x00000400L
12381 #define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK                                                                   0x00000800L
12382 #define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK                                                                   0x00001000L
12383 #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK                                                              0x0FFFE000L
12384 #define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK                                                                  0x10000000L
12385 //SPI_GDBG_TRAP_DATA0
12386 #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT                                                                      0x0
12387 #define SPI_GDBG_TRAP_DATA0__DATA_MASK                                                                        0xFFFFFFFFL
12388 //SPI_GDBG_TRAP_DATA1
12389 #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT                                                                      0x0
12390 #define SPI_GDBG_TRAP_DATA1__DATA_MASK                                                                        0xFFFFFFFFL
12391 //SPI_RESET_DEBUG
12392 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT                                                             0x0
12393 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT                                                    0x1
12394 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT                                                    0x2
12395 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT                                                    0x3
12396 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT                                                    0x4
12397 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK                                                               0x01L
12398 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK                                                      0x02L
12399 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK                                                      0x04L
12400 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK                                                      0x08L
12401 #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK                                                      0x10L
12402 //SPI_COMPUTE_QUEUE_RESET
12403 #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT                                                                 0x0
12404 #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK                                                                   0x01L
12405 //SPI_RESOURCE_RESERVE_CU_0
12406 #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT                                                                0x0
12407 #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT                                                                0x4
12408 #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT                                                                 0x8
12409 #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT                                                               0xc
12410 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT                                                            0xf
12411 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK                                                                  0x0000000FL
12412 #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK                                                                  0x000000F0L
12413 #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK                                                                   0x00000F00L
12414 #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK                                                                 0x00007000L
12415 #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK                                                              0x00078000L
12416 //SPI_RESOURCE_RESERVE_CU_1
12417 #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT                                                                0x0
12418 #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT                                                                0x4
12419 #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT                                                                 0x8
12420 #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT                                                               0xc
12421 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT                                                            0xf
12422 #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK                                                                  0x0000000FL
12423 #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK                                                                  0x000000F0L
12424 #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK                                                                   0x00000F00L
12425 #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK                                                                 0x00007000L
12426 #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK                                                              0x00078000L
12427 //SPI_RESOURCE_RESERVE_CU_2
12428 #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT                                                                0x0
12429 #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT                                                                0x4
12430 #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT                                                                 0x8
12431 #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT                                                               0xc
12432 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT                                                            0xf
12433 #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK                                                                  0x0000000FL
12434 #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK                                                                  0x000000F0L
12435 #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK                                                                   0x00000F00L
12436 #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK                                                                 0x00007000L
12437 #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK                                                              0x00078000L
12438 //SPI_RESOURCE_RESERVE_CU_3
12439 #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT                                                                0x0
12440 #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT                                                                0x4
12441 #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT                                                                 0x8
12442 #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT                                                               0xc
12443 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT                                                            0xf
12444 #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK                                                                  0x0000000FL
12445 #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK                                                                  0x000000F0L
12446 #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK                                                                   0x00000F00L
12447 #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK                                                                 0x00007000L
12448 #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK                                                              0x00078000L
12449 //SPI_RESOURCE_RESERVE_CU_4
12450 #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT                                                                0x0
12451 #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT                                                                0x4
12452 #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT                                                                 0x8
12453 #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT                                                               0xc
12454 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT                                                            0xf
12455 #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK                                                                  0x0000000FL
12456 #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK                                                                  0x000000F0L
12457 #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK                                                                   0x00000F00L
12458 #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK                                                                 0x00007000L
12459 #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK                                                              0x00078000L
12460 //SPI_RESOURCE_RESERVE_CU_5
12461 #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT                                                                0x0
12462 #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT                                                                0x4
12463 #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT                                                                 0x8
12464 #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT                                                               0xc
12465 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT                                                            0xf
12466 #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK                                                                  0x0000000FL
12467 #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK                                                                  0x000000F0L
12468 #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK                                                                   0x00000F00L
12469 #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK                                                                 0x00007000L
12470 #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK                                                              0x00078000L
12471 //SPI_RESOURCE_RESERVE_CU_6
12472 #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT                                                                0x0
12473 #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT                                                                0x4
12474 #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT                                                                 0x8
12475 #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT                                                               0xc
12476 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT                                                            0xf
12477 #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK                                                                  0x0000000FL
12478 #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK                                                                  0x000000F0L
12479 #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK                                                                   0x00000F00L
12480 #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK                                                                 0x00007000L
12481 #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK                                                              0x00078000L
12482 //SPI_RESOURCE_RESERVE_CU_7
12483 #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT                                                                0x0
12484 #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT                                                                0x4
12485 #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT                                                                 0x8
12486 #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT                                                               0xc
12487 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT                                                            0xf
12488 #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK                                                                  0x0000000FL
12489 #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK                                                                  0x000000F0L
12490 #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK                                                                   0x00000F00L
12491 #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK                                                                 0x00007000L
12492 #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK                                                              0x00078000L
12493 //SPI_RESOURCE_RESERVE_CU_8
12494 #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT                                                                0x0
12495 #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT                                                                0x4
12496 #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT                                                                 0x8
12497 #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT                                                               0xc
12498 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT                                                            0xf
12499 #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK                                                                  0x0000000FL
12500 #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK                                                                  0x000000F0L
12501 #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK                                                                   0x00000F00L
12502 #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK                                                                 0x00007000L
12503 #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK                                                              0x00078000L
12504 //SPI_RESOURCE_RESERVE_CU_9
12505 #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT                                                                0x0
12506 #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT                                                                0x4
12507 #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT                                                                 0x8
12508 #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT                                                               0xc
12509 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT                                                            0xf
12510 #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK                                                                  0x0000000FL
12511 #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK                                                                  0x000000F0L
12512 #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK                                                                   0x00000F00L
12513 #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK                                                                 0x00007000L
12514 #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK                                                              0x00078000L
12515 //SPI_RESOURCE_RESERVE_EN_CU_0
12516 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT                                                               0x0
12517 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT                                                        0x1
12518 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT                                                       0x10
12519 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12520 #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK                                                                 0x00000001L
12521 #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK                                                          0x0000FFFEL
12522 #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK                                                         0x00FF0000L
12523 #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12524 //SPI_RESOURCE_RESERVE_EN_CU_1
12525 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT                                                               0x0
12526 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT                                                        0x1
12527 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT                                                       0x10
12528 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12529 #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK                                                                 0x00000001L
12530 #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK                                                          0x0000FFFEL
12531 #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK                                                         0x00FF0000L
12532 #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12533 //SPI_RESOURCE_RESERVE_EN_CU_2
12534 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT                                                               0x0
12535 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT                                                        0x1
12536 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT                                                       0x10
12537 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12538 #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK                                                                 0x00000001L
12539 #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK                                                          0x0000FFFEL
12540 #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK                                                         0x00FF0000L
12541 #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12542 //SPI_RESOURCE_RESERVE_EN_CU_3
12543 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT                                                               0x0
12544 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT                                                        0x1
12545 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT                                                       0x10
12546 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12547 #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK                                                                 0x00000001L
12548 #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK                                                          0x0000FFFEL
12549 #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK                                                         0x00FF0000L
12550 #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12551 //SPI_RESOURCE_RESERVE_EN_CU_4
12552 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT                                                               0x0
12553 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT                                                        0x1
12554 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT                                                       0x10
12555 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12556 #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK                                                                 0x00000001L
12557 #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK                                                          0x0000FFFEL
12558 #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK                                                         0x00FF0000L
12559 #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12560 //SPI_RESOURCE_RESERVE_EN_CU_5
12561 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT                                                               0x0
12562 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT                                                        0x1
12563 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT                                                       0x10
12564 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12565 #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK                                                                 0x00000001L
12566 #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK                                                          0x0000FFFEL
12567 #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK                                                         0x00FF0000L
12568 #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12569 //SPI_RESOURCE_RESERVE_EN_CU_6
12570 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT                                                               0x0
12571 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT                                                        0x1
12572 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT                                                       0x10
12573 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12574 #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK                                                                 0x00000001L
12575 #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK                                                          0x0000FFFEL
12576 #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK                                                         0x00FF0000L
12577 #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12578 //SPI_RESOURCE_RESERVE_EN_CU_7
12579 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT                                                               0x0
12580 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT                                                        0x1
12581 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT                                                       0x10
12582 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12583 #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK                                                                 0x00000001L
12584 #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK                                                          0x0000FFFEL
12585 #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK                                                         0x00FF0000L
12586 #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12587 //SPI_RESOURCE_RESERVE_EN_CU_8
12588 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT                                                               0x0
12589 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT                                                        0x1
12590 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT                                                       0x10
12591 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12592 #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK                                                                 0x00000001L
12593 #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK                                                          0x0000FFFEL
12594 #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK                                                         0x00FF0000L
12595 #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12596 //SPI_RESOURCE_RESERVE_EN_CU_9
12597 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT                                                               0x0
12598 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT                                                        0x1
12599 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT                                                       0x10
12600 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT                                               0x18
12601 #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK                                                                 0x00000001L
12602 #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK                                                          0x0000FFFEL
12603 #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK                                                         0x00FF0000L
12604 #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK                                                 0x01000000L
12605 //SPI_RESOURCE_RESERVE_CU_10
12606 #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT                                                               0x0
12607 #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT                                                               0x4
12608 #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT                                                                0x8
12609 #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT                                                              0xc
12610 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT                                                           0xf
12611 #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK                                                                 0x0000000FL
12612 #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK                                                                 0x000000F0L
12613 #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK                                                                  0x00000F00L
12614 #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK                                                                0x00007000L
12615 #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK                                                             0x00078000L
12616 //SPI_RESOURCE_RESERVE_CU_11
12617 #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT                                                               0x0
12618 #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT                                                               0x4
12619 #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT                                                                0x8
12620 #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT                                                              0xc
12621 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT                                                           0xf
12622 #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK                                                                 0x0000000FL
12623 #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK                                                                 0x000000F0L
12624 #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK                                                                  0x00000F00L
12625 #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK                                                                0x00007000L
12626 #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK                                                             0x00078000L
12627 //SPI_RESOURCE_RESERVE_EN_CU_10
12628 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT                                                              0x0
12629 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT                                                       0x1
12630 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT                                                      0x10
12631 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12632 #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK                                                                0x00000001L
12633 #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK                                                         0x0000FFFEL
12634 #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK                                                        0x00FF0000L
12635 #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12636 //SPI_RESOURCE_RESERVE_EN_CU_11
12637 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT                                                              0x0
12638 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT                                                       0x1
12639 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT                                                      0x10
12640 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12641 #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK                                                                0x00000001L
12642 #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK                                                         0x0000FFFEL
12643 #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK                                                        0x00FF0000L
12644 #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12645 //SPI_RESOURCE_RESERVE_CU_12
12646 #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT                                                               0x0
12647 #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT                                                               0x4
12648 #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT                                                                0x8
12649 #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT                                                              0xc
12650 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT                                                           0xf
12651 #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK                                                                 0x0000000FL
12652 #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK                                                                 0x000000F0L
12653 #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK                                                                  0x00000F00L
12654 #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK                                                                0x00007000L
12655 #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK                                                             0x00078000L
12656 //SPI_RESOURCE_RESERVE_CU_13
12657 #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT                                                               0x0
12658 #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT                                                               0x4
12659 #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT                                                                0x8
12660 #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT                                                              0xc
12661 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT                                                           0xf
12662 #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK                                                                 0x0000000FL
12663 #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK                                                                 0x000000F0L
12664 #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK                                                                  0x00000F00L
12665 #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK                                                                0x00007000L
12666 #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK                                                             0x00078000L
12667 //SPI_RESOURCE_RESERVE_CU_14
12668 #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT                                                               0x0
12669 #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT                                                               0x4
12670 #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT                                                                0x8
12671 #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT                                                              0xc
12672 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT                                                           0xf
12673 #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK                                                                 0x0000000FL
12674 #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK                                                                 0x000000F0L
12675 #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK                                                                  0x00000F00L
12676 #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK                                                                0x00007000L
12677 #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK                                                             0x00078000L
12678 //SPI_RESOURCE_RESERVE_CU_15
12679 #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT                                                               0x0
12680 #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT                                                               0x4
12681 #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT                                                                0x8
12682 #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT                                                              0xc
12683 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT                                                           0xf
12684 #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK                                                                 0x0000000FL
12685 #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK                                                                 0x000000F0L
12686 #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK                                                                  0x00000F00L
12687 #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK                                                                0x00007000L
12688 #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK                                                             0x00078000L
12689 //SPI_RESOURCE_RESERVE_EN_CU_12
12690 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT                                                              0x0
12691 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT                                                       0x1
12692 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT                                                      0x10
12693 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12694 #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK                                                                0x00000001L
12695 #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK                                                         0x0000FFFEL
12696 #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK                                                        0x00FF0000L
12697 #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12698 //SPI_RESOURCE_RESERVE_EN_CU_13
12699 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT                                                              0x0
12700 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT                                                       0x1
12701 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT                                                      0x10
12702 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12703 #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK                                                                0x00000001L
12704 #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK                                                         0x0000FFFEL
12705 #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK                                                        0x00FF0000L
12706 #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12707 //SPI_RESOURCE_RESERVE_EN_CU_14
12708 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT                                                              0x0
12709 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT                                                       0x1
12710 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT                                                      0x10
12711 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12712 #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK                                                                0x00000001L
12713 #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK                                                         0x0000FFFEL
12714 #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK                                                        0x00FF0000L
12715 #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12716 //SPI_RESOURCE_RESERVE_EN_CU_15
12717 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT                                                              0x0
12718 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT                                                       0x1
12719 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT                                                      0x10
12720 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT                                              0x18
12721 #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK                                                                0x00000001L
12722 #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK                                                         0x0000FFFEL
12723 #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK                                                        0x00FF0000L
12724 #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK                                                0x01000000L
12725 //SPI_COMPUTE_WF_CTX_SAVE
12726 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT                                                              0x0
12727 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT                                                      0x1
12728 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT                                                     0x2
12729 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT                                                          0x1e
12730 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT                                                             0x1f
12731 #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK                                                                0x00000001L
12732 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK                                                        0x00000002L
12733 #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK                                                       0x00000004L
12734 #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK                                                            0x40000000L
12735 #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK                                                               0x80000000L
12736 //SPI_ARB_CNTL_0
12737 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT                                                                 0x0
12738 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT                                                                 0x4
12739 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT                                                                 0x8
12740 #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK                                                                   0x0000000FL
12741 #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK                                                                   0x000000F0L
12742 #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK                                                                   0x00000F00L
12743 
12744 
12745 // addressBlock: gc_cpphqddec
12746 //CP_HQD_GFX_CONTROL
12747 #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT                                                                    0x0
12748 #define CP_HQD_GFX_CONTROL__MISC__SHIFT                                                                       0x4
12749 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT                                                          0xf
12750 #define CP_HQD_GFX_CONTROL__MESSAGE_MASK                                                                      0x0000000FL
12751 #define CP_HQD_GFX_CONTROL__MISC_MASK                                                                         0x00007FF0L
12752 #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK                                                            0x00008000L
12753 //CP_HQD_GFX_STATUS
12754 #define CP_HQD_GFX_STATUS__STATUS__SHIFT                                                                      0x0
12755 #define CP_HQD_GFX_STATUS__STATUS_MASK                                                                        0x0000FFFFL
12756 //CP_HPD_ROQ_OFFSETS
12757 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT                                                                  0x0
12758 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT                                                                  0x8
12759 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT                                                                  0x10
12760 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK                                                                    0x00000007L
12761 #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK                                                                    0x00003F00L
12762 #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK                                                                    0x003F0000L
12763 //CP_HPD_STATUS0
12764 #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT                                                                    0x0
12765 #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT                                                                   0x5
12766 #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT                                                                0x8
12767 #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT                                                                   0x10
12768 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT                                                           0x11
12769 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT                                                             0x12
12770 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT                                                              0x14
12771 #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT                                                                    0x1f
12772 #define CP_HPD_STATUS0__QUEUE_STATE_MASK                                                                      0x0000001FL
12773 #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK                                                                     0x000000E0L
12774 #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK                                                                  0x0000FF00L
12775 #define CP_HPD_STATUS0__FETCHING_MQD_MASK                                                                     0x00010000L
12776 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK                                                             0x00020000L
12777 #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK                                                               0x00040000L
12778 #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK                                                                0x01F00000L
12779 #define CP_HPD_STATUS0__FORCE_QUEUE_MASK                                                                      0x80000000L
12780 //CP_HPD_UTCL1_CNTL
12781 #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT                                                                      0x0
12782 #define CP_HPD_UTCL1_CNTL__SELECT_MASK                                                                        0x0000000FL
12783 //CP_HPD_UTCL1_ERROR
12784 #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT                                                                    0x0
12785 #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT                                                                       0x10
12786 #define CP_HPD_UTCL1_ERROR__VMID__SHIFT                                                                       0x14
12787 #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK                                                                      0x0000FFFFL
12788 #define CP_HPD_UTCL1_ERROR__TYPE_MASK                                                                         0x00010000L
12789 #define CP_HPD_UTCL1_ERROR__VMID_MASK                                                                         0x00F00000L
12790 //CP_HPD_UTCL1_ERROR_ADDR
12791 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT                                                                  0xc
12792 #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK                                                                    0xFFFFF000L
12793 //CP_MQD_BASE_ADDR
12794 #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT                                                                    0x2
12795 #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK                                                                      0xFFFFFFFCL
12796 //CP_MQD_BASE_ADDR_HI
12797 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                              0x0
12798 #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                                0x0000FFFFL
12799 //CP_HQD_ACTIVE
12800 #define CP_HQD_ACTIVE__ACTIVE__SHIFT                                                                          0x0
12801 #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT                                                                       0x1
12802 #define CP_HQD_ACTIVE__ACTIVE_MASK                                                                            0x00000001L
12803 #define CP_HQD_ACTIVE__BUSY_GATE_MASK                                                                         0x00000002L
12804 //CP_HQD_VMID
12805 #define CP_HQD_VMID__VMID__SHIFT                                                                              0x0
12806 #define CP_HQD_VMID__IB_VMID__SHIFT                                                                           0x8
12807 #define CP_HQD_VMID__VQID__SHIFT                                                                              0x10
12808 #define CP_HQD_VMID__VMID_MASK                                                                                0x0000000FL
12809 #define CP_HQD_VMID__IB_VMID_MASK                                                                             0x00000F00L
12810 #define CP_HQD_VMID__VQID_MASK                                                                                0x03FF0000L
12811 //CP_HQD_PERSISTENT_STATE
12812 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT                                                           0x0
12813 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT                                                          0x8
12814 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT                                                     0x15
12815 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT                                                      0x16
12816 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT                                                      0x17
12817 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT                                                     0x18
12818 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT                                                      0x19
12819 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT                                                     0x1a
12820 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT                                                  0x1b
12821 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT                                                        0x1c
12822 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT                                                        0x1d
12823 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT                                                          0x1e
12824 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT                                                           0x1f
12825 #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK                                                             0x00000001L
12826 #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK                                                            0x0003FF00L
12827 #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK                                                       0x00200000L
12828 #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK                                                        0x00400000L
12829 #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK                                                        0x00800000L
12830 #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK                                                       0x01000000L
12831 #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK                                                        0x02000000L
12832 #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK                                                       0x04000000L
12833 #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK                                                    0x08000000L
12834 #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK                                                          0x10000000L
12835 #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK                                                          0x20000000L
12836 #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK                                                            0x40000000L
12837 #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK                                                             0x80000000L
12838 //CP_HQD_PIPE_PRIORITY
12839 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT                                                            0x0
12840 #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK                                                              0x00000003L
12841 //CP_HQD_QUEUE_PRIORITY
12842 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT                                                          0x0
12843 #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK                                                            0x0000000FL
12844 //CP_HQD_QUANTUM
12845 #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT                                                                     0x0
12846 #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT                                                                  0x4
12847 #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT                                                               0x8
12848 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT                                                                 0x1f
12849 #define CP_HQD_QUANTUM__QUANTUM_EN_MASK                                                                       0x00000001L
12850 #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK                                                                    0x00000010L
12851 #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK                                                                 0x00003F00L
12852 #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK                                                                   0x80000000L
12853 //CP_HQD_PQ_BASE
12854 #define CP_HQD_PQ_BASE__ADDR__SHIFT                                                                           0x0
12855 #define CP_HQD_PQ_BASE__ADDR_MASK                                                                             0xFFFFFFFFL
12856 //CP_HQD_PQ_BASE_HI
12857 #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT                                                                     0x0
12858 #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK                                                                       0x000000FFL
12859 //CP_HQD_PQ_RPTR
12860 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
12861 #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK                                                                  0xFFFFFFFFL
12862 //CP_HQD_PQ_RPTR_REPORT_ADDR
12863 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT                                                   0x2
12864 #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK                                                     0xFFFFFFFCL
12865 //CP_HQD_PQ_RPTR_REPORT_ADDR_HI
12866 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT                                             0x0
12867 #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK                                               0x0000FFFFL
12868 //CP_HQD_PQ_WPTR_POLL_ADDR
12869 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT                                                            0x3
12870 #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK                                                              0xFFFFFFF8L
12871 //CP_HQD_PQ_WPTR_POLL_ADDR_HI
12872 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT                                                      0x0
12873 #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK                                                        0x0000FFFFL
12874 //CP_HQD_PQ_DOORBELL_CONTROL
12875 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT                                                      0x0
12876 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT                                                  0x1
12877 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT                                                    0x2
12878 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT                                                    0x1c
12879 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT                                                  0x1d
12880 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT                                                        0x1e
12881 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT                                                       0x1f
12882 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK                                                        0x00000001L
12883 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK                                                    0x00000002L
12884 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK                                                      0x0FFFFFFCL
12885 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK                                                      0x10000000L
12886 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK                                                    0x20000000L
12887 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK                                                          0x40000000L
12888 #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK                                                         0x80000000L
12889 //CP_HQD_PQ_CONTROL
12890 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT                                                                  0x0
12891 #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT                                                                  0x6
12892 #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT                                                                  0x7
12893 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT                                                             0x8
12894 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT                                                               0xe
12895 #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT                                                                    0xf
12896 #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT                                                                0x10
12897 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT                                                                 0x11
12898 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT                                                              0x14
12899 #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT                                                                 0x17
12900 #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT                                                                0x18
12901 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT                                                             0x19
12902 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT                                                              0x1b
12903 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT                                                              0x1c
12904 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT                                                              0x1d
12905 #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT                                                                  0x1e
12906 #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT                                                                   0x1f
12907 #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK                                                                    0x0000003FL
12908 #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK                                                                    0x00000040L
12909 #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK                                                                    0x00000080L
12910 #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK                                                               0x00003F00L
12911 #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK                                                                 0x00004000L
12912 #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK                                                                      0x00008000L
12913 #define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK                                                                  0x00010000L
12914 #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK                                                                   0x00060000L
12915 #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK                                                                0x00300000L
12916 #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK                                                                   0x00800000L
12917 #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK                                                                  0x01000000L
12918 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK                                                               0x06000000L
12919 #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK                                                                0x08000000L
12920 #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK                                                                0x10000000L
12921 #define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK                                                                0x20000000L
12922 #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK                                                                    0x40000000L
12923 #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK                                                                     0x80000000L
12924 //CP_HQD_IB_BASE_ADDR
12925 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT                                                              0x2
12926 #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK                                                                0xFFFFFFFCL
12927 //CP_HQD_IB_BASE_ADDR_HI
12928 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT                                                        0x0
12929 #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK                                                          0x0000FFFFL
12930 //CP_HQD_IB_RPTR
12931 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT                                                                0x0
12932 #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK                                                                  0x000FFFFFL
12933 //CP_HQD_IB_CONTROL
12934 #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT                                                                     0x0
12935 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT                                                           0x14
12936 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT                                                              0x17
12937 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT                                                             0x18
12938 #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT                                                               0x1f
12939 #define CP_HQD_IB_CONTROL__IB_SIZE_MASK                                                                       0x000FFFFFL
12940 #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK                                                             0x00300000L
12941 #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK                                                                0x00800000L
12942 #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK                                                               0x01000000L
12943 #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK                                                                 0x80000000L
12944 //CP_HQD_IQ_TIMER
12945 #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT                                                                     0x0
12946 #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT                                                                    0x8
12947 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT                                                              0xb
12948 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT                                                                0xc
12949 #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT                                                                   0xe
12950 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT                                                                0x10
12951 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT                                                                 0x16
12952 #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT                                                                   0x17
12953 #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT                                                                  0x18
12954 #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT                                                                    0x19
12955 #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT                                                                   0x1c
12956 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT                                                                 0x1d
12957 #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT                                                                 0x1e
12958 #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT                                                                        0x1f
12959 #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK                                                                       0x000000FFL
12960 #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK                                                                      0x00000700L
12961 #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK                                                                0x00000800L
12962 #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK                                                                  0x00003000L
12963 #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK                                                                     0x0000C000L
12964 #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK                                                                  0x003F0000L
12965 #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK                                                                   0x00400000L
12966 #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK                                                                     0x00800000L
12967 #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK                                                                    0x01000000L
12968 #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK                                                                      0x02000000L
12969 #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK                                                                     0x10000000L
12970 #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK                                                                   0x20000000L
12971 #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK                                                                   0x40000000L
12972 #define CP_HQD_IQ_TIMER__ACTIVE_MASK                                                                          0x80000000L
12973 //CP_HQD_IQ_RPTR
12974 #define CP_HQD_IQ_RPTR__OFFSET__SHIFT                                                                         0x0
12975 #define CP_HQD_IQ_RPTR__OFFSET_MASK                                                                           0x0000003FL
12976 //CP_HQD_DEQUEUE_REQUEST
12977 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT                                                            0x0
12978 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT                                                            0x4
12979 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT                                                            0x8
12980 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT                                                         0x9
12981 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT                                                         0xa
12982 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK                                                              0x00000007L
12983 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK                                                              0x00000010L
12984 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK                                                              0x00000100L
12985 #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK                                                           0x00000200L
12986 #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK                                                           0x00000400L
12987 //CP_HQD_DMA_OFFLOAD
12988 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                0x0
12989 #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK                                                                  0x00000001L
12990 //CP_HQD_OFFLOAD
12991 #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT                                                                    0x0
12992 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT                                                                 0x1
12993 #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT                                                                    0x2
12994 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT                                                                 0x3
12995 #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT                                                                    0x4
12996 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT                                                                 0x5
12997 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK                                                                      0x00000001L
12998 #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK                                                                   0x00000002L
12999 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK                                                                      0x00000004L
13000 #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK                                                                   0x00000008L
13001 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK                                                                      0x00000010L
13002 #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK                                                                   0x00000020L
13003 //CP_HQD_SEMA_CMD
13004 #define CP_HQD_SEMA_CMD__RETRY__SHIFT                                                                         0x0
13005 #define CP_HQD_SEMA_CMD__RESULT__SHIFT                                                                        0x1
13006 #define CP_HQD_SEMA_CMD__RETRY_MASK                                                                           0x00000001L
13007 #define CP_HQD_SEMA_CMD__RESULT_MASK                                                                          0x00000006L
13008 //CP_HQD_MSG_TYPE
13009 #define CP_HQD_MSG_TYPE__ACTION__SHIFT                                                                        0x0
13010 #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT                                                                    0x4
13011 #define CP_HQD_MSG_TYPE__ACTION_MASK                                                                          0x00000007L
13012 #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK                                                                      0x00000070L
13013 //CP_HQD_ATOMIC0_PREOP_LO
13014 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT                                                      0x0
13015 #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK                                                        0xFFFFFFFFL
13016 //CP_HQD_ATOMIC0_PREOP_HI
13017 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT                                                      0x0
13018 #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK                                                        0xFFFFFFFFL
13019 //CP_HQD_ATOMIC1_PREOP_LO
13020 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT                                                      0x0
13021 #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK                                                        0xFFFFFFFFL
13022 //CP_HQD_ATOMIC1_PREOP_HI
13023 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT                                                      0x0
13024 #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK                                                        0xFFFFFFFFL
13025 //CP_HQD_HQ_SCHEDULER0
13026 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT                                                                0x0
13027 #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK                                                                  0xFFFFFFFFL
13028 //CP_HQD_HQ_STATUS0
13029 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT                                                              0x0
13030 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT                                                           0x2
13031 #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT                                                                     0x4
13032 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT                                                            0x7
13033 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT                                                                  0x8
13034 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT                                                                0x9
13035 #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT                                                                  0xa
13036 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT                                                                  0x1e
13037 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT                                                           0x1f
13038 #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK                                                                0x00000003L
13039 #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK                                                             0x0000000CL
13040 #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK                                                                       0x00000070L
13041 #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK                                                              0x00000080L
13042 #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK                                                                    0x00000100L
13043 #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK                                                                  0x00000200L
13044 #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK                                                                    0x3FFFFC00L
13045 #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK                                                                    0x40000000L
13046 #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK                                                             0x80000000L
13047 //CP_HQD_HQ_CONTROL0
13048 #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT                                                                    0x0
13049 #define CP_HQD_HQ_CONTROL0__CONTROL_MASK                                                                      0xFFFFFFFFL
13050 //CP_HQD_HQ_SCHEDULER1
13051 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT                                                                0x0
13052 #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK                                                                  0xFFFFFFFFL
13053 //CP_MQD_CONTROL
13054 #define CP_MQD_CONTROL__VMID__SHIFT                                                                           0x0
13055 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT                                                                     0x8
13056 #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT                                                                 0xc
13057 #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT                                                              0xd
13058 #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT                                                                    0x17
13059 #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT                                                                   0x18
13060 #define CP_MQD_CONTROL__VMID_MASK                                                                             0x0000000FL
13061 #define CP_MQD_CONTROL__PRIV_STATE_MASK                                                                       0x00000100L
13062 #define CP_MQD_CONTROL__PROCESSING_MQD_MASK                                                                   0x00001000L
13063 #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK                                                                0x00002000L
13064 #define CP_MQD_CONTROL__EXE_DISABLE_MASK                                                                      0x00800000L
13065 #define CP_MQD_CONTROL__CACHE_POLICY_MASK                                                                     0x01000000L
13066 //CP_HQD_HQ_STATUS1
13067 #define CP_HQD_HQ_STATUS1__STATUS__SHIFT                                                                      0x0
13068 #define CP_HQD_HQ_STATUS1__STATUS_MASK                                                                        0xFFFFFFFFL
13069 //CP_HQD_HQ_CONTROL1
13070 #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT                                                                    0x0
13071 #define CP_HQD_HQ_CONTROL1__CONTROL_MASK                                                                      0xFFFFFFFFL
13072 //CP_HQD_EOP_BASE_ADDR
13073 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT                                                                0x0
13074 #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK                                                                  0xFFFFFFFFL
13075 //CP_HQD_EOP_BASE_ADDR_HI
13076 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT                                                          0x0
13077 #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK                                                            0x000000FFL
13078 //CP_HQD_EOP_CONTROL
13079 #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT                                                                   0x0
13080 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT                                                             0x8
13081 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT                                                             0xc
13082 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT                                                           0xd
13083 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT                                                           0xe
13084 #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT                                                               0x15
13085 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT                                                            0x16
13086 #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT                                                                0x17
13087 #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT                                                               0x18
13088 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT                                                             0x1d
13089 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT                                                               0x1f
13090 #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK                                                                     0x0000003FL
13091 #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK                                                               0x00000100L
13092 #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK                                                               0x00001000L
13093 #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK                                                             0x00002000L
13094 #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK                                                             0x00004000L
13095 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK                                                                 0x00200000L
13096 #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK                                                              0x00400000L
13097 #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK                                                                  0x00800000L
13098 #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK                                                                 0x01000000L
13099 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK                                                               0x60000000L
13100 #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK                                                                 0x80000000L
13101 //CP_HQD_EOP_RPTR
13102 #define CP_HQD_EOP_RPTR__RPTR__SHIFT                                                                          0x0
13103 #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT                                                                 0x1c
13104 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT                                                                  0x1d
13105 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT                                                             0x1e
13106 #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT                                                                  0x1f
13107 #define CP_HQD_EOP_RPTR__RPTR_MASK                                                                            0x00001FFFL
13108 #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK                                                                   0x10000000L
13109 #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK                                                                    0x20000000L
13110 #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK                                                               0x40000000L
13111 #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK                                                                    0x80000000L
13112 //CP_HQD_EOP_WPTR
13113 #define CP_HQD_EOP_WPTR__WPTR__SHIFT                                                                          0x0
13114 #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT                                                                     0xf
13115 #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT                                                                     0x10
13116 #define CP_HQD_EOP_WPTR__WPTR_MASK                                                                            0x00001FFFL
13117 #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK                                                                       0x00008000L
13118 #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK                                                                       0x1FFF0000L
13119 //CP_HQD_EOP_EVENTS
13120 #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT                                                                 0x0
13121 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT                                                       0x10
13122 #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK                                                                   0x00000FFFL
13123 #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK                                                         0x00010000L
13124 //CP_HQD_CTX_SAVE_BASE_ADDR_LO
13125 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT                                                             0xc
13126 #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK                                                               0xFFFFF000L
13127 //CP_HQD_CTX_SAVE_BASE_ADDR_HI
13128 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
13129 #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
13130 //CP_HQD_CTX_SAVE_CONTROL
13131 #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT                                                                0x3
13132 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT                                                           0x17
13133 #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK                                                                  0x00000008L
13134 #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK                                                             0x00800000L
13135 //CP_HQD_CNTL_STACK_OFFSET
13136 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT                                                               0x2
13137 #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK                                                                 0x00007FFCL
13138 //CP_HQD_CNTL_STACK_SIZE
13139 #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT                                                                   0xc
13140 #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK                                                                     0x00007000L
13141 //CP_HQD_WG_STATE_OFFSET
13142 #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT                                                                 0x2
13143 #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK                                                                   0x01FFFFFCL
13144 //CP_HQD_CTX_SAVE_SIZE
13145 #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT                                                                     0xc
13146 #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK                                                                       0x01FFF000L
13147 //CP_HQD_GDS_RESOURCE_STATE
13148 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT                                                         0x0
13149 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT                                                         0x1
13150 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT                                                            0x4
13151 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT                                                            0xc
13152 #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK                                                           0x00000001L
13153 #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK                                                           0x00000002L
13154 #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK                                                              0x000003F0L
13155 #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK                                                              0x0003F000L
13156 //CP_HQD_ERROR
13157 #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT                                                                     0x0
13158 #define CP_HQD_ERROR__SUA_ERROR__SHIFT                                                                        0x4
13159 #define CP_HQD_ERROR__AQL_ERROR__SHIFT                                                                        0x5
13160 #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT                                                                   0x8
13161 #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT                                                                   0x9
13162 #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT                                                                  0xa
13163 #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT                                                                   0xb
13164 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT                                                                 0xc
13165 #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT                                                                  0xd
13166 #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT                                                                  0xe
13167 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT                                                              0xf
13168 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT                                                              0x10
13169 #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT                                                                   0x11
13170 #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT                                                                   0x12
13171 #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT                                                                   0x13
13172 #define CP_HQD_ERROR__EDC_ERROR_ID_MASK                                                                       0x0000000FL
13173 #define CP_HQD_ERROR__SUA_ERROR_MASK                                                                          0x00000010L
13174 #define CP_HQD_ERROR__AQL_ERROR_MASK                                                                          0x00000020L
13175 #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK                                                                     0x00000100L
13176 #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK                                                                     0x00000200L
13177 #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK                                                                    0x00000400L
13178 #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK                                                                     0x00000800L
13179 #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK                                                                   0x00001000L
13180 #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK                                                                    0x00002000L
13181 #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK                                                                    0x00004000L
13182 #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK                                                                0x00008000L
13183 #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK                                                                0x00010000L
13184 #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK                                                                     0x00020000L
13185 #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK                                                                     0x00040000L
13186 #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK                                                                     0x00080000L
13187 //CP_HQD_EOP_WPTR_MEM
13188 #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT                                                                      0x0
13189 #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK                                                                        0x00001FFFL
13190 //CP_HQD_AQL_CONTROL
13191 #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT                                                                   0x0
13192 #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT                                                                0xf
13193 #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT                                                                   0x10
13194 #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT                                                                0x1f
13195 #define CP_HQD_AQL_CONTROL__CONTROL0_MASK                                                                     0x00007FFFL
13196 #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK                                                                  0x00008000L
13197 #define CP_HQD_AQL_CONTROL__CONTROL1_MASK                                                                     0x7FFF0000L
13198 #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK                                                                  0x80000000L
13199 //CP_HQD_PQ_WPTR_LO
13200 #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT                                                                      0x0
13201 #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK                                                                        0xFFFFFFFFL
13202 //CP_HQD_PQ_WPTR_HI
13203 #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT                                                                        0x0
13204 #define CP_HQD_PQ_WPTR_HI__DATA_MASK                                                                          0xFFFFFFFFL
13205 
13206 
13207 // addressBlock: gc_didtdec
13208 //DIDT_IND_INDEX
13209 #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT                                                                 0x0
13210 #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK                                                                   0xFFFFFFFFL
13211 //DIDT_IND_DATA
13212 #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT                                                                   0x0
13213 #define DIDT_IND_DATA__DIDT_IND_DATA_MASK                                                                     0xFFFFFFFFL
13214 
13215 
13216 // addressBlock: gc_gccacdec
13217 //GC_CAC_CTRL_1
13218 #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT                                                                      0x0
13219 #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT                                                                      0x18
13220 #define GC_CAC_CTRL_1__CAC_WINDOW_MASK                                                                        0x00FFFFFFL
13221 #define GC_CAC_CTRL_1__TDP_WINDOW_MASK                                                                        0xFF000000L
13222 //GC_CAC_CTRL_2
13223 #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT                                                                      0x0
13224 #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT                                                            0x1
13225 #define GC_CAC_CTRL_2__UNUSED_0__SHIFT                                                                        0x2
13226 #define GC_CAC_CTRL_2__CAC_ENABLE_MASK                                                                        0x00000001L
13227 #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK                                                              0x00000002L
13228 #define GC_CAC_CTRL_2__UNUSED_0_MASK                                                                          0xFFFFFFFCL
13229 //GC_CAC_CGTT_CLK_CTRL
13230 #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
13231 #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
13232 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                        0x1e
13233 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                        0x1f
13234 #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
13235 #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
13236 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                          0x40000000L
13237 #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                          0x80000000L
13238 //GC_CAC_AGGR_LOWER
13239 #define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT                                                                   0x0
13240 #define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK                                                                     0xFFFFFFFFL
13241 //GC_CAC_AGGR_UPPER
13242 #define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT                                                                  0x0
13243 #define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK                                                                    0xFFFFFFFFL
13244 //GC_CAC_SOFT_CTRL
13245 #define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT                                                                    0x0
13246 #define GC_CAC_SOFT_CTRL__UNUSED__SHIFT                                                                       0x1
13247 #define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK                                                                      0x00000001L
13248 #define GC_CAC_SOFT_CTRL__UNUSED_MASK                                                                         0xFFFFFFFEL
13249 //GC_DIDT_CTRL0
13250 #define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
13251 #define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
13252 #define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT                                                                     0x3
13253 #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
13254 #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x5
13255 #define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
13256 #define GC_DIDT_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
13257 #define GC_DIDT_CTRL0__DIDT_SW_RST_MASK                                                                       0x00000008L
13258 #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
13259 #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001E0L
13260 //GC_DIDT_CTRL1
13261 #define GC_DIDT_CTRL1__MIN_POWER__SHIFT                                                                       0x0
13262 #define GC_DIDT_CTRL1__MAX_POWER__SHIFT                                                                       0x10
13263 #define GC_DIDT_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
13264 #define GC_DIDT_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
13265 //GC_DIDT_CTRL2
13266 #define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
13267 #define GC_DIDT_CTRL2__UNUSED_0__SHIFT                                                                        0xe
13268 #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
13269 #define GC_DIDT_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
13270 #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
13271 #define GC_DIDT_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
13272 #define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
13273 #define GC_DIDT_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
13274 #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
13275 #define GC_DIDT_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
13276 #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
13277 #define GC_DIDT_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
13278 //GC_DIDT_WEIGHT
13279 #define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT                                                                      0x0
13280 #define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT                                                                      0x8
13281 #define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT                                                                      0x10
13282 #define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT                                                                     0x18
13283 #define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK                                                                        0x000000FFL
13284 #define GC_DIDT_WEIGHT__DB_WEIGHT_MASK                                                                        0x0000FF00L
13285 #define GC_DIDT_WEIGHT__TD_WEIGHT_MASK                                                                        0x00FF0000L
13286 #define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK                                                                       0xFF000000L
13287 //GC_DIDT_WEIGHT_1
13288 #define GC_DIDT_WEIGHT_1__DBR_WEIGHT__SHIFT                                                                   0x0
13289 #define GC_DIDT_WEIGHT_1__DBR_WEIGHT_MASK                                                                     0x000000FFL
13290 //GC_EDC_CTRL
13291 #define GC_EDC_CTRL__EDC_EN__SHIFT                                                                            0x0
13292 #define GC_EDC_CTRL__EDC_SW_RST__SHIFT                                                                        0x1
13293 #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                               0x2
13294 #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                                   0x3
13295 #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                       0x4
13296 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                          0x9
13297 #define GC_EDC_CTRL__UNUSED_0__SHIFT                                                                          0xa
13298 #define GC_EDC_CTRL__EDC_EN_MASK                                                                              0x00000001L
13299 #define GC_EDC_CTRL__EDC_SW_RST_MASK                                                                          0x00000002L
13300 #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                                 0x00000004L
13301 #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                     0x00000008L
13302 #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                         0x000001F0L
13303 #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                            0x00000200L
13304 #define GC_EDC_CTRL__UNUSED_0_MASK                                                                            0xFFFFFC00L
13305 //GC_EDC_THRESHOLD
13306 #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                                0x0
13307 #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                                  0xFFFFFFFFL
13308 //GC_EDC_STATUS
13309 #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                              0x0
13310 #define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT                                                         0x3
13311 #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                                0x00000007L
13312 #define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK                                                           0x03FFFFF8L
13313 //GC_EDC_OVERFLOW
13314 #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                              0x0
13315 #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                           0x1
13316 #define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT                                                      0x11
13317 #define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT                                                                   0x12
13318 #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                                0x00000001L
13319 #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                             0x0001FFFEL
13320 #define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK                                                        0x00020000L
13321 #define GC_EDC_OVERFLOW__PSM_COUNTER_MASK                                                                     0xFFFC0000L
13322 //GC_EDC_ROLLING_POWER_DELTA
13323 #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                            0x0
13324 #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                              0xFFFFFFFFL
13325 //GC_DIDT_DROOP_CTRL
13326 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT                                                        0x0
13327 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT                                                       0x1
13328 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT                                                     0xf
13329 #define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT                                                             0x13
13330 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT                                                  0x1f
13331 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK                                                          0x00000001L
13332 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK                                                         0x00007FFEL
13333 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK                                                       0x00078000L
13334 #define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK                                                               0x00080000L
13335 #define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK                                                    0x80000000L
13336 //GC_EDC_DROOP_CTRL
13337 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT                                                          0x0
13338 #define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT                                                         0x1
13339 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT                                                       0xf
13340 #define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT                                                                 0x14
13341 #define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT                                                               0x15
13342 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK                                                            0x00000001L
13343 #define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK                                                           0x00007FFEL
13344 #define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK                                                         0x000F8000L
13345 #define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK                                                                   0x00100000L
13346 #define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK                                                                 0x00200000L
13347 //GC_CAC_IND_INDEX
13348 #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT                                                              0x0
13349 #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
13350 //GC_CAC_IND_DATA
13351 #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT                                                               0x0
13352 #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
13353 //SE_CAC_CGTT_CLK_CTRL
13354 #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
13355 #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
13356 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                        0x1e
13357 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                        0x1f
13358 #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
13359 #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
13360 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                          0x40000000L
13361 #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                          0x80000000L
13362 //SE_CAC_IND_INDEX
13363 #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT                                                              0x0
13364 #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK                                                                0xFFFFFFFFL
13365 //SE_CAC_IND_DATA
13366 #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT                                                               0x0
13367 #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK                                                                 0xFFFFFFFFL
13368 
13369 
13370 // addressBlock: gc_tcpdec
13371 //TCP_WATCH0_ADDR_H
13372 #define TCP_WATCH0_ADDR_H__ADDR__SHIFT                                                                        0x0
13373 #define TCP_WATCH0_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13374 //TCP_WATCH0_ADDR_L
13375 #define TCP_WATCH0_ADDR_L__ADDR__SHIFT                                                                        0x6
13376 #define TCP_WATCH0_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13377 //TCP_WATCH0_CNTL
13378 #define TCP_WATCH0_CNTL__MASK__SHIFT                                                                          0x0
13379 #define TCP_WATCH0_CNTL__VMID__SHIFT                                                                          0x18
13380 #define TCP_WATCH0_CNTL__ATC__SHIFT                                                                           0x1c
13381 #define TCP_WATCH0_CNTL__MODE__SHIFT                                                                          0x1d
13382 #define TCP_WATCH0_CNTL__VALID__SHIFT                                                                         0x1f
13383 #define TCP_WATCH0_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13384 #define TCP_WATCH0_CNTL__VMID_MASK                                                                            0x0F000000L
13385 #define TCP_WATCH0_CNTL__ATC_MASK                                                                             0x10000000L
13386 #define TCP_WATCH0_CNTL__MODE_MASK                                                                            0x60000000L
13387 #define TCP_WATCH0_CNTL__VALID_MASK                                                                           0x80000000L
13388 //TCP_WATCH1_ADDR_H
13389 #define TCP_WATCH1_ADDR_H__ADDR__SHIFT                                                                        0x0
13390 #define TCP_WATCH1_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13391 //TCP_WATCH1_ADDR_L
13392 #define TCP_WATCH1_ADDR_L__ADDR__SHIFT                                                                        0x6
13393 #define TCP_WATCH1_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13394 //TCP_WATCH1_CNTL
13395 #define TCP_WATCH1_CNTL__MASK__SHIFT                                                                          0x0
13396 #define TCP_WATCH1_CNTL__VMID__SHIFT                                                                          0x18
13397 #define TCP_WATCH1_CNTL__ATC__SHIFT                                                                           0x1c
13398 #define TCP_WATCH1_CNTL__MODE__SHIFT                                                                          0x1d
13399 #define TCP_WATCH1_CNTL__VALID__SHIFT                                                                         0x1f
13400 #define TCP_WATCH1_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13401 #define TCP_WATCH1_CNTL__VMID_MASK                                                                            0x0F000000L
13402 #define TCP_WATCH1_CNTL__ATC_MASK                                                                             0x10000000L
13403 #define TCP_WATCH1_CNTL__MODE_MASK                                                                            0x60000000L
13404 #define TCP_WATCH1_CNTL__VALID_MASK                                                                           0x80000000L
13405 //TCP_WATCH2_ADDR_H
13406 #define TCP_WATCH2_ADDR_H__ADDR__SHIFT                                                                        0x0
13407 #define TCP_WATCH2_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13408 //TCP_WATCH2_ADDR_L
13409 #define TCP_WATCH2_ADDR_L__ADDR__SHIFT                                                                        0x6
13410 #define TCP_WATCH2_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13411 //TCP_WATCH2_CNTL
13412 #define TCP_WATCH2_CNTL__MASK__SHIFT                                                                          0x0
13413 #define TCP_WATCH2_CNTL__VMID__SHIFT                                                                          0x18
13414 #define TCP_WATCH2_CNTL__ATC__SHIFT                                                                           0x1c
13415 #define TCP_WATCH2_CNTL__MODE__SHIFT                                                                          0x1d
13416 #define TCP_WATCH2_CNTL__VALID__SHIFT                                                                         0x1f
13417 #define TCP_WATCH2_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13418 #define TCP_WATCH2_CNTL__VMID_MASK                                                                            0x0F000000L
13419 #define TCP_WATCH2_CNTL__ATC_MASK                                                                             0x10000000L
13420 #define TCP_WATCH2_CNTL__MODE_MASK                                                                            0x60000000L
13421 #define TCP_WATCH2_CNTL__VALID_MASK                                                                           0x80000000L
13422 //TCP_WATCH3_ADDR_H
13423 #define TCP_WATCH3_ADDR_H__ADDR__SHIFT                                                                        0x0
13424 #define TCP_WATCH3_ADDR_H__ADDR_MASK                                                                          0x0000FFFFL
13425 //TCP_WATCH3_ADDR_L
13426 #define TCP_WATCH3_ADDR_L__ADDR__SHIFT                                                                        0x6
13427 #define TCP_WATCH3_ADDR_L__ADDR_MASK                                                                          0xFFFFFFC0L
13428 //TCP_WATCH3_CNTL
13429 #define TCP_WATCH3_CNTL__MASK__SHIFT                                                                          0x0
13430 #define TCP_WATCH3_CNTL__VMID__SHIFT                                                                          0x18
13431 #define TCP_WATCH3_CNTL__ATC__SHIFT                                                                           0x1c
13432 #define TCP_WATCH3_CNTL__MODE__SHIFT                                                                          0x1d
13433 #define TCP_WATCH3_CNTL__VALID__SHIFT                                                                         0x1f
13434 #define TCP_WATCH3_CNTL__MASK_MASK                                                                            0x00FFFFFFL
13435 #define TCP_WATCH3_CNTL__VMID_MASK                                                                            0x0F000000L
13436 #define TCP_WATCH3_CNTL__ATC_MASK                                                                             0x10000000L
13437 #define TCP_WATCH3_CNTL__MODE_MASK                                                                            0x60000000L
13438 #define TCP_WATCH3_CNTL__VALID_MASK                                                                           0x80000000L
13439 //TCP_GATCL1_CNTL
13440 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT                                                           0x19
13441 #define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT                                                                    0x1a
13442 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT                                                                0x1b
13443 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
13444 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
13445 #define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK                                                             0x02000000L
13446 #define TCP_GATCL1_CNTL__FORCE_MISS_MASK                                                                      0x04000000L
13447 #define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK                                                                  0x08000000L
13448 #define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
13449 #define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
13450 //TCP_ATC_EDC_GATCL1_CNT
13451 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT                                                               0x0
13452 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK                                                                 0x000000FFL
13453 //TCP_GATCL1_DSM_CNTL
13454 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT                                      0x0
13455 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT                                      0x1
13456 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT                                          0x2
13457 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK                                        0x00000001L
13458 #define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK                                        0x00000002L
13459 #define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK                                            0x00000004L
13460 //TCP_CNTL2
13461 #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT                                                                   0x0
13462 #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK                                                                     0x000000FFL
13463 //TCP_UTCL1_CNTL1
13464 #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT                                                              0x0
13465 #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT                                                             0x1
13466 #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT                                                               0x2
13467 #define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT                                                                     0x3
13468 #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT                                                               0x5
13469 #define TCP_UTCL1_CNTL1__CLIENTID__SHIFT                                                                      0x7
13470 #define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT                                                                  0x13
13471 #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT                                                              0x17
13472 #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT                                                                0x18
13473 #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT                                                    0x19
13474 #define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT                                                                    0x1a
13475 #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT                                                        0x1c
13476 #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT                                                        0x1e
13477 #define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK                                                                0x00000001L
13478 #define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK                                                               0x00000002L
13479 #define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK                                                                 0x00000004L
13480 #define TCP_UTCL1_CNTL1__RESP_MODE_MASK                                                                       0x00000018L
13481 #define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK                                                                 0x00000060L
13482 #define TCP_UTCL1_CNTL1__CLIENTID_MASK                                                                        0x0000FF80L
13483 #define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK                                                                    0x00780000L
13484 #define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK                                                                0x00800000L
13485 #define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK                                                                  0x01000000L
13486 #define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK                                                      0x02000000L
13487 #define TCP_UTCL1_CNTL1__FORCE_MISS_MASK                                                                      0x04000000L
13488 #define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK                                                          0x30000000L
13489 #define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK                                                          0xC0000000L
13490 //TCP_UTCL1_CNTL2
13491 #define TCP_UTCL1_CNTL2__SPARE__SHIFT                                                                         0x0
13492 #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT                                                                0x9
13493 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT                                                                0xa
13494 #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT                                                                0xc
13495 #define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT                                                                   0xe
13496 #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT                                                           0xf
13497 #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT                                                          0x1a
13498 #define TCP_UTCL1_CNTL2__SPARE_MASK                                                                           0x000000FFL
13499 #define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK                                                                  0x00000200L
13500 #define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK                                                                  0x00000400L
13501 #define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK                                                                  0x00001000L
13502 #define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK                                                                     0x00004000L
13503 #define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK                                                             0x00008000L
13504 #define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK                                                            0x04000000L
13505 //TCP_UTCL1_STATUS
13506 #define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
13507 #define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
13508 #define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
13509 #define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
13510 #define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
13511 #define TCP_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
13512 //TCP_PERFCOUNTER_FILTER
13513 #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT                                                                 0x0
13514 #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT                                                                   0x1
13515 #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT                                                                    0x2
13516 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT                                                            0x5
13517 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT                                                             0xb
13518 #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT                                                                0xf
13519 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT                                                            0x14
13520 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT                                                            0x16
13521 #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT                                                                    0x19
13522 #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT                                                                    0x1a
13523 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT                                                     0x1b
13524 #define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT                                                              0x1c
13525 #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK                                                                   0x00000001L
13526 #define TCP_PERFCOUNTER_FILTER__FLAT_MASK                                                                     0x00000002L
13527 #define TCP_PERFCOUNTER_FILTER__DIM_MASK                                                                      0x0000001CL
13528 #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK                                                              0x000007E0L
13529 #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK                                                               0x00007800L
13530 #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK                                                                  0x000F8000L
13531 #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK                                                              0x00300000L
13532 #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK                                                              0x01C00000L
13533 #define TCP_PERFCOUNTER_FILTER__GLC_MASK                                                                      0x02000000L
13534 #define TCP_PERFCOUNTER_FILTER__SLC_MASK                                                                      0x04000000L
13535 #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK                                                       0x08000000L
13536 #define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK                                                                0x70000000L
13537 //TCP_PERFCOUNTER_FILTER_EN
13538 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT                                                              0x0
13539 #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT                                                                0x1
13540 #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT                                                                 0x2
13541 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT                                                         0x3
13542 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT                                                          0x4
13543 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT                                                             0x5
13544 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT                                                         0x6
13545 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT                                                         0x7
13546 #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT                                                                 0x8
13547 #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT                                                                 0x9
13548 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT                                                  0xa
13549 #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT                                                           0xb
13550 #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK                                                                0x00000001L
13551 #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK                                                                  0x00000002L
13552 #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK                                                                   0x00000004L
13553 #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK                                                           0x00000008L
13554 #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK                                                            0x00000010L
13555 #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK                                                               0x00000020L
13556 #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK                                                           0x00000040L
13557 #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK                                                           0x00000080L
13558 #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK                                                                   0x00000100L
13559 #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK                                                                   0x00000200L
13560 #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK                                                    0x00000400L
13561 #define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK                                                             0x00000800L
13562 
13563 
13564 // addressBlock: gc_gdspdec
13565 //GDS_VMID0_BASE
13566 #define GDS_VMID0_BASE__BASE__SHIFT                                                                           0x0
13567 #define GDS_VMID0_BASE__BASE_MASK                                                                             0x0000FFFFL
13568 //GDS_VMID0_SIZE
13569 #define GDS_VMID0_SIZE__SIZE__SHIFT                                                                           0x0
13570 #define GDS_VMID0_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13571 //GDS_VMID1_BASE
13572 #define GDS_VMID1_BASE__BASE__SHIFT                                                                           0x0
13573 #define GDS_VMID1_BASE__BASE_MASK                                                                             0x0000FFFFL
13574 //GDS_VMID1_SIZE
13575 #define GDS_VMID1_SIZE__SIZE__SHIFT                                                                           0x0
13576 #define GDS_VMID1_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13577 //GDS_VMID2_BASE
13578 #define GDS_VMID2_BASE__BASE__SHIFT                                                                           0x0
13579 #define GDS_VMID2_BASE__BASE_MASK                                                                             0x0000FFFFL
13580 //GDS_VMID2_SIZE
13581 #define GDS_VMID2_SIZE__SIZE__SHIFT                                                                           0x0
13582 #define GDS_VMID2_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13583 //GDS_VMID3_BASE
13584 #define GDS_VMID3_BASE__BASE__SHIFT                                                                           0x0
13585 #define GDS_VMID3_BASE__BASE_MASK                                                                             0x0000FFFFL
13586 //GDS_VMID3_SIZE
13587 #define GDS_VMID3_SIZE__SIZE__SHIFT                                                                           0x0
13588 #define GDS_VMID3_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13589 //GDS_VMID4_BASE
13590 #define GDS_VMID4_BASE__BASE__SHIFT                                                                           0x0
13591 #define GDS_VMID4_BASE__BASE_MASK                                                                             0x0000FFFFL
13592 //GDS_VMID4_SIZE
13593 #define GDS_VMID4_SIZE__SIZE__SHIFT                                                                           0x0
13594 #define GDS_VMID4_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13595 //GDS_VMID5_BASE
13596 #define GDS_VMID5_BASE__BASE__SHIFT                                                                           0x0
13597 #define GDS_VMID5_BASE__BASE_MASK                                                                             0x0000FFFFL
13598 //GDS_VMID5_SIZE
13599 #define GDS_VMID5_SIZE__SIZE__SHIFT                                                                           0x0
13600 #define GDS_VMID5_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13601 //GDS_VMID6_BASE
13602 #define GDS_VMID6_BASE__BASE__SHIFT                                                                           0x0
13603 #define GDS_VMID6_BASE__BASE_MASK                                                                             0x0000FFFFL
13604 //GDS_VMID6_SIZE
13605 #define GDS_VMID6_SIZE__SIZE__SHIFT                                                                           0x0
13606 #define GDS_VMID6_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13607 //GDS_VMID7_BASE
13608 #define GDS_VMID7_BASE__BASE__SHIFT                                                                           0x0
13609 #define GDS_VMID7_BASE__BASE_MASK                                                                             0x0000FFFFL
13610 //GDS_VMID7_SIZE
13611 #define GDS_VMID7_SIZE__SIZE__SHIFT                                                                           0x0
13612 #define GDS_VMID7_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13613 //GDS_VMID8_BASE
13614 #define GDS_VMID8_BASE__BASE__SHIFT                                                                           0x0
13615 #define GDS_VMID8_BASE__BASE_MASK                                                                             0x0000FFFFL
13616 //GDS_VMID8_SIZE
13617 #define GDS_VMID8_SIZE__SIZE__SHIFT                                                                           0x0
13618 #define GDS_VMID8_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13619 //GDS_VMID9_BASE
13620 #define GDS_VMID9_BASE__BASE__SHIFT                                                                           0x0
13621 #define GDS_VMID9_BASE__BASE_MASK                                                                             0x0000FFFFL
13622 //GDS_VMID9_SIZE
13623 #define GDS_VMID9_SIZE__SIZE__SHIFT                                                                           0x0
13624 #define GDS_VMID9_SIZE__SIZE_MASK                                                                             0x0001FFFFL
13625 //GDS_VMID10_BASE
13626 #define GDS_VMID10_BASE__BASE__SHIFT                                                                          0x0
13627 #define GDS_VMID10_BASE__BASE_MASK                                                                            0x0000FFFFL
13628 //GDS_VMID10_SIZE
13629 #define GDS_VMID10_SIZE__SIZE__SHIFT                                                                          0x0
13630 #define GDS_VMID10_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13631 //GDS_VMID11_BASE
13632 #define GDS_VMID11_BASE__BASE__SHIFT                                                                          0x0
13633 #define GDS_VMID11_BASE__BASE_MASK                                                                            0x0000FFFFL
13634 //GDS_VMID11_SIZE
13635 #define GDS_VMID11_SIZE__SIZE__SHIFT                                                                          0x0
13636 #define GDS_VMID11_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13637 //GDS_VMID12_BASE
13638 #define GDS_VMID12_BASE__BASE__SHIFT                                                                          0x0
13639 #define GDS_VMID12_BASE__BASE_MASK                                                                            0x0000FFFFL
13640 //GDS_VMID12_SIZE
13641 #define GDS_VMID12_SIZE__SIZE__SHIFT                                                                          0x0
13642 #define GDS_VMID12_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13643 //GDS_VMID13_BASE
13644 #define GDS_VMID13_BASE__BASE__SHIFT                                                                          0x0
13645 #define GDS_VMID13_BASE__BASE_MASK                                                                            0x0000FFFFL
13646 //GDS_VMID13_SIZE
13647 #define GDS_VMID13_SIZE__SIZE__SHIFT                                                                          0x0
13648 #define GDS_VMID13_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13649 //GDS_VMID14_BASE
13650 #define GDS_VMID14_BASE__BASE__SHIFT                                                                          0x0
13651 #define GDS_VMID14_BASE__BASE_MASK                                                                            0x0000FFFFL
13652 //GDS_VMID14_SIZE
13653 #define GDS_VMID14_SIZE__SIZE__SHIFT                                                                          0x0
13654 #define GDS_VMID14_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13655 //GDS_VMID15_BASE
13656 #define GDS_VMID15_BASE__BASE__SHIFT                                                                          0x0
13657 #define GDS_VMID15_BASE__BASE_MASK                                                                            0x0000FFFFL
13658 //GDS_VMID15_SIZE
13659 #define GDS_VMID15_SIZE__SIZE__SHIFT                                                                          0x0
13660 #define GDS_VMID15_SIZE__SIZE_MASK                                                                            0x0001FFFFL
13661 //GDS_GWS_VMID0
13662 #define GDS_GWS_VMID0__BASE__SHIFT                                                                            0x0
13663 #define GDS_GWS_VMID0__SIZE__SHIFT                                                                            0x10
13664 #define GDS_GWS_VMID0__BASE_MASK                                                                              0x0000003FL
13665 #define GDS_GWS_VMID0__SIZE_MASK                                                                              0x007F0000L
13666 //GDS_GWS_VMID1
13667 #define GDS_GWS_VMID1__BASE__SHIFT                                                                            0x0
13668 #define GDS_GWS_VMID1__SIZE__SHIFT                                                                            0x10
13669 #define GDS_GWS_VMID1__BASE_MASK                                                                              0x0000003FL
13670 #define GDS_GWS_VMID1__SIZE_MASK                                                                              0x007F0000L
13671 //GDS_GWS_VMID2
13672 #define GDS_GWS_VMID2__BASE__SHIFT                                                                            0x0
13673 #define GDS_GWS_VMID2__SIZE__SHIFT                                                                            0x10
13674 #define GDS_GWS_VMID2__BASE_MASK                                                                              0x0000003FL
13675 #define GDS_GWS_VMID2__SIZE_MASK                                                                              0x007F0000L
13676 //GDS_GWS_VMID3
13677 #define GDS_GWS_VMID3__BASE__SHIFT                                                                            0x0
13678 #define GDS_GWS_VMID3__SIZE__SHIFT                                                                            0x10
13679 #define GDS_GWS_VMID3__BASE_MASK                                                                              0x0000003FL
13680 #define GDS_GWS_VMID3__SIZE_MASK                                                                              0x007F0000L
13681 //GDS_GWS_VMID4
13682 #define GDS_GWS_VMID4__BASE__SHIFT                                                                            0x0
13683 #define GDS_GWS_VMID4__SIZE__SHIFT                                                                            0x10
13684 #define GDS_GWS_VMID4__BASE_MASK                                                                              0x0000003FL
13685 #define GDS_GWS_VMID4__SIZE_MASK                                                                              0x007F0000L
13686 //GDS_GWS_VMID5
13687 #define GDS_GWS_VMID5__BASE__SHIFT                                                                            0x0
13688 #define GDS_GWS_VMID5__SIZE__SHIFT                                                                            0x10
13689 #define GDS_GWS_VMID5__BASE_MASK                                                                              0x0000003FL
13690 #define GDS_GWS_VMID5__SIZE_MASK                                                                              0x007F0000L
13691 //GDS_GWS_VMID6
13692 #define GDS_GWS_VMID6__BASE__SHIFT                                                                            0x0
13693 #define GDS_GWS_VMID6__SIZE__SHIFT                                                                            0x10
13694 #define GDS_GWS_VMID6__BASE_MASK                                                                              0x0000003FL
13695 #define GDS_GWS_VMID6__SIZE_MASK                                                                              0x007F0000L
13696 //GDS_GWS_VMID7
13697 #define GDS_GWS_VMID7__BASE__SHIFT                                                                            0x0
13698 #define GDS_GWS_VMID7__SIZE__SHIFT                                                                            0x10
13699 #define GDS_GWS_VMID7__BASE_MASK                                                                              0x0000003FL
13700 #define GDS_GWS_VMID7__SIZE_MASK                                                                              0x007F0000L
13701 //GDS_GWS_VMID8
13702 #define GDS_GWS_VMID8__BASE__SHIFT                                                                            0x0
13703 #define GDS_GWS_VMID8__SIZE__SHIFT                                                                            0x10
13704 #define GDS_GWS_VMID8__BASE_MASK                                                                              0x0000003FL
13705 #define GDS_GWS_VMID8__SIZE_MASK                                                                              0x007F0000L
13706 //GDS_GWS_VMID9
13707 #define GDS_GWS_VMID9__BASE__SHIFT                                                                            0x0
13708 #define GDS_GWS_VMID9__SIZE__SHIFT                                                                            0x10
13709 #define GDS_GWS_VMID9__BASE_MASK                                                                              0x0000003FL
13710 #define GDS_GWS_VMID9__SIZE_MASK                                                                              0x007F0000L
13711 //GDS_GWS_VMID10
13712 #define GDS_GWS_VMID10__BASE__SHIFT                                                                           0x0
13713 #define GDS_GWS_VMID10__SIZE__SHIFT                                                                           0x10
13714 #define GDS_GWS_VMID10__BASE_MASK                                                                             0x0000003FL
13715 #define GDS_GWS_VMID10__SIZE_MASK                                                                             0x007F0000L
13716 //GDS_GWS_VMID11
13717 #define GDS_GWS_VMID11__BASE__SHIFT                                                                           0x0
13718 #define GDS_GWS_VMID11__SIZE__SHIFT                                                                           0x10
13719 #define GDS_GWS_VMID11__BASE_MASK                                                                             0x0000003FL
13720 #define GDS_GWS_VMID11__SIZE_MASK                                                                             0x007F0000L
13721 //GDS_GWS_VMID12
13722 #define GDS_GWS_VMID12__BASE__SHIFT                                                                           0x0
13723 #define GDS_GWS_VMID12__SIZE__SHIFT                                                                           0x10
13724 #define GDS_GWS_VMID12__BASE_MASK                                                                             0x0000003FL
13725 #define GDS_GWS_VMID12__SIZE_MASK                                                                             0x007F0000L
13726 //GDS_GWS_VMID13
13727 #define GDS_GWS_VMID13__BASE__SHIFT                                                                           0x0
13728 #define GDS_GWS_VMID13__SIZE__SHIFT                                                                           0x10
13729 #define GDS_GWS_VMID13__BASE_MASK                                                                             0x0000003FL
13730 #define GDS_GWS_VMID13__SIZE_MASK                                                                             0x007F0000L
13731 //GDS_GWS_VMID14
13732 #define GDS_GWS_VMID14__BASE__SHIFT                                                                           0x0
13733 #define GDS_GWS_VMID14__SIZE__SHIFT                                                                           0x10
13734 #define GDS_GWS_VMID14__BASE_MASK                                                                             0x0000003FL
13735 #define GDS_GWS_VMID14__SIZE_MASK                                                                             0x007F0000L
13736 //GDS_GWS_VMID15
13737 #define GDS_GWS_VMID15__BASE__SHIFT                                                                           0x0
13738 #define GDS_GWS_VMID15__SIZE__SHIFT                                                                           0x10
13739 #define GDS_GWS_VMID15__BASE_MASK                                                                             0x0000003FL
13740 #define GDS_GWS_VMID15__SIZE_MASK                                                                             0x007F0000L
13741 //GDS_OA_VMID0
13742 #define GDS_OA_VMID0__MASK__SHIFT                                                                             0x0
13743 #define GDS_OA_VMID0__UNUSED__SHIFT                                                                           0x10
13744 #define GDS_OA_VMID0__MASK_MASK                                                                               0x0000FFFFL
13745 #define GDS_OA_VMID0__UNUSED_MASK                                                                             0xFFFF0000L
13746 //GDS_OA_VMID1
13747 #define GDS_OA_VMID1__MASK__SHIFT                                                                             0x0
13748 #define GDS_OA_VMID1__UNUSED__SHIFT                                                                           0x10
13749 #define GDS_OA_VMID1__MASK_MASK                                                                               0x0000FFFFL
13750 #define GDS_OA_VMID1__UNUSED_MASK                                                                             0xFFFF0000L
13751 //GDS_OA_VMID2
13752 #define GDS_OA_VMID2__MASK__SHIFT                                                                             0x0
13753 #define GDS_OA_VMID2__UNUSED__SHIFT                                                                           0x10
13754 #define GDS_OA_VMID2__MASK_MASK                                                                               0x0000FFFFL
13755 #define GDS_OA_VMID2__UNUSED_MASK                                                                             0xFFFF0000L
13756 //GDS_OA_VMID3
13757 #define GDS_OA_VMID3__MASK__SHIFT                                                                             0x0
13758 #define GDS_OA_VMID3__UNUSED__SHIFT                                                                           0x10
13759 #define GDS_OA_VMID3__MASK_MASK                                                                               0x0000FFFFL
13760 #define GDS_OA_VMID3__UNUSED_MASK                                                                             0xFFFF0000L
13761 //GDS_OA_VMID4
13762 #define GDS_OA_VMID4__MASK__SHIFT                                                                             0x0
13763 #define GDS_OA_VMID4__UNUSED__SHIFT                                                                           0x10
13764 #define GDS_OA_VMID4__MASK_MASK                                                                               0x0000FFFFL
13765 #define GDS_OA_VMID4__UNUSED_MASK                                                                             0xFFFF0000L
13766 //GDS_OA_VMID5
13767 #define GDS_OA_VMID5__MASK__SHIFT                                                                             0x0
13768 #define GDS_OA_VMID5__UNUSED__SHIFT                                                                           0x10
13769 #define GDS_OA_VMID5__MASK_MASK                                                                               0x0000FFFFL
13770 #define GDS_OA_VMID5__UNUSED_MASK                                                                             0xFFFF0000L
13771 //GDS_OA_VMID6
13772 #define GDS_OA_VMID6__MASK__SHIFT                                                                             0x0
13773 #define GDS_OA_VMID6__UNUSED__SHIFT                                                                           0x10
13774 #define GDS_OA_VMID6__MASK_MASK                                                                               0x0000FFFFL
13775 #define GDS_OA_VMID6__UNUSED_MASK                                                                             0xFFFF0000L
13776 //GDS_OA_VMID7
13777 #define GDS_OA_VMID7__MASK__SHIFT                                                                             0x0
13778 #define GDS_OA_VMID7__UNUSED__SHIFT                                                                           0x10
13779 #define GDS_OA_VMID7__MASK_MASK                                                                               0x0000FFFFL
13780 #define GDS_OA_VMID7__UNUSED_MASK                                                                             0xFFFF0000L
13781 //GDS_OA_VMID8
13782 #define GDS_OA_VMID8__MASK__SHIFT                                                                             0x0
13783 #define GDS_OA_VMID8__UNUSED__SHIFT                                                                           0x10
13784 #define GDS_OA_VMID8__MASK_MASK                                                                               0x0000FFFFL
13785 #define GDS_OA_VMID8__UNUSED_MASK                                                                             0xFFFF0000L
13786 //GDS_OA_VMID9
13787 #define GDS_OA_VMID9__MASK__SHIFT                                                                             0x0
13788 #define GDS_OA_VMID9__UNUSED__SHIFT                                                                           0x10
13789 #define GDS_OA_VMID9__MASK_MASK                                                                               0x0000FFFFL
13790 #define GDS_OA_VMID9__UNUSED_MASK                                                                             0xFFFF0000L
13791 //GDS_OA_VMID10
13792 #define GDS_OA_VMID10__MASK__SHIFT                                                                            0x0
13793 #define GDS_OA_VMID10__UNUSED__SHIFT                                                                          0x10
13794 #define GDS_OA_VMID10__MASK_MASK                                                                              0x0000FFFFL
13795 #define GDS_OA_VMID10__UNUSED_MASK                                                                            0xFFFF0000L
13796 //GDS_OA_VMID11
13797 #define GDS_OA_VMID11__MASK__SHIFT                                                                            0x0
13798 #define GDS_OA_VMID11__UNUSED__SHIFT                                                                          0x10
13799 #define GDS_OA_VMID11__MASK_MASK                                                                              0x0000FFFFL
13800 #define GDS_OA_VMID11__UNUSED_MASK                                                                            0xFFFF0000L
13801 //GDS_OA_VMID12
13802 #define GDS_OA_VMID12__MASK__SHIFT                                                                            0x0
13803 #define GDS_OA_VMID12__UNUSED__SHIFT                                                                          0x10
13804 #define GDS_OA_VMID12__MASK_MASK                                                                              0x0000FFFFL
13805 #define GDS_OA_VMID12__UNUSED_MASK                                                                            0xFFFF0000L
13806 //GDS_OA_VMID13
13807 #define GDS_OA_VMID13__MASK__SHIFT                                                                            0x0
13808 #define GDS_OA_VMID13__UNUSED__SHIFT                                                                          0x10
13809 #define GDS_OA_VMID13__MASK_MASK                                                                              0x0000FFFFL
13810 #define GDS_OA_VMID13__UNUSED_MASK                                                                            0xFFFF0000L
13811 //GDS_OA_VMID14
13812 #define GDS_OA_VMID14__MASK__SHIFT                                                                            0x0
13813 #define GDS_OA_VMID14__UNUSED__SHIFT                                                                          0x10
13814 #define GDS_OA_VMID14__MASK_MASK                                                                              0x0000FFFFL
13815 #define GDS_OA_VMID14__UNUSED_MASK                                                                            0xFFFF0000L
13816 //GDS_OA_VMID15
13817 #define GDS_OA_VMID15__MASK__SHIFT                                                                            0x0
13818 #define GDS_OA_VMID15__UNUSED__SHIFT                                                                          0x10
13819 #define GDS_OA_VMID15__MASK_MASK                                                                              0x0000FFFFL
13820 #define GDS_OA_VMID15__UNUSED_MASK                                                                            0xFFFF0000L
13821 //GDS_GWS_RESET0
13822 #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT                                                                0x0
13823 #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT                                                                0x1
13824 #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT                                                                0x2
13825 #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT                                                                0x3
13826 #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT                                                                0x4
13827 #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT                                                                0x5
13828 #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT                                                                0x6
13829 #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT                                                                0x7
13830 #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT                                                                0x8
13831 #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT                                                                0x9
13832 #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT                                                               0xa
13833 #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT                                                               0xb
13834 #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT                                                               0xc
13835 #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT                                                               0xd
13836 #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT                                                               0xe
13837 #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT                                                               0xf
13838 #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT                                                               0x10
13839 #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT                                                               0x11
13840 #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT                                                               0x12
13841 #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT                                                               0x13
13842 #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT                                                               0x14
13843 #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT                                                               0x15
13844 #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT                                                               0x16
13845 #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT                                                               0x17
13846 #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT                                                               0x18
13847 #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT                                                               0x19
13848 #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT                                                               0x1a
13849 #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT                                                               0x1b
13850 #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT                                                               0x1c
13851 #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT                                                               0x1d
13852 #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT                                                               0x1e
13853 #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT                                                               0x1f
13854 #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK                                                                  0x00000001L
13855 #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK                                                                  0x00000002L
13856 #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK                                                                  0x00000004L
13857 #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK                                                                  0x00000008L
13858 #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK                                                                  0x00000010L
13859 #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK                                                                  0x00000020L
13860 #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK                                                                  0x00000040L
13861 #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK                                                                  0x00000080L
13862 #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK                                                                  0x00000100L
13863 #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK                                                                  0x00000200L
13864 #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK                                                                 0x00000400L
13865 #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK                                                                 0x00000800L
13866 #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK                                                                 0x00001000L
13867 #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK                                                                 0x00002000L
13868 #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK                                                                 0x00004000L
13869 #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK                                                                 0x00008000L
13870 #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK                                                                 0x00010000L
13871 #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK                                                                 0x00020000L
13872 #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK                                                                 0x00040000L
13873 #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK                                                                 0x00080000L
13874 #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK                                                                 0x00100000L
13875 #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK                                                                 0x00200000L
13876 #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK                                                                 0x00400000L
13877 #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK                                                                 0x00800000L
13878 #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK                                                                 0x01000000L
13879 #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK                                                                 0x02000000L
13880 #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK                                                                 0x04000000L
13881 #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK                                                                 0x08000000L
13882 #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK                                                                 0x10000000L
13883 #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK                                                                 0x20000000L
13884 #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK                                                                 0x40000000L
13885 #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK                                                                 0x80000000L
13886 //GDS_GWS_RESET1
13887 #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT                                                               0x0
13888 #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT                                                               0x1
13889 #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT                                                               0x2
13890 #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT                                                               0x3
13891 #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT                                                               0x4
13892 #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT                                                               0x5
13893 #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT                                                               0x6
13894 #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT                                                               0x7
13895 #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT                                                               0x8
13896 #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT                                                               0x9
13897 #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT                                                               0xa
13898 #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT                                                               0xb
13899 #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT                                                               0xc
13900 #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT                                                               0xd
13901 #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT                                                               0xe
13902 #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT                                                               0xf
13903 #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT                                                               0x10
13904 #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT                                                               0x11
13905 #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT                                                               0x12
13906 #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT                                                               0x13
13907 #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT                                                               0x14
13908 #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT                                                               0x15
13909 #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT                                                               0x16
13910 #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT                                                               0x17
13911 #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT                                                               0x18
13912 #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT                                                               0x19
13913 #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT                                                               0x1a
13914 #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT                                                               0x1b
13915 #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT                                                               0x1c
13916 #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT                                                               0x1d
13917 #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT                                                               0x1e
13918 #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT                                                               0x1f
13919 #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK                                                                 0x00000001L
13920 #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK                                                                 0x00000002L
13921 #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK                                                                 0x00000004L
13922 #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK                                                                 0x00000008L
13923 #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK                                                                 0x00000010L
13924 #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK                                                                 0x00000020L
13925 #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK                                                                 0x00000040L
13926 #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK                                                                 0x00000080L
13927 #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK                                                                 0x00000100L
13928 #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK                                                                 0x00000200L
13929 #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK                                                                 0x00000400L
13930 #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK                                                                 0x00000800L
13931 #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK                                                                 0x00001000L
13932 #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK                                                                 0x00002000L
13933 #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK                                                                 0x00004000L
13934 #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK                                                                 0x00008000L
13935 #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK                                                                 0x00010000L
13936 #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK                                                                 0x00020000L
13937 #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK                                                                 0x00040000L
13938 #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK                                                                 0x00080000L
13939 #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK                                                                 0x00100000L
13940 #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK                                                                 0x00200000L
13941 #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK                                                                 0x00400000L
13942 #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK                                                                 0x00800000L
13943 #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK                                                                 0x01000000L
13944 #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK                                                                 0x02000000L
13945 #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK                                                                 0x04000000L
13946 #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK                                                                 0x08000000L
13947 #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK                                                                 0x10000000L
13948 #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK                                                                 0x20000000L
13949 #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK                                                                 0x40000000L
13950 #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK                                                                 0x80000000L
13951 //GDS_GWS_RESOURCE_RESET
13952 #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT                                                                  0x0
13953 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT                                                            0x8
13954 #define GDS_GWS_RESOURCE_RESET__RESET_MASK                                                                    0x00000001L
13955 #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK                                                              0x0000FF00L
13956 //GDS_COMPUTE_MAX_WAVE_ID
13957 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT                                                           0x0
13958 #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK                                                             0x00000FFFL
13959 //GDS_OA_RESET_MASK
13960 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT                                                       0x0
13961 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT                                                       0x1
13962 #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT                                                                0x2
13963 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT                                                        0x3
13964 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT                                                             0x4
13965 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT                                                             0x5
13966 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT                                                             0x6
13967 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT                                                             0x7
13968 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT                                                             0x8
13969 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT                                                             0x9
13970 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT                                                             0xa
13971 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT                                                             0xb
13972 #define GDS_OA_RESET_MASK__UNUSED1__SHIFT                                                                     0xc
13973 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK                                                         0x00000001L
13974 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK                                                         0x00000002L
13975 #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK                                                                  0x00000004L
13976 #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK                                                          0x00000008L
13977 #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK                                                               0x00000010L
13978 #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK                                                               0x00000020L
13979 #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK                                                               0x00000040L
13980 #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK                                                               0x00000080L
13981 #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK                                                               0x00000100L
13982 #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK                                                               0x00000200L
13983 #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK                                                               0x00000400L
13984 #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK                                                               0x00000800L
13985 #define GDS_OA_RESET_MASK__UNUSED1_MASK                                                                       0xFFFFF000L
13986 //GDS_OA_RESET
13987 #define GDS_OA_RESET__RESET__SHIFT                                                                            0x0
13988 #define GDS_OA_RESET__PIPE_ID__SHIFT                                                                          0x8
13989 #define GDS_OA_RESET__RESET_MASK                                                                              0x00000001L
13990 #define GDS_OA_RESET__PIPE_ID_MASK                                                                            0x0000FF00L
13991 //GDS_ENHANCE
13992 #define GDS_ENHANCE__MISC__SHIFT                                                                              0x0
13993 #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT                                                                    0x10
13994 #define GDS_ENHANCE__CGPG_RESTORE__SHIFT                                                                      0x11
13995 #define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT                                                                   0x12
13996 #define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT                                                                  0x13
13997 #define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT                                                                  0x14
13998 #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT                                                               0x15
13999 #define GDS_ENHANCE__UNUSED__SHIFT                                                                            0x16
14000 #define GDS_ENHANCE__MISC_MASK                                                                                0x0000FFFFL
14001 #define GDS_ENHANCE__AUTO_INC_INDEX_MASK                                                                      0x00010000L
14002 #define GDS_ENHANCE__CGPG_RESTORE_MASK                                                                        0x00020000L
14003 #define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK                                                                     0x00040000L
14004 #define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK                                                                    0x00080000L
14005 #define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK                                                                    0x00100000L
14006 #define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK                                                                 0x00200000L
14007 #define GDS_ENHANCE__UNUSED_MASK                                                                              0xFFC00000L
14008 //GDS_OA_CGPG_RESTORE
14009 #define GDS_OA_CGPG_RESTORE__VMID__SHIFT                                                                      0x0
14010 #define GDS_OA_CGPG_RESTORE__MEID__SHIFT                                                                      0x8
14011 #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT                                                                    0xc
14012 #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT                                                                   0x10
14013 #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT                                                                    0x14
14014 #define GDS_OA_CGPG_RESTORE__VMID_MASK                                                                        0x000000FFL
14015 #define GDS_OA_CGPG_RESTORE__MEID_MASK                                                                        0x00000F00L
14016 #define GDS_OA_CGPG_RESTORE__PIPEID_MASK                                                                      0x0000F000L
14017 #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK                                                                     0x000F0000L
14018 #define GDS_OA_CGPG_RESTORE__UNUSED_MASK                                                                      0xFFF00000L
14019 //GDS_CS_CTXSW_STATUS
14020 #define GDS_CS_CTXSW_STATUS__R__SHIFT                                                                         0x0
14021 #define GDS_CS_CTXSW_STATUS__W__SHIFT                                                                         0x1
14022 #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT                                                                    0x2
14023 #define GDS_CS_CTXSW_STATUS__R_MASK                                                                           0x00000001L
14024 #define GDS_CS_CTXSW_STATUS__W_MASK                                                                           0x00000002L
14025 #define GDS_CS_CTXSW_STATUS__UNUSED_MASK                                                                      0xFFFFFFFCL
14026 //GDS_CS_CTXSW_CNT0
14027 #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
14028 #define GDS_CS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
14029 #define GDS_CS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
14030 #define GDS_CS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
14031 //GDS_CS_CTXSW_CNT1
14032 #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
14033 #define GDS_CS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
14034 #define GDS_CS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
14035 #define GDS_CS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
14036 //GDS_CS_CTXSW_CNT2
14037 #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
14038 #define GDS_CS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
14039 #define GDS_CS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
14040 #define GDS_CS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
14041 //GDS_CS_CTXSW_CNT3
14042 #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
14043 #define GDS_CS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
14044 #define GDS_CS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
14045 #define GDS_CS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
14046 //GDS_GFX_CTXSW_STATUS
14047 #define GDS_GFX_CTXSW_STATUS__R__SHIFT                                                                        0x0
14048 #define GDS_GFX_CTXSW_STATUS__W__SHIFT                                                                        0x1
14049 #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT                                                                   0x2
14050 #define GDS_GFX_CTXSW_STATUS__R_MASK                                                                          0x00000001L
14051 #define GDS_GFX_CTXSW_STATUS__W_MASK                                                                          0x00000002L
14052 #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK                                                                     0xFFFFFFFCL
14053 //GDS_VS_CTXSW_CNT0
14054 #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
14055 #define GDS_VS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
14056 #define GDS_VS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
14057 #define GDS_VS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
14058 //GDS_VS_CTXSW_CNT1
14059 #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
14060 #define GDS_VS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
14061 #define GDS_VS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
14062 #define GDS_VS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
14063 //GDS_VS_CTXSW_CNT2
14064 #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
14065 #define GDS_VS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
14066 #define GDS_VS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
14067 #define GDS_VS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
14068 //GDS_VS_CTXSW_CNT3
14069 #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
14070 #define GDS_VS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
14071 #define GDS_VS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
14072 #define GDS_VS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
14073 //GDS_PS0_CTXSW_CNT0
14074 #define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14075 #define GDS_PS0_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14076 #define GDS_PS0_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14077 #define GDS_PS0_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14078 //GDS_PS0_CTXSW_CNT1
14079 #define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14080 #define GDS_PS0_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14081 #define GDS_PS0_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14082 #define GDS_PS0_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14083 //GDS_PS0_CTXSW_CNT2
14084 #define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14085 #define GDS_PS0_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14086 #define GDS_PS0_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14087 #define GDS_PS0_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14088 //GDS_PS0_CTXSW_CNT3
14089 #define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14090 #define GDS_PS0_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14091 #define GDS_PS0_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14092 #define GDS_PS0_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14093 //GDS_PS1_CTXSW_CNT0
14094 #define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14095 #define GDS_PS1_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14096 #define GDS_PS1_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14097 #define GDS_PS1_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14098 //GDS_PS1_CTXSW_CNT1
14099 #define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14100 #define GDS_PS1_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14101 #define GDS_PS1_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14102 #define GDS_PS1_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14103 //GDS_PS1_CTXSW_CNT2
14104 #define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14105 #define GDS_PS1_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14106 #define GDS_PS1_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14107 #define GDS_PS1_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14108 //GDS_PS1_CTXSW_CNT3
14109 #define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14110 #define GDS_PS1_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14111 #define GDS_PS1_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14112 #define GDS_PS1_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14113 //GDS_PS2_CTXSW_CNT0
14114 #define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14115 #define GDS_PS2_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14116 #define GDS_PS2_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14117 #define GDS_PS2_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14118 //GDS_PS2_CTXSW_CNT1
14119 #define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14120 #define GDS_PS2_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14121 #define GDS_PS2_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14122 #define GDS_PS2_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14123 //GDS_PS2_CTXSW_CNT2
14124 #define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14125 #define GDS_PS2_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14126 #define GDS_PS2_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14127 #define GDS_PS2_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14128 //GDS_PS2_CTXSW_CNT3
14129 #define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14130 #define GDS_PS2_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14131 #define GDS_PS2_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14132 #define GDS_PS2_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14133 //GDS_PS3_CTXSW_CNT0
14134 #define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14135 #define GDS_PS3_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14136 #define GDS_PS3_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14137 #define GDS_PS3_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14138 //GDS_PS3_CTXSW_CNT1
14139 #define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14140 #define GDS_PS3_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14141 #define GDS_PS3_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14142 #define GDS_PS3_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14143 //GDS_PS3_CTXSW_CNT2
14144 #define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14145 #define GDS_PS3_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14146 #define GDS_PS3_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14147 #define GDS_PS3_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14148 //GDS_PS3_CTXSW_CNT3
14149 #define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14150 #define GDS_PS3_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14151 #define GDS_PS3_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14152 #define GDS_PS3_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14153 //GDS_PS4_CTXSW_CNT0
14154 #define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14155 #define GDS_PS4_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14156 #define GDS_PS4_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14157 #define GDS_PS4_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14158 //GDS_PS4_CTXSW_CNT1
14159 #define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14160 #define GDS_PS4_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14161 #define GDS_PS4_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14162 #define GDS_PS4_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14163 //GDS_PS4_CTXSW_CNT2
14164 #define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14165 #define GDS_PS4_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14166 #define GDS_PS4_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14167 #define GDS_PS4_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14168 //GDS_PS4_CTXSW_CNT3
14169 #define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14170 #define GDS_PS4_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14171 #define GDS_PS4_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14172 #define GDS_PS4_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14173 //GDS_PS5_CTXSW_CNT0
14174 #define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14175 #define GDS_PS5_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14176 #define GDS_PS5_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14177 #define GDS_PS5_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14178 //GDS_PS5_CTXSW_CNT1
14179 #define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14180 #define GDS_PS5_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14181 #define GDS_PS5_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14182 #define GDS_PS5_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14183 //GDS_PS5_CTXSW_CNT2
14184 #define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14185 #define GDS_PS5_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14186 #define GDS_PS5_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14187 #define GDS_PS5_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14188 //GDS_PS5_CTXSW_CNT3
14189 #define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14190 #define GDS_PS5_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14191 #define GDS_PS5_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14192 #define GDS_PS5_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14193 //GDS_PS6_CTXSW_CNT0
14194 #define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14195 #define GDS_PS6_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14196 #define GDS_PS6_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14197 #define GDS_PS6_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14198 //GDS_PS6_CTXSW_CNT1
14199 #define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14200 #define GDS_PS6_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14201 #define GDS_PS6_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14202 #define GDS_PS6_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14203 //GDS_PS6_CTXSW_CNT2
14204 #define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14205 #define GDS_PS6_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14206 #define GDS_PS6_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14207 #define GDS_PS6_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14208 //GDS_PS6_CTXSW_CNT3
14209 #define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14210 #define GDS_PS6_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14211 #define GDS_PS6_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14212 #define GDS_PS6_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14213 //GDS_PS7_CTXSW_CNT0
14214 #define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT                                                                       0x0
14215 #define GDS_PS7_CTXSW_CNT0__PTR__SHIFT                                                                        0x10
14216 #define GDS_PS7_CTXSW_CNT0__UPDN_MASK                                                                         0x0000FFFFL
14217 #define GDS_PS7_CTXSW_CNT0__PTR_MASK                                                                          0xFFFF0000L
14218 //GDS_PS7_CTXSW_CNT1
14219 #define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT                                                                       0x0
14220 #define GDS_PS7_CTXSW_CNT1__PTR__SHIFT                                                                        0x10
14221 #define GDS_PS7_CTXSW_CNT1__UPDN_MASK                                                                         0x0000FFFFL
14222 #define GDS_PS7_CTXSW_CNT1__PTR_MASK                                                                          0xFFFF0000L
14223 //GDS_PS7_CTXSW_CNT2
14224 #define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT                                                                       0x0
14225 #define GDS_PS7_CTXSW_CNT2__PTR__SHIFT                                                                        0x10
14226 #define GDS_PS7_CTXSW_CNT2__UPDN_MASK                                                                         0x0000FFFFL
14227 #define GDS_PS7_CTXSW_CNT2__PTR_MASK                                                                          0xFFFF0000L
14228 //GDS_PS7_CTXSW_CNT3
14229 #define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT                                                                       0x0
14230 #define GDS_PS7_CTXSW_CNT3__PTR__SHIFT                                                                        0x10
14231 #define GDS_PS7_CTXSW_CNT3__UPDN_MASK                                                                         0x0000FFFFL
14232 #define GDS_PS7_CTXSW_CNT3__PTR_MASK                                                                          0xFFFF0000L
14233 //GDS_GS_CTXSW_CNT0
14234 #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT                                                                        0x0
14235 #define GDS_GS_CTXSW_CNT0__PTR__SHIFT                                                                         0x10
14236 #define GDS_GS_CTXSW_CNT0__UPDN_MASK                                                                          0x0000FFFFL
14237 #define GDS_GS_CTXSW_CNT0__PTR_MASK                                                                           0xFFFF0000L
14238 //GDS_GS_CTXSW_CNT1
14239 #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT                                                                        0x0
14240 #define GDS_GS_CTXSW_CNT1__PTR__SHIFT                                                                         0x10
14241 #define GDS_GS_CTXSW_CNT1__UPDN_MASK                                                                          0x0000FFFFL
14242 #define GDS_GS_CTXSW_CNT1__PTR_MASK                                                                           0xFFFF0000L
14243 //GDS_GS_CTXSW_CNT2
14244 #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT                                                                        0x0
14245 #define GDS_GS_CTXSW_CNT2__PTR__SHIFT                                                                         0x10
14246 #define GDS_GS_CTXSW_CNT2__UPDN_MASK                                                                          0x0000FFFFL
14247 #define GDS_GS_CTXSW_CNT2__PTR_MASK                                                                           0xFFFF0000L
14248 //GDS_GS_CTXSW_CNT3
14249 #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT                                                                        0x0
14250 #define GDS_GS_CTXSW_CNT3__PTR__SHIFT                                                                         0x10
14251 #define GDS_GS_CTXSW_CNT3__UPDN_MASK                                                                          0x0000FFFFL
14252 #define GDS_GS_CTXSW_CNT3__PTR_MASK                                                                           0xFFFF0000L
14253 
14254 
14255 // addressBlock: gc_rasdec
14256 //RAS_SIGNATURE_CONTROL
14257 #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT                                                                  0x0
14258 #define RAS_SIGNATURE_CONTROL__ENABLE_MASK                                                                    0x00000001L
14259 //RAS_SIGNATURE_MASK
14260 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT                                                             0x0
14261 #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK                                                               0xFFFFFFFFL
14262 //RAS_SX_SIGNATURE0
14263 #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14264 #define RAS_SX_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14265 //RAS_SX_SIGNATURE1
14266 #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14267 #define RAS_SX_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14268 //RAS_SX_SIGNATURE2
14269 #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT                                                                   0x0
14270 #define RAS_SX_SIGNATURE2__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14271 //RAS_SX_SIGNATURE3
14272 #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT                                                                   0x0
14273 #define RAS_SX_SIGNATURE3__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14274 //RAS_DB_SIGNATURE0
14275 #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14276 #define RAS_DB_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14277 //RAS_PA_SIGNATURE0
14278 #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14279 #define RAS_PA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14280 //RAS_VGT_SIGNATURE0
14281 #define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
14282 #define RAS_VGT_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14283 //RAS_SQ_SIGNATURE0
14284 #define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14285 #define RAS_SQ_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14286 //RAS_SC_SIGNATURE0
14287 #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14288 #define RAS_SC_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14289 //RAS_SC_SIGNATURE1
14290 #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14291 #define RAS_SC_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14292 //RAS_SC_SIGNATURE2
14293 #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT                                                                   0x0
14294 #define RAS_SC_SIGNATURE2__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14295 //RAS_SC_SIGNATURE3
14296 #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT                                                                   0x0
14297 #define RAS_SC_SIGNATURE3__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14298 //RAS_SC_SIGNATURE4
14299 #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT                                                                   0x0
14300 #define RAS_SC_SIGNATURE4__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14301 //RAS_SC_SIGNATURE5
14302 #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT                                                                   0x0
14303 #define RAS_SC_SIGNATURE5__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14304 //RAS_SC_SIGNATURE6
14305 #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT                                                                   0x0
14306 #define RAS_SC_SIGNATURE6__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14307 //RAS_SC_SIGNATURE7
14308 #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT                                                                   0x0
14309 #define RAS_SC_SIGNATURE7__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14310 //RAS_IA_SIGNATURE0
14311 #define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14312 #define RAS_IA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14313 //RAS_IA_SIGNATURE1
14314 #define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14315 #define RAS_IA_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14316 //RAS_SPI_SIGNATURE0
14317 #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
14318 #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14319 //RAS_SPI_SIGNATURE1
14320 #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT                                                                  0x0
14321 #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14322 //RAS_TA_SIGNATURE0
14323 #define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14324 #define RAS_TA_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14325 //RAS_TD_SIGNATURE0
14326 #define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14327 #define RAS_TD_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14328 //RAS_CB_SIGNATURE0
14329 #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT                                                                   0x0
14330 #define RAS_CB_SIGNATURE0__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14331 //RAS_BCI_SIGNATURE0
14332 #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT                                                                  0x0
14333 #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14334 //RAS_BCI_SIGNATURE1
14335 #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT                                                                  0x0
14336 #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK                                                                    0xFFFFFFFFL
14337 //RAS_TA_SIGNATURE1
14338 #define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT                                                                   0x0
14339 #define RAS_TA_SIGNATURE1__SIGNATURE_MASK                                                                     0xFFFFFFFFL
14340 
14341 
14342 // addressBlock: gc_gfxdec0
14343 //DB_RENDER_CONTROL
14344 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT                                                          0x0
14345 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT                                                        0x1
14346 #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT                                                                  0x2
14347 #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT                                                                0x3
14348 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT                                                          0x4
14349 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT                                                    0x5
14350 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT                                                      0x6
14351 #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT                                                               0x7
14352 #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT                                                                 0x8
14353 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT                                                           0xc
14354 #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK                                                            0x00000001L
14355 #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK                                                          0x00000002L
14356 #define DB_RENDER_CONTROL__DEPTH_COPY_MASK                                                                    0x00000004L
14357 #define DB_RENDER_CONTROL__STENCIL_COPY_MASK                                                                  0x00000008L
14358 #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK                                                            0x00000010L
14359 #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK                                                      0x00000020L
14360 #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK                                                        0x00000040L
14361 #define DB_RENDER_CONTROL__COPY_CENTROID_MASK                                                                 0x00000080L
14362 #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK                                                                   0x00000F00L
14363 #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK                                                             0x00001000L
14364 //DB_COUNT_CONTROL
14365 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT                                                      0x0
14366 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT                                                         0x1
14367 #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT                                                                  0x4
14368 #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT                                                                 0x8
14369 #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT                                                                 0xc
14370 #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT                                                                 0x10
14371 #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT                                                                0x14
14372 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                            0x18
14373 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                             0x1c
14374 #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK                                                        0x00000001L
14375 #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK                                                           0x00000002L
14376 #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK                                                                    0x00000070L
14377 #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK                                                                   0x00000F00L
14378 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK                                                                   0x0000F000L
14379 #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK                                                                   0x000F0000L
14380 #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK                                                                  0x00F00000L
14381 #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                              0x0F000000L
14382 #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK                                                               0xF0000000L
14383 //DB_DEPTH_VIEW
14384 #define DB_DEPTH_VIEW__SLICE_START__SHIFT                                                                     0x0
14385 #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT                                                                       0xd
14386 #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT                                                                     0x18
14387 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT                                                               0x19
14388 #define DB_DEPTH_VIEW__MIPID__SHIFT                                                                           0x1a
14389 #define DB_DEPTH_VIEW__SLICE_START_MASK                                                                       0x000007FFL
14390 #define DB_DEPTH_VIEW__SLICE_MAX_MASK                                                                         0x00FFE000L
14391 #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK                                                                       0x01000000L
14392 #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK                                                                 0x02000000L
14393 #define DB_DEPTH_VIEW__MIPID_MASK                                                                             0x3C000000L
14394 //DB_RENDER_OVERRIDE
14395 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT                                                           0x0
14396 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT                                                          0x2
14397 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT                                                          0x4
14398 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT                                                       0x6
14399 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT                                                             0x7
14400 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT                                                       0x8
14401 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT                                                          0x9
14402 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT                                                           0xa
14403 #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT                                                               0xb
14404 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT                                                         0xc
14405 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT                                                         0xd
14406 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT                                                    0xf
14407 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT                                                     0x10
14408 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT                                                           0x11
14409 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT                                                      0x12
14410 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT                                                         0x13
14411 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT                                                           0x15
14412 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT                                                    0x1a
14413 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT                                                              0x1b
14414 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT                                                        0x1c
14415 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT                                                              0x1d
14416 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT                                                        0x1e
14417 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT                                                       0x1f
14418 #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK                                                             0x00000003L
14419 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK                                                            0x0000000CL
14420 #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK                                                            0x00000030L
14421 #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK                                                         0x00000040L
14422 #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK                                                               0x00000080L
14423 #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK                                                         0x00000100L
14424 #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK                                                            0x00000200L
14425 #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK                                                             0x00000400L
14426 #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK                                                                 0x00000800L
14427 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK                                                           0x00001000L
14428 #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK                                                           0x00006000L
14429 #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK                                                      0x00008000L
14430 #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK                                                       0x00010000L
14431 #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK                                                             0x00020000L
14432 #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK                                                        0x00040000L
14433 #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK                                                           0x00180000L
14434 #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK                                                             0x03E00000L
14435 #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK                                                      0x04000000L
14436 #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK                                                                0x08000000L
14437 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK                                                          0x10000000L
14438 #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK                                                                0x20000000L
14439 #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK                                                          0x40000000L
14440 #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK                                                         0x80000000L
14441 //DB_RENDER_OVERRIDE2
14442 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT                                              0x0
14443 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT                                            0x2
14444 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT                                       0x5
14445 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT                                        0x6
14446 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT                                               0x7
14447 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT                                                     0x8
14448 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT                                                         0x9
14449 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT                                           0xa
14450 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT                                                 0xb
14451 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT                                                                 0xc
14452 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT                                                              0xf
14453 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT                                                              0x12
14454 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT                                                           0x15
14455 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT                                                         0x16
14456 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT                                                         0x17
14457 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT                                               0x19
14458 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK                                                0x00000003L
14459 #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK                                              0x0000001CL
14460 #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK                                         0x00000020L
14461 #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK                                          0x00000040L
14462 #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK                                                 0x00000080L
14463 #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK                                                       0x00000100L
14464 #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK                                                           0x00000200L
14465 #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK                                             0x00000400L
14466 #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK                                                   0x00000800L
14467 #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK                                                                   0x00007000L
14468 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK                                                                0x00038000L
14469 #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK                                                                0x001C0000L
14470 #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK                                                             0x00200000L
14471 #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK                                                           0x00400000L
14472 #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK                                                           0x00800000L
14473 #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK                                                 0x02000000L
14474 //DB_HTILE_DATA_BASE
14475 #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT                                                                  0x0
14476 #define DB_HTILE_DATA_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
14477 //DB_HTILE_DATA_BASE_HI
14478 #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT                                                                 0x0
14479 #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
14480 //DB_DEPTH_SIZE
14481 #define DB_DEPTH_SIZE__X_MAX__SHIFT                                                                           0x0
14482 #define DB_DEPTH_SIZE__Y_MAX__SHIFT                                                                           0x10
14483 #define DB_DEPTH_SIZE__X_MAX_MASK                                                                             0x00003FFFL
14484 #define DB_DEPTH_SIZE__Y_MAX_MASK                                                                             0x3FFF0000L
14485 //DB_DEPTH_BOUNDS_MIN
14486 #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT                                                                       0x0
14487 #define DB_DEPTH_BOUNDS_MIN__MIN_MASK                                                                         0xFFFFFFFFL
14488 //DB_DEPTH_BOUNDS_MAX
14489 #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT                                                                       0x0
14490 #define DB_DEPTH_BOUNDS_MAX__MAX_MASK                                                                         0xFFFFFFFFL
14491 //DB_STENCIL_CLEAR
14492 #define DB_STENCIL_CLEAR__CLEAR__SHIFT                                                                        0x0
14493 #define DB_STENCIL_CLEAR__CLEAR_MASK                                                                          0x000000FFL
14494 //DB_DEPTH_CLEAR
14495 #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT                                                                    0x0
14496 #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK                                                                      0xFFFFFFFFL
14497 //PA_SC_SCREEN_SCISSOR_TL
14498 #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
14499 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
14500 #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK                                                                    0x0000FFFFL
14501 #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK                                                                    0xFFFF0000L
14502 //PA_SC_SCREEN_SCISSOR_BR
14503 #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
14504 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
14505 #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK                                                                    0x0000FFFFL
14506 #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK                                                                    0xFFFF0000L
14507 //DB_Z_INFO
14508 #define DB_Z_INFO__FORMAT__SHIFT                                                                              0x0
14509 #define DB_Z_INFO__NUM_SAMPLES__SHIFT                                                                         0x2
14510 #define DB_Z_INFO__SW_MODE__SHIFT                                                                             0x4
14511 #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT                                                                  0xc
14512 #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT                                                                      0xd
14513 #define DB_Z_INFO__ITERATE_FLUSH__SHIFT                                                                       0xf
14514 #define DB_Z_INFO__MAXMIP__SHIFT                                                                              0x10
14515 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT                                                             0x17
14516 #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT                                                                      0x1b
14517 #define DB_Z_INFO__READ_SIZE__SHIFT                                                                           0x1c
14518 #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT                                                                 0x1d
14519 #define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT                                                                    0x1e
14520 #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT                                                                    0x1f
14521 #define DB_Z_INFO__FORMAT_MASK                                                                                0x00000003L
14522 #define DB_Z_INFO__NUM_SAMPLES_MASK                                                                           0x0000000CL
14523 #define DB_Z_INFO__SW_MODE_MASK                                                                               0x000001F0L
14524 #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK                                                                    0x00001000L
14525 #define DB_Z_INFO__FAULT_BEHAVIOR_MASK                                                                        0x00006000L
14526 #define DB_Z_INFO__ITERATE_FLUSH_MASK                                                                         0x00008000L
14527 #define DB_Z_INFO__MAXMIP_MASK                                                                                0x000F0000L
14528 #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK                                                               0x07800000L
14529 #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK                                                                        0x08000000L
14530 #define DB_Z_INFO__READ_SIZE_MASK                                                                             0x10000000L
14531 #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK                                                                   0x20000000L
14532 #define DB_Z_INFO__CLEAR_DISALLOWED_MASK                                                                      0x40000000L
14533 #define DB_Z_INFO__ZRANGE_PRECISION_MASK                                                                      0x80000000L
14534 //DB_STENCIL_INFO
14535 #define DB_STENCIL_INFO__FORMAT__SHIFT                                                                        0x0
14536 #define DB_STENCIL_INFO__SW_MODE__SHIFT                                                                       0x4
14537 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT                                                            0xc
14538 #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT                                                                0xd
14539 #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT                                                                 0xf
14540 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT                                                                0x1b
14541 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT                                                          0x1d
14542 #define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT                                                              0x1e
14543 #define DB_STENCIL_INFO__FORMAT_MASK                                                                          0x00000001L
14544 #define DB_STENCIL_INFO__SW_MODE_MASK                                                                         0x000001F0L
14545 #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK                                                              0x00001000L
14546 #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK                                                                  0x00006000L
14547 #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK                                                                   0x00008000L
14548 #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK                                                                  0x08000000L
14549 #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK                                                            0x20000000L
14550 #define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK                                                                0x40000000L
14551 //DB_Z_READ_BASE
14552 #define DB_Z_READ_BASE__BASE_256B__SHIFT                                                                      0x0
14553 #define DB_Z_READ_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
14554 //DB_Z_READ_BASE_HI
14555 #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT                                                                     0x0
14556 #define DB_Z_READ_BASE_HI__BASE_HI_MASK                                                                       0x000000FFL
14557 //DB_STENCIL_READ_BASE
14558 #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT                                                                0x0
14559 #define DB_STENCIL_READ_BASE__BASE_256B_MASK                                                                  0xFFFFFFFFL
14560 //DB_STENCIL_READ_BASE_HI
14561 #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT                                                               0x0
14562 #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK                                                                 0x000000FFL
14563 //DB_Z_WRITE_BASE
14564 #define DB_Z_WRITE_BASE__BASE_256B__SHIFT                                                                     0x0
14565 #define DB_Z_WRITE_BASE__BASE_256B_MASK                                                                       0xFFFFFFFFL
14566 //DB_Z_WRITE_BASE_HI
14567 #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT                                                                    0x0
14568 #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
14569 //DB_STENCIL_WRITE_BASE
14570 #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT                                                               0x0
14571 #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK                                                                 0xFFFFFFFFL
14572 //DB_STENCIL_WRITE_BASE_HI
14573 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT                                                              0x0
14574 #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK                                                                0x000000FFL
14575 //DB_DFSM_CONTROL
14576 #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT                                                                 0x0
14577 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT                                                      0x2
14578 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT                                                             0x3
14579 #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK                                                                   0x00000003L
14580 #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK                                                        0x00000004L
14581 #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK                                                               0x00000008L
14582 //DB_Z_INFO2
14583 #define DB_Z_INFO2__EPITCH__SHIFT                                                                             0x0
14584 #define DB_Z_INFO2__EPITCH_MASK                                                                               0x0000FFFFL
14585 //DB_STENCIL_INFO2
14586 #define DB_STENCIL_INFO2__EPITCH__SHIFT                                                                       0x0
14587 #define DB_STENCIL_INFO2__EPITCH_MASK                                                                         0x0000FFFFL
14588 //TA_BC_BASE_ADDR
14589 #define TA_BC_BASE_ADDR__ADDRESS__SHIFT                                                                       0x0
14590 #define TA_BC_BASE_ADDR__ADDRESS_MASK                                                                         0xFFFFFFFFL
14591 //TA_BC_BASE_ADDR_HI
14592 #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                    0x0
14593 #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                      0x000000FFL
14594 //COHER_DEST_BASE_HI_0
14595 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT                                                        0x0
14596 #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14597 //COHER_DEST_BASE_HI_1
14598 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT                                                        0x0
14599 #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14600 //COHER_DEST_BASE_HI_2
14601 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT                                                        0x0
14602 #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14603 //COHER_DEST_BASE_HI_3
14604 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT                                                        0x0
14605 #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK                                                          0x000000FFL
14606 //COHER_DEST_BASE_2
14607 #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT                                                              0x0
14608 #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14609 //COHER_DEST_BASE_3
14610 #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT                                                              0x0
14611 #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14612 //PA_SC_WINDOW_OFFSET
14613 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT                                                           0x0
14614 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT                                                           0x10
14615 #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK                                                             0x0000FFFFL
14616 #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK                                                             0xFFFF0000L
14617 //PA_SC_WINDOW_SCISSOR_TL
14618 #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT                                                                  0x0
14619 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT                                                                  0x10
14620 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                 0x1f
14621 #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK                                                                    0x00007FFFL
14622 #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK                                                                    0x7FFF0000L
14623 #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                   0x80000000L
14624 //PA_SC_WINDOW_SCISSOR_BR
14625 #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT                                                                  0x0
14626 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT                                                                  0x10
14627 #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK                                                                    0x00007FFFL
14628 #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK                                                                    0x7FFF0000L
14629 //PA_SC_CLIPRECT_RULE
14630 #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT                                                                 0x0
14631 #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK                                                                   0x0000FFFFL
14632 //PA_SC_CLIPRECT_0_TL
14633 #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT                                                                      0x0
14634 #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT                                                                      0x10
14635 #define PA_SC_CLIPRECT_0_TL__TL_X_MASK                                                                        0x00007FFFL
14636 #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK                                                                        0x7FFF0000L
14637 //PA_SC_CLIPRECT_0_BR
14638 #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT                                                                      0x0
14639 #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT                                                                      0x10
14640 #define PA_SC_CLIPRECT_0_BR__BR_X_MASK                                                                        0x00007FFFL
14641 #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK                                                                        0x7FFF0000L
14642 //PA_SC_CLIPRECT_1_TL
14643 #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT                                                                      0x0
14644 #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT                                                                      0x10
14645 #define PA_SC_CLIPRECT_1_TL__TL_X_MASK                                                                        0x00007FFFL
14646 #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK                                                                        0x7FFF0000L
14647 //PA_SC_CLIPRECT_1_BR
14648 #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT                                                                      0x0
14649 #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT                                                                      0x10
14650 #define PA_SC_CLIPRECT_1_BR__BR_X_MASK                                                                        0x00007FFFL
14651 #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK                                                                        0x7FFF0000L
14652 //PA_SC_CLIPRECT_2_TL
14653 #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT                                                                      0x0
14654 #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT                                                                      0x10
14655 #define PA_SC_CLIPRECT_2_TL__TL_X_MASK                                                                        0x00007FFFL
14656 #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK                                                                        0x7FFF0000L
14657 //PA_SC_CLIPRECT_2_BR
14658 #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT                                                                      0x0
14659 #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT                                                                      0x10
14660 #define PA_SC_CLIPRECT_2_BR__BR_X_MASK                                                                        0x00007FFFL
14661 #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK                                                                        0x7FFF0000L
14662 //PA_SC_CLIPRECT_3_TL
14663 #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT                                                                      0x0
14664 #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT                                                                      0x10
14665 #define PA_SC_CLIPRECT_3_TL__TL_X_MASK                                                                        0x00007FFFL
14666 #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK                                                                        0x7FFF0000L
14667 //PA_SC_CLIPRECT_3_BR
14668 #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT                                                                      0x0
14669 #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT                                                                      0x10
14670 #define PA_SC_CLIPRECT_3_BR__BR_X_MASK                                                                        0x00007FFFL
14671 #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK                                                                        0x7FFF0000L
14672 //PA_SC_EDGERULE
14673 #define PA_SC_EDGERULE__ER_TRI__SHIFT                                                                         0x0
14674 #define PA_SC_EDGERULE__ER_POINT__SHIFT                                                                       0x4
14675 #define PA_SC_EDGERULE__ER_RECT__SHIFT                                                                        0x8
14676 #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT                                                                     0xc
14677 #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT                                                                     0x12
14678 #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT                                                                     0x18
14679 #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT                                                                     0x1c
14680 #define PA_SC_EDGERULE__ER_TRI_MASK                                                                           0x0000000FL
14681 #define PA_SC_EDGERULE__ER_POINT_MASK                                                                         0x000000F0L
14682 #define PA_SC_EDGERULE__ER_RECT_MASK                                                                          0x00000F00L
14683 #define PA_SC_EDGERULE__ER_LINE_LR_MASK                                                                       0x0003F000L
14684 #define PA_SC_EDGERULE__ER_LINE_RL_MASK                                                                       0x00FC0000L
14685 #define PA_SC_EDGERULE__ER_LINE_TB_MASK                                                                       0x0F000000L
14686 #define PA_SC_EDGERULE__ER_LINE_BT_MASK                                                                       0xF0000000L
14687 //PA_SU_HARDWARE_SCREEN_OFFSET
14688 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT                                               0x0
14689 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT                                               0x10
14690 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK                                                 0x000001FFL
14691 #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK                                                 0x01FF0000L
14692 //CB_TARGET_MASK
14693 #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT                                                                 0x0
14694 #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT                                                                 0x4
14695 #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT                                                                 0x8
14696 #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT                                                                 0xc
14697 #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT                                                                 0x10
14698 #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT                                                                 0x14
14699 #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT                                                                 0x18
14700 #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT                                                                 0x1c
14701 #define CB_TARGET_MASK__TARGET0_ENABLE_MASK                                                                   0x0000000FL
14702 #define CB_TARGET_MASK__TARGET1_ENABLE_MASK                                                                   0x000000F0L
14703 #define CB_TARGET_MASK__TARGET2_ENABLE_MASK                                                                   0x00000F00L
14704 #define CB_TARGET_MASK__TARGET3_ENABLE_MASK                                                                   0x0000F000L
14705 #define CB_TARGET_MASK__TARGET4_ENABLE_MASK                                                                   0x000F0000L
14706 #define CB_TARGET_MASK__TARGET5_ENABLE_MASK                                                                   0x00F00000L
14707 #define CB_TARGET_MASK__TARGET6_ENABLE_MASK                                                                   0x0F000000L
14708 #define CB_TARGET_MASK__TARGET7_ENABLE_MASK                                                                   0xF0000000L
14709 //CB_SHADER_MASK
14710 #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT                                                                 0x0
14711 #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT                                                                 0x4
14712 #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT                                                                 0x8
14713 #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT                                                                 0xc
14714 #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT                                                                 0x10
14715 #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT                                                                 0x14
14716 #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT                                                                 0x18
14717 #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT                                                                 0x1c
14718 #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK                                                                   0x0000000FL
14719 #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK                                                                   0x000000F0L
14720 #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK                                                                   0x00000F00L
14721 #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK                                                                   0x0000F000L
14722 #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK                                                                   0x000F0000L
14723 #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK                                                                   0x00F00000L
14724 #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK                                                                   0x0F000000L
14725 #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK                                                                   0xF0000000L
14726 //PA_SC_GENERIC_SCISSOR_TL
14727 #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT                                                                 0x0
14728 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT                                                                 0x10
14729 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14730 #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK                                                                   0x00007FFFL
14731 #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK                                                                   0x7FFF0000L
14732 #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14733 //PA_SC_GENERIC_SCISSOR_BR
14734 #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT                                                                 0x0
14735 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT                                                                 0x10
14736 #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK                                                                   0x00007FFFL
14737 #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK                                                                   0x7FFF0000L
14738 //COHER_DEST_BASE_0
14739 #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT                                                              0x0
14740 #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14741 //COHER_DEST_BASE_1
14742 #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT                                                              0x0
14743 #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK                                                                0xFFFFFFFFL
14744 //PA_SC_VPORT_SCISSOR_0_TL
14745 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT                                                                 0x0
14746 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT                                                                 0x10
14747 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14748 #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK                                                                   0x00007FFFL
14749 #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK                                                                   0x7FFF0000L
14750 #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14751 //PA_SC_VPORT_SCISSOR_0_BR
14752 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT                                                                 0x0
14753 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT                                                                 0x10
14754 #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK                                                                   0x00007FFFL
14755 #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK                                                                   0x7FFF0000L
14756 //PA_SC_VPORT_SCISSOR_1_TL
14757 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT                                                                 0x0
14758 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT                                                                 0x10
14759 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14760 #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK                                                                   0x00007FFFL
14761 #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK                                                                   0x7FFF0000L
14762 #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14763 //PA_SC_VPORT_SCISSOR_1_BR
14764 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT                                                                 0x0
14765 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT                                                                 0x10
14766 #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK                                                                   0x00007FFFL
14767 #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK                                                                   0x7FFF0000L
14768 //PA_SC_VPORT_SCISSOR_2_TL
14769 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT                                                                 0x0
14770 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT                                                                 0x10
14771 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14772 #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK                                                                   0x00007FFFL
14773 #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK                                                                   0x7FFF0000L
14774 #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14775 //PA_SC_VPORT_SCISSOR_2_BR
14776 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT                                                                 0x0
14777 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT                                                                 0x10
14778 #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK                                                                   0x00007FFFL
14779 #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK                                                                   0x7FFF0000L
14780 //PA_SC_VPORT_SCISSOR_3_TL
14781 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT                                                                 0x0
14782 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT                                                                 0x10
14783 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14784 #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK                                                                   0x00007FFFL
14785 #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK                                                                   0x7FFF0000L
14786 #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14787 //PA_SC_VPORT_SCISSOR_3_BR
14788 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT                                                                 0x0
14789 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT                                                                 0x10
14790 #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK                                                                   0x00007FFFL
14791 #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK                                                                   0x7FFF0000L
14792 //PA_SC_VPORT_SCISSOR_4_TL
14793 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT                                                                 0x0
14794 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT                                                                 0x10
14795 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14796 #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK                                                                   0x00007FFFL
14797 #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK                                                                   0x7FFF0000L
14798 #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14799 //PA_SC_VPORT_SCISSOR_4_BR
14800 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT                                                                 0x0
14801 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT                                                                 0x10
14802 #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK                                                                   0x00007FFFL
14803 #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK                                                                   0x7FFF0000L
14804 //PA_SC_VPORT_SCISSOR_5_TL
14805 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT                                                                 0x0
14806 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT                                                                 0x10
14807 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14808 #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK                                                                   0x00007FFFL
14809 #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK                                                                   0x7FFF0000L
14810 #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14811 //PA_SC_VPORT_SCISSOR_5_BR
14812 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT                                                                 0x0
14813 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT                                                                 0x10
14814 #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK                                                                   0x00007FFFL
14815 #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK                                                                   0x7FFF0000L
14816 //PA_SC_VPORT_SCISSOR_6_TL
14817 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT                                                                 0x0
14818 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT                                                                 0x10
14819 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14820 #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK                                                                   0x00007FFFL
14821 #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK                                                                   0x7FFF0000L
14822 #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14823 //PA_SC_VPORT_SCISSOR_6_BR
14824 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT                                                                 0x0
14825 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT                                                                 0x10
14826 #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK                                                                   0x00007FFFL
14827 #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK                                                                   0x7FFF0000L
14828 //PA_SC_VPORT_SCISSOR_7_TL
14829 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT                                                                 0x0
14830 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT                                                                 0x10
14831 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14832 #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK                                                                   0x00007FFFL
14833 #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK                                                                   0x7FFF0000L
14834 #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14835 //PA_SC_VPORT_SCISSOR_7_BR
14836 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT                                                                 0x0
14837 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT                                                                 0x10
14838 #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK                                                                   0x00007FFFL
14839 #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK                                                                   0x7FFF0000L
14840 //PA_SC_VPORT_SCISSOR_8_TL
14841 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT                                                                 0x0
14842 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT                                                                 0x10
14843 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14844 #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK                                                                   0x00007FFFL
14845 #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK                                                                   0x7FFF0000L
14846 #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14847 //PA_SC_VPORT_SCISSOR_8_BR
14848 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT                                                                 0x0
14849 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT                                                                 0x10
14850 #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK                                                                   0x00007FFFL
14851 #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK                                                                   0x7FFF0000L
14852 //PA_SC_VPORT_SCISSOR_9_TL
14853 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT                                                                 0x0
14854 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT                                                                 0x10
14855 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT                                                0x1f
14856 #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK                                                                   0x00007FFFL
14857 #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK                                                                   0x7FFF0000L
14858 #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK                                                  0x80000000L
14859 //PA_SC_VPORT_SCISSOR_9_BR
14860 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT                                                                 0x0
14861 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT                                                                 0x10
14862 #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK                                                                   0x00007FFFL
14863 #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK                                                                   0x7FFF0000L
14864 //PA_SC_VPORT_SCISSOR_10_TL
14865 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT                                                                0x0
14866 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT                                                                0x10
14867 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14868 #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK                                                                  0x00007FFFL
14869 #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK                                                                  0x7FFF0000L
14870 #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14871 //PA_SC_VPORT_SCISSOR_10_BR
14872 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT                                                                0x0
14873 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT                                                                0x10
14874 #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK                                                                  0x00007FFFL
14875 #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK                                                                  0x7FFF0000L
14876 //PA_SC_VPORT_SCISSOR_11_TL
14877 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT                                                                0x0
14878 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT                                                                0x10
14879 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14880 #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK                                                                  0x00007FFFL
14881 #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK                                                                  0x7FFF0000L
14882 #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14883 //PA_SC_VPORT_SCISSOR_11_BR
14884 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT                                                                0x0
14885 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT                                                                0x10
14886 #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK                                                                  0x00007FFFL
14887 #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK                                                                  0x7FFF0000L
14888 //PA_SC_VPORT_SCISSOR_12_TL
14889 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT                                                                0x0
14890 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT                                                                0x10
14891 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14892 #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK                                                                  0x00007FFFL
14893 #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK                                                                  0x7FFF0000L
14894 #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14895 //PA_SC_VPORT_SCISSOR_12_BR
14896 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT                                                                0x0
14897 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT                                                                0x10
14898 #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK                                                                  0x00007FFFL
14899 #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK                                                                  0x7FFF0000L
14900 //PA_SC_VPORT_SCISSOR_13_TL
14901 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT                                                                0x0
14902 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT                                                                0x10
14903 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14904 #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK                                                                  0x00007FFFL
14905 #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK                                                                  0x7FFF0000L
14906 #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14907 //PA_SC_VPORT_SCISSOR_13_BR
14908 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT                                                                0x0
14909 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT                                                                0x10
14910 #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK                                                                  0x00007FFFL
14911 #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK                                                                  0x7FFF0000L
14912 //PA_SC_VPORT_SCISSOR_14_TL
14913 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT                                                                0x0
14914 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT                                                                0x10
14915 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14916 #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK                                                                  0x00007FFFL
14917 #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK                                                                  0x7FFF0000L
14918 #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14919 //PA_SC_VPORT_SCISSOR_14_BR
14920 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT                                                                0x0
14921 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT                                                                0x10
14922 #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK                                                                  0x00007FFFL
14923 #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK                                                                  0x7FFF0000L
14924 //PA_SC_VPORT_SCISSOR_15_TL
14925 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT                                                                0x0
14926 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT                                                                0x10
14927 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT                                               0x1f
14928 #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK                                                                  0x00007FFFL
14929 #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK                                                                  0x7FFF0000L
14930 #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK                                                 0x80000000L
14931 //PA_SC_VPORT_SCISSOR_15_BR
14932 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT                                                                0x0
14933 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT                                                                0x10
14934 #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK                                                                  0x00007FFFL
14935 #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK                                                                  0x7FFF0000L
14936 //PA_SC_VPORT_ZMIN_0
14937 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT                                                                 0x0
14938 #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14939 //PA_SC_VPORT_ZMAX_0
14940 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT                                                                 0x0
14941 #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14942 //PA_SC_VPORT_ZMIN_1
14943 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT                                                                 0x0
14944 #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14945 //PA_SC_VPORT_ZMAX_1
14946 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT                                                                 0x0
14947 #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14948 //PA_SC_VPORT_ZMIN_2
14949 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT                                                                 0x0
14950 #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14951 //PA_SC_VPORT_ZMAX_2
14952 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT                                                                 0x0
14953 #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14954 //PA_SC_VPORT_ZMIN_3
14955 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT                                                                 0x0
14956 #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14957 //PA_SC_VPORT_ZMAX_3
14958 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT                                                                 0x0
14959 #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14960 //PA_SC_VPORT_ZMIN_4
14961 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT                                                                 0x0
14962 #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14963 //PA_SC_VPORT_ZMAX_4
14964 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT                                                                 0x0
14965 #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14966 //PA_SC_VPORT_ZMIN_5
14967 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT                                                                 0x0
14968 #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14969 //PA_SC_VPORT_ZMAX_5
14970 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT                                                                 0x0
14971 #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14972 //PA_SC_VPORT_ZMIN_6
14973 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT                                                                 0x0
14974 #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14975 //PA_SC_VPORT_ZMAX_6
14976 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT                                                                 0x0
14977 #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14978 //PA_SC_VPORT_ZMIN_7
14979 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT                                                                 0x0
14980 #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14981 //PA_SC_VPORT_ZMAX_7
14982 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT                                                                 0x0
14983 #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14984 //PA_SC_VPORT_ZMIN_8
14985 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT                                                                 0x0
14986 #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14987 //PA_SC_VPORT_ZMAX_8
14988 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT                                                                 0x0
14989 #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14990 //PA_SC_VPORT_ZMIN_9
14991 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT                                                                 0x0
14992 #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK                                                                   0xFFFFFFFFL
14993 //PA_SC_VPORT_ZMAX_9
14994 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT                                                                 0x0
14995 #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK                                                                   0xFFFFFFFFL
14996 //PA_SC_VPORT_ZMIN_10
14997 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT                                                                0x0
14998 #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
14999 //PA_SC_VPORT_ZMAX_10
15000 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT                                                                0x0
15001 #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15002 //PA_SC_VPORT_ZMIN_11
15003 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT                                                                0x0
15004 #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
15005 //PA_SC_VPORT_ZMAX_11
15006 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT                                                                0x0
15007 #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15008 //PA_SC_VPORT_ZMIN_12
15009 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT                                                                0x0
15010 #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
15011 //PA_SC_VPORT_ZMAX_12
15012 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT                                                                0x0
15013 #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15014 //PA_SC_VPORT_ZMIN_13
15015 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT                                                                0x0
15016 #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
15017 //PA_SC_VPORT_ZMAX_13
15018 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT                                                                0x0
15019 #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15020 //PA_SC_VPORT_ZMIN_14
15021 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT                                                                0x0
15022 #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
15023 //PA_SC_VPORT_ZMAX_14
15024 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT                                                                0x0
15025 #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15026 //PA_SC_VPORT_ZMIN_15
15027 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT                                                                0x0
15028 #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK                                                                  0xFFFFFFFFL
15029 //PA_SC_VPORT_ZMAX_15
15030 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT                                                                0x0
15031 #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK                                                                  0xFFFFFFFFL
15032 //PA_SC_RASTER_CONFIG
15033 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT                                                               0x0
15034 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT                                                               0x2
15035 #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT                                                                  0x4
15036 #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT                                                                   0x6
15037 #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT                                                                   0x7
15038 #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT                                                                   0x8
15039 #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT                                                                  0xa
15040 #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT                                                                  0xc
15041 #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT                                                                 0xe
15042 #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT                                                                    0x10
15043 #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT                                                                   0x12
15044 #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT                                                                   0x14
15045 #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT                                                                    0x18
15046 #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT                                                                   0x1a
15047 #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT                                                                   0x1d
15048 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK                                                                 0x00000003L
15049 #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK                                                                 0x0000000CL
15050 #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK                                                                    0x00000030L
15051 #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK                                                                     0x00000040L
15052 #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK                                                                     0x00000080L
15053 #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK                                                                     0x00000300L
15054 #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK                                                                    0x00000C00L
15055 #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK                                                                    0x00003000L
15056 #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK                                                                   0x0000C000L
15057 #define PA_SC_RASTER_CONFIG__SC_MAP_MASK                                                                      0x00030000L
15058 #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK                                                                     0x000C0000L
15059 #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK                                                                     0x00300000L
15060 #define PA_SC_RASTER_CONFIG__SE_MAP_MASK                                                                      0x03000000L
15061 #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK                                                                     0x1C000000L
15062 #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK                                                                     0xE0000000L
15063 //PA_SC_RASTER_CONFIG_1
15064 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT                                                             0x0
15065 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT                                                            0x2
15066 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT                                                            0x5
15067 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK                                                               0x00000003L
15068 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK                                                              0x0000001CL
15069 #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK                                                              0x000000E0L
15070 //PA_SC_SCREEN_EXTENT_CONTROL
15071 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT                                                 0x0
15072 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT                                                  0x2
15073 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK                                                   0x00000003L
15074 #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK                                                    0x0000000CL
15075 //PA_SC_TILE_STEERING_OVERRIDE
15076 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT                                                           0x0
15077 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT                                                           0x1
15078 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT                                                    0x5
15079 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK                                                             0x00000001L
15080 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK                                                             0x00000006L
15081 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK                                                      0x00000060L
15082 //CP_PERFMON_CNTX_CNTL
15083 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT                                                           0x1f
15084 #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK                                                             0x80000000L
15085 //CP_PIPEID
15086 #define CP_PIPEID__PIPE_ID__SHIFT                                                                             0x0
15087 #define CP_PIPEID__PIPE_ID_MASK                                                                               0x00000003L
15088 //CP_RINGID
15089 #define CP_RINGID__RINGID__SHIFT                                                                              0x0
15090 #define CP_RINGID__RINGID_MASK                                                                                0x00000003L
15091 //CP_VMID
15092 #define CP_VMID__VMID__SHIFT                                                                                  0x0
15093 #define CP_VMID__VMID_MASK                                                                                    0x0000000FL
15094 //PA_SC_RIGHT_VERT_GRID
15095 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT                                                                0x0
15096 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT                                                               0x8
15097 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT                                                              0x10
15098 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT                                                               0x18
15099 #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK                                                                  0x000000FFL
15100 #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK                                                                 0x0000FF00L
15101 #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK                                                                0x00FF0000L
15102 #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK                                                                 0xFF000000L
15103 //PA_SC_LEFT_VERT_GRID
15104 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT                                                                 0x0
15105 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT                                                                0x8
15106 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT                                                               0x10
15107 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT                                                                0x18
15108 #define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK                                                                   0x000000FFL
15109 #define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK                                                                  0x0000FF00L
15110 #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK                                                                 0x00FF0000L
15111 #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK                                                                  0xFF000000L
15112 //PA_SC_HORIZ_GRID
15113 #define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT                                                                      0x0
15114 #define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT                                                                     0x8
15115 #define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT                                                                     0x10
15116 #define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT                                                                      0x18
15117 #define PA_SC_HORIZ_GRID__TOP_QTR_MASK                                                                        0x000000FFL
15118 #define PA_SC_HORIZ_GRID__TOP_HALF_MASK                                                                       0x0000FF00L
15119 #define PA_SC_HORIZ_GRID__BOT_HALF_MASK                                                                       0x00FF0000L
15120 #define PA_SC_HORIZ_GRID__BOT_QTR_MASK                                                                        0xFF000000L
15121 //VGT_MULTI_PRIM_IB_RESET_INDX
15122 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT                                                       0x0
15123 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK                                                         0xFFFFFFFFL
15124 //CB_BLEND_RED
15125 #define CB_BLEND_RED__BLEND_RED__SHIFT                                                                        0x0
15126 #define CB_BLEND_RED__BLEND_RED_MASK                                                                          0xFFFFFFFFL
15127 //CB_BLEND_GREEN
15128 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT                                                                    0x0
15129 #define CB_BLEND_GREEN__BLEND_GREEN_MASK                                                                      0xFFFFFFFFL
15130 //CB_BLEND_BLUE
15131 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT                                                                      0x0
15132 #define CB_BLEND_BLUE__BLEND_BLUE_MASK                                                                        0xFFFFFFFFL
15133 //CB_BLEND_ALPHA
15134 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT                                                                    0x0
15135 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK                                                                      0xFFFFFFFFL
15136 //CB_DCC_CONTROL
15137 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                                     0x0
15138 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT                                         0x1
15139 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT                                                   0x2
15140 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                       0x00000001L
15141 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK                                           0x00000002L
15142 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK                                                     0x0000007CL
15143 //DB_STENCIL_CONTROL
15144 #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT                                                                0x0
15145 #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT                                                               0x4
15146 #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT                                                               0x8
15147 #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT                                                             0xc
15148 #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT                                                            0x10
15149 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT                                                            0x14
15150 #define DB_STENCIL_CONTROL__STENCILFAIL_MASK                                                                  0x0000000FL
15151 #define DB_STENCIL_CONTROL__STENCILZPASS_MASK                                                                 0x000000F0L
15152 #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK                                                                 0x00000F00L
15153 #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK                                                               0x0000F000L
15154 #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK                                                              0x000F0000L
15155 #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK                                                              0x00F00000L
15156 //DB_STENCILREFMASK
15157 #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT                                                              0x0
15158 #define DB_STENCILREFMASK__STENCILMASK__SHIFT                                                                 0x8
15159 #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT                                                            0x10
15160 #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT                                                                0x18
15161 #define DB_STENCILREFMASK__STENCILTESTVAL_MASK                                                                0x000000FFL
15162 #define DB_STENCILREFMASK__STENCILMASK_MASK                                                                   0x0000FF00L
15163 #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK                                                              0x00FF0000L
15164 #define DB_STENCILREFMASK__STENCILOPVAL_MASK                                                                  0xFF000000L
15165 //DB_STENCILREFMASK_BF
15166 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT                                                        0x0
15167 #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT                                                           0x8
15168 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT                                                      0x10
15169 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT                                                          0x18
15170 #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK                                                          0x000000FFL
15171 #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK                                                             0x0000FF00L
15172 #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK                                                        0x00FF0000L
15173 #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK                                                            0xFF000000L
15174 //PA_CL_VPORT_XSCALE
15175 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT                                                               0x0
15176 #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK                                                                 0xFFFFFFFFL
15177 //PA_CL_VPORT_XOFFSET
15178 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT                                                             0x0
15179 #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK                                                               0xFFFFFFFFL
15180 //PA_CL_VPORT_YSCALE
15181 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT                                                               0x0
15182 #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK                                                                 0xFFFFFFFFL
15183 //PA_CL_VPORT_YOFFSET
15184 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT                                                             0x0
15185 #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK                                                               0xFFFFFFFFL
15186 //PA_CL_VPORT_ZSCALE
15187 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT                                                               0x0
15188 #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK                                                                 0xFFFFFFFFL
15189 //PA_CL_VPORT_ZOFFSET
15190 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT                                                             0x0
15191 #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK                                                               0xFFFFFFFFL
15192 //PA_CL_VPORT_XSCALE_1
15193 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT                                                             0x0
15194 #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15195 //PA_CL_VPORT_XOFFSET_1
15196 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT                                                           0x0
15197 #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15198 //PA_CL_VPORT_YSCALE_1
15199 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT                                                             0x0
15200 #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15201 //PA_CL_VPORT_YOFFSET_1
15202 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT                                                           0x0
15203 #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15204 //PA_CL_VPORT_ZSCALE_1
15205 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT                                                             0x0
15206 #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15207 //PA_CL_VPORT_ZOFFSET_1
15208 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT                                                           0x0
15209 #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15210 //PA_CL_VPORT_XSCALE_2
15211 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT                                                             0x0
15212 #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15213 //PA_CL_VPORT_XOFFSET_2
15214 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT                                                           0x0
15215 #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15216 //PA_CL_VPORT_YSCALE_2
15217 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT                                                             0x0
15218 #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15219 //PA_CL_VPORT_YOFFSET_2
15220 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT                                                           0x0
15221 #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15222 //PA_CL_VPORT_ZSCALE_2
15223 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT                                                             0x0
15224 #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15225 //PA_CL_VPORT_ZOFFSET_2
15226 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT                                                           0x0
15227 #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15228 //PA_CL_VPORT_XSCALE_3
15229 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT                                                             0x0
15230 #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15231 //PA_CL_VPORT_XOFFSET_3
15232 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT                                                           0x0
15233 #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15234 //PA_CL_VPORT_YSCALE_3
15235 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT                                                             0x0
15236 #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15237 //PA_CL_VPORT_YOFFSET_3
15238 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT                                                           0x0
15239 #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15240 //PA_CL_VPORT_ZSCALE_3
15241 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT                                                             0x0
15242 #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15243 //PA_CL_VPORT_ZOFFSET_3
15244 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT                                                           0x0
15245 #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15246 //PA_CL_VPORT_XSCALE_4
15247 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT                                                             0x0
15248 #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15249 //PA_CL_VPORT_XOFFSET_4
15250 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT                                                           0x0
15251 #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15252 //PA_CL_VPORT_YSCALE_4
15253 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT                                                             0x0
15254 #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15255 //PA_CL_VPORT_YOFFSET_4
15256 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT                                                           0x0
15257 #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15258 //PA_CL_VPORT_ZSCALE_4
15259 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT                                                             0x0
15260 #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15261 //PA_CL_VPORT_ZOFFSET_4
15262 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT                                                           0x0
15263 #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15264 //PA_CL_VPORT_XSCALE_5
15265 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT                                                             0x0
15266 #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15267 //PA_CL_VPORT_XOFFSET_5
15268 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT                                                           0x0
15269 #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15270 //PA_CL_VPORT_YSCALE_5
15271 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT                                                             0x0
15272 #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15273 //PA_CL_VPORT_YOFFSET_5
15274 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT                                                           0x0
15275 #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15276 //PA_CL_VPORT_ZSCALE_5
15277 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT                                                             0x0
15278 #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15279 //PA_CL_VPORT_ZOFFSET_5
15280 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT                                                           0x0
15281 #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15282 //PA_CL_VPORT_XSCALE_6
15283 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT                                                             0x0
15284 #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15285 //PA_CL_VPORT_XOFFSET_6
15286 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT                                                           0x0
15287 #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15288 //PA_CL_VPORT_YSCALE_6
15289 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT                                                             0x0
15290 #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15291 //PA_CL_VPORT_YOFFSET_6
15292 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT                                                           0x0
15293 #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15294 //PA_CL_VPORT_ZSCALE_6
15295 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT                                                             0x0
15296 #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15297 //PA_CL_VPORT_ZOFFSET_6
15298 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT                                                           0x0
15299 #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15300 //PA_CL_VPORT_XSCALE_7
15301 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT                                                             0x0
15302 #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15303 //PA_CL_VPORT_XOFFSET_7
15304 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT                                                           0x0
15305 #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15306 //PA_CL_VPORT_YSCALE_7
15307 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT                                                             0x0
15308 #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15309 //PA_CL_VPORT_YOFFSET_7
15310 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT                                                           0x0
15311 #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15312 //PA_CL_VPORT_ZSCALE_7
15313 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT                                                             0x0
15314 #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15315 //PA_CL_VPORT_ZOFFSET_7
15316 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT                                                           0x0
15317 #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15318 //PA_CL_VPORT_XSCALE_8
15319 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT                                                             0x0
15320 #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15321 //PA_CL_VPORT_XOFFSET_8
15322 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT                                                           0x0
15323 #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15324 //PA_CL_VPORT_YSCALE_8
15325 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT                                                             0x0
15326 #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15327 //PA_CL_VPORT_YOFFSET_8
15328 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT                                                           0x0
15329 #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15330 //PA_CL_VPORT_ZSCALE_8
15331 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT                                                             0x0
15332 #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15333 //PA_CL_VPORT_ZOFFSET_8
15334 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT                                                           0x0
15335 #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15336 //PA_CL_VPORT_XSCALE_9
15337 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT                                                             0x0
15338 #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK                                                               0xFFFFFFFFL
15339 //PA_CL_VPORT_XOFFSET_9
15340 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT                                                           0x0
15341 #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK                                                             0xFFFFFFFFL
15342 //PA_CL_VPORT_YSCALE_9
15343 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT                                                             0x0
15344 #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK                                                               0xFFFFFFFFL
15345 //PA_CL_VPORT_YOFFSET_9
15346 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT                                                           0x0
15347 #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK                                                             0xFFFFFFFFL
15348 //PA_CL_VPORT_ZSCALE_9
15349 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT                                                             0x0
15350 #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK                                                               0xFFFFFFFFL
15351 //PA_CL_VPORT_ZOFFSET_9
15352 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT                                                           0x0
15353 #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK                                                             0xFFFFFFFFL
15354 //PA_CL_VPORT_XSCALE_10
15355 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT                                                            0x0
15356 #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15357 //PA_CL_VPORT_XOFFSET_10
15358 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT                                                          0x0
15359 #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15360 //PA_CL_VPORT_YSCALE_10
15361 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT                                                            0x0
15362 #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15363 //PA_CL_VPORT_YOFFSET_10
15364 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT                                                          0x0
15365 #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15366 //PA_CL_VPORT_ZSCALE_10
15367 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT                                                            0x0
15368 #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15369 //PA_CL_VPORT_ZOFFSET_10
15370 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT                                                          0x0
15371 #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15372 //PA_CL_VPORT_XSCALE_11
15373 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT                                                            0x0
15374 #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15375 //PA_CL_VPORT_XOFFSET_11
15376 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT                                                          0x0
15377 #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15378 //PA_CL_VPORT_YSCALE_11
15379 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT                                                            0x0
15380 #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15381 //PA_CL_VPORT_YOFFSET_11
15382 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT                                                          0x0
15383 #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15384 //PA_CL_VPORT_ZSCALE_11
15385 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT                                                            0x0
15386 #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15387 //PA_CL_VPORT_ZOFFSET_11
15388 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT                                                          0x0
15389 #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15390 //PA_CL_VPORT_XSCALE_12
15391 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT                                                            0x0
15392 #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15393 //PA_CL_VPORT_XOFFSET_12
15394 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT                                                          0x0
15395 #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15396 //PA_CL_VPORT_YSCALE_12
15397 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT                                                            0x0
15398 #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15399 //PA_CL_VPORT_YOFFSET_12
15400 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT                                                          0x0
15401 #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15402 //PA_CL_VPORT_ZSCALE_12
15403 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT                                                            0x0
15404 #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15405 //PA_CL_VPORT_ZOFFSET_12
15406 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT                                                          0x0
15407 #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15408 //PA_CL_VPORT_XSCALE_13
15409 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT                                                            0x0
15410 #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15411 //PA_CL_VPORT_XOFFSET_13
15412 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT                                                          0x0
15413 #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15414 //PA_CL_VPORT_YSCALE_13
15415 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT                                                            0x0
15416 #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15417 //PA_CL_VPORT_YOFFSET_13
15418 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT                                                          0x0
15419 #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15420 //PA_CL_VPORT_ZSCALE_13
15421 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT                                                            0x0
15422 #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15423 //PA_CL_VPORT_ZOFFSET_13
15424 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT                                                          0x0
15425 #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15426 //PA_CL_VPORT_XSCALE_14
15427 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT                                                            0x0
15428 #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15429 //PA_CL_VPORT_XOFFSET_14
15430 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT                                                          0x0
15431 #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15432 //PA_CL_VPORT_YSCALE_14
15433 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT                                                            0x0
15434 #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15435 //PA_CL_VPORT_YOFFSET_14
15436 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT                                                          0x0
15437 #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15438 //PA_CL_VPORT_ZSCALE_14
15439 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT                                                            0x0
15440 #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15441 //PA_CL_VPORT_ZOFFSET_14
15442 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT                                                          0x0
15443 #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15444 //PA_CL_VPORT_XSCALE_15
15445 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT                                                            0x0
15446 #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK                                                              0xFFFFFFFFL
15447 //PA_CL_VPORT_XOFFSET_15
15448 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT                                                          0x0
15449 #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK                                                            0xFFFFFFFFL
15450 //PA_CL_VPORT_YSCALE_15
15451 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT                                                            0x0
15452 #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK                                                              0xFFFFFFFFL
15453 //PA_CL_VPORT_YOFFSET_15
15454 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT                                                          0x0
15455 #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK                                                            0xFFFFFFFFL
15456 //PA_CL_VPORT_ZSCALE_15
15457 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT                                                            0x0
15458 #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK                                                              0xFFFFFFFFL
15459 //PA_CL_VPORT_ZOFFSET_15
15460 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT                                                          0x0
15461 #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK                                                            0xFFFFFFFFL
15462 //PA_CL_UCP_0_X
15463 #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT                                                                   0x0
15464 #define PA_CL_UCP_0_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15465 //PA_CL_UCP_0_Y
15466 #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT                                                                   0x0
15467 #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15468 //PA_CL_UCP_0_Z
15469 #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT                                                                   0x0
15470 #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15471 //PA_CL_UCP_0_W
15472 #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT                                                                   0x0
15473 #define PA_CL_UCP_0_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15474 //PA_CL_UCP_1_X
15475 #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT                                                                   0x0
15476 #define PA_CL_UCP_1_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15477 //PA_CL_UCP_1_Y
15478 #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT                                                                   0x0
15479 #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15480 //PA_CL_UCP_1_Z
15481 #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT                                                                   0x0
15482 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15483 //PA_CL_UCP_1_W
15484 #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT                                                                   0x0
15485 #define PA_CL_UCP_1_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15486 //PA_CL_UCP_2_X
15487 #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT                                                                   0x0
15488 #define PA_CL_UCP_2_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15489 //PA_CL_UCP_2_Y
15490 #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT                                                                   0x0
15491 #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15492 //PA_CL_UCP_2_Z
15493 #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT                                                                   0x0
15494 #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15495 //PA_CL_UCP_2_W
15496 #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT                                                                   0x0
15497 #define PA_CL_UCP_2_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15498 //PA_CL_UCP_3_X
15499 #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT                                                                   0x0
15500 #define PA_CL_UCP_3_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15501 //PA_CL_UCP_3_Y
15502 #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT                                                                   0x0
15503 #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15504 //PA_CL_UCP_3_Z
15505 #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT                                                                   0x0
15506 #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15507 //PA_CL_UCP_3_W
15508 #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT                                                                   0x0
15509 #define PA_CL_UCP_3_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15510 //PA_CL_UCP_4_X
15511 #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT                                                                   0x0
15512 #define PA_CL_UCP_4_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15513 //PA_CL_UCP_4_Y
15514 #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT                                                                   0x0
15515 #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15516 //PA_CL_UCP_4_Z
15517 #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT                                                                   0x0
15518 #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15519 //PA_CL_UCP_4_W
15520 #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT                                                                   0x0
15521 #define PA_CL_UCP_4_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15522 //PA_CL_UCP_5_X
15523 #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT                                                                   0x0
15524 #define PA_CL_UCP_5_X__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15525 //PA_CL_UCP_5_Y
15526 #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT                                                                   0x0
15527 #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15528 //PA_CL_UCP_5_Z
15529 #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT                                                                   0x0
15530 #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15531 //PA_CL_UCP_5_W
15532 #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT                                                                   0x0
15533 #define PA_CL_UCP_5_W__DATA_REGISTER_MASK                                                                     0xFFFFFFFFL
15534 //SPI_PS_INPUT_CNTL_0
15535 #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT                                                                    0x0
15536 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT                                                               0x8
15537 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT                                                                0xa
15538 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT                                                                  0xd
15539 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT                                                             0x11
15540 #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT                                                                       0x12
15541 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT                                                          0x13
15542 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15543 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15544 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15545 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT                                                               0x18
15546 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT                                                               0x19
15547 #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK                                                                      0x0000003FL
15548 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK                                                                 0x00000300L
15549 #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK                                                                  0x00000400L
15550 #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK                                                                    0x0001E000L
15551 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK                                                               0x00020000L
15552 #define SPI_PS_INPUT_CNTL_0__DUP_MASK                                                                         0x00040000L
15553 #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK                                                            0x00080000L
15554 #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15555 #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15556 #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15557 #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK                                                                 0x01000000L
15558 #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK                                                                 0x02000000L
15559 //SPI_PS_INPUT_CNTL_1
15560 #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT                                                                    0x0
15561 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT                                                               0x8
15562 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT                                                                0xa
15563 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT                                                                  0xd
15564 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT                                                             0x11
15565 #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT                                                                       0x12
15566 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT                                                          0x13
15567 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15568 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15569 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15570 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT                                                               0x18
15571 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT                                                               0x19
15572 #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK                                                                      0x0000003FL
15573 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK                                                                 0x00000300L
15574 #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK                                                                  0x00000400L
15575 #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK                                                                    0x0001E000L
15576 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK                                                               0x00020000L
15577 #define SPI_PS_INPUT_CNTL_1__DUP_MASK                                                                         0x00040000L
15578 #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK                                                            0x00080000L
15579 #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15580 #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15581 #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15582 #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK                                                                 0x01000000L
15583 #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK                                                                 0x02000000L
15584 //SPI_PS_INPUT_CNTL_2
15585 #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT                                                                    0x0
15586 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT                                                               0x8
15587 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT                                                                0xa
15588 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT                                                                  0xd
15589 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT                                                             0x11
15590 #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT                                                                       0x12
15591 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT                                                          0x13
15592 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15593 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15594 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15595 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT                                                               0x18
15596 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT                                                               0x19
15597 #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK                                                                      0x0000003FL
15598 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK                                                                 0x00000300L
15599 #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK                                                                  0x00000400L
15600 #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK                                                                    0x0001E000L
15601 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK                                                               0x00020000L
15602 #define SPI_PS_INPUT_CNTL_2__DUP_MASK                                                                         0x00040000L
15603 #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK                                                            0x00080000L
15604 #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15605 #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15606 #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15607 #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK                                                                 0x01000000L
15608 #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK                                                                 0x02000000L
15609 //SPI_PS_INPUT_CNTL_3
15610 #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT                                                                    0x0
15611 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT                                                               0x8
15612 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT                                                                0xa
15613 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT                                                                  0xd
15614 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT                                                             0x11
15615 #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT                                                                       0x12
15616 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT                                                          0x13
15617 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15618 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15619 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15620 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT                                                               0x18
15621 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT                                                               0x19
15622 #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK                                                                      0x0000003FL
15623 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK                                                                 0x00000300L
15624 #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK                                                                  0x00000400L
15625 #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK                                                                    0x0001E000L
15626 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK                                                               0x00020000L
15627 #define SPI_PS_INPUT_CNTL_3__DUP_MASK                                                                         0x00040000L
15628 #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK                                                            0x00080000L
15629 #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15630 #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15631 #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15632 #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK                                                                 0x01000000L
15633 #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK                                                                 0x02000000L
15634 //SPI_PS_INPUT_CNTL_4
15635 #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT                                                                    0x0
15636 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT                                                               0x8
15637 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT                                                                0xa
15638 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT                                                                  0xd
15639 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT                                                             0x11
15640 #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT                                                                       0x12
15641 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT                                                          0x13
15642 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15643 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15644 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15645 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT                                                               0x18
15646 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT                                                               0x19
15647 #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK                                                                      0x0000003FL
15648 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK                                                                 0x00000300L
15649 #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK                                                                  0x00000400L
15650 #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK                                                                    0x0001E000L
15651 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK                                                               0x00020000L
15652 #define SPI_PS_INPUT_CNTL_4__DUP_MASK                                                                         0x00040000L
15653 #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK                                                            0x00080000L
15654 #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15655 #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15656 #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15657 #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK                                                                 0x01000000L
15658 #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK                                                                 0x02000000L
15659 //SPI_PS_INPUT_CNTL_5
15660 #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT                                                                    0x0
15661 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT                                                               0x8
15662 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT                                                                0xa
15663 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT                                                                  0xd
15664 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT                                                             0x11
15665 #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT                                                                       0x12
15666 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT                                                          0x13
15667 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15668 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15669 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15670 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT                                                               0x18
15671 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT                                                               0x19
15672 #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK                                                                      0x0000003FL
15673 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK                                                                 0x00000300L
15674 #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK                                                                  0x00000400L
15675 #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK                                                                    0x0001E000L
15676 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK                                                               0x00020000L
15677 #define SPI_PS_INPUT_CNTL_5__DUP_MASK                                                                         0x00040000L
15678 #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK                                                            0x00080000L
15679 #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15680 #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15681 #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15682 #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK                                                                 0x01000000L
15683 #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK                                                                 0x02000000L
15684 //SPI_PS_INPUT_CNTL_6
15685 #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT                                                                    0x0
15686 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT                                                               0x8
15687 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT                                                                0xa
15688 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT                                                                  0xd
15689 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT                                                             0x11
15690 #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT                                                                       0x12
15691 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT                                                          0x13
15692 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15693 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15694 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15695 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT                                                               0x18
15696 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT                                                               0x19
15697 #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK                                                                      0x0000003FL
15698 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK                                                                 0x00000300L
15699 #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK                                                                  0x00000400L
15700 #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK                                                                    0x0001E000L
15701 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK                                                               0x00020000L
15702 #define SPI_PS_INPUT_CNTL_6__DUP_MASK                                                                         0x00040000L
15703 #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK                                                            0x00080000L
15704 #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15705 #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15706 #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15707 #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK                                                                 0x01000000L
15708 #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK                                                                 0x02000000L
15709 //SPI_PS_INPUT_CNTL_7
15710 #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT                                                                    0x0
15711 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT                                                               0x8
15712 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT                                                                0xa
15713 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT                                                                  0xd
15714 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT                                                             0x11
15715 #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT                                                                       0x12
15716 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT                                                          0x13
15717 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15718 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15719 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15720 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT                                                               0x18
15721 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT                                                               0x19
15722 #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK                                                                      0x0000003FL
15723 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK                                                                 0x00000300L
15724 #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK                                                                  0x00000400L
15725 #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK                                                                    0x0001E000L
15726 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK                                                               0x00020000L
15727 #define SPI_PS_INPUT_CNTL_7__DUP_MASK                                                                         0x00040000L
15728 #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK                                                            0x00080000L
15729 #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15730 #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15731 #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15732 #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK                                                                 0x01000000L
15733 #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK                                                                 0x02000000L
15734 //SPI_PS_INPUT_CNTL_8
15735 #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT                                                                    0x0
15736 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT                                                               0x8
15737 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT                                                                0xa
15738 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT                                                                  0xd
15739 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT                                                             0x11
15740 #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT                                                                       0x12
15741 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT                                                          0x13
15742 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15743 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15744 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15745 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT                                                               0x18
15746 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT                                                               0x19
15747 #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK                                                                      0x0000003FL
15748 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK                                                                 0x00000300L
15749 #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK                                                                  0x00000400L
15750 #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK                                                                    0x0001E000L
15751 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK                                                               0x00020000L
15752 #define SPI_PS_INPUT_CNTL_8__DUP_MASK                                                                         0x00040000L
15753 #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK                                                            0x00080000L
15754 #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15755 #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15756 #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15757 #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK                                                                 0x01000000L
15758 #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK                                                                 0x02000000L
15759 //SPI_PS_INPUT_CNTL_9
15760 #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT                                                                    0x0
15761 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT                                                               0x8
15762 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT                                                                0xa
15763 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT                                                                  0xd
15764 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT                                                             0x11
15765 #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT                                                                       0x12
15766 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT                                                          0x13
15767 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT                                                         0x14
15768 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT                                                         0x15
15769 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT                                                       0x17
15770 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT                                                               0x18
15771 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT                                                               0x19
15772 #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK                                                                      0x0000003FL
15773 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK                                                                 0x00000300L
15774 #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK                                                                  0x00000400L
15775 #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK                                                                    0x0001E000L
15776 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK                                                               0x00020000L
15777 #define SPI_PS_INPUT_CNTL_9__DUP_MASK                                                                         0x00040000L
15778 #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK                                                            0x00080000L
15779 #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK                                                           0x00100000L
15780 #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK                                                           0x00600000L
15781 #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK                                                         0x00800000L
15782 #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK                                                                 0x01000000L
15783 #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK                                                                 0x02000000L
15784 //SPI_PS_INPUT_CNTL_10
15785 #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT                                                                   0x0
15786 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT                                                              0x8
15787 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT                                                               0xa
15788 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT                                                                 0xd
15789 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT                                                            0x11
15790 #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT                                                                      0x12
15791 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT                                                         0x13
15792 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15793 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15794 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15795 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT                                                              0x18
15796 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT                                                              0x19
15797 #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK                                                                     0x0000003FL
15798 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK                                                                0x00000300L
15799 #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK                                                                 0x00000400L
15800 #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK                                                                   0x0001E000L
15801 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK                                                              0x00020000L
15802 #define SPI_PS_INPUT_CNTL_10__DUP_MASK                                                                        0x00040000L
15803 #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK                                                           0x00080000L
15804 #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15805 #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15806 #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15807 #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK                                                                0x01000000L
15808 #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK                                                                0x02000000L
15809 //SPI_PS_INPUT_CNTL_11
15810 #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT                                                                   0x0
15811 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT                                                              0x8
15812 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT                                                               0xa
15813 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT                                                                 0xd
15814 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT                                                            0x11
15815 #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT                                                                      0x12
15816 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT                                                         0x13
15817 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15818 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15819 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15820 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT                                                              0x18
15821 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT                                                              0x19
15822 #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK                                                                     0x0000003FL
15823 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK                                                                0x00000300L
15824 #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK                                                                 0x00000400L
15825 #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK                                                                   0x0001E000L
15826 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK                                                              0x00020000L
15827 #define SPI_PS_INPUT_CNTL_11__DUP_MASK                                                                        0x00040000L
15828 #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK                                                           0x00080000L
15829 #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15830 #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15831 #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15832 #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK                                                                0x01000000L
15833 #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK                                                                0x02000000L
15834 //SPI_PS_INPUT_CNTL_12
15835 #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT                                                                   0x0
15836 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT                                                              0x8
15837 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT                                                               0xa
15838 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT                                                                 0xd
15839 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT                                                            0x11
15840 #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT                                                                      0x12
15841 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT                                                         0x13
15842 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15843 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15844 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15845 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT                                                              0x18
15846 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT                                                              0x19
15847 #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK                                                                     0x0000003FL
15848 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK                                                                0x00000300L
15849 #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK                                                                 0x00000400L
15850 #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK                                                                   0x0001E000L
15851 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK                                                              0x00020000L
15852 #define SPI_PS_INPUT_CNTL_12__DUP_MASK                                                                        0x00040000L
15853 #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK                                                           0x00080000L
15854 #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15855 #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15856 #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15857 #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK                                                                0x01000000L
15858 #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK                                                                0x02000000L
15859 //SPI_PS_INPUT_CNTL_13
15860 #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT                                                                   0x0
15861 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT                                                              0x8
15862 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT                                                               0xa
15863 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT                                                                 0xd
15864 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT                                                            0x11
15865 #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT                                                                      0x12
15866 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT                                                         0x13
15867 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15868 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15869 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15870 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT                                                              0x18
15871 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT                                                              0x19
15872 #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK                                                                     0x0000003FL
15873 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK                                                                0x00000300L
15874 #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK                                                                 0x00000400L
15875 #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK                                                                   0x0001E000L
15876 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK                                                              0x00020000L
15877 #define SPI_PS_INPUT_CNTL_13__DUP_MASK                                                                        0x00040000L
15878 #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK                                                           0x00080000L
15879 #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15880 #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15881 #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15882 #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK                                                                0x01000000L
15883 #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK                                                                0x02000000L
15884 //SPI_PS_INPUT_CNTL_14
15885 #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT                                                                   0x0
15886 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT                                                              0x8
15887 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT                                                               0xa
15888 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT                                                                 0xd
15889 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT                                                            0x11
15890 #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT                                                                      0x12
15891 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT                                                         0x13
15892 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15893 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15894 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15895 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT                                                              0x18
15896 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT                                                              0x19
15897 #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK                                                                     0x0000003FL
15898 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK                                                                0x00000300L
15899 #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK                                                                 0x00000400L
15900 #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK                                                                   0x0001E000L
15901 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK                                                              0x00020000L
15902 #define SPI_PS_INPUT_CNTL_14__DUP_MASK                                                                        0x00040000L
15903 #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK                                                           0x00080000L
15904 #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15905 #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15906 #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15907 #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK                                                                0x01000000L
15908 #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK                                                                0x02000000L
15909 //SPI_PS_INPUT_CNTL_15
15910 #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT                                                                   0x0
15911 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT                                                              0x8
15912 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT                                                               0xa
15913 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT                                                                 0xd
15914 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT                                                            0x11
15915 #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT                                                                      0x12
15916 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT                                                         0x13
15917 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15918 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15919 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15920 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT                                                              0x18
15921 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT                                                              0x19
15922 #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK                                                                     0x0000003FL
15923 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK                                                                0x00000300L
15924 #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK                                                                 0x00000400L
15925 #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK                                                                   0x0001E000L
15926 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK                                                              0x00020000L
15927 #define SPI_PS_INPUT_CNTL_15__DUP_MASK                                                                        0x00040000L
15928 #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK                                                           0x00080000L
15929 #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15930 #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15931 #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15932 #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK                                                                0x01000000L
15933 #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK                                                                0x02000000L
15934 //SPI_PS_INPUT_CNTL_16
15935 #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT                                                                   0x0
15936 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT                                                              0x8
15937 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT                                                               0xa
15938 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT                                                                 0xd
15939 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT                                                            0x11
15940 #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT                                                                      0x12
15941 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT                                                         0x13
15942 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15943 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15944 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15945 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT                                                              0x18
15946 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT                                                              0x19
15947 #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK                                                                     0x0000003FL
15948 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK                                                                0x00000300L
15949 #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK                                                                 0x00000400L
15950 #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK                                                                   0x0001E000L
15951 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK                                                              0x00020000L
15952 #define SPI_PS_INPUT_CNTL_16__DUP_MASK                                                                        0x00040000L
15953 #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK                                                           0x00080000L
15954 #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15955 #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15956 #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15957 #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK                                                                0x01000000L
15958 #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK                                                                0x02000000L
15959 //SPI_PS_INPUT_CNTL_17
15960 #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT                                                                   0x0
15961 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT                                                              0x8
15962 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT                                                               0xa
15963 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT                                                                 0xd
15964 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT                                                            0x11
15965 #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT                                                                      0x12
15966 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT                                                         0x13
15967 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15968 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15969 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15970 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT                                                              0x18
15971 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT                                                              0x19
15972 #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK                                                                     0x0000003FL
15973 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK                                                                0x00000300L
15974 #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK                                                                 0x00000400L
15975 #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK                                                                   0x0001E000L
15976 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK                                                              0x00020000L
15977 #define SPI_PS_INPUT_CNTL_17__DUP_MASK                                                                        0x00040000L
15978 #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK                                                           0x00080000L
15979 #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
15980 #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
15981 #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
15982 #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK                                                                0x01000000L
15983 #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK                                                                0x02000000L
15984 //SPI_PS_INPUT_CNTL_18
15985 #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT                                                                   0x0
15986 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT                                                              0x8
15987 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT                                                               0xa
15988 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT                                                                 0xd
15989 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT                                                            0x11
15990 #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT                                                                      0x12
15991 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT                                                         0x13
15992 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
15993 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
15994 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
15995 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT                                                              0x18
15996 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT                                                              0x19
15997 #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK                                                                     0x0000003FL
15998 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK                                                                0x00000300L
15999 #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK                                                                 0x00000400L
16000 #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK                                                                   0x0001E000L
16001 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK                                                              0x00020000L
16002 #define SPI_PS_INPUT_CNTL_18__DUP_MASK                                                                        0x00040000L
16003 #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK                                                           0x00080000L
16004 #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16005 #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16006 #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
16007 #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK                                                                0x01000000L
16008 #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK                                                                0x02000000L
16009 //SPI_PS_INPUT_CNTL_19
16010 #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT                                                                   0x0
16011 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT                                                              0x8
16012 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT                                                               0xa
16013 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT                                                                 0xd
16014 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT                                                            0x11
16015 #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT                                                                      0x12
16016 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT                                                         0x13
16017 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16018 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16019 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT                                                      0x17
16020 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT                                                              0x18
16021 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT                                                              0x19
16022 #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK                                                                     0x0000003FL
16023 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK                                                                0x00000300L
16024 #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK                                                                 0x00000400L
16025 #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK                                                                   0x0001E000L
16026 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK                                                              0x00020000L
16027 #define SPI_PS_INPUT_CNTL_19__DUP_MASK                                                                        0x00040000L
16028 #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK                                                           0x00080000L
16029 #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16030 #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16031 #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK                                                        0x00800000L
16032 #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK                                                                0x01000000L
16033 #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK                                                                0x02000000L
16034 //SPI_PS_INPUT_CNTL_20
16035 #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT                                                                   0x0
16036 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT                                                              0x8
16037 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT                                                               0xa
16038 #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT                                                                      0x12
16039 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT                                                         0x13
16040 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16041 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16042 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT                                                              0x18
16043 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT                                                              0x19
16044 #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK                                                                     0x0000003FL
16045 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK                                                                0x00000300L
16046 #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK                                                                 0x00000400L
16047 #define SPI_PS_INPUT_CNTL_20__DUP_MASK                                                                        0x00040000L
16048 #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK                                                           0x00080000L
16049 #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16050 #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16051 #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK                                                                0x01000000L
16052 #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK                                                                0x02000000L
16053 //SPI_PS_INPUT_CNTL_21
16054 #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT                                                                   0x0
16055 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT                                                              0x8
16056 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT                                                               0xa
16057 #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT                                                                      0x12
16058 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT                                                         0x13
16059 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16060 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16061 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT                                                              0x18
16062 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT                                                              0x19
16063 #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK                                                                     0x0000003FL
16064 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK                                                                0x00000300L
16065 #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK                                                                 0x00000400L
16066 #define SPI_PS_INPUT_CNTL_21__DUP_MASK                                                                        0x00040000L
16067 #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK                                                           0x00080000L
16068 #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16069 #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16070 #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK                                                                0x01000000L
16071 #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK                                                                0x02000000L
16072 //SPI_PS_INPUT_CNTL_22
16073 #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT                                                                   0x0
16074 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT                                                              0x8
16075 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT                                                               0xa
16076 #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT                                                                      0x12
16077 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT                                                         0x13
16078 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16079 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16080 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT                                                              0x18
16081 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT                                                              0x19
16082 #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK                                                                     0x0000003FL
16083 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK                                                                0x00000300L
16084 #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK                                                                 0x00000400L
16085 #define SPI_PS_INPUT_CNTL_22__DUP_MASK                                                                        0x00040000L
16086 #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK                                                           0x00080000L
16087 #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16088 #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16089 #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK                                                                0x01000000L
16090 #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK                                                                0x02000000L
16091 //SPI_PS_INPUT_CNTL_23
16092 #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT                                                                   0x0
16093 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT                                                              0x8
16094 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT                                                               0xa
16095 #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT                                                                      0x12
16096 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT                                                         0x13
16097 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16098 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16099 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT                                                              0x18
16100 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT                                                              0x19
16101 #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK                                                                     0x0000003FL
16102 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK                                                                0x00000300L
16103 #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK                                                                 0x00000400L
16104 #define SPI_PS_INPUT_CNTL_23__DUP_MASK                                                                        0x00040000L
16105 #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK                                                           0x00080000L
16106 #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16107 #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16108 #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK                                                                0x01000000L
16109 #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK                                                                0x02000000L
16110 //SPI_PS_INPUT_CNTL_24
16111 #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT                                                                   0x0
16112 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT                                                              0x8
16113 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT                                                               0xa
16114 #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT                                                                      0x12
16115 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT                                                         0x13
16116 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16117 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16118 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT                                                              0x18
16119 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT                                                              0x19
16120 #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK                                                                     0x0000003FL
16121 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK                                                                0x00000300L
16122 #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK                                                                 0x00000400L
16123 #define SPI_PS_INPUT_CNTL_24__DUP_MASK                                                                        0x00040000L
16124 #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK                                                           0x00080000L
16125 #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16126 #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16127 #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK                                                                0x01000000L
16128 #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK                                                                0x02000000L
16129 //SPI_PS_INPUT_CNTL_25
16130 #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT                                                                   0x0
16131 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT                                                              0x8
16132 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT                                                               0xa
16133 #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT                                                                      0x12
16134 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT                                                         0x13
16135 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16136 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16137 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT                                                              0x18
16138 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT                                                              0x19
16139 #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK                                                                     0x0000003FL
16140 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK                                                                0x00000300L
16141 #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK                                                                 0x00000400L
16142 #define SPI_PS_INPUT_CNTL_25__DUP_MASK                                                                        0x00040000L
16143 #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK                                                           0x00080000L
16144 #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16145 #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16146 #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK                                                                0x01000000L
16147 #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK                                                                0x02000000L
16148 //SPI_PS_INPUT_CNTL_26
16149 #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT                                                                   0x0
16150 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT                                                              0x8
16151 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT                                                               0xa
16152 #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT                                                                      0x12
16153 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT                                                         0x13
16154 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16155 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16156 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT                                                              0x18
16157 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT                                                              0x19
16158 #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK                                                                     0x0000003FL
16159 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK                                                                0x00000300L
16160 #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK                                                                 0x00000400L
16161 #define SPI_PS_INPUT_CNTL_26__DUP_MASK                                                                        0x00040000L
16162 #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK                                                           0x00080000L
16163 #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16164 #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16165 #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK                                                                0x01000000L
16166 #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK                                                                0x02000000L
16167 //SPI_PS_INPUT_CNTL_27
16168 #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT                                                                   0x0
16169 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT                                                              0x8
16170 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT                                                               0xa
16171 #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT                                                                      0x12
16172 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT                                                         0x13
16173 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16174 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16175 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT                                                              0x18
16176 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT                                                              0x19
16177 #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK                                                                     0x0000003FL
16178 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK                                                                0x00000300L
16179 #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK                                                                 0x00000400L
16180 #define SPI_PS_INPUT_CNTL_27__DUP_MASK                                                                        0x00040000L
16181 #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK                                                           0x00080000L
16182 #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16183 #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16184 #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK                                                                0x01000000L
16185 #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK                                                                0x02000000L
16186 //SPI_PS_INPUT_CNTL_28
16187 #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT                                                                   0x0
16188 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT                                                              0x8
16189 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT                                                               0xa
16190 #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT                                                                      0x12
16191 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT                                                         0x13
16192 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16193 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16194 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT                                                              0x18
16195 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT                                                              0x19
16196 #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK                                                                     0x0000003FL
16197 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK                                                                0x00000300L
16198 #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK                                                                 0x00000400L
16199 #define SPI_PS_INPUT_CNTL_28__DUP_MASK                                                                        0x00040000L
16200 #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK                                                           0x00080000L
16201 #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16202 #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16203 #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK                                                                0x01000000L
16204 #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK                                                                0x02000000L
16205 //SPI_PS_INPUT_CNTL_29
16206 #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT                                                                   0x0
16207 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT                                                              0x8
16208 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT                                                               0xa
16209 #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT                                                                      0x12
16210 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT                                                         0x13
16211 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16212 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16213 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT                                                              0x18
16214 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT                                                              0x19
16215 #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK                                                                     0x0000003FL
16216 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK                                                                0x00000300L
16217 #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK                                                                 0x00000400L
16218 #define SPI_PS_INPUT_CNTL_29__DUP_MASK                                                                        0x00040000L
16219 #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK                                                           0x00080000L
16220 #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16221 #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16222 #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK                                                                0x01000000L
16223 #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK                                                                0x02000000L
16224 //SPI_PS_INPUT_CNTL_30
16225 #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT                                                                   0x0
16226 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT                                                              0x8
16227 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT                                                               0xa
16228 #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT                                                                      0x12
16229 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT                                                         0x13
16230 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16231 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16232 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT                                                              0x18
16233 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT                                                              0x19
16234 #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK                                                                     0x0000003FL
16235 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK                                                                0x00000300L
16236 #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK                                                                 0x00000400L
16237 #define SPI_PS_INPUT_CNTL_30__DUP_MASK                                                                        0x00040000L
16238 #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK                                                           0x00080000L
16239 #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16240 #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16241 #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK                                                                0x01000000L
16242 #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK                                                                0x02000000L
16243 //SPI_PS_INPUT_CNTL_31
16244 #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT                                                                   0x0
16245 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT                                                              0x8
16246 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT                                                               0xa
16247 #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT                                                                      0x12
16248 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT                                                         0x13
16249 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT                                                        0x14
16250 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT                                                        0x15
16251 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT                                                              0x18
16252 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT                                                              0x19
16253 #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK                                                                     0x0000003FL
16254 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK                                                                0x00000300L
16255 #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK                                                                 0x00000400L
16256 #define SPI_PS_INPUT_CNTL_31__DUP_MASK                                                                        0x00040000L
16257 #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK                                                           0x00080000L
16258 #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK                                                          0x00100000L
16259 #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK                                                          0x00600000L
16260 #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK                                                                0x01000000L
16261 #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK                                                                0x02000000L
16262 //SPI_VS_OUT_CONFIG
16263 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT                                                             0x1
16264 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT                                                                0x6
16265 #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK                                                               0x0000003EL
16266 #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK                                                                  0x00000040L
16267 //SPI_PS_INPUT_ENA
16268 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT                                                             0x0
16269 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT                                                             0x1
16270 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT                                                           0x2
16271 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT                                                         0x3
16272 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT                                                            0x4
16273 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT                                                            0x5
16274 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT                                                          0x6
16275 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT                                                         0x7
16276 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT                                                              0x8
16277 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT                                                              0x9
16278 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT                                                              0xa
16279 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT                                                              0xb
16280 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT                                                               0xc
16281 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT                                                                0xd
16282 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT                                                          0xe
16283 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT                                                             0xf
16284 #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK                                                               0x00000001L
16285 #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK                                                               0x00000002L
16286 #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK                                                             0x00000004L
16287 #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK                                                           0x00000008L
16288 #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK                                                              0x00000010L
16289 #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK                                                              0x00000020L
16290 #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK                                                            0x00000040L
16291 #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK                                                           0x00000080L
16292 #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK                                                                0x00000100L
16293 #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK                                                                0x00000200L
16294 #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK                                                                0x00000400L
16295 #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK                                                                0x00000800L
16296 #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK                                                                 0x00001000L
16297 #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK                                                                  0x00002000L
16298 #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK                                                            0x00004000L
16299 #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK                                                               0x00008000L
16300 //SPI_PS_INPUT_ADDR
16301 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT                                                            0x0
16302 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT                                                            0x1
16303 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT                                                          0x2
16304 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT                                                        0x3
16305 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT                                                           0x4
16306 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT                                                           0x5
16307 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT                                                         0x6
16308 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT                                                        0x7
16309 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT                                                             0x8
16310 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT                                                             0x9
16311 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT                                                             0xa
16312 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT                                                             0xb
16313 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT                                                              0xc
16314 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT                                                               0xd
16315 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT                                                         0xe
16316 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT                                                            0xf
16317 #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK                                                              0x00000001L
16318 #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK                                                              0x00000002L
16319 #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK                                                            0x00000004L
16320 #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK                                                          0x00000008L
16321 #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK                                                             0x00000010L
16322 #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK                                                             0x00000020L
16323 #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK                                                           0x00000040L
16324 #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK                                                          0x00000080L
16325 #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK                                                               0x00000100L
16326 #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK                                                               0x00000200L
16327 #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK                                                               0x00000400L
16328 #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK                                                               0x00000800L
16329 #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK                                                                0x00001000L
16330 #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK                                                                 0x00002000L
16331 #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK                                                           0x00004000L
16332 #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK                                                              0x00008000L
16333 //SPI_INTERP_CONTROL_0
16334 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT                                                           0x0
16335 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT                                                           0x1
16336 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT                                                        0x2
16337 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT                                                        0x5
16338 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT                                                        0x8
16339 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT                                                        0xb
16340 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT                                                         0xe
16341 #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK                                                             0x00000001L
16342 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK                                                             0x00000002L
16343 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK                                                          0x0000001CL
16344 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK                                                          0x000000E0L
16345 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK                                                          0x00000700L
16346 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK                                                          0x00003800L
16347 #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK                                                           0x00004000L
16348 //SPI_PS_IN_CONTROL
16349 #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT                                                                  0x0
16350 #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT                                                                   0x6
16351 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT                                                            0x7
16352 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT                                                             0x8
16353 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT                                                         0xe
16354 #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK                                                                    0x0000003FL
16355 #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK                                                                     0x00000040L
16356 #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK                                                              0x00000080L
16357 #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK                                                               0x00000100L
16358 #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK                                                           0x00004000L
16359 //SPI_BARYC_CNTL
16360 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT                                                              0x0
16361 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT                                                            0x4
16362 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT                                                             0x8
16363 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT                                                           0xc
16364 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT                                                             0x10
16365 #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT                                                                  0x14
16366 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT                                                            0x18
16367 #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK                                                                0x00000001L
16368 #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK                                                              0x00000010L
16369 #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK                                                               0x00000100L
16370 #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK                                                             0x00001000L
16371 #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK                                                               0x00030000L
16372 #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK                                                                    0x00100000L
16373 #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK                                                              0x01000000L
16374 //SPI_TMPRING_SIZE
16375 #define SPI_TMPRING_SIZE__WAVES__SHIFT                                                                        0x0
16376 #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT                                                                     0xc
16377 #define SPI_TMPRING_SIZE__WAVES_MASK                                                                          0x00000FFFL
16378 #define SPI_TMPRING_SIZE__WAVESIZE_MASK                                                                       0x01FFF000L
16379 //SPI_SHADER_POS_FORMAT
16380 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT                                                      0x0
16381 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT                                                      0x4
16382 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT                                                      0x8
16383 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT                                                      0xc
16384 #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK                                                        0x0000000FL
16385 #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK                                                        0x000000F0L
16386 #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK                                                        0x00000F00L
16387 #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK                                                        0x0000F000L
16388 //SPI_SHADER_Z_FORMAT
16389 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT                                                           0x0
16390 #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK                                                             0x0000000FL
16391 //SPI_SHADER_COL_FORMAT
16392 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT                                                      0x0
16393 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT                                                      0x4
16394 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT                                                      0x8
16395 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT                                                      0xc
16396 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT                                                      0x10
16397 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT                                                      0x14
16398 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT                                                      0x18
16399 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT                                                      0x1c
16400 #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK                                                        0x0000000FL
16401 #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK                                                        0x000000F0L
16402 #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK                                                        0x00000F00L
16403 #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK                                                        0x0000F000L
16404 #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK                                                        0x000F0000L
16405 #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK                                                        0x00F00000L
16406 #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK                                                        0x0F000000L
16407 #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK                                                        0xF0000000L
16408 //SX_PS_DOWNCONVERT
16409 #define SX_PS_DOWNCONVERT__MRT0__SHIFT                                                                        0x0
16410 #define SX_PS_DOWNCONVERT__MRT1__SHIFT                                                                        0x4
16411 #define SX_PS_DOWNCONVERT__MRT2__SHIFT                                                                        0x8
16412 #define SX_PS_DOWNCONVERT__MRT3__SHIFT                                                                        0xc
16413 #define SX_PS_DOWNCONVERT__MRT4__SHIFT                                                                        0x10
16414 #define SX_PS_DOWNCONVERT__MRT5__SHIFT                                                                        0x14
16415 #define SX_PS_DOWNCONVERT__MRT6__SHIFT                                                                        0x18
16416 #define SX_PS_DOWNCONVERT__MRT7__SHIFT                                                                        0x1c
16417 #define SX_PS_DOWNCONVERT__MRT0_MASK                                                                          0x0000000FL
16418 #define SX_PS_DOWNCONVERT__MRT1_MASK                                                                          0x000000F0L
16419 #define SX_PS_DOWNCONVERT__MRT2_MASK                                                                          0x00000F00L
16420 #define SX_PS_DOWNCONVERT__MRT3_MASK                                                                          0x0000F000L
16421 #define SX_PS_DOWNCONVERT__MRT4_MASK                                                                          0x000F0000L
16422 #define SX_PS_DOWNCONVERT__MRT5_MASK                                                                          0x00F00000L
16423 #define SX_PS_DOWNCONVERT__MRT6_MASK                                                                          0x0F000000L
16424 #define SX_PS_DOWNCONVERT__MRT7_MASK                                                                          0xF0000000L
16425 //SX_BLEND_OPT_EPSILON
16426 #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT                                                             0x0
16427 #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT                                                             0x4
16428 #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT                                                             0x8
16429 #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT                                                             0xc
16430 #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT                                                             0x10
16431 #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT                                                             0x14
16432 #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT                                                             0x18
16433 #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT                                                             0x1c
16434 #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK                                                               0x0000000FL
16435 #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK                                                               0x000000F0L
16436 #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK                                                               0x00000F00L
16437 #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK                                                               0x0000F000L
16438 #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK                                                               0x000F0000L
16439 #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK                                                               0x00F00000L
16440 #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK                                                               0x0F000000L
16441 #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK                                                               0xF0000000L
16442 //SX_BLEND_OPT_CONTROL
16443 #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT                                                   0x0
16444 #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT                                                   0x1
16445 #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT                                                   0x4
16446 #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT                                                   0x5
16447 #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT                                                   0x8
16448 #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT                                                   0x9
16449 #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT                                                   0xc
16450 #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT                                                   0xd
16451 #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT                                                   0x10
16452 #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT                                                   0x11
16453 #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT                                                   0x14
16454 #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT                                                   0x15
16455 #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT                                                   0x18
16456 #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT                                                   0x19
16457 #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT                                                   0x1c
16458 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT                                                   0x1d
16459 #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT                                                   0x1f
16460 #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK                                                     0x00000001L
16461 #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK                                                     0x00000002L
16462 #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK                                                     0x00000010L
16463 #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK                                                     0x00000020L
16464 #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK                                                     0x00000100L
16465 #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK                                                     0x00000200L
16466 #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK                                                     0x00001000L
16467 #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK                                                     0x00002000L
16468 #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK                                                     0x00010000L
16469 #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK                                                     0x00020000L
16470 #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK                                                     0x00100000L
16471 #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK                                                     0x00200000L
16472 #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK                                                     0x01000000L
16473 #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK                                                     0x02000000L
16474 #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK                                                     0x10000000L
16475 #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK                                                     0x20000000L
16476 #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK                                                     0x80000000L
16477 //SX_MRT0_BLEND_OPT
16478 #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16479 #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16480 #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16481 #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16482 #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16483 #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16484 #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16485 #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16486 #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16487 #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16488 #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16489 #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16490 //SX_MRT1_BLEND_OPT
16491 #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16492 #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16493 #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16494 #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16495 #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16496 #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16497 #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16498 #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16499 #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16500 #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16501 #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16502 #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16503 //SX_MRT2_BLEND_OPT
16504 #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16505 #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16506 #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16507 #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16508 #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16509 #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16510 #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16511 #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16512 #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16513 #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16514 #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16515 #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16516 //SX_MRT3_BLEND_OPT
16517 #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16518 #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16519 #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16520 #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16521 #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16522 #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16523 #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16524 #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16525 #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16526 #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16527 #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16528 #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16529 //SX_MRT4_BLEND_OPT
16530 #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16531 #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16532 #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16533 #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16534 #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16535 #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16536 #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16537 #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16538 #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16539 #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16540 #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16541 #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16542 //SX_MRT5_BLEND_OPT
16543 #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16544 #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16545 #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16546 #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16547 #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16548 #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16549 #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16550 #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16551 #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16552 #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16553 #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16554 #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16555 //SX_MRT6_BLEND_OPT
16556 #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16557 #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16558 #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16559 #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16560 #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16561 #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16562 #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16563 #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16564 #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16565 #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16566 #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16567 #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16568 //SX_MRT7_BLEND_OPT
16569 #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT                                                               0x0
16570 #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT                                                               0x4
16571 #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT                                                              0x8
16572 #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT                                                               0x10
16573 #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT                                                               0x14
16574 #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT                                                              0x18
16575 #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK                                                                 0x00000007L
16576 #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK                                                                 0x00000070L
16577 #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK                                                                0x00000700L
16578 #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK                                                                 0x00070000L
16579 #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK                                                                 0x00700000L
16580 #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK                                                                0x07000000L
16581 //CB_BLEND0_CONTROL
16582 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16583 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16584 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16585 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16586 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16587 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16588 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16589 #define CB_BLEND0_CONTROL__ENABLE__SHIFT                                                                      0x1e
16590 #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16591 #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16592 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16593 #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16594 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16595 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16596 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16597 #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16598 #define CB_BLEND0_CONTROL__ENABLE_MASK                                                                        0x40000000L
16599 #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16600 //CB_BLEND1_CONTROL
16601 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16602 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16603 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16604 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16605 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16606 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16607 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16608 #define CB_BLEND1_CONTROL__ENABLE__SHIFT                                                                      0x1e
16609 #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16610 #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16611 #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16612 #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16613 #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16614 #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16615 #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16616 #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16617 #define CB_BLEND1_CONTROL__ENABLE_MASK                                                                        0x40000000L
16618 #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16619 //CB_BLEND2_CONTROL
16620 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16621 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16622 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16623 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16624 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16625 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16626 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16627 #define CB_BLEND2_CONTROL__ENABLE__SHIFT                                                                      0x1e
16628 #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16629 #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16630 #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16631 #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16632 #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16633 #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16634 #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16635 #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16636 #define CB_BLEND2_CONTROL__ENABLE_MASK                                                                        0x40000000L
16637 #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16638 //CB_BLEND3_CONTROL
16639 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16640 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16641 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16642 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16643 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16644 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16645 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16646 #define CB_BLEND3_CONTROL__ENABLE__SHIFT                                                                      0x1e
16647 #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16648 #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16649 #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16650 #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16651 #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16652 #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16653 #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16654 #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16655 #define CB_BLEND3_CONTROL__ENABLE_MASK                                                                        0x40000000L
16656 #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16657 //CB_BLEND4_CONTROL
16658 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16659 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16660 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16661 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16662 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16663 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16664 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16665 #define CB_BLEND4_CONTROL__ENABLE__SHIFT                                                                      0x1e
16666 #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16667 #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16668 #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16669 #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16670 #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16671 #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16672 #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16673 #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16674 #define CB_BLEND4_CONTROL__ENABLE_MASK                                                                        0x40000000L
16675 #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16676 //CB_BLEND5_CONTROL
16677 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16678 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16679 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16680 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16681 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16682 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16683 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16684 #define CB_BLEND5_CONTROL__ENABLE__SHIFT                                                                      0x1e
16685 #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16686 #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16687 #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16688 #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16689 #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16690 #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16691 #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16692 #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16693 #define CB_BLEND5_CONTROL__ENABLE_MASK                                                                        0x40000000L
16694 #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16695 //CB_BLEND6_CONTROL
16696 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16697 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16698 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16699 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16700 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16701 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16702 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16703 #define CB_BLEND6_CONTROL__ENABLE__SHIFT                                                                      0x1e
16704 #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16705 #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16706 #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16707 #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16708 #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16709 #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16710 #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16711 #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16712 #define CB_BLEND6_CONTROL__ENABLE_MASK                                                                        0x40000000L
16713 #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16714 //CB_BLEND7_CONTROL
16715 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT                                                              0x0
16716 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT                                                              0x5
16717 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT                                                             0x8
16718 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT                                                              0x10
16719 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT                                                              0x15
16720 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT                                                             0x18
16721 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT                                                        0x1d
16722 #define CB_BLEND7_CONTROL__ENABLE__SHIFT                                                                      0x1e
16723 #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT                                                                0x1f
16724 #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK                                                                0x0000001FL
16725 #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK                                                                0x000000E0L
16726 #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK                                                               0x00001F00L
16727 #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK                                                                0x001F0000L
16728 #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK                                                                0x00E00000L
16729 #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK                                                               0x1F000000L
16730 #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK                                                          0x20000000L
16731 #define CB_BLEND7_CONTROL__ENABLE_MASK                                                                        0x40000000L
16732 #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK                                                                  0x80000000L
16733 //CB_MRT0_EPITCH
16734 #define CB_MRT0_EPITCH__EPITCH__SHIFT                                                                         0x0
16735 #define CB_MRT0_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16736 //CB_MRT1_EPITCH
16737 #define CB_MRT1_EPITCH__EPITCH__SHIFT                                                                         0x0
16738 #define CB_MRT1_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16739 //CB_MRT2_EPITCH
16740 #define CB_MRT2_EPITCH__EPITCH__SHIFT                                                                         0x0
16741 #define CB_MRT2_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16742 //CB_MRT3_EPITCH
16743 #define CB_MRT3_EPITCH__EPITCH__SHIFT                                                                         0x0
16744 #define CB_MRT3_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16745 //CB_MRT4_EPITCH
16746 #define CB_MRT4_EPITCH__EPITCH__SHIFT                                                                         0x0
16747 #define CB_MRT4_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16748 //CB_MRT5_EPITCH
16749 #define CB_MRT5_EPITCH__EPITCH__SHIFT                                                                         0x0
16750 #define CB_MRT5_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16751 //CB_MRT6_EPITCH
16752 #define CB_MRT6_EPITCH__EPITCH__SHIFT                                                                         0x0
16753 #define CB_MRT6_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16754 //CB_MRT7_EPITCH
16755 #define CB_MRT7_EPITCH__EPITCH__SHIFT                                                                         0x0
16756 #define CB_MRT7_EPITCH__EPITCH_MASK                                                                           0x0000FFFFL
16757 //CS_COPY_STATE
16758 #define CS_COPY_STATE__SRC_STATE_ID__SHIFT                                                                    0x0
16759 #define CS_COPY_STATE__SRC_STATE_ID_MASK                                                                      0x00000007L
16760 //GFX_COPY_STATE
16761 #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT                                                                   0x0
16762 #define GFX_COPY_STATE__SRC_STATE_ID_MASK                                                                     0x00000007L
16763 //PA_CL_POINT_X_RAD
16764 #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT                                                               0x0
16765 #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
16766 //PA_CL_POINT_Y_RAD
16767 #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT                                                               0x0
16768 #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK                                                                 0xFFFFFFFFL
16769 //PA_CL_POINT_SIZE
16770 #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT                                                                0x0
16771 #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK                                                                  0xFFFFFFFFL
16772 //PA_CL_POINT_CULL_RAD
16773 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT                                                            0x0
16774 #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK                                                              0xFFFFFFFFL
16775 //VGT_DMA_BASE_HI
16776 #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT                                                                     0x0
16777 #define VGT_DMA_BASE_HI__BASE_ADDR_MASK                                                                       0x0000FFFFL
16778 //VGT_DMA_BASE
16779 #define VGT_DMA_BASE__BASE_ADDR__SHIFT                                                                        0x0
16780 #define VGT_DMA_BASE__BASE_ADDR_MASK                                                                          0xFFFFFFFFL
16781 //VGT_DRAW_INITIATOR
16782 #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT                                                              0x0
16783 #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT                                                                 0x2
16784 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT                                                             0x4
16785 #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT                                                                    0x5
16786 #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT                                                                 0x6
16787 #define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT                                                              0x7
16788 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT                                                           0x8
16789 #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT                                                               0x1d
16790 #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK                                                                0x00000003L
16791 #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK                                                                   0x0000000CL
16792 #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK                                                               0x00000010L
16793 #define VGT_DRAW_INITIATOR__NOT_EOP_MASK                                                                      0x00000020L
16794 #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK                                                                   0x00000040L
16795 #define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK                                                                0x00000080L
16796 #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK                                                             0x00000100L
16797 #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK                                                                 0xE0000000L
16798 //VGT_IMMED_DATA
16799 #define VGT_IMMED_DATA__DATA__SHIFT                                                                           0x0
16800 #define VGT_IMMED_DATA__DATA_MASK                                                                             0xFFFFFFFFL
16801 //VGT_EVENT_ADDRESS_REG
16802 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT                                                             0x0
16803 #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK                                                               0x0FFFFFFFL
16804 //DB_DEPTH_CONTROL
16805 #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT                                                               0x0
16806 #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT                                                                     0x1
16807 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT                                                               0x2
16808 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT                                                          0x3
16809 #define DB_DEPTH_CONTROL__ZFUNC__SHIFT                                                                        0x4
16810 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT                                                              0x7
16811 #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT                                                                  0x8
16812 #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT                                                               0x14
16813 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT                                            0x1e
16814 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT                                           0x1f
16815 #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK                                                                 0x00000001L
16816 #define DB_DEPTH_CONTROL__Z_ENABLE_MASK                                                                       0x00000002L
16817 #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK                                                                 0x00000004L
16818 #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK                                                            0x00000008L
16819 #define DB_DEPTH_CONTROL__ZFUNC_MASK                                                                          0x00000070L
16820 #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK                                                                0x00000080L
16821 #define DB_DEPTH_CONTROL__STENCILFUNC_MASK                                                                    0x00000700L
16822 #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK                                                                 0x00700000L
16823 #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK                                              0x40000000L
16824 #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK                                             0x80000000L
16825 //DB_EQAA
16826 #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT                                                                    0x0
16827 #define DB_EQAA__PS_ITER_SAMPLES__SHIFT                                                                       0x4
16828 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT                                                               0x8
16829 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT                                                             0xc
16830 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT                                                            0x10
16831 #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT                                                                 0x11
16832 #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT                                                                    0x12
16833 #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT                                                                     0x13
16834 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT                                                            0x14
16835 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT                                                            0x15
16836 #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT                                                              0x18
16837 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT                                                        0x1b
16838 #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK                                                                      0x00000007L
16839 #define DB_EQAA__PS_ITER_SAMPLES_MASK                                                                         0x00000070L
16840 #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK                                                                 0x00000700L
16841 #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK                                                               0x00007000L
16842 #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK                                                              0x00010000L
16843 #define DB_EQAA__INCOHERENT_EQAA_READS_MASK                                                                   0x00020000L
16844 #define DB_EQAA__INTERPOLATE_COMP_Z_MASK                                                                      0x00040000L
16845 #define DB_EQAA__INTERPOLATE_SRC_Z_MASK                                                                       0x00080000L
16846 #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK                                                              0x00100000L
16847 #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK                                                              0x00200000L
16848 #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK                                                                0x07000000L
16849 #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK                                                          0x08000000L
16850 //CB_COLOR_CONTROL
16851 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT                                                            0x0
16852 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT                                                               0x3
16853 #define CB_COLOR_CONTROL__MODE__SHIFT                                                                         0x4
16854 #define CB_COLOR_CONTROL__ROP3__SHIFT                                                                         0x10
16855 #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK                                                              0x00000001L
16856 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK                                                                 0x00000008L
16857 #define CB_COLOR_CONTROL__MODE_MASK                                                                           0x00000070L
16858 #define CB_COLOR_CONTROL__ROP3_MASK                                                                           0x00FF0000L
16859 //DB_SHADER_CONTROL
16860 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT                                                             0x0
16861 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT                                              0x1
16862 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT                                                0x2
16863 #define DB_SHADER_CONTROL__Z_ORDER__SHIFT                                                                     0x4
16864 #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT                                                                 0x6
16865 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT                                                     0x7
16866 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT                                                          0x8
16867 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT                                                           0x9
16868 #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT                                                                0xa
16869 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT                                                       0xb
16870 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT                                                         0xc
16871 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT                                                       0xd
16872 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT                                                           0xf
16873 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT                                              0x10
16874 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT                                                          0x11
16875 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT                                                    0x14
16876 #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK                                                               0x00000001L
16877 #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK                                                0x00000002L
16878 #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK                                                  0x00000004L
16879 #define DB_SHADER_CONTROL__Z_ORDER_MASK                                                                       0x00000030L
16880 #define DB_SHADER_CONTROL__KILL_ENABLE_MASK                                                                   0x00000040L
16881 #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK                                                       0x00000080L
16882 #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK                                                            0x00000100L
16883 #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK                                                             0x00000200L
16884 #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK                                                                  0x00000400L
16885 #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK                                                         0x00000800L
16886 #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK                                                           0x00001000L
16887 #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK                                                         0x00006000L
16888 #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK                                                             0x00008000L
16889 #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK                                                0x00010000L
16890 #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK                                                            0x00020000L
16891 #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK                                                      0x00700000L
16892 //PA_CL_CLIP_CNTL
16893 #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT                                                                     0x0
16894 #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT                                                                     0x1
16895 #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT                                                                     0x2
16896 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT                                                                     0x3
16897 #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT                                                                     0x4
16898 #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT                                                                     0x5
16899 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT                                                            0xd
16900 #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT                                                                   0xe
16901 #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT                                                                  0x10
16902 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT                                                             0x11
16903 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT                                                        0x12
16904 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT                                                             0x13
16905 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT                                                           0x14
16906 #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT                                                                   0x15
16907 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT                                                         0x16
16908 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT                                                       0x18
16909 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT                                                     0x19
16910 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT                                                            0x1a
16911 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT                                                             0x1b
16912 #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK                                                                       0x00000001L
16913 #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK                                                                       0x00000002L
16914 #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK                                                                       0x00000004L
16915 #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK                                                                       0x00000008L
16916 #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK                                                                       0x00000010L
16917 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK                                                                       0x00000020L
16918 #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK                                                              0x00002000L
16919 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK                                                                     0x0000C000L
16920 #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK                                                                    0x00010000L
16921 #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK                                                               0x00020000L
16922 #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK                                                          0x00040000L
16923 #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK                                                               0x00080000L
16924 #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK                                                             0x00100000L
16925 #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK                                                                     0x00200000L
16926 #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK                                                           0x00400000L
16927 #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK                                                         0x01000000L
16928 #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK                                                       0x02000000L
16929 #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK                                                              0x04000000L
16930 #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK                                                               0x08000000L
16931 //PA_SU_SC_MODE_CNTL
16932 #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT                                                                 0x0
16933 #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT                                                                  0x1
16934 #define PA_SU_SC_MODE_CNTL__FACE__SHIFT                                                                       0x2
16935 #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT                                                                  0x3
16936 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT                                                       0x5
16937 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT                                                        0x8
16938 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT                                                   0xb
16939 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT                                                    0xc
16940 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT                                                    0xd
16941 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT                                                   0x10
16942 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT                                                         0x13
16943 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT                                                             0x14
16944 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT                                                          0x15
16945 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT                                      0x16
16946 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT                                                     0x17
16947 #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK                                                                   0x00000001L
16948 #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK                                                                    0x00000002L
16949 #define PA_SU_SC_MODE_CNTL__FACE_MASK                                                                         0x00000004L
16950 #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK                                                                    0x00000018L
16951 #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK                                                         0x000000E0L
16952 #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK                                                          0x00000700L
16953 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK                                                     0x00000800L
16954 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK                                                      0x00001000L
16955 #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK                                                      0x00002000L
16956 #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK                                                     0x00010000L
16957 #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK                                                           0x00080000L
16958 #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK                                                               0x00100000L
16959 #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK                                                            0x00200000L
16960 #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK                                        0x00400000L
16961 #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK                                                       0x00800000L
16962 //PA_CL_VTE_CNTL
16963 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT                                                              0x0
16964 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT                                                             0x1
16965 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT                                                              0x2
16966 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT                                                             0x3
16967 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT                                                              0x4
16968 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT                                                             0x5
16969 #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT                                                                     0x8
16970 #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT                                                                      0x9
16971 #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT                                                                     0xa
16972 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT                                                                0xb
16973 #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK                                                                0x00000001L
16974 #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK                                                               0x00000002L
16975 #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK                                                                0x00000004L
16976 #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK                                                               0x00000008L
16977 #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK                                                                0x00000010L
16978 #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK                                                               0x00000020L
16979 #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK                                                                       0x00000100L
16980 #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK                                                                        0x00000200L
16981 #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK                                                                       0x00000400L
16982 #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK                                                                  0x00000800L
16983 //PA_CL_VS_OUT_CNTL
16984 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT                                                             0x0
16985 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT                                                             0x1
16986 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT                                                             0x2
16987 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT                                                             0x3
16988 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT                                                             0x4
16989 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT                                                             0x5
16990 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT                                                             0x6
16991 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT                                                             0x7
16992 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT                                                             0x8
16993 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT                                                             0x9
16994 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT                                                             0xa
16995 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT                                                             0xb
16996 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT                                                             0xc
16997 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT                                                             0xd
16998 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT                                                             0xe
16999 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT                                                             0xf
17000 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT                                                          0x10
17001 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT                                                           0x11
17002 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT                                                  0x12
17003 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT                                                       0x13
17004 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT                                                           0x14
17005 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT                                                         0x15
17006 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT                                                      0x16
17007 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT                                                      0x17
17008 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT                                                    0x18
17009 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT                                                         0x19
17010 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT                                                          0x1a
17011 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT                                                      0x1b
17012 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK                                                               0x00000001L
17013 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK                                                               0x00000002L
17014 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK                                                               0x00000004L
17015 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK                                                               0x00000008L
17016 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK                                                               0x00000010L
17017 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK                                                               0x00000020L
17018 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK                                                               0x00000040L
17019 #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK                                                               0x00000080L
17020 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK                                                               0x00000100L
17021 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK                                                               0x00000200L
17022 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK                                                               0x00000400L
17023 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK                                                               0x00000800L
17024 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK                                                               0x00001000L
17025 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK                                                               0x00002000L
17026 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK                                                               0x00004000L
17027 #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK                                                               0x00008000L
17028 #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK                                                            0x00010000L
17029 #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK                                                             0x00020000L
17030 #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK                                                    0x00040000L
17031 #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK                                                         0x00080000L
17032 #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK                                                             0x00100000L
17033 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK                                                           0x00200000L
17034 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK                                                        0x00400000L
17035 #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK                                                        0x00800000L
17036 #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK                                                      0x01000000L
17037 #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK                                                           0x02000000L
17038 #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK                                                            0x04000000L
17039 #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK                                                        0x08000000L
17040 //PA_CL_NANINF_CNTL
17041 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT                                                          0x0
17042 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT                                                           0x1
17043 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT                                                           0x2
17044 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT                                                           0x3
17045 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT                                                           0x4
17046 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT                                                            0x5
17047 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT                                                            0x6
17048 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT                                                        0x7
17049 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT                                                            0x8
17050 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT                                                            0x9
17051 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT                                                             0xa
17052 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT                                                             0xb
17053 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT                                                             0xc
17054 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT                                                             0xd
17055 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT                                                    0xe
17056 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT                                                         0x14
17057 #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK                                                            0x00000001L
17058 #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK                                                             0x00000002L
17059 #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK                                                             0x00000004L
17060 #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK                                                             0x00000008L
17061 #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK                                                             0x00000010L
17062 #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK                                                              0x00000020L
17063 #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK                                                              0x00000040L
17064 #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK                                                          0x00000080L
17065 #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK                                                              0x00000100L
17066 #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK                                                              0x00000200L
17067 #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK                                                               0x00000400L
17068 #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK                                                               0x00000800L
17069 #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK                                                               0x00001000L
17070 #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK                                                               0x00002000L
17071 #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK                                                      0x00004000L
17072 #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK                                                           0x00100000L
17073 //PA_SU_LINE_STIPPLE_CNTL
17074 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT                                                    0x0
17075 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT                                                    0x2
17076 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT                                                      0x3
17077 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT                                                        0x4
17078 #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK                                                      0x00000003L
17079 #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK                                                      0x00000004L
17080 #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK                                                        0x00000008L
17081 #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK                                                          0x00000010L
17082 //PA_SU_LINE_STIPPLE_SCALE
17083 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT                                                   0x0
17084 #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK                                                     0xFFFFFFFFL
17085 //PA_SU_PRIM_FILTER_CNTL
17086 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                                0x0
17087 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                                    0x1
17088 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                                   0x2
17089 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                               0x3
17090 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT                                                    0x4
17091 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT                                                        0x5
17092 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT                                                       0x6
17093 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT                                                   0x7
17094 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT                                                   0x8
17095 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT                                                   0x1e
17096 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT                                                  0x1f
17097 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                                  0x00000001L
17098 #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                      0x00000002L
17099 #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                                     0x00000004L
17100 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                                 0x00000008L
17101 #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK                                                      0x00000010L
17102 #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK                                                          0x00000020L
17103 #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK                                                         0x00000040L
17104 #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK                                                     0x00000080L
17105 #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK                                                     0x0000FF00L
17106 #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK                                                     0x40000000L
17107 #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK                                                    0x80000000L
17108 //PA_SU_SMALL_PRIM_FILTER_CNTL
17109 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT                                         0x0
17110 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT                                          0x1
17111 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT                                              0x2
17112 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT                                             0x3
17113 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT                                         0x4
17114 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK                                           0x00000001L
17115 #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK                                            0x00000002L
17116 #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK                                                0x00000004L
17117 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK                                               0x00000008L
17118 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK                                           0x00000010L
17119 //PA_CL_OBJPRIM_ID_CNTL
17120 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT                                                              0x0
17121 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT                                                       0x1
17122 #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT                                                      0x2
17123 #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK                                                                0x00000001L
17124 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK                                                         0x00000002L
17125 #define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK                                                        0x00000004L
17126 //PA_CL_NGG_CNTL
17127 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT                                                               0x0
17128 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT                                                        0x1
17129 #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK                                                                 0x00000001L
17130 #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK                                                          0x00000002L
17131 //PA_SU_OVER_RASTERIZATION_CNTL
17132 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT                                        0x0
17133 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT                                            0x1
17134 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT                                           0x2
17135 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT                                       0x3
17136 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT                                                0x4
17137 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK                                          0x00000001L
17138 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK                                              0x00000002L
17139 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK                                             0x00000004L
17140 #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK                                         0x00000008L
17141 #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK                                                  0x00000010L
17142 //PA_SU_POINT_SIZE
17143 #define PA_SU_POINT_SIZE__HEIGHT__SHIFT                                                                       0x0
17144 #define PA_SU_POINT_SIZE__WIDTH__SHIFT                                                                        0x10
17145 #define PA_SU_POINT_SIZE__HEIGHT_MASK                                                                         0x0000FFFFL
17146 #define PA_SU_POINT_SIZE__WIDTH_MASK                                                                          0xFFFF0000L
17147 //PA_SU_POINT_MINMAX
17148 #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT                                                                   0x0
17149 #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT                                                                   0x10
17150 #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK                                                                     0x0000FFFFL
17151 #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK                                                                     0xFFFF0000L
17152 //PA_SU_LINE_CNTL
17153 #define PA_SU_LINE_CNTL__WIDTH__SHIFT                                                                         0x0
17154 #define PA_SU_LINE_CNTL__WIDTH_MASK                                                                           0x0000FFFFL
17155 //PA_SC_LINE_STIPPLE
17156 #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT                                                               0x0
17157 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT                                                               0x10
17158 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT                                                          0x1c
17159 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT                                                            0x1d
17160 #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK                                                                 0x0000FFFFL
17161 #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK                                                                 0x00FF0000L
17162 #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK                                                            0x10000000L
17163 #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK                                                              0x60000000L
17164 //VGT_OUTPUT_PATH_CNTL
17165 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT                                                              0x0
17166 #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK                                                                0x00000007L
17167 //VGT_HOS_CNTL
17168 #define VGT_HOS_CNTL__TESS_MODE__SHIFT                                                                        0x0
17169 #define VGT_HOS_CNTL__TESS_MODE_MASK                                                                          0x00000003L
17170 //VGT_HOS_MAX_TESS_LEVEL
17171 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT                                                               0x0
17172 #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK                                                                 0xFFFFFFFFL
17173 //VGT_HOS_MIN_TESS_LEVEL
17174 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT                                                               0x0
17175 #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK                                                                 0xFFFFFFFFL
17176 //VGT_HOS_REUSE_DEPTH
17177 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT                                                               0x0
17178 #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK                                                                 0x000000FFL
17179 //VGT_GROUP_PRIM_TYPE
17180 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT                                                                 0x0
17181 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT                                                              0xe
17182 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT                                                              0xf
17183 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT                                                                0x10
17184 #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK                                                                   0x0000001FL
17185 #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK                                                                0x00004000L
17186 #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK                                                                0x00008000L
17187 #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK                                                                  0x00070000L
17188 //VGT_GROUP_FIRST_DECR
17189 #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT                                                               0x0
17190 #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK                                                                 0x0000000FL
17191 //VGT_GROUP_DECR
17192 #define VGT_GROUP_DECR__DECR__SHIFT                                                                           0x0
17193 #define VGT_GROUP_DECR__DECR_MASK                                                                             0x0000000FL
17194 //VGT_GROUP_VECT_0_CNTL
17195 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT                                                               0x0
17196 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT                                                               0x1
17197 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT                                                               0x2
17198 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT                                                               0x3
17199 #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT                                                                  0x8
17200 #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT                                                                   0x10
17201 #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
17202 #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
17203 #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
17204 #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
17205 #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK                                                                    0x0000FF00L
17206 #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK                                                                     0x00FF0000L
17207 //VGT_GROUP_VECT_1_CNTL
17208 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT                                                               0x0
17209 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT                                                               0x1
17210 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT                                                               0x2
17211 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT                                                               0x3
17212 #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT                                                                  0x8
17213 #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT                                                                   0x10
17214 #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK                                                                 0x00000001L
17215 #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK                                                                 0x00000002L
17216 #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK                                                                 0x00000004L
17217 #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK                                                                 0x00000008L
17218 #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK                                                                    0x0000FF00L
17219 #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK                                                                     0x00FF0000L
17220 //VGT_GROUP_VECT_0_FMT_CNTL
17221 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT                                                              0x0
17222 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
17223 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
17224 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
17225 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
17226 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
17227 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT                                                              0x18
17228 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
17229 #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
17230 #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
17231 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
17232 #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
17233 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
17234 #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
17235 #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
17236 #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
17237 //VGT_GROUP_VECT_1_FMT_CNTL
17238 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT                                                              0x0
17239 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT                                                            0x4
17240 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT                                                              0x8
17241 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT                                                            0xc
17242 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT                                                              0x10
17243 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT                                                            0x14
17244 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT                                                              0x18
17245 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT                                                            0x1c
17246 #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK                                                                0x0000000FL
17247 #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK                                                              0x000000F0L
17248 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK                                                                0x00000F00L
17249 #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK                                                              0x0000F000L
17250 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK                                                                0x000F0000L
17251 #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK                                                              0x00F00000L
17252 #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK                                                                0x0F000000L
17253 #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK                                                              0xF0000000L
17254 //VGT_GS_MODE
17255 #define VGT_GS_MODE__MODE__SHIFT                                                                              0x0
17256 #define VGT_GS_MODE__RESERVED_0__SHIFT                                                                        0x3
17257 #define VGT_GS_MODE__CUT_MODE__SHIFT                                                                          0x4
17258 #define VGT_GS_MODE__RESERVED_1__SHIFT                                                                        0x6
17259 #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT                                                                      0xb
17260 #define VGT_GS_MODE__RESERVED_2__SHIFT                                                                        0xc
17261 #define VGT_GS_MODE__ES_PASSTHRU__SHIFT                                                                       0xd
17262 #define VGT_GS_MODE__RESERVED_3__SHIFT                                                                        0xe
17263 #define VGT_GS_MODE__RESERVED_4__SHIFT                                                                        0xf
17264 #define VGT_GS_MODE__RESERVED_5__SHIFT                                                                        0x10
17265 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT                                                                0x11
17266 #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT                                                                     0x12
17267 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT                                                                 0x13
17268 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT                                                                 0x14
17269 #define VGT_GS_MODE__ONCHIP__SHIFT                                                                            0x15
17270 #define VGT_GS_MODE__MODE_MASK                                                                                0x00000007L
17271 #define VGT_GS_MODE__RESERVED_0_MASK                                                                          0x00000008L
17272 #define VGT_GS_MODE__CUT_MODE_MASK                                                                            0x00000030L
17273 #define VGT_GS_MODE__RESERVED_1_MASK                                                                          0x000007C0L
17274 #define VGT_GS_MODE__GS_C_PACK_EN_MASK                                                                        0x00000800L
17275 #define VGT_GS_MODE__RESERVED_2_MASK                                                                          0x00001000L
17276 #define VGT_GS_MODE__ES_PASSTHRU_MASK                                                                         0x00002000L
17277 #define VGT_GS_MODE__RESERVED_3_MASK                                                                          0x00004000L
17278 #define VGT_GS_MODE__RESERVED_4_MASK                                                                          0x00008000L
17279 #define VGT_GS_MODE__RESERVED_5_MASK                                                                          0x00010000L
17280 #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK                                                                  0x00020000L
17281 #define VGT_GS_MODE__SUPPRESS_CUTS_MASK                                                                       0x00040000L
17282 #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK                                                                   0x00080000L
17283 #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK                                                                   0x00100000L
17284 #define VGT_GS_MODE__ONCHIP_MASK                                                                              0x00600000L
17285 //VGT_GS_ONCHIP_CNTL
17286 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT                                                        0x0
17287 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT                                                        0xb
17288 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT                                                    0x16
17289 #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK                                                          0x000007FFL
17290 #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK                                                          0x003FF800L
17291 #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK                                                      0xFFC00000L
17292 //PA_SC_MODE_CNTL_0
17293 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT                                                                 0x0
17294 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT                                                        0x1
17295 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT                                                         0x2
17296 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT                                                    0x3
17297 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT                                                        0x4
17298 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT                                                      0x5
17299 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT                                               0x6
17300 #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK                                                                   0x00000001L
17301 #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK                                                          0x00000002L
17302 #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK                                                           0x00000004L
17303 #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK                                                      0x00000008L
17304 #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK                                                          0x00000010L
17305 #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK                                                        0x00000020L
17306 #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK                                                 0x00000040L
17307 //PA_SC_MODE_CNTL_1
17308 #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT                                                                   0x0
17309 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT                                                              0x1
17310 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT                                                    0x2
17311 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT                                                           0x3
17312 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT                                                             0x4
17313 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT                                                 0x7
17314 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT                                                      0x8
17315 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT                                                          0x9
17316 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT                                                       0xa
17317 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT                                                             0xb
17318 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT                                                             0xc
17319 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT                                                             0xd
17320 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT                                                          0xe
17321 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT                                                   0xf
17322 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT                                                              0x10
17323 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT                                     0x11
17324 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT                                                  0x12
17325 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT                                                      0x13
17326 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT                                                             0x14
17327 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT                                               0x18
17328 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT                                                     0x19
17329 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT                                                        0x1a
17330 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT                                               0x1b
17331 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT                                                     0x1c
17332 #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK                                                                     0x00000001L
17333 #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK                                                                0x00000002L
17334 #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK                                                      0x00000004L
17335 #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK                                                             0x00000008L
17336 #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK                                                               0x00000070L
17337 #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK                                                   0x00000080L
17338 #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK                                                        0x00000100L
17339 #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK                                                            0x00000200L
17340 #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK                                                         0x00000400L
17341 #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK                                                               0x00000800L
17342 #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK                                                               0x00001000L
17343 #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK                                                               0x00002000L
17344 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK                                                            0x00004000L
17345 #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK                                                     0x00008000L
17346 #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK                                                                0x00010000L
17347 #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK                                       0x00020000L
17348 #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK                                                    0x00040000L
17349 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK                                                        0x00080000L
17350 #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK                                                               0x00F00000L
17351 #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK                                                 0x01000000L
17352 #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK                                                       0x02000000L
17353 #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK                                                          0x04000000L
17354 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK                                                 0x08000000L
17355 #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK                                                       0x70000000L
17356 //VGT_ENHANCE
17357 #define VGT_ENHANCE__MISC__SHIFT                                                                              0x0
17358 #define VGT_ENHANCE__MISC_MASK                                                                                0xFFFFFFFFL
17359 //VGT_GS_PER_ES
17360 #define VGT_GS_PER_ES__GS_PER_ES__SHIFT                                                                       0x0
17361 #define VGT_GS_PER_ES__GS_PER_ES_MASK                                                                         0x000007FFL
17362 //VGT_ES_PER_GS
17363 #define VGT_ES_PER_GS__ES_PER_GS__SHIFT                                                                       0x0
17364 #define VGT_ES_PER_GS__ES_PER_GS_MASK                                                                         0x000007FFL
17365 //VGT_GS_PER_VS
17366 #define VGT_GS_PER_VS__GS_PER_VS__SHIFT                                                                       0x0
17367 #define VGT_GS_PER_VS__GS_PER_VS_MASK                                                                         0x0000000FL
17368 //VGT_GSVS_RING_OFFSET_1
17369 #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT                                                                 0x0
17370 #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK                                                                   0x00007FFFL
17371 //VGT_GSVS_RING_OFFSET_2
17372 #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT                                                                 0x0
17373 #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK                                                                   0x00007FFFL
17374 //VGT_GSVS_RING_OFFSET_3
17375 #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT                                                                 0x0
17376 #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK                                                                   0x00007FFFL
17377 //VGT_GS_OUT_PRIM_TYPE
17378 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT                                                             0x0
17379 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT                                                           0x8
17380 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT                                                           0x10
17381 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT                                                           0x16
17382 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT                                                   0x1f
17383 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK                                                               0x0000003FL
17384 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK                                                             0x00003F00L
17385 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK                                                             0x003F0000L
17386 #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK                                                             0x0FC00000L
17387 #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK                                                     0x80000000L
17388 //IA_ENHANCE
17389 #define IA_ENHANCE__MISC__SHIFT                                                                               0x0
17390 #define IA_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
17391 //VGT_DMA_SIZE
17392 #define VGT_DMA_SIZE__NUM_INDICES__SHIFT                                                                      0x0
17393 #define VGT_DMA_SIZE__NUM_INDICES_MASK                                                                        0xFFFFFFFFL
17394 //VGT_DMA_MAX_SIZE
17395 #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT                                                                     0x0
17396 #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK                                                                       0xFFFFFFFFL
17397 //VGT_DMA_INDEX_TYPE
17398 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                 0x0
17399 #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT                                                                  0x2
17400 #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT                                                                   0x4
17401 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT                                                               0x6
17402 #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT                                                                 0x8
17403 #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT                                                                    0x9
17404 #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT                                                                   0xa
17405 #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK                                                                   0x00000003L
17406 #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK                                                                    0x0000000CL
17407 #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK                                                                     0x00000030L
17408 #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK                                                                 0x00000040L
17409 #define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK                                                                   0x00000100L
17410 #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK                                                                      0x00000200L
17411 #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK                                                                     0x00000400L
17412 //WD_ENHANCE
17413 #define WD_ENHANCE__MISC__SHIFT                                                                               0x0
17414 #define WD_ENHANCE__MISC_MASK                                                                                 0xFFFFFFFFL
17415 //VGT_PRIMITIVEID_EN
17416 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT                                                             0x0
17417 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT                                                       0x1
17418 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT                                                   0x2
17419 #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK                                                               0x00000001L
17420 #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK                                                         0x00000002L
17421 #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK                                                     0x00000004L
17422 //VGT_DMA_NUM_INSTANCES
17423 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                           0x0
17424 #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK                                                             0xFFFFFFFFL
17425 //VGT_PRIMITIVEID_RESET
17426 #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT                                                                   0x0
17427 #define VGT_PRIMITIVEID_RESET__VALUE_MASK                                                                     0xFFFFFFFFL
17428 //VGT_EVENT_INITIATOR
17429 #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                                0x0
17430 #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                                0xa
17431 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                            0x1b
17432 #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK                                                                  0x0000003FL
17433 #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK                                                                  0x07FFFC00L
17434 #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                              0x08000000L
17435 //VGT_GS_MAX_PRIMS_PER_SUBGROUP
17436 #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT                                          0x0
17437 #define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK                                            0x0000FFFFL
17438 //VGT_DRAW_PAYLOAD_CNTL
17439 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT                                                           0x0
17440 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT                                                         0x1
17441 #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT                                                      0x2
17442 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT                                                       0x3
17443 #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK                                                             0x00000001L
17444 #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK                                                           0x00000002L
17445 #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK                                                        0x00000004L
17446 #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK                                                         0x00000008L
17447 //VGT_INSTANCE_STEP_RATE_0
17448 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT                                                            0x0
17449 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK                                                              0xFFFFFFFFL
17450 //VGT_INSTANCE_STEP_RATE_1
17451 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT                                                            0x0
17452 #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK                                                              0xFFFFFFFFL
17453 //VGT_ESGS_RING_ITEMSIZE
17454 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
17455 #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
17456 //VGT_GSVS_RING_ITEMSIZE
17457 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT                                                               0x0
17458 #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK                                                                 0x00007FFFL
17459 //VGT_REUSE_OFF
17460 #define VGT_REUSE_OFF__REUSE_OFF__SHIFT                                                                       0x0
17461 #define VGT_REUSE_OFF__REUSE_OFF_MASK                                                                         0x00000001L
17462 //VGT_VTX_CNT_EN
17463 #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT                                                                     0x0
17464 #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK                                                                       0x00000001L
17465 //DB_HTILE_SURFACE
17466 #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT                                                                   0x1
17467 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT                                                       0x2
17468 #define DB_HTILE_SURFACE__PRELOAD__SHIFT                                                                      0x3
17469 #define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT                                                               0x4
17470 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT                                                              0xa
17471 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT                                                      0x10
17472 #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT                                                                 0x12
17473 #define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT                                                                   0x13
17474 #define DB_HTILE_SURFACE__FULL_CACHE_MASK                                                                     0x00000002L
17475 #define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK                                                         0x00000004L
17476 #define DB_HTILE_SURFACE__PRELOAD_MASK                                                                        0x00000008L
17477 #define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK                                                                 0x000003F0L
17478 #define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK                                                                0x0000FC00L
17479 #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK                                                        0x00010000L
17480 #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK                                                                   0x00040000L
17481 #define DB_HTILE_SURFACE__RB_ALIGNED_MASK                                                                     0x00080000L
17482 //DB_SRESULTS_COMPARE_STATE0
17483 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT                                                       0x0
17484 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT                                                      0x4
17485 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT                                                       0xc
17486 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT                                                            0x18
17487 #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK                                                         0x00000007L
17488 #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK                                                        0x00000FF0L
17489 #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK                                                         0x000FF000L
17490 #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK                                                              0x01000000L
17491 //DB_SRESULTS_COMPARE_STATE1
17492 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT                                                       0x0
17493 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT                                                      0x4
17494 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT                                                       0xc
17495 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT                                                            0x18
17496 #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK                                                         0x00000007L
17497 #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK                                                        0x00000FF0L
17498 #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK                                                         0x000FF000L
17499 #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK                                                              0x01000000L
17500 //DB_PRELOAD_CONTROL
17501 #define DB_PRELOAD_CONTROL__START_X__SHIFT                                                                    0x0
17502 #define DB_PRELOAD_CONTROL__START_Y__SHIFT                                                                    0x8
17503 #define DB_PRELOAD_CONTROL__MAX_X__SHIFT                                                                      0x10
17504 #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT                                                                      0x18
17505 #define DB_PRELOAD_CONTROL__START_X_MASK                                                                      0x000000FFL
17506 #define DB_PRELOAD_CONTROL__START_Y_MASK                                                                      0x0000FF00L
17507 #define DB_PRELOAD_CONTROL__MAX_X_MASK                                                                        0x00FF0000L
17508 #define DB_PRELOAD_CONTROL__MAX_Y_MASK                                                                        0xFF000000L
17509 //VGT_STRMOUT_BUFFER_SIZE_0
17510 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT                                                                0x0
17511 #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK                                                                  0xFFFFFFFFL
17512 //VGT_STRMOUT_VTX_STRIDE_0
17513 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT                                                               0x0
17514 #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK                                                                 0x000003FFL
17515 //VGT_STRMOUT_BUFFER_OFFSET_0
17516 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT                                                            0x0
17517 #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK                                                              0xFFFFFFFFL
17518 //VGT_STRMOUT_BUFFER_SIZE_1
17519 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT                                                                0x0
17520 #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK                                                                  0xFFFFFFFFL
17521 //VGT_STRMOUT_VTX_STRIDE_1
17522 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT                                                               0x0
17523 #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK                                                                 0x000003FFL
17524 //VGT_STRMOUT_BUFFER_OFFSET_1
17525 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT                                                            0x0
17526 #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK                                                              0xFFFFFFFFL
17527 //VGT_STRMOUT_BUFFER_SIZE_2
17528 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT                                                                0x0
17529 #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK                                                                  0xFFFFFFFFL
17530 //VGT_STRMOUT_VTX_STRIDE_2
17531 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT                                                               0x0
17532 #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK                                                                 0x000003FFL
17533 //VGT_STRMOUT_BUFFER_OFFSET_2
17534 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT                                                            0x0
17535 #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK                                                              0xFFFFFFFFL
17536 //VGT_STRMOUT_BUFFER_SIZE_3
17537 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT                                                                0x0
17538 #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK                                                                  0xFFFFFFFFL
17539 //VGT_STRMOUT_VTX_STRIDE_3
17540 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT                                                               0x0
17541 #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK                                                                 0x000003FFL
17542 //VGT_STRMOUT_BUFFER_OFFSET_3
17543 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT                                                            0x0
17544 #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK                                                              0xFFFFFFFFL
17545 //VGT_STRMOUT_DRAW_OPAQUE_OFFSET
17546 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT                                                         0x0
17547 #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
17548 //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
17549 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT                                               0x0
17550 #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK                                                 0xFFFFFFFFL
17551 //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
17552 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT                                           0x0
17553 #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK                                             0x000001FFL
17554 //VGT_GS_MAX_VERT_OUT
17555 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT                                                              0x0
17556 #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK                                                                0x000007FFL
17557 //VGT_TESS_DISTRIBUTION
17558 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT                                                           0x0
17559 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT                                                               0x8
17560 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT                                                              0x10
17561 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT                                                             0x18
17562 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT                                                              0x1d
17563 #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK                                                             0x000000FFL
17564 #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK                                                                 0x0000FF00L
17565 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK                                                                0x00FF0000L
17566 #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK                                                               0x1F000000L
17567 #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK                                                                0xE0000000L
17568 //VGT_SHADER_STAGES_EN
17569 #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT                                                                    0x0
17570 #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT                                                                    0x2
17571 #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT                                                                    0x3
17572 #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT                                                                    0x5
17573 #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT                                                                    0x6
17574 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT                                                         0x9
17575 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT                                                      0xa
17576 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT                                                      0xb
17577 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT                                                            0xc
17578 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT                                                               0xd
17579 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT                                                          0xe
17580 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT                                                      0xf
17581 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT                                                           0x13
17582 #define VGT_SHADER_STAGES_EN__LS_EN_MASK                                                                      0x00000003L
17583 #define VGT_SHADER_STAGES_EN__HS_EN_MASK                                                                      0x00000004L
17584 #define VGT_SHADER_STAGES_EN__ES_EN_MASK                                                                      0x00000018L
17585 #define VGT_SHADER_STAGES_EN__GS_EN_MASK                                                                      0x00000020L
17586 #define VGT_SHADER_STAGES_EN__VS_EN_MASK                                                                      0x000000C0L
17587 #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK                                                           0x00000200L
17588 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK                                                        0x00000400L
17589 #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK                                                        0x00000800L
17590 #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK                                                              0x00001000L
17591 #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK                                                                 0x00002000L
17592 #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK                                                            0x00004000L
17593 #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK                                                        0x00078000L
17594 #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK                                                             0x00080000L
17595 //VGT_LS_HS_CONFIG
17596 #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT                                                                  0x0
17597 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT                                                              0x8
17598 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT                                                             0xe
17599 #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK                                                                    0x000000FFL
17600 #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK                                                                0x00003F00L
17601 #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK                                                               0x000FC000L
17602 //VGT_GS_VERT_ITEMSIZE
17603 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT                                                                 0x0
17604 #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK                                                                   0x00007FFFL
17605 //VGT_GS_VERT_ITEMSIZE_1
17606 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT                                                               0x0
17607 #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK                                                                 0x00007FFFL
17608 //VGT_GS_VERT_ITEMSIZE_2
17609 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT                                                               0x0
17610 #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK                                                                 0x00007FFFL
17611 //VGT_GS_VERT_ITEMSIZE_3
17612 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT                                                               0x0
17613 #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK                                                                 0x00007FFFL
17614 //VGT_TF_PARAM
17615 #define VGT_TF_PARAM__TYPE__SHIFT                                                                             0x0
17616 #define VGT_TF_PARAM__PARTITIONING__SHIFT                                                                     0x2
17617 #define VGT_TF_PARAM__TOPOLOGY__SHIFT                                                                         0x5
17618 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT                                                              0x8
17619 #define VGT_TF_PARAM__DEPRECATED__SHIFT                                                                       0x9
17620 #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT                                                                   0xe
17621 #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT                                                                     0xf
17622 #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT                                                                0x11
17623 #define VGT_TF_PARAM__TYPE_MASK                                                                               0x00000003L
17624 #define VGT_TF_PARAM__PARTITIONING_MASK                                                                       0x0000001CL
17625 #define VGT_TF_PARAM__TOPOLOGY_MASK                                                                           0x000000E0L
17626 #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK                                                                0x00000100L
17627 #define VGT_TF_PARAM__DEPRECATED_MASK                                                                         0x00000200L
17628 #define VGT_TF_PARAM__DISABLE_DONUTS_MASK                                                                     0x00004000L
17629 #define VGT_TF_PARAM__RDREQ_POLICY_MASK                                                                       0x00008000L
17630 #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK                                                                  0x00060000L
17631 //DB_ALPHA_TO_MASK
17632 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT                                                         0x0
17633 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT                                                        0x8
17634 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT                                                        0xa
17635 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT                                                        0xc
17636 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT                                                        0xe
17637 #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT                                                                 0x10
17638 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK                                                           0x00000001L
17639 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK                                                          0x00000300L
17640 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK                                                          0x00000C00L
17641 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK                                                          0x00003000L
17642 #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK                                                          0x0000C000L
17643 #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK                                                                   0x00010000L
17644 //VGT_DISPATCH_DRAW_INDEX
17645 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT                                                           0x0
17646 #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK                                                             0xFFFFFFFFL
17647 //PA_SU_POLY_OFFSET_DB_FMT_CNTL
17648 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT                                     0x0
17649 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT                                     0x8
17650 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK                                       0x000000FFL
17651 #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK                                       0x00000100L
17652 //PA_SU_POLY_OFFSET_CLAMP
17653 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT                                                                 0x0
17654 #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK                                                                   0xFFFFFFFFL
17655 //PA_SU_POLY_OFFSET_FRONT_SCALE
17656 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT                                                           0x0
17657 #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK                                                             0xFFFFFFFFL
17658 //PA_SU_POLY_OFFSET_FRONT_OFFSET
17659 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT                                                         0x0
17660 #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK                                                           0xFFFFFFFFL
17661 //PA_SU_POLY_OFFSET_BACK_SCALE
17662 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT                                                            0x0
17663 #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK                                                              0xFFFFFFFFL
17664 //PA_SU_POLY_OFFSET_BACK_OFFSET
17665 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT                                                          0x0
17666 #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK                                                            0xFFFFFFFFL
17667 //VGT_GS_INSTANCE_CNT
17668 #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT                                                                    0x0
17669 #define VGT_GS_INSTANCE_CNT__CNT__SHIFT                                                                       0x2
17670 #define VGT_GS_INSTANCE_CNT__ENABLE_MASK                                                                      0x00000001L
17671 #define VGT_GS_INSTANCE_CNT__CNT_MASK                                                                         0x000001FCL
17672 //VGT_STRMOUT_CONFIG
17673 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT                                                             0x0
17674 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT                                                             0x1
17675 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT                                                             0x2
17676 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT                                                             0x3
17677 #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT                                                                0x4
17678 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT                                                        0x7
17679 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT                                                           0x8
17680 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT                                                       0x1f
17681 #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK                                                               0x00000001L
17682 #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK                                                               0x00000002L
17683 #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK                                                               0x00000004L
17684 #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK                                                               0x00000008L
17685 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK                                                                  0x00000070L
17686 #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK                                                          0x00000080L
17687 #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK                                                             0x00000F00L
17688 #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK                                                         0x80000000L
17689 //VGT_STRMOUT_BUFFER_CONFIG
17690 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT                                                  0x0
17691 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT                                                  0x4
17692 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT                                                  0x8
17693 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT                                                  0xc
17694 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK                                                    0x0000000FL
17695 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK                                                    0x000000F0L
17696 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK                                                    0x00000F00L
17697 #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK                                                    0x0000F000L
17698 //VGT_DMA_EVENT_INITIATOR
17699 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT                                                            0x0
17700 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT                                                            0xa
17701 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT                                                        0x1b
17702 #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK                                                              0x0000003FL
17703 #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK                                                              0x07FFFC00L
17704 #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK                                                          0x08000000L
17705 //PA_SC_CENTROID_PRIORITY_0
17706 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT                                                          0x0
17707 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT                                                          0x4
17708 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT                                                          0x8
17709 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT                                                          0xc
17710 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT                                                          0x10
17711 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT                                                          0x14
17712 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT                                                          0x18
17713 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT                                                          0x1c
17714 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK                                                            0x0000000FL
17715 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK                                                            0x000000F0L
17716 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK                                                            0x00000F00L
17717 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK                                                            0x0000F000L
17718 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK                                                            0x000F0000L
17719 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK                                                            0x00F00000L
17720 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK                                                            0x0F000000L
17721 #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK                                                            0xF0000000L
17722 //PA_SC_CENTROID_PRIORITY_1
17723 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT                                                          0x0
17724 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT                                                          0x4
17725 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT                                                         0x8
17726 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT                                                         0xc
17727 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT                                                         0x10
17728 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT                                                         0x14
17729 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT                                                         0x18
17730 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT                                                         0x1c
17731 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK                                                            0x0000000FL
17732 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK                                                            0x000000F0L
17733 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK                                                           0x00000F00L
17734 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK                                                           0x0000F000L
17735 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK                                                           0x000F0000L
17736 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK                                                           0x00F00000L
17737 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK                                                           0x0F000000L
17738 #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK                                                           0xF0000000L
17739 //PA_SC_LINE_CNTL
17740 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT                                                             0x9
17741 #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT                                                                    0xa
17742 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT                                                      0xb
17743 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT                                                         0xc
17744 #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK                                                               0x00000200L
17745 #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK                                                                      0x00000400L
17746 #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK                                                        0x00000800L
17747 #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK                                                           0x00001000L
17748 //PA_SC_AA_CONFIG
17749 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT                                                              0x0
17750 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT                                                         0x4
17751 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT                                                               0xd
17752 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT                                                          0x14
17753 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT                                                        0x18
17754 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT                                                     0x1a
17755 #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK                                                                0x00000007L
17756 #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK                                                           0x00000010L
17757 #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK                                                                 0x0001E000L
17758 #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK                                                            0x00700000L
17759 #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK                                                          0x03000000L
17760 #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK                                                       0x0C000000L
17761 //PA_SU_VTX_CNTL
17762 #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT                                                                     0x0
17763 #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT                                                                     0x1
17764 #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT                                                                     0x3
17765 #define PA_SU_VTX_CNTL__PIX_CENTER_MASK                                                                       0x00000001L
17766 #define PA_SU_VTX_CNTL__ROUND_MODE_MASK                                                                       0x00000006L
17767 #define PA_SU_VTX_CNTL__QUANT_MODE_MASK                                                                       0x00000038L
17768 //PA_CL_GB_VERT_CLIP_ADJ
17769 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17770 #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17771 //PA_CL_GB_VERT_DISC_ADJ
17772 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17773 #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17774 //PA_CL_GB_HORZ_CLIP_ADJ
17775 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17776 #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17777 //PA_CL_GB_HORZ_DISC_ADJ
17778 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT                                                          0x0
17779 #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK                                                            0xFFFFFFFFL
17780 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
17781 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT                                                        0x0
17782 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT                                                        0x4
17783 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT                                                        0x8
17784 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT                                                        0xc
17785 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT                                                        0x10
17786 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT                                                        0x14
17787 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT                                                        0x18
17788 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT                                                        0x1c
17789 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK                                                          0x0000000FL
17790 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK                                                          0x000000F0L
17791 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK                                                          0x00000F00L
17792 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK                                                          0x0000F000L
17793 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK                                                          0x000F0000L
17794 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK                                                          0x00F00000L
17795 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK                                                          0x0F000000L
17796 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK                                                          0xF0000000L
17797 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
17798 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT                                                        0x0
17799 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT                                                        0x4
17800 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT                                                        0x8
17801 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT                                                        0xc
17802 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT                                                        0x10
17803 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT                                                        0x14
17804 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT                                                        0x18
17805 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT                                                        0x1c
17806 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK                                                          0x0000000FL
17807 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK                                                          0x000000F0L
17808 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK                                                          0x00000F00L
17809 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK                                                          0x0000F000L
17810 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK                                                          0x000F0000L
17811 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK                                                          0x00F00000L
17812 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK                                                          0x0F000000L
17813 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK                                                          0xF0000000L
17814 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
17815 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT                                                        0x0
17816 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT                                                        0x4
17817 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT                                                        0x8
17818 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT                                                        0xc
17819 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT                                                       0x10
17820 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT                                                       0x14
17821 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT                                                       0x18
17822 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT                                                       0x1c
17823 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK                                                          0x0000000FL
17824 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK                                                          0x000000F0L
17825 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK                                                          0x00000F00L
17826 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK                                                          0x0000F000L
17827 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK                                                         0x000F0000L
17828 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK                                                         0x00F00000L
17829 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK                                                         0x0F000000L
17830 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK                                                         0xF0000000L
17831 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
17832 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT                                                       0x0
17833 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT                                                       0x4
17834 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT                                                       0x8
17835 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT                                                       0xc
17836 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT                                                       0x10
17837 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT                                                       0x14
17838 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT                                                       0x18
17839 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT                                                       0x1c
17840 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK                                                         0x0000000FL
17841 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK                                                         0x000000F0L
17842 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK                                                         0x00000F00L
17843 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK                                                         0x0000F000L
17844 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK                                                         0x000F0000L
17845 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK                                                         0x00F00000L
17846 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK                                                         0x0F000000L
17847 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK                                                         0xF0000000L
17848 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
17849 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT                                                        0x0
17850 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT                                                        0x4
17851 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT                                                        0x8
17852 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT                                                        0xc
17853 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT                                                        0x10
17854 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT                                                        0x14
17855 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT                                                        0x18
17856 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT                                                        0x1c
17857 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK                                                          0x0000000FL
17858 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK                                                          0x000000F0L
17859 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK                                                          0x00000F00L
17860 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK                                                          0x0000F000L
17861 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK                                                          0x000F0000L
17862 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK                                                          0x00F00000L
17863 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK                                                          0x0F000000L
17864 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK                                                          0xF0000000L
17865 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
17866 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT                                                        0x0
17867 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT                                                        0x4
17868 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT                                                        0x8
17869 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT                                                        0xc
17870 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT                                                        0x10
17871 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT                                                        0x14
17872 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT                                                        0x18
17873 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT                                                        0x1c
17874 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK                                                          0x0000000FL
17875 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK                                                          0x000000F0L
17876 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK                                                          0x00000F00L
17877 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK                                                          0x0000F000L
17878 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK                                                          0x000F0000L
17879 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK                                                          0x00F00000L
17880 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK                                                          0x0F000000L
17881 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK                                                          0xF0000000L
17882 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
17883 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT                                                        0x0
17884 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT                                                        0x4
17885 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT                                                        0x8
17886 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT                                                        0xc
17887 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT                                                       0x10
17888 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT                                                       0x14
17889 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT                                                       0x18
17890 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT                                                       0x1c
17891 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK                                                          0x0000000FL
17892 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK                                                          0x000000F0L
17893 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK                                                          0x00000F00L
17894 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK                                                          0x0000F000L
17895 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK                                                         0x000F0000L
17896 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK                                                         0x00F00000L
17897 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK                                                         0x0F000000L
17898 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK                                                         0xF0000000L
17899 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
17900 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT                                                       0x0
17901 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT                                                       0x4
17902 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT                                                       0x8
17903 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT                                                       0xc
17904 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT                                                       0x10
17905 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT                                                       0x14
17906 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT                                                       0x18
17907 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT                                                       0x1c
17908 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK                                                         0x0000000FL
17909 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK                                                         0x000000F0L
17910 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK                                                         0x00000F00L
17911 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK                                                         0x0000F000L
17912 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK                                                         0x000F0000L
17913 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK                                                         0x00F00000L
17914 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK                                                         0x0F000000L
17915 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK                                                         0xF0000000L
17916 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
17917 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT                                                        0x0
17918 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT                                                        0x4
17919 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT                                                        0x8
17920 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT                                                        0xc
17921 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT                                                        0x10
17922 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT                                                        0x14
17923 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT                                                        0x18
17924 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT                                                        0x1c
17925 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK                                                          0x0000000FL
17926 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK                                                          0x000000F0L
17927 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK                                                          0x00000F00L
17928 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK                                                          0x0000F000L
17929 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK                                                          0x000F0000L
17930 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK                                                          0x00F00000L
17931 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK                                                          0x0F000000L
17932 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK                                                          0xF0000000L
17933 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
17934 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT                                                        0x0
17935 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT                                                        0x4
17936 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT                                                        0x8
17937 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT                                                        0xc
17938 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT                                                        0x10
17939 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT                                                        0x14
17940 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT                                                        0x18
17941 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT                                                        0x1c
17942 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK                                                          0x0000000FL
17943 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK                                                          0x000000F0L
17944 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK                                                          0x00000F00L
17945 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK                                                          0x0000F000L
17946 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK                                                          0x000F0000L
17947 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK                                                          0x00F00000L
17948 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK                                                          0x0F000000L
17949 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK                                                          0xF0000000L
17950 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
17951 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT                                                        0x0
17952 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT                                                        0x4
17953 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT                                                        0x8
17954 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT                                                        0xc
17955 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT                                                       0x10
17956 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT                                                       0x14
17957 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT                                                       0x18
17958 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT                                                       0x1c
17959 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK                                                          0x0000000FL
17960 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK                                                          0x000000F0L
17961 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK                                                          0x00000F00L
17962 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK                                                          0x0000F000L
17963 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK                                                         0x000F0000L
17964 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK                                                         0x00F00000L
17965 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK                                                         0x0F000000L
17966 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK                                                         0xF0000000L
17967 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
17968 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT                                                       0x0
17969 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT                                                       0x4
17970 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT                                                       0x8
17971 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT                                                       0xc
17972 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT                                                       0x10
17973 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT                                                       0x14
17974 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT                                                       0x18
17975 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT                                                       0x1c
17976 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK                                                         0x0000000FL
17977 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK                                                         0x000000F0L
17978 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK                                                         0x00000F00L
17979 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK                                                         0x0000F000L
17980 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK                                                         0x000F0000L
17981 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK                                                         0x00F00000L
17982 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK                                                         0x0F000000L
17983 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK                                                         0xF0000000L
17984 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
17985 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT                                                        0x0
17986 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT                                                        0x4
17987 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT                                                        0x8
17988 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT                                                        0xc
17989 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT                                                        0x10
17990 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT                                                        0x14
17991 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT                                                        0x18
17992 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT                                                        0x1c
17993 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK                                                          0x0000000FL
17994 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK                                                          0x000000F0L
17995 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK                                                          0x00000F00L
17996 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK                                                          0x0000F000L
17997 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK                                                          0x000F0000L
17998 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK                                                          0x00F00000L
17999 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK                                                          0x0F000000L
18000 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK                                                          0xF0000000L
18001 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
18002 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT                                                        0x0
18003 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT                                                        0x4
18004 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT                                                        0x8
18005 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT                                                        0xc
18006 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT                                                        0x10
18007 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT                                                        0x14
18008 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT                                                        0x18
18009 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT                                                        0x1c
18010 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK                                                          0x0000000FL
18011 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK                                                          0x000000F0L
18012 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK                                                          0x00000F00L
18013 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK                                                          0x0000F000L
18014 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK                                                          0x000F0000L
18015 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK                                                          0x00F00000L
18016 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK                                                          0x0F000000L
18017 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK                                                          0xF0000000L
18018 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
18019 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT                                                        0x0
18020 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT                                                        0x4
18021 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT                                                        0x8
18022 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT                                                        0xc
18023 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT                                                       0x10
18024 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT                                                       0x14
18025 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT                                                       0x18
18026 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT                                                       0x1c
18027 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK                                                          0x0000000FL
18028 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK                                                          0x000000F0L
18029 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK                                                          0x00000F00L
18030 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK                                                          0x0000F000L
18031 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK                                                         0x000F0000L
18032 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK                                                         0x00F00000L
18033 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK                                                         0x0F000000L
18034 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK                                                         0xF0000000L
18035 //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
18036 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT                                                       0x0
18037 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT                                                       0x4
18038 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT                                                       0x8
18039 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT                                                       0xc
18040 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT                                                       0x10
18041 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT                                                       0x14
18042 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT                                                       0x18
18043 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT                                                       0x1c
18044 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK                                                         0x0000000FL
18045 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK                                                         0x000000F0L
18046 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK                                                         0x00000F00L
18047 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK                                                         0x0000F000L
18048 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK                                                         0x000F0000L
18049 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK                                                         0x00F00000L
18050 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK                                                         0x0F000000L
18051 #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK                                                         0xF0000000L
18052 //PA_SC_AA_MASK_X0Y0_X1Y0
18053 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT                                                          0x0
18054 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT                                                          0x10
18055 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK                                                            0x0000FFFFL
18056 #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK                                                            0xFFFF0000L
18057 //PA_SC_AA_MASK_X0Y1_X1Y1
18058 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT                                                          0x0
18059 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT                                                          0x10
18060 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK                                                            0x0000FFFFL
18061 #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK                                                            0xFFFF0000L
18062 //PA_SC_SHADER_CONTROL
18063 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT                                             0x0
18064 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT                                                    0x2
18065 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT                                                 0x3
18066 #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK                                               0x00000003L
18067 #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK                                                      0x00000004L
18068 #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK                                                   0x00000008L
18069 //PA_SC_BINNER_CNTL_0
18070 #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT                                                              0x0
18071 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT                                                                0x2
18072 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT                                                                0x3
18073 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT                                                         0x4
18074 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT                                                         0x7
18075 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT                                                    0xa
18076 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT                                                 0xd
18077 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT                                                     0x12
18078 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT                                                           0x13
18079 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT                                                     0x1b
18080 #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK                                                                0x00000003L
18081 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK                                                                  0x00000004L
18082 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK                                                                  0x00000008L
18083 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK                                                           0x00000070L
18084 #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK                                                           0x00000380L
18085 #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK                                                      0x00001C00L
18086 #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK                                                   0x0003E000L
18087 #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK                                                       0x00040000L
18088 #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK                                                             0x07F80000L
18089 #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK                                                       0x08000000L
18090 //PA_SC_BINNER_CNTL_1
18091 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT                                                           0x0
18092 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT                                                        0x10
18093 #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK                                                             0x0000FFFFL
18094 #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK                                                          0xFFFF0000L
18095 //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
18096 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT                                        0x0
18097 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT                                 0x1
18098 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT                                       0x5
18099 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT                                0x6
18100 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT                           0xa
18101 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT                                          0xb
18102 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT                                          0xc
18103 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT                      0xd
18104 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT                     0xe
18105 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT             0xf
18106 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT                                 0x10
18107 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x12
18108 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT                     0x13
18109 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT                               0x14
18110 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT                                 0x15
18111 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT                                     0x16
18112 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT                                    0x17
18113 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT                                0x18
18114 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK                                          0x00000001L
18115 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK                                   0x0000001EL
18116 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK                                         0x00000020L
18117 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK                                  0x000003C0L
18118 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK                             0x00000400L
18119 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK                                            0x00000800L
18120 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK                                            0x00001000L
18121 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK                        0x00002000L
18122 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK                       0x00004000L
18123 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK               0x00008000L
18124 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK                                   0x00030000L
18125 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00040000L
18126 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK                       0x00080000L
18127 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK                                 0x00100000L
18128 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK                                   0x00200000L
18129 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK                                       0x00400000L
18130 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK                                      0x00800000L
18131 #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK                                  0x01000000L
18132 //PA_SC_NGG_MODE_CNTL
18133 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT                                                      0x0
18134 #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK                                                        0x000007FFL
18135 //VGT_VERTEX_REUSE_BLOCK_CNTL
18136 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT                                                   0x0
18137 #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK                                                     0x000000FFL
18138 //VGT_OUT_DEALLOC_CNTL
18139 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT                                                             0x0
18140 #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK                                                               0x0000007FL
18141 //CB_COLOR0_BASE
18142 #define CB_COLOR0_BASE__BASE_256B__SHIFT                                                                      0x0
18143 #define CB_COLOR0_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18144 //CB_COLOR0_BASE_EXT
18145 #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18146 #define CB_COLOR0_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18147 //CB_COLOR0_ATTRIB2
18148 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18149 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18150 #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18151 #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18152 #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18153 #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18154 //CB_COLOR0_VIEW
18155 #define CB_COLOR0_VIEW__SLICE_START__SHIFT                                                                    0x0
18156 #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18157 #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18158 #define CB_COLOR0_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18159 #define CB_COLOR0_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18160 #define CB_COLOR0_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18161 //CB_COLOR0_INFO
18162 #define CB_COLOR0_INFO__ENDIAN__SHIFT                                                                         0x0
18163 #define CB_COLOR0_INFO__FORMAT__SHIFT                                                                         0x2
18164 #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18165 #define CB_COLOR0_INFO__COMP_SWAP__SHIFT                                                                      0xb
18166 #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18167 #define CB_COLOR0_INFO__COMPRESSION__SHIFT                                                                    0xe
18168 #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18169 #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18170 #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18171 #define CB_COLOR0_INFO__ROUND_MODE__SHIFT                                                                     0x12
18172 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18173 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18174 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18175 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18176 #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18177 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18178 #define CB_COLOR0_INFO__ENDIAN_MASK                                                                           0x00000003L
18179 #define CB_COLOR0_INFO__FORMAT_MASK                                                                           0x0000007CL
18180 #define CB_COLOR0_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18181 #define CB_COLOR0_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18182 #define CB_COLOR0_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18183 #define CB_COLOR0_INFO__COMPRESSION_MASK                                                                      0x00004000L
18184 #define CB_COLOR0_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18185 #define CB_COLOR0_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18186 #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18187 #define CB_COLOR0_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18188 #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18189 #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18190 #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18191 #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18192 #define CB_COLOR0_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18193 #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18194 //CB_COLOR0_ATTRIB
18195 #define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18196 #define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18197 #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18198 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18199 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18200 #define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18201 #define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18202 #define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18203 #define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18204 #define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18205 #define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18206 #define CB_COLOR0_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18207 #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18208 #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18209 #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18210 #define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18211 #define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18212 #define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18213 #define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18214 #define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18215 //CB_COLOR0_DCC_CONTROL
18216 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18217 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18218 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18219 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18220 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18221 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18222 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18223 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18224 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18225 #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18226 #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18227 #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18228 #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18229 #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18230 #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18231 #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18232 #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18233 #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18234 //CB_COLOR0_CMASK
18235 #define CB_COLOR0_CMASK__BASE_256B__SHIFT                                                                     0x0
18236 #define CB_COLOR0_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18237 //CB_COLOR0_CMASK_BASE_EXT
18238 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18239 #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18240 //CB_COLOR0_FMASK
18241 #define CB_COLOR0_FMASK__BASE_256B__SHIFT                                                                     0x0
18242 #define CB_COLOR0_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18243 //CB_COLOR0_FMASK_BASE_EXT
18244 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18245 #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18246 //CB_COLOR0_CLEAR_WORD0
18247 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18248 #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18249 //CB_COLOR0_CLEAR_WORD1
18250 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18251 #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18252 //CB_COLOR0_DCC_BASE
18253 #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18254 #define CB_COLOR0_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18255 //CB_COLOR0_DCC_BASE_EXT
18256 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18257 #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18258 //CB_COLOR1_BASE
18259 #define CB_COLOR1_BASE__BASE_256B__SHIFT                                                                      0x0
18260 #define CB_COLOR1_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18261 //CB_COLOR1_BASE_EXT
18262 #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18263 #define CB_COLOR1_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18264 //CB_COLOR1_ATTRIB2
18265 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18266 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18267 #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18268 #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18269 #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18270 #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18271 //CB_COLOR1_VIEW
18272 #define CB_COLOR1_VIEW__SLICE_START__SHIFT                                                                    0x0
18273 #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18274 #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18275 #define CB_COLOR1_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18276 #define CB_COLOR1_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18277 #define CB_COLOR1_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18278 //CB_COLOR1_INFO
18279 #define CB_COLOR1_INFO__ENDIAN__SHIFT                                                                         0x0
18280 #define CB_COLOR1_INFO__FORMAT__SHIFT                                                                         0x2
18281 #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18282 #define CB_COLOR1_INFO__COMP_SWAP__SHIFT                                                                      0xb
18283 #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18284 #define CB_COLOR1_INFO__COMPRESSION__SHIFT                                                                    0xe
18285 #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18286 #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18287 #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18288 #define CB_COLOR1_INFO__ROUND_MODE__SHIFT                                                                     0x12
18289 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18290 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18291 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18292 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18293 #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18294 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18295 #define CB_COLOR1_INFO__ENDIAN_MASK                                                                           0x00000003L
18296 #define CB_COLOR1_INFO__FORMAT_MASK                                                                           0x0000007CL
18297 #define CB_COLOR1_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18298 #define CB_COLOR1_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18299 #define CB_COLOR1_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18300 #define CB_COLOR1_INFO__COMPRESSION_MASK                                                                      0x00004000L
18301 #define CB_COLOR1_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18302 #define CB_COLOR1_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18303 #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18304 #define CB_COLOR1_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18305 #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18306 #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18307 #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18308 #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18309 #define CB_COLOR1_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18310 #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18311 //CB_COLOR1_ATTRIB
18312 #define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18313 #define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18314 #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18315 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18316 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18317 #define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18318 #define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18319 #define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18320 #define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18321 #define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18322 #define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18323 #define CB_COLOR1_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18324 #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18325 #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18326 #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18327 #define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18328 #define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18329 #define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18330 #define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18331 #define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18332 //CB_COLOR1_DCC_CONTROL
18333 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18334 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18335 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18336 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18337 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18338 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18339 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18340 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18341 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18342 #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18343 #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18344 #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18345 #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18346 #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18347 #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18348 #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18349 #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18350 #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18351 //CB_COLOR1_CMASK
18352 #define CB_COLOR1_CMASK__BASE_256B__SHIFT                                                                     0x0
18353 #define CB_COLOR1_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18354 //CB_COLOR1_CMASK_BASE_EXT
18355 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18356 #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18357 //CB_COLOR1_FMASK
18358 #define CB_COLOR1_FMASK__BASE_256B__SHIFT                                                                     0x0
18359 #define CB_COLOR1_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18360 //CB_COLOR1_FMASK_BASE_EXT
18361 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18362 #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18363 //CB_COLOR1_CLEAR_WORD0
18364 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18365 #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18366 //CB_COLOR1_CLEAR_WORD1
18367 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18368 #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18369 //CB_COLOR1_DCC_BASE
18370 #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18371 #define CB_COLOR1_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18372 //CB_COLOR1_DCC_BASE_EXT
18373 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18374 #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18375 //CB_COLOR2_BASE
18376 #define CB_COLOR2_BASE__BASE_256B__SHIFT                                                                      0x0
18377 #define CB_COLOR2_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18378 //CB_COLOR2_BASE_EXT
18379 #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18380 #define CB_COLOR2_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18381 //CB_COLOR2_ATTRIB2
18382 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18383 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18384 #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18385 #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18386 #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18387 #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18388 //CB_COLOR2_VIEW
18389 #define CB_COLOR2_VIEW__SLICE_START__SHIFT                                                                    0x0
18390 #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18391 #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18392 #define CB_COLOR2_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18393 #define CB_COLOR2_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18394 #define CB_COLOR2_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18395 //CB_COLOR2_INFO
18396 #define CB_COLOR2_INFO__ENDIAN__SHIFT                                                                         0x0
18397 #define CB_COLOR2_INFO__FORMAT__SHIFT                                                                         0x2
18398 #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18399 #define CB_COLOR2_INFO__COMP_SWAP__SHIFT                                                                      0xb
18400 #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18401 #define CB_COLOR2_INFO__COMPRESSION__SHIFT                                                                    0xe
18402 #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18403 #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18404 #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18405 #define CB_COLOR2_INFO__ROUND_MODE__SHIFT                                                                     0x12
18406 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18407 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18408 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18409 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18410 #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18411 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18412 #define CB_COLOR2_INFO__ENDIAN_MASK                                                                           0x00000003L
18413 #define CB_COLOR2_INFO__FORMAT_MASK                                                                           0x0000007CL
18414 #define CB_COLOR2_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18415 #define CB_COLOR2_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18416 #define CB_COLOR2_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18417 #define CB_COLOR2_INFO__COMPRESSION_MASK                                                                      0x00004000L
18418 #define CB_COLOR2_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18419 #define CB_COLOR2_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18420 #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18421 #define CB_COLOR2_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18422 #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18423 #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18424 #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18425 #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18426 #define CB_COLOR2_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18427 #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18428 //CB_COLOR2_ATTRIB
18429 #define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18430 #define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18431 #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18432 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18433 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18434 #define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18435 #define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18436 #define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18437 #define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18438 #define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18439 #define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18440 #define CB_COLOR2_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18441 #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18442 #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18443 #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18444 #define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18445 #define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18446 #define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18447 #define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18448 #define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18449 //CB_COLOR2_DCC_CONTROL
18450 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18451 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18452 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18453 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18454 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18455 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18456 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18457 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18458 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18459 #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18460 #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18461 #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18462 #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18463 #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18464 #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18465 #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18466 #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18467 #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18468 //CB_COLOR2_CMASK
18469 #define CB_COLOR2_CMASK__BASE_256B__SHIFT                                                                     0x0
18470 #define CB_COLOR2_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18471 //CB_COLOR2_CMASK_BASE_EXT
18472 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18473 #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18474 //CB_COLOR2_FMASK
18475 #define CB_COLOR2_FMASK__BASE_256B__SHIFT                                                                     0x0
18476 #define CB_COLOR2_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18477 //CB_COLOR2_FMASK_BASE_EXT
18478 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18479 #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18480 //CB_COLOR2_CLEAR_WORD0
18481 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18482 #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18483 //CB_COLOR2_CLEAR_WORD1
18484 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18485 #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18486 //CB_COLOR2_DCC_BASE
18487 #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18488 #define CB_COLOR2_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18489 //CB_COLOR2_DCC_BASE_EXT
18490 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18491 #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18492 //CB_COLOR3_BASE
18493 #define CB_COLOR3_BASE__BASE_256B__SHIFT                                                                      0x0
18494 #define CB_COLOR3_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18495 //CB_COLOR3_BASE_EXT
18496 #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18497 #define CB_COLOR3_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18498 //CB_COLOR3_ATTRIB2
18499 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18500 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18501 #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18502 #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18503 #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18504 #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18505 //CB_COLOR3_VIEW
18506 #define CB_COLOR3_VIEW__SLICE_START__SHIFT                                                                    0x0
18507 #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18508 #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18509 #define CB_COLOR3_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18510 #define CB_COLOR3_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18511 #define CB_COLOR3_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18512 //CB_COLOR3_INFO
18513 #define CB_COLOR3_INFO__ENDIAN__SHIFT                                                                         0x0
18514 #define CB_COLOR3_INFO__FORMAT__SHIFT                                                                         0x2
18515 #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18516 #define CB_COLOR3_INFO__COMP_SWAP__SHIFT                                                                      0xb
18517 #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18518 #define CB_COLOR3_INFO__COMPRESSION__SHIFT                                                                    0xe
18519 #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18520 #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18521 #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18522 #define CB_COLOR3_INFO__ROUND_MODE__SHIFT                                                                     0x12
18523 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18524 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18525 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18526 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18527 #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18528 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18529 #define CB_COLOR3_INFO__ENDIAN_MASK                                                                           0x00000003L
18530 #define CB_COLOR3_INFO__FORMAT_MASK                                                                           0x0000007CL
18531 #define CB_COLOR3_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18532 #define CB_COLOR3_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18533 #define CB_COLOR3_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18534 #define CB_COLOR3_INFO__COMPRESSION_MASK                                                                      0x00004000L
18535 #define CB_COLOR3_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18536 #define CB_COLOR3_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18537 #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18538 #define CB_COLOR3_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18539 #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18540 #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18541 #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18542 #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18543 #define CB_COLOR3_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18544 #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18545 //CB_COLOR3_ATTRIB
18546 #define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18547 #define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18548 #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18549 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18550 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18551 #define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18552 #define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18553 #define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18554 #define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18555 #define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18556 #define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18557 #define CB_COLOR3_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18558 #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18559 #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18560 #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18561 #define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18562 #define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18563 #define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18564 #define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18565 #define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18566 //CB_COLOR3_DCC_CONTROL
18567 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18568 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18569 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18570 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18571 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18572 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18573 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18574 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18575 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18576 #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18577 #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18578 #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18579 #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18580 #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18581 #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18582 #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18583 #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18584 #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18585 //CB_COLOR3_CMASK
18586 #define CB_COLOR3_CMASK__BASE_256B__SHIFT                                                                     0x0
18587 #define CB_COLOR3_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18588 //CB_COLOR3_CMASK_BASE_EXT
18589 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18590 #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18591 //CB_COLOR3_FMASK
18592 #define CB_COLOR3_FMASK__BASE_256B__SHIFT                                                                     0x0
18593 #define CB_COLOR3_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18594 //CB_COLOR3_FMASK_BASE_EXT
18595 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18596 #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18597 //CB_COLOR3_CLEAR_WORD0
18598 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18599 #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18600 //CB_COLOR3_CLEAR_WORD1
18601 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18602 #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18603 //CB_COLOR3_DCC_BASE
18604 #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18605 #define CB_COLOR3_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18606 //CB_COLOR3_DCC_BASE_EXT
18607 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18608 #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18609 //CB_COLOR4_BASE
18610 #define CB_COLOR4_BASE__BASE_256B__SHIFT                                                                      0x0
18611 #define CB_COLOR4_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18612 //CB_COLOR4_BASE_EXT
18613 #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18614 #define CB_COLOR4_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18615 //CB_COLOR4_ATTRIB2
18616 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18617 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18618 #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18619 #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18620 #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18621 #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18622 //CB_COLOR4_VIEW
18623 #define CB_COLOR4_VIEW__SLICE_START__SHIFT                                                                    0x0
18624 #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18625 #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18626 #define CB_COLOR4_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18627 #define CB_COLOR4_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18628 #define CB_COLOR4_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18629 //CB_COLOR4_INFO
18630 #define CB_COLOR4_INFO__ENDIAN__SHIFT                                                                         0x0
18631 #define CB_COLOR4_INFO__FORMAT__SHIFT                                                                         0x2
18632 #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18633 #define CB_COLOR4_INFO__COMP_SWAP__SHIFT                                                                      0xb
18634 #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18635 #define CB_COLOR4_INFO__COMPRESSION__SHIFT                                                                    0xe
18636 #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18637 #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18638 #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18639 #define CB_COLOR4_INFO__ROUND_MODE__SHIFT                                                                     0x12
18640 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18641 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18642 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18643 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18644 #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18645 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18646 #define CB_COLOR4_INFO__ENDIAN_MASK                                                                           0x00000003L
18647 #define CB_COLOR4_INFO__FORMAT_MASK                                                                           0x0000007CL
18648 #define CB_COLOR4_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18649 #define CB_COLOR4_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18650 #define CB_COLOR4_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18651 #define CB_COLOR4_INFO__COMPRESSION_MASK                                                                      0x00004000L
18652 #define CB_COLOR4_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18653 #define CB_COLOR4_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18654 #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18655 #define CB_COLOR4_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18656 #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18657 #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18658 #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18659 #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18660 #define CB_COLOR4_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18661 #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18662 //CB_COLOR4_ATTRIB
18663 #define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18664 #define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18665 #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18666 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18667 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18668 #define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18669 #define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18670 #define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18671 #define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18672 #define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18673 #define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18674 #define CB_COLOR4_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18675 #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18676 #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18677 #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18678 #define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18679 #define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18680 #define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18681 #define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18682 #define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18683 //CB_COLOR4_DCC_CONTROL
18684 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18685 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18686 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18687 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18688 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18689 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18690 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18691 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18692 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18693 #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18694 #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18695 #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18696 #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18697 #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18698 #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18699 #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18700 #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18701 #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18702 //CB_COLOR4_CMASK
18703 #define CB_COLOR4_CMASK__BASE_256B__SHIFT                                                                     0x0
18704 #define CB_COLOR4_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18705 //CB_COLOR4_CMASK_BASE_EXT
18706 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18707 #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18708 //CB_COLOR4_FMASK
18709 #define CB_COLOR4_FMASK__BASE_256B__SHIFT                                                                     0x0
18710 #define CB_COLOR4_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18711 //CB_COLOR4_FMASK_BASE_EXT
18712 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18713 #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18714 //CB_COLOR4_CLEAR_WORD0
18715 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18716 #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18717 //CB_COLOR4_CLEAR_WORD1
18718 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18719 #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18720 //CB_COLOR4_DCC_BASE
18721 #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18722 #define CB_COLOR4_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18723 //CB_COLOR4_DCC_BASE_EXT
18724 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18725 #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18726 //CB_COLOR5_BASE
18727 #define CB_COLOR5_BASE__BASE_256B__SHIFT                                                                      0x0
18728 #define CB_COLOR5_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18729 //CB_COLOR5_BASE_EXT
18730 #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18731 #define CB_COLOR5_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18732 //CB_COLOR5_ATTRIB2
18733 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18734 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18735 #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18736 #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18737 #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18738 #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18739 //CB_COLOR5_VIEW
18740 #define CB_COLOR5_VIEW__SLICE_START__SHIFT                                                                    0x0
18741 #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18742 #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18743 #define CB_COLOR5_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18744 #define CB_COLOR5_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18745 #define CB_COLOR5_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18746 //CB_COLOR5_INFO
18747 #define CB_COLOR5_INFO__ENDIAN__SHIFT                                                                         0x0
18748 #define CB_COLOR5_INFO__FORMAT__SHIFT                                                                         0x2
18749 #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18750 #define CB_COLOR5_INFO__COMP_SWAP__SHIFT                                                                      0xb
18751 #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18752 #define CB_COLOR5_INFO__COMPRESSION__SHIFT                                                                    0xe
18753 #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18754 #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18755 #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18756 #define CB_COLOR5_INFO__ROUND_MODE__SHIFT                                                                     0x12
18757 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18758 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18759 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18760 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18761 #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18762 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18763 #define CB_COLOR5_INFO__ENDIAN_MASK                                                                           0x00000003L
18764 #define CB_COLOR5_INFO__FORMAT_MASK                                                                           0x0000007CL
18765 #define CB_COLOR5_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18766 #define CB_COLOR5_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18767 #define CB_COLOR5_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18768 #define CB_COLOR5_INFO__COMPRESSION_MASK                                                                      0x00004000L
18769 #define CB_COLOR5_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18770 #define CB_COLOR5_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18771 #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18772 #define CB_COLOR5_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18773 #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18774 #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18775 #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18776 #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18777 #define CB_COLOR5_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18778 #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18779 //CB_COLOR5_ATTRIB
18780 #define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18781 #define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18782 #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18783 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18784 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18785 #define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18786 #define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18787 #define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18788 #define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18789 #define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18790 #define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18791 #define CB_COLOR5_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18792 #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18793 #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18794 #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18795 #define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18796 #define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18797 #define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18798 #define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18799 #define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18800 //CB_COLOR5_DCC_CONTROL
18801 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18802 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18803 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18804 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18805 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18806 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18807 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18808 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18809 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18810 #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18811 #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18812 #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18813 #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18814 #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18815 #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18816 #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18817 #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18818 #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18819 //CB_COLOR5_CMASK
18820 #define CB_COLOR5_CMASK__BASE_256B__SHIFT                                                                     0x0
18821 #define CB_COLOR5_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18822 //CB_COLOR5_CMASK_BASE_EXT
18823 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18824 #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18825 //CB_COLOR5_FMASK
18826 #define CB_COLOR5_FMASK__BASE_256B__SHIFT                                                                     0x0
18827 #define CB_COLOR5_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18828 //CB_COLOR5_FMASK_BASE_EXT
18829 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18830 #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18831 //CB_COLOR5_CLEAR_WORD0
18832 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18833 #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18834 //CB_COLOR5_CLEAR_WORD1
18835 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18836 #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18837 //CB_COLOR5_DCC_BASE
18838 #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18839 #define CB_COLOR5_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18840 //CB_COLOR5_DCC_BASE_EXT
18841 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18842 #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18843 //CB_COLOR6_BASE
18844 #define CB_COLOR6_BASE__BASE_256B__SHIFT                                                                      0x0
18845 #define CB_COLOR6_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18846 //CB_COLOR6_BASE_EXT
18847 #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18848 #define CB_COLOR6_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18849 //CB_COLOR6_ATTRIB2
18850 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18851 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18852 #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18853 #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18854 #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18855 #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18856 //CB_COLOR6_VIEW
18857 #define CB_COLOR6_VIEW__SLICE_START__SHIFT                                                                    0x0
18858 #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18859 #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18860 #define CB_COLOR6_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18861 #define CB_COLOR6_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18862 #define CB_COLOR6_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18863 //CB_COLOR6_INFO
18864 #define CB_COLOR6_INFO__ENDIAN__SHIFT                                                                         0x0
18865 #define CB_COLOR6_INFO__FORMAT__SHIFT                                                                         0x2
18866 #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18867 #define CB_COLOR6_INFO__COMP_SWAP__SHIFT                                                                      0xb
18868 #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18869 #define CB_COLOR6_INFO__COMPRESSION__SHIFT                                                                    0xe
18870 #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18871 #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18872 #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18873 #define CB_COLOR6_INFO__ROUND_MODE__SHIFT                                                                     0x12
18874 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18875 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18876 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18877 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18878 #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18879 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18880 #define CB_COLOR6_INFO__ENDIAN_MASK                                                                           0x00000003L
18881 #define CB_COLOR6_INFO__FORMAT_MASK                                                                           0x0000007CL
18882 #define CB_COLOR6_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
18883 #define CB_COLOR6_INFO__COMP_SWAP_MASK                                                                        0x00001800L
18884 #define CB_COLOR6_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
18885 #define CB_COLOR6_INFO__COMPRESSION_MASK                                                                      0x00004000L
18886 #define CB_COLOR6_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
18887 #define CB_COLOR6_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
18888 #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
18889 #define CB_COLOR6_INFO__ROUND_MODE_MASK                                                                       0x00040000L
18890 #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
18891 #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
18892 #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
18893 #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
18894 #define CB_COLOR6_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
18895 #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
18896 //CB_COLOR6_ATTRIB
18897 #define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
18898 #define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
18899 #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
18900 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
18901 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
18902 #define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
18903 #define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
18904 #define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
18905 #define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
18906 #define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
18907 #define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
18908 #define CB_COLOR6_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
18909 #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
18910 #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
18911 #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
18912 #define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
18913 #define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
18914 #define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
18915 #define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
18916 #define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
18917 //CB_COLOR6_DCC_CONTROL
18918 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
18919 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
18920 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
18921 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
18922 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
18923 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
18924 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
18925 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
18926 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
18927 #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
18928 #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
18929 #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
18930 #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
18931 #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
18932 #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
18933 #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
18934 #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
18935 #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
18936 //CB_COLOR6_CMASK
18937 #define CB_COLOR6_CMASK__BASE_256B__SHIFT                                                                     0x0
18938 #define CB_COLOR6_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18939 //CB_COLOR6_CMASK_BASE_EXT
18940 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18941 #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18942 //CB_COLOR6_FMASK
18943 #define CB_COLOR6_FMASK__BASE_256B__SHIFT                                                                     0x0
18944 #define CB_COLOR6_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
18945 //CB_COLOR6_FMASK_BASE_EXT
18946 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
18947 #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
18948 //CB_COLOR6_CLEAR_WORD0
18949 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
18950 #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
18951 //CB_COLOR6_CLEAR_WORD1
18952 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
18953 #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
18954 //CB_COLOR6_DCC_BASE
18955 #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
18956 #define CB_COLOR6_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
18957 //CB_COLOR6_DCC_BASE_EXT
18958 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
18959 #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
18960 //CB_COLOR7_BASE
18961 #define CB_COLOR7_BASE__BASE_256B__SHIFT                                                                      0x0
18962 #define CB_COLOR7_BASE__BASE_256B_MASK                                                                        0xFFFFFFFFL
18963 //CB_COLOR7_BASE_EXT
18964 #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT                                                                  0x0
18965 #define CB_COLOR7_BASE_EXT__BASE_256B_MASK                                                                    0x000000FFL
18966 //CB_COLOR7_ATTRIB2
18967 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT                                                                 0x0
18968 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT                                                                  0xe
18969 #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT                                                                     0x1c
18970 #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK                                                                   0x00003FFFL
18971 #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK                                                                    0x0FFFC000L
18972 #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK                                                                       0xF0000000L
18973 //CB_COLOR7_VIEW
18974 #define CB_COLOR7_VIEW__SLICE_START__SHIFT                                                                    0x0
18975 #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT                                                                      0xd
18976 #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT                                                                      0x18
18977 #define CB_COLOR7_VIEW__SLICE_START_MASK                                                                      0x000007FFL
18978 #define CB_COLOR7_VIEW__SLICE_MAX_MASK                                                                        0x00FFE000L
18979 #define CB_COLOR7_VIEW__MIP_LEVEL_MASK                                                                        0x0F000000L
18980 //CB_COLOR7_INFO
18981 #define CB_COLOR7_INFO__ENDIAN__SHIFT                                                                         0x0
18982 #define CB_COLOR7_INFO__FORMAT__SHIFT                                                                         0x2
18983 #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT                                                                    0x8
18984 #define CB_COLOR7_INFO__COMP_SWAP__SHIFT                                                                      0xb
18985 #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT                                                                     0xd
18986 #define CB_COLOR7_INFO__COMPRESSION__SHIFT                                                                    0xe
18987 #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT                                                                    0xf
18988 #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT                                                                   0x10
18989 #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT                                                                   0x11
18990 #define CB_COLOR7_INFO__ROUND_MODE__SHIFT                                                                     0x12
18991 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT                                                          0x14
18992 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT                                                        0x17
18993 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT                                                      0x1a
18994 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT                                                      0x1b
18995 #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT                                                                     0x1c
18996 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT                                                                0x1d
18997 #define CB_COLOR7_INFO__ENDIAN_MASK                                                                           0x00000003L
18998 #define CB_COLOR7_INFO__FORMAT_MASK                                                                           0x0000007CL
18999 #define CB_COLOR7_INFO__NUMBER_TYPE_MASK                                                                      0x00000700L
19000 #define CB_COLOR7_INFO__COMP_SWAP_MASK                                                                        0x00001800L
19001 #define CB_COLOR7_INFO__FAST_CLEAR_MASK                                                                       0x00002000L
19002 #define CB_COLOR7_INFO__COMPRESSION_MASK                                                                      0x00004000L
19003 #define CB_COLOR7_INFO__BLEND_CLAMP_MASK                                                                      0x00008000L
19004 #define CB_COLOR7_INFO__BLEND_BYPASS_MASK                                                                     0x00010000L
19005 #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK                                                                     0x00020000L
19006 #define CB_COLOR7_INFO__ROUND_MODE_MASK                                                                       0x00040000L
19007 #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK                                                            0x00700000L
19008 #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK                                                          0x03800000L
19009 #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK                                                        0x04000000L
19010 #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK                                                        0x08000000L
19011 #define CB_COLOR7_INFO__DCC_ENABLE_MASK                                                                       0x10000000L
19012 #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK                                                                  0x60000000L
19013 //CB_COLOR7_ATTRIB
19014 #define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT                                                                   0x0
19015 #define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT                                                                  0xb
19016 #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT                                                                  0xc
19017 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT                                                                0xf
19018 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT                                                            0x11
19019 #define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT                                                                0x12
19020 #define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT                                                                0x17
19021 #define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT                                                                0x1c
19022 #define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT                                                                   0x1e
19023 #define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT                                                                 0x1f
19024 #define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK                                                                     0x000007FFL
19025 #define CB_COLOR7_ATTRIB__META_LINEAR_MASK                                                                    0x00000800L
19026 #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK                                                                    0x00007000L
19027 #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK                                                                  0x00018000L
19028 #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK                                                              0x00020000L
19029 #define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK                                                                  0x007C0000L
19030 #define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK                                                                  0x0F800000L
19031 #define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK                                                                  0x30000000L
19032 #define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK                                                                     0x40000000L
19033 #define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK                                                                   0x80000000L
19034 //CB_COLOR7_DCC_CONTROL
19035 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT                                              0x0
19036 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT                                                        0x1
19037 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT                                             0x2
19038 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x4
19039 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT                                               0x5
19040 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT                                                         0x7
19041 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT                                                  0x9
19042 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT                                                     0xa
19043 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT                                                   0xe
19044 #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK                                                0x00000001L
19045 #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK                                                          0x00000002L
19046 #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK                                               0x0000000CL
19047 #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000010L
19048 #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK                                                 0x00000060L
19049 #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK                                                           0x00000180L
19050 #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK                                                    0x00000200L
19051 #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK                                                       0x00003C00L
19052 #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK                                                     0x0003C000L
19053 //CB_COLOR7_CMASK
19054 #define CB_COLOR7_CMASK__BASE_256B__SHIFT                                                                     0x0
19055 #define CB_COLOR7_CMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
19056 //CB_COLOR7_CMASK_BASE_EXT
19057 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
19058 #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
19059 //CB_COLOR7_FMASK
19060 #define CB_COLOR7_FMASK__BASE_256B__SHIFT                                                                     0x0
19061 #define CB_COLOR7_FMASK__BASE_256B_MASK                                                                       0xFFFFFFFFL
19062 //CB_COLOR7_FMASK_BASE_EXT
19063 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT                                                            0x0
19064 #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK                                                              0x000000FFL
19065 //CB_COLOR7_CLEAR_WORD0
19066 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT                                                             0x0
19067 #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK                                                               0xFFFFFFFFL
19068 //CB_COLOR7_CLEAR_WORD1
19069 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT                                                             0x0
19070 #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK                                                               0xFFFFFFFFL
19071 //CB_COLOR7_DCC_BASE
19072 #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT                                                                  0x0
19073 #define CB_COLOR7_DCC_BASE__BASE_256B_MASK                                                                    0xFFFFFFFFL
19074 //CB_COLOR7_DCC_BASE_EXT
19075 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT                                                              0x0
19076 #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK                                                                0x000000FFL
19077 
19078 
19079 // addressBlock: gc_gfxudec
19080 //CP_EOP_DONE_ADDR_LO
19081 #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT                                                                   0x2
19082 #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK                                                                     0xFFFFFFFCL
19083 //CP_EOP_DONE_ADDR_HI
19084 #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
19085 #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
19086 //CP_EOP_DONE_DATA_LO
19087 #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT                                                                   0x0
19088 #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK                                                                     0xFFFFFFFFL
19089 //CP_EOP_DONE_DATA_HI
19090 #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT                                                                   0x0
19091 #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK                                                                     0xFFFFFFFFL
19092 //CP_EOP_LAST_FENCE_LO
19093 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT                                                            0x0
19094 #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK                                                              0xFFFFFFFFL
19095 //CP_EOP_LAST_FENCE_HI
19096 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT                                                            0x0
19097 #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK                                                              0xFFFFFFFFL
19098 //CP_STREAM_OUT_ADDR_LO
19099 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT                                                      0x2
19100 #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK                                                        0xFFFFFFFCL
19101 //CP_STREAM_OUT_ADDR_HI
19102 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT                                                      0x0
19103 #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK                                                        0x0000FFFFL
19104 //CP_NUM_PRIM_WRITTEN_COUNT0_LO
19105 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT                                        0x0
19106 #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK                                          0xFFFFFFFFL
19107 //CP_NUM_PRIM_WRITTEN_COUNT0_HI
19108 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT                                        0x0
19109 #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK                                          0xFFFFFFFFL
19110 //CP_NUM_PRIM_NEEDED_COUNT0_LO
19111 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT                                          0x0
19112 #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK                                            0xFFFFFFFFL
19113 //CP_NUM_PRIM_NEEDED_COUNT0_HI
19114 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT                                          0x0
19115 #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK                                            0xFFFFFFFFL
19116 //CP_NUM_PRIM_WRITTEN_COUNT1_LO
19117 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT                                        0x0
19118 #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK                                          0xFFFFFFFFL
19119 //CP_NUM_PRIM_WRITTEN_COUNT1_HI
19120 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT                                        0x0
19121 #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK                                          0xFFFFFFFFL
19122 //CP_NUM_PRIM_NEEDED_COUNT1_LO
19123 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT                                          0x0
19124 #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK                                            0xFFFFFFFFL
19125 //CP_NUM_PRIM_NEEDED_COUNT1_HI
19126 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT                                          0x0
19127 #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK                                            0xFFFFFFFFL
19128 //CP_NUM_PRIM_WRITTEN_COUNT2_LO
19129 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT                                        0x0
19130 #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK                                          0xFFFFFFFFL
19131 //CP_NUM_PRIM_WRITTEN_COUNT2_HI
19132 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT                                        0x0
19133 #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK                                          0xFFFFFFFFL
19134 //CP_NUM_PRIM_NEEDED_COUNT2_LO
19135 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT                                          0x0
19136 #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK                                            0xFFFFFFFFL
19137 //CP_NUM_PRIM_NEEDED_COUNT2_HI
19138 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT                                          0x0
19139 #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK                                            0xFFFFFFFFL
19140 //CP_NUM_PRIM_WRITTEN_COUNT3_LO
19141 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT                                        0x0
19142 #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK                                          0xFFFFFFFFL
19143 //CP_NUM_PRIM_WRITTEN_COUNT3_HI
19144 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT                                        0x0
19145 #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK                                          0xFFFFFFFFL
19146 //CP_NUM_PRIM_NEEDED_COUNT3_LO
19147 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT                                          0x0
19148 #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK                                            0xFFFFFFFFL
19149 //CP_NUM_PRIM_NEEDED_COUNT3_HI
19150 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT                                          0x0
19151 #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK                                            0xFFFFFFFFL
19152 //CP_PIPE_STATS_ADDR_LO
19153 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT                                                      0x2
19154 #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK                                                        0xFFFFFFFCL
19155 //CP_PIPE_STATS_ADDR_HI
19156 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT                                                      0x0
19157 #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK                                                        0x0000FFFFL
19158 //CP_VGT_IAVERT_COUNT_LO
19159 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT                                                        0x0
19160 #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK                                                          0xFFFFFFFFL
19161 //CP_VGT_IAVERT_COUNT_HI
19162 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT                                                        0x0
19163 #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK                                                          0xFFFFFFFFL
19164 //CP_VGT_IAPRIM_COUNT_LO
19165 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT                                                        0x0
19166 #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
19167 //CP_VGT_IAPRIM_COUNT_HI
19168 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT                                                        0x0
19169 #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
19170 //CP_VGT_GSPRIM_COUNT_LO
19171 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT                                                        0x0
19172 #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK                                                          0xFFFFFFFFL
19173 //CP_VGT_GSPRIM_COUNT_HI
19174 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT                                                        0x0
19175 #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK                                                          0xFFFFFFFFL
19176 //CP_VGT_VSINVOC_COUNT_LO
19177 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT                                                      0x0
19178 #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19179 //CP_VGT_VSINVOC_COUNT_HI
19180 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT                                                      0x0
19181 #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19182 //CP_VGT_GSINVOC_COUNT_LO
19183 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT                                                      0x0
19184 #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19185 //CP_VGT_GSINVOC_COUNT_HI
19186 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT                                                      0x0
19187 #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19188 //CP_VGT_HSINVOC_COUNT_LO
19189 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT                                                      0x0
19190 #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19191 //CP_VGT_HSINVOC_COUNT_HI
19192 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT                                                      0x0
19193 #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19194 //CP_VGT_DSINVOC_COUNT_LO
19195 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT                                                      0x0
19196 #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19197 //CP_VGT_DSINVOC_COUNT_HI
19198 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT                                                      0x0
19199 #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19200 //CP_PA_CINVOC_COUNT_LO
19201 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT                                                         0x0
19202 #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK                                                           0xFFFFFFFFL
19203 //CP_PA_CINVOC_COUNT_HI
19204 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT                                                         0x0
19205 #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK                                                           0xFFFFFFFFL
19206 //CP_PA_CPRIM_COUNT_LO
19207 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT                                                           0x0
19208 #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK                                                             0xFFFFFFFFL
19209 //CP_PA_CPRIM_COUNT_HI
19210 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT                                                           0x0
19211 #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK                                                             0xFFFFFFFFL
19212 //CP_SC_PSINVOC_COUNT0_LO
19213 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT                                                     0x0
19214 #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK                                                       0xFFFFFFFFL
19215 //CP_SC_PSINVOC_COUNT0_HI
19216 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT                                                     0x0
19217 #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK                                                       0xFFFFFFFFL
19218 //CP_SC_PSINVOC_COUNT1_LO
19219 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT                                                              0x0
19220 #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK                                                                0xFFFFFFFFL
19221 //CP_SC_PSINVOC_COUNT1_HI
19222 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT                                                              0x0
19223 #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK                                                                0xFFFFFFFFL
19224 //CP_VGT_CSINVOC_COUNT_LO
19225 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT                                                      0x0
19226 #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK                                                        0xFFFFFFFFL
19227 //CP_VGT_CSINVOC_COUNT_HI
19228 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT                                                      0x0
19229 #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK                                                        0xFFFFFFFFL
19230 //CP_PIPE_STATS_CONTROL
19231 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
19232 #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK                                                              0x02000000L
19233 //CP_STREAM_OUT_CONTROL
19234 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT                                                            0x19
19235 #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK                                                              0x02000000L
19236 //CP_STRMOUT_CNTL
19237 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT                                                            0x0
19238 #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK                                                              0x00000001L
19239 //SCRATCH_REG0
19240 #define SCRATCH_REG0__SCRATCH_REG0__SHIFT                                                                     0x0
19241 #define SCRATCH_REG0__SCRATCH_REG0_MASK                                                                       0xFFFFFFFFL
19242 //SCRATCH_REG1
19243 #define SCRATCH_REG1__SCRATCH_REG1__SHIFT                                                                     0x0
19244 #define SCRATCH_REG1__SCRATCH_REG1_MASK                                                                       0xFFFFFFFFL
19245 //SCRATCH_REG2
19246 #define SCRATCH_REG2__SCRATCH_REG2__SHIFT                                                                     0x0
19247 #define SCRATCH_REG2__SCRATCH_REG2_MASK                                                                       0xFFFFFFFFL
19248 //SCRATCH_REG3
19249 #define SCRATCH_REG3__SCRATCH_REG3__SHIFT                                                                     0x0
19250 #define SCRATCH_REG3__SCRATCH_REG3_MASK                                                                       0xFFFFFFFFL
19251 //SCRATCH_REG4
19252 #define SCRATCH_REG4__SCRATCH_REG4__SHIFT                                                                     0x0
19253 #define SCRATCH_REG4__SCRATCH_REG4_MASK                                                                       0xFFFFFFFFL
19254 //SCRATCH_REG5
19255 #define SCRATCH_REG5__SCRATCH_REG5__SHIFT                                                                     0x0
19256 #define SCRATCH_REG5__SCRATCH_REG5_MASK                                                                       0xFFFFFFFFL
19257 //SCRATCH_REG6
19258 #define SCRATCH_REG6__SCRATCH_REG6__SHIFT                                                                     0x0
19259 #define SCRATCH_REG6__SCRATCH_REG6_MASK                                                                       0xFFFFFFFFL
19260 //SCRATCH_REG7
19261 #define SCRATCH_REG7__SCRATCH_REG7__SHIFT                                                                     0x0
19262 #define SCRATCH_REG7__SCRATCH_REG7_MASK                                                                       0xFFFFFFFFL
19263 //CP_APPEND_DATA_HI
19264 #define CP_APPEND_DATA_HI__DATA__SHIFT                                                                        0x0
19265 #define CP_APPEND_DATA_HI__DATA_MASK                                                                          0xFFFFFFFFL
19266 //CP_APPEND_LAST_CS_FENCE_HI
19267 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
19268 #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19269 //CP_APPEND_LAST_PS_FENCE_HI
19270 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT                                                         0x0
19271 #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19272 //SCRATCH_UMSK
19273 #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT                                                                    0x0
19274 #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT                                                                    0x10
19275 #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK                                                                      0x000000FFL
19276 #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK                                                                      0x00030000L
19277 //SCRATCH_ADDR
19278 #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT                                                                    0x0
19279 #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK                                                                      0xFFFFFFFFL
19280 //CP_PFP_ATOMIC_PREOP_LO
19281 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                        0x0
19282 #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                          0xFFFFFFFFL
19283 //CP_PFP_ATOMIC_PREOP_HI
19284 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                        0x0
19285 #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                          0xFFFFFFFFL
19286 //CP_PFP_GDS_ATOMIC0_PREOP_LO
19287 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                              0x0
19288 #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                0xFFFFFFFFL
19289 //CP_PFP_GDS_ATOMIC0_PREOP_HI
19290 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                              0x0
19291 #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                0xFFFFFFFFL
19292 //CP_PFP_GDS_ATOMIC1_PREOP_LO
19293 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                              0x0
19294 #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                0xFFFFFFFFL
19295 //CP_PFP_GDS_ATOMIC1_PREOP_HI
19296 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                              0x0
19297 #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                0xFFFFFFFFL
19298 //CP_APPEND_ADDR_LO
19299 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT                                                                 0x2
19300 #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK                                                                   0xFFFFFFFCL
19301 //CP_APPEND_ADDR_HI
19302 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT                                                                 0x0
19303 #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT                                                                   0x10
19304 #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT                                                                0x19
19305 #define CP_APPEND_ADDR_HI__COMMAND__SHIFT                                                                     0x1d
19306 #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK                                                                   0x0000FFFFL
19307 #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK                                                                     0x00010000L
19308 #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK                                                                  0x02000000L
19309 #define CP_APPEND_ADDR_HI__COMMAND_MASK                                                                       0xE0000000L
19310 //CP_APPEND_DATA_LO
19311 #define CP_APPEND_DATA_LO__DATA__SHIFT                                                                        0x0
19312 #define CP_APPEND_DATA_LO__DATA_MASK                                                                          0xFFFFFFFFL
19313 //CP_APPEND_LAST_CS_FENCE_LO
19314 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
19315 #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19316 //CP_APPEND_LAST_PS_FENCE_LO
19317 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT                                                         0x0
19318 #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK                                                           0xFFFFFFFFL
19319 //CP_ATOMIC_PREOP_LO
19320 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                            0x0
19321 #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                              0xFFFFFFFFL
19322 //CP_ME_ATOMIC_PREOP_LO
19323 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT                                                         0x0
19324 #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK                                                           0xFFFFFFFFL
19325 //CP_ATOMIC_PREOP_HI
19326 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                            0x0
19327 #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                              0xFFFFFFFFL
19328 //CP_ME_ATOMIC_PREOP_HI
19329 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT                                                         0x0
19330 #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK                                                           0xFFFFFFFFL
19331 //CP_GDS_ATOMIC0_PREOP_LO
19332 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                                  0x0
19333 #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                    0xFFFFFFFFL
19334 //CP_ME_GDS_ATOMIC0_PREOP_LO
19335 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT                                               0x0
19336 #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK                                                 0xFFFFFFFFL
19337 //CP_GDS_ATOMIC0_PREOP_HI
19338 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                                  0x0
19339 #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                    0xFFFFFFFFL
19340 //CP_ME_GDS_ATOMIC0_PREOP_HI
19341 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT                                               0x0
19342 #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK                                                 0xFFFFFFFFL
19343 //CP_GDS_ATOMIC1_PREOP_LO
19344 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                                  0x0
19345 #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                    0xFFFFFFFFL
19346 //CP_ME_GDS_ATOMIC1_PREOP_LO
19347 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT                                               0x0
19348 #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK                                                 0xFFFFFFFFL
19349 //CP_GDS_ATOMIC1_PREOP_HI
19350 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                                  0x0
19351 #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                    0xFFFFFFFFL
19352 //CP_ME_GDS_ATOMIC1_PREOP_HI
19353 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT                                               0x0
19354 #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK                                                 0xFFFFFFFFL
19355 //CP_ME_MC_WADDR_LO
19356 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT                                                              0x2
19357 #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK                                                                0xFFFFFFFCL
19358 //CP_ME_MC_WADDR_HI
19359 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT                                                              0x0
19360 #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
19361 #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK                                                                0x0000FFFFL
19362 #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK                                                                  0x00400000L
19363 //CP_ME_MC_WDATA_LO
19364 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT                                                              0x0
19365 #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK                                                                0xFFFFFFFFL
19366 //CP_ME_MC_WDATA_HI
19367 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT                                                              0x0
19368 #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK                                                                0xFFFFFFFFL
19369 //CP_ME_MC_RADDR_LO
19370 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT                                                              0x2
19371 #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK                                                                0xFFFFFFFCL
19372 //CP_ME_MC_RADDR_HI
19373 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT                                                              0x0
19374 #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT                                                                0x16
19375 #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK                                                                0x0000FFFFL
19376 #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK                                                                  0x00400000L
19377 //CP_SEM_WAIT_TIMER
19378 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT                                                              0x0
19379 #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK                                                                0xFFFFFFFFL
19380 //CP_SIG_SEM_ADDR_LO
19381 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                              0x0
19382 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                                0x3
19383 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                                0x00000003L
19384 #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                  0xFFFFFFF8L
19385 //CP_SIG_SEM_ADDR_HI
19386 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                                0x0
19387 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                            0x10
19388 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                            0x14
19389 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                            0x18
19390 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                 0x1d
19391 #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                  0x0000FFFFL
19392 #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                              0x00010000L
19393 #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                              0x00100000L
19394 #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                              0x03000000L
19395 #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK                                                                   0xE0000000L
19396 //CP_WAIT_REG_MEM_TIMEOUT
19397 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT                                                  0x0
19398 #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK                                                    0xFFFFFFFFL
19399 //CP_WAIT_SEM_ADDR_LO
19400 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT                                                             0x0
19401 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT                                                               0x3
19402 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK                                                               0x00000003L
19403 #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK                                                                 0xFFFFFFF8L
19404 //CP_WAIT_SEM_ADDR_HI
19405 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT                                                               0x0
19406 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT                                                           0x10
19407 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT                                                           0x14
19408 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT                                                           0x18
19409 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT                                                                0x1d
19410 #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK                                                                 0x0000FFFFL
19411 #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK                                                             0x00010000L
19412 #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK                                                             0x00100000L
19413 #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK                                                             0x03000000L
19414 #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK                                                                  0xE0000000L
19415 //CP_DMA_PFP_CONTROL
19416 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT                                                               0xa
19417 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT                                                           0xd
19418 #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT                                                                 0x14
19419 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT                                                           0x19
19420 #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT                                                                 0x1d
19421 #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK                                                                 0x00000400L
19422 #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK                                                             0x00002000L
19423 #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK                                                                   0x00300000L
19424 #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK                                                             0x02000000L
19425 #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK                                                                   0x60000000L
19426 //CP_DMA_ME_CONTROL
19427 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT                                                                0xa
19428 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT                                                            0xd
19429 #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT                                                                  0x14
19430 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT                                                            0x19
19431 #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT                                                                  0x1d
19432 #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK                                                                  0x00000400L
19433 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK                                                              0x00002000L
19434 #define CP_DMA_ME_CONTROL__DST_SELECT_MASK                                                                    0x00300000L
19435 #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK                                                              0x02000000L
19436 #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK                                                                    0x60000000L
19437 //CP_COHER_BASE_HI
19438 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                           0x0
19439 #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                             0x000000FFL
19440 //CP_COHER_START_DELAY
19441 #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT                                                        0x0
19442 #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK                                                          0x0000003FL
19443 //CP_COHER_CNTL
19444 #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT                                                                0x3
19445 #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT                                                                0x4
19446 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT                                                      0x5
19447 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT                                                             0xf
19448 #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT                                                                0x12
19449 #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT                                                                 0x16
19450 #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT                                                                   0x17
19451 #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT                                                                   0x19
19452 #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT                                                                   0x1a
19453 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT                                                            0x1b
19454 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT                                                        0x1c
19455 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT                                                            0x1d
19456 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT                                                         0x1e
19457 #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK                                                                  0x00000008L
19458 #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK                                                                  0x00000010L
19459 #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK                                                        0x00000020L
19460 #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK                                                               0x00008000L
19461 #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK                                                                  0x00040000L
19462 #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK                                                                   0x00400000L
19463 #define CP_COHER_CNTL__TC_ACTION_ENA_MASK                                                                     0x00800000L
19464 #define CP_COHER_CNTL__CB_ACTION_ENA_MASK                                                                     0x02000000L
19465 #define CP_COHER_CNTL__DB_ACTION_ENA_MASK                                                                     0x04000000L
19466 #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK                                                              0x08000000L
19467 #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK                                                          0x10000000L
19468 #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK                                                              0x20000000L
19469 #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK                                                           0x40000000L
19470 //CP_COHER_SIZE
19471 #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                                 0x0
19472 #define CP_COHER_SIZE__COHER_SIZE_256B_MASK                                                                   0xFFFFFFFFL
19473 //CP_COHER_BASE
19474 #define CP_COHER_BASE__COHER_BASE_256B__SHIFT                                                                 0x0
19475 #define CP_COHER_BASE__COHER_BASE_256B_MASK                                                                   0xFFFFFFFFL
19476 //CP_COHER_STATUS
19477 #define CP_COHER_STATUS__MEID__SHIFT                                                                          0x18
19478 #define CP_COHER_STATUS__STATUS__SHIFT                                                                        0x1f
19479 #define CP_COHER_STATUS__MEID_MASK                                                                            0x03000000L
19480 #define CP_COHER_STATUS__STATUS_MASK                                                                          0x80000000L
19481 //CP_DMA_ME_SRC_ADDR
19482 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT                                                                   0x0
19483 #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK                                                                     0xFFFFFFFFL
19484 //CP_DMA_ME_SRC_ADDR_HI
19485 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                             0x0
19486 #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                               0x0000FFFFL
19487 //CP_DMA_ME_DST_ADDR
19488 #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT                                                                   0x0
19489 #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK                                                                     0xFFFFFFFFL
19490 //CP_DMA_ME_DST_ADDR_HI
19491 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                             0x0
19492 #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK                                                               0x0000FFFFL
19493 //CP_DMA_ME_COMMAND
19494 #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT                                                                  0x0
19495 #define CP_DMA_ME_COMMAND__SAS__SHIFT                                                                         0x1a
19496 #define CP_DMA_ME_COMMAND__DAS__SHIFT                                                                         0x1b
19497 #define CP_DMA_ME_COMMAND__SAIC__SHIFT                                                                        0x1c
19498 #define CP_DMA_ME_COMMAND__DAIC__SHIFT                                                                        0x1d
19499 #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT                                                                    0x1e
19500 #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT                                                                      0x1f
19501 #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK                                                                    0x03FFFFFFL
19502 #define CP_DMA_ME_COMMAND__SAS_MASK                                                                           0x04000000L
19503 #define CP_DMA_ME_COMMAND__DAS_MASK                                                                           0x08000000L
19504 #define CP_DMA_ME_COMMAND__SAIC_MASK                                                                          0x10000000L
19505 #define CP_DMA_ME_COMMAND__DAIC_MASK                                                                          0x20000000L
19506 #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK                                                                      0x40000000L
19507 #define CP_DMA_ME_COMMAND__DIS_WC_MASK                                                                        0x80000000L
19508 //CP_DMA_PFP_SRC_ADDR
19509 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT                                                                  0x0
19510 #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK                                                                    0xFFFFFFFFL
19511 //CP_DMA_PFP_SRC_ADDR_HI
19512 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT                                                            0x0
19513 #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK                                                              0x0000FFFFL
19514 //CP_DMA_PFP_DST_ADDR
19515 #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT                                                                  0x0
19516 #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK                                                                    0xFFFFFFFFL
19517 //CP_DMA_PFP_DST_ADDR_HI
19518 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT                                                            0x0
19519 #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK                                                              0x0000FFFFL
19520 //CP_DMA_PFP_COMMAND
19521 #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT                                                                 0x0
19522 #define CP_DMA_PFP_COMMAND__SAS__SHIFT                                                                        0x1a
19523 #define CP_DMA_PFP_COMMAND__DAS__SHIFT                                                                        0x1b
19524 #define CP_DMA_PFP_COMMAND__SAIC__SHIFT                                                                       0x1c
19525 #define CP_DMA_PFP_COMMAND__DAIC__SHIFT                                                                       0x1d
19526 #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT                                                                   0x1e
19527 #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT                                                                     0x1f
19528 #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK                                                                   0x03FFFFFFL
19529 #define CP_DMA_PFP_COMMAND__SAS_MASK                                                                          0x04000000L
19530 #define CP_DMA_PFP_COMMAND__DAS_MASK                                                                          0x08000000L
19531 #define CP_DMA_PFP_COMMAND__SAIC_MASK                                                                         0x10000000L
19532 #define CP_DMA_PFP_COMMAND__DAIC_MASK                                                                         0x20000000L
19533 #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK                                                                     0x40000000L
19534 #define CP_DMA_PFP_COMMAND__DIS_WC_MASK                                                                       0x80000000L
19535 //CP_DMA_CNTL
19536 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT                                                               0x0
19537 #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT                                                                       0x4
19538 #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT                                                                      0x10
19539 #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT                                                                    0x1c
19540 #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT                                                                     0x1d
19541 #define CP_DMA_CNTL__PIO_COUNT__SHIFT                                                                         0x1e
19542 #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK                                                                 0x00000001L
19543 #define CP_DMA_CNTL__MIN_AVAILSZ_MASK                                                                         0x00000030L
19544 #define CP_DMA_CNTL__BUFFER_DEPTH_MASK                                                                        0x000F0000L
19545 #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK                                                                      0x10000000L
19546 #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK                                                                       0x20000000L
19547 #define CP_DMA_CNTL__PIO_COUNT_MASK                                                                           0xC0000000L
19548 //CP_DMA_READ_TAGS
19549 #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT                                                                 0x0
19550 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT                                                           0x1c
19551 #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK                                                                   0x03FFFFFFL
19552 #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK                                                             0x10000000L
19553 //CP_COHER_SIZE_HI
19554 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                           0x0
19555 #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                             0x000000FFL
19556 //CP_PFP_IB_CONTROL
19557 #define CP_PFP_IB_CONTROL__IB_EN__SHIFT                                                                       0x0
19558 #define CP_PFP_IB_CONTROL__IB_EN_MASK                                                                         0x000000FFL
19559 //CP_PFP_LOAD_CONTROL
19560 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT                                                             0x0
19561 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT                                                               0x1
19562 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT                                                             0x10
19563 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT                                                              0x18
19564 #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK                                                               0x00000001L
19565 #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK                                                                 0x00000002L
19566 #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK                                                               0x00010000L
19567 #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK                                                                0x01000000L
19568 //CP_SCRATCH_INDEX
19569 #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT                                                                0x0
19570 #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK                                                                  0x000000FFL
19571 //CP_SCRATCH_DATA
19572 #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT                                                                  0x0
19573 #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK                                                                    0xFFFFFFFFL
19574 //CP_RB_OFFSET
19575 #define CP_RB_OFFSET__RB_OFFSET__SHIFT                                                                        0x0
19576 #define CP_RB_OFFSET__RB_OFFSET_MASK                                                                          0x000FFFFFL
19577 //CP_IB1_OFFSET
19578 #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                      0x0
19579 #define CP_IB1_OFFSET__IB1_OFFSET_MASK                                                                        0x000FFFFFL
19580 //CP_IB2_OFFSET
19581 #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                      0x0
19582 #define CP_IB2_OFFSET__IB2_OFFSET_MASK                                                                        0x000FFFFFL
19583 //CP_IB1_PREAMBLE_BEGIN
19584 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT                                                      0x0
19585 #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
19586 //CP_IB1_PREAMBLE_END
19587 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT                                                          0x0
19588 #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK                                                            0x000FFFFFL
19589 //CP_IB2_PREAMBLE_BEGIN
19590 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT                                                      0x0
19591 #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK                                                        0x000FFFFFL
19592 //CP_IB2_PREAMBLE_END
19593 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT                                                          0x0
19594 #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK                                                            0x000FFFFFL
19595 //CP_CE_IB1_OFFSET
19596 #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT                                                                   0x0
19597 #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK                                                                     0x000FFFFFL
19598 //CP_CE_IB2_OFFSET
19599 #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT                                                                   0x0
19600 #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK                                                                     0x000FFFFFL
19601 //CP_CE_COUNTER
19602 #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT                                                              0x0
19603 #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK                                                                0xFFFFFFFFL
19604 //CP_CE_RB_OFFSET
19605 #define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT                                                                     0x0
19606 #define CP_CE_RB_OFFSET__RB_OFFSET_MASK                                                                       0x000FFFFFL
19607 //CP_CE_INIT_CMD_BUFSZ
19608 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT                                                           0x0
19609 #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK                                                             0x00000FFFL
19610 //CP_CE_IB1_CMD_BUFSZ
19611 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                             0x0
19612 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                               0x000FFFFFL
19613 //CP_CE_IB2_CMD_BUFSZ
19614 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                             0x0
19615 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                               0x000FFFFFL
19616 //CP_IB1_CMD_BUFSZ
19617 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT                                                                0x0
19618 #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK                                                                  0x000FFFFFL
19619 //CP_IB2_CMD_BUFSZ
19620 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT                                                                0x0
19621 #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK                                                                  0x000FFFFFL
19622 //CP_ST_CMD_BUFSZ
19623 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT                                                                  0x0
19624 #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK                                                                    0x000FFFFFL
19625 //CP_CE_INIT_BASE_LO
19626 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT                                                               0x5
19627 #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK                                                                 0xFFFFFFE0L
19628 //CP_CE_INIT_BASE_HI
19629 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT                                                               0x0
19630 #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK                                                                 0x0000FFFFL
19631 //CP_CE_INIT_BUFSZ
19632 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT                                                                   0x0
19633 #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK                                                                     0x00000FFFL
19634 //CP_CE_IB1_BASE_LO
19635 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                 0x2
19636 #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                   0xFFFFFFFCL
19637 //CP_CE_IB1_BASE_HI
19638 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                 0x0
19639 #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                   0x0000FFFFL
19640 //CP_CE_IB1_BUFSZ
19641 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                     0x0
19642 #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                       0x000FFFFFL
19643 //CP_CE_IB2_BASE_LO
19644 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                 0x2
19645 #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                   0xFFFFFFFCL
19646 //CP_CE_IB2_BASE_HI
19647 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                 0x0
19648 #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                   0x0000FFFFL
19649 //CP_CE_IB2_BUFSZ
19650 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                     0x0
19651 #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                       0x000FFFFFL
19652 //CP_IB1_BASE_LO
19653 #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT                                                                    0x2
19654 #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK                                                                      0xFFFFFFFCL
19655 //CP_IB1_BASE_HI
19656 #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT                                                                    0x0
19657 #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK                                                                      0x0000FFFFL
19658 //CP_IB1_BUFSZ
19659 #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT                                                                        0x0
19660 #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK                                                                          0x000FFFFFL
19661 //CP_IB2_BASE_LO
19662 #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT                                                                    0x2
19663 #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK                                                                      0xFFFFFFFCL
19664 //CP_IB2_BASE_HI
19665 #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT                                                                    0x0
19666 #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK                                                                      0x0000FFFFL
19667 //CP_IB2_BUFSZ
19668 #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT                                                                        0x0
19669 #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK                                                                          0x000FFFFFL
19670 //CP_ST_BASE_LO
19671 #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT                                                                      0x2
19672 #define CP_ST_BASE_LO__ST_BASE_LO_MASK                                                                        0xFFFFFFFCL
19673 //CP_ST_BASE_HI
19674 #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT                                                                      0x0
19675 #define CP_ST_BASE_HI__ST_BASE_HI_MASK                                                                        0x0000FFFFL
19676 //CP_ST_BUFSZ
19677 #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT                                                                          0x0
19678 #define CP_ST_BUFSZ__ST_BUFSZ_MASK                                                                            0x000FFFFFL
19679 //CP_EOP_DONE_EVENT_CNTL
19680 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT                                                            0x0
19681 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT                                                       0xc
19682 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT                                                           0x19
19683 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT                                                                0x1c
19684 #define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK                                                              0x0000007FL
19685 #define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK                                                         0x0003F000L
19686 #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK                                                             0x02000000L
19687 #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK                                                                  0x10000000L
19688 //CP_EOP_DONE_DATA_CNTL
19689 #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT                                                                 0x10
19690 #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT                                                                 0x18
19691 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT                                                                0x1d
19692 #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK                                                                   0x00030000L
19693 #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK                                                                   0x07000000L
19694 #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK                                                                  0xE0000000L
19695 //CP_EOP_DONE_CNTX_ID
19696 #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT                                                                   0x0
19697 #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK                                                                     0xFFFFFFFFL
19698 //CP_PFP_COMPLETION_STATUS
19699 #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT                                                               0x0
19700 #define CP_PFP_COMPLETION_STATUS__STATUS_MASK                                                                 0x00000003L
19701 //CP_CE_COMPLETION_STATUS
19702 #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT                                                                0x0
19703 #define CP_CE_COMPLETION_STATUS__STATUS_MASK                                                                  0x00000003L
19704 //CP_PRED_NOT_VISIBLE
19705 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT                                                               0x0
19706 #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK                                                                 0x00000001L
19707 //CP_PFP_METADATA_BASE_ADDR
19708 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                             0x0
19709 #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK                                                               0xFFFFFFFFL
19710 //CP_PFP_METADATA_BASE_ADDR_HI
19711 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                          0x0
19712 #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                            0x0000FFFFL
19713 //CP_CE_METADATA_BASE_ADDR
19714 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT                                                              0x0
19715 #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK                                                                0xFFFFFFFFL
19716 //CP_CE_METADATA_BASE_ADDR_HI
19717 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT                                                           0x0
19718 #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK                                                             0x0000FFFFL
19719 //CP_DRAW_INDX_INDR_ADDR
19720 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT                                                                0x0
19721 #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK                                                                  0xFFFFFFFFL
19722 //CP_DRAW_INDX_INDR_ADDR_HI
19723 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT                                                             0x0
19724 #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK                                                               0x0000FFFFL
19725 //CP_DISPATCH_INDR_ADDR
19726 #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT                                                                 0x0
19727 #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK                                                                   0xFFFFFFFFL
19728 //CP_DISPATCH_INDR_ADDR_HI
19729 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT                                                              0x0
19730 #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK                                                                0x0000FFFFL
19731 //CP_INDEX_BASE_ADDR
19732 #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT                                                                    0x0
19733 #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK                                                                      0xFFFFFFFFL
19734 //CP_INDEX_BASE_ADDR_HI
19735 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT                                                                 0x0
19736 #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK                                                                   0x0000FFFFL
19737 //CP_INDEX_TYPE
19738 #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                      0x0
19739 #define CP_INDEX_TYPE__INDEX_TYPE_MASK                                                                        0x00000003L
19740 //CP_GDS_BKUP_ADDR
19741 #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT                                                                      0x0
19742 #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK                                                                        0xFFFFFFFFL
19743 //CP_GDS_BKUP_ADDR_HI
19744 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT                                                                   0x0
19745 #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK                                                                     0x0000FFFFL
19746 //CP_SAMPLE_STATUS
19747 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT                                                                0x0
19748 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT                                                             0x1
19749 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT                                                              0x2
19750 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT                                                               0x3
19751 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT                                                           0x4
19752 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT                                                            0x5
19753 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT                                                         0x6
19754 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT                                                         0x7
19755 #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK                                                                  0x00000001L
19756 #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK                                                               0x00000002L
19757 #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK                                                                0x00000004L
19758 #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK                                                                 0x00000008L
19759 #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK                                                             0x00000010L
19760 #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK                                                              0x00000020L
19761 #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK                                                           0x00000040L
19762 #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK                                                           0x00000080L
19763 //CP_ME_COHER_CNTL
19764 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT                                                              0x0
19765 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT                                                              0x1
19766 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT                                                            0x6
19767 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT                                                            0x7
19768 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT                                                            0x8
19769 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT                                                            0x9
19770 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT                                                            0xa
19771 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT                                                            0xb
19772 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT                                                            0xc
19773 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT                                                            0xd
19774 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT                                                             0xe
19775 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT                                                              0x13
19776 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT                                                              0x15
19777 #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK                                                                0x00000001L
19778 #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK                                                                0x00000002L
19779 #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK                                                              0x00000040L
19780 #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK                                                              0x00000080L
19781 #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK                                                              0x00000100L
19782 #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK                                                              0x00000200L
19783 #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK                                                              0x00000400L
19784 #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK                                                              0x00000800L
19785 #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK                                                              0x00001000L
19786 #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK                                                              0x00002000L
19787 #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK                                                               0x00004000L
19788 #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK                                                                0x00080000L
19789 #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK                                                                0x00200000L
19790 //CP_ME_COHER_SIZE
19791 #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT                                                              0x0
19792 #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK                                                                0xFFFFFFFFL
19793 //CP_ME_COHER_SIZE_HI
19794 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT                                                        0x0
19795 #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK                                                          0x000000FFL
19796 //CP_ME_COHER_BASE
19797 #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT                                                              0x0
19798 #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK                                                                0xFFFFFFFFL
19799 //CP_ME_COHER_BASE_HI
19800 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT                                                        0x0
19801 #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK                                                          0x000000FFL
19802 //CP_ME_COHER_STATUS
19803 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT                                                          0x0
19804 #define CP_ME_COHER_STATUS__STATUS__SHIFT                                                                     0x1f
19805 #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK                                                            0x000000FFL
19806 #define CP_ME_COHER_STATUS__STATUS_MASK                                                                       0x80000000L
19807 //RLC_GPM_PERF_COUNT_0
19808 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT                                                              0x0
19809 #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT                                                                 0x4
19810 #define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT                                                                 0x8
19811 #define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT                                                                 0xc
19812 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT                                                                0x10
19813 #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT                                                                   0x12
19814 #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT                                                                   0x14
19815 #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT                                                                 0x15
19816 #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK                                                                0x0000000FL
19817 #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK                                                                   0x000000F0L
19818 #define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK                                                                   0x00000F00L
19819 #define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK                                                                   0x0000F000L
19820 #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK                                                                  0x00030000L
19821 #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK                                                                     0x000C0000L
19822 #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK                                                                     0x00100000L
19823 #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK                                                                   0xFFE00000L
19824 //RLC_GPM_PERF_COUNT_1
19825 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT                                                              0x0
19826 #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT                                                                 0x4
19827 #define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT                                                                 0x8
19828 #define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT                                                                 0xc
19829 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT                                                                0x10
19830 #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT                                                                   0x12
19831 #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT                                                                   0x14
19832 #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT                                                                 0x15
19833 #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK                                                                0x0000000FL
19834 #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK                                                                   0x000000F0L
19835 #define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK                                                                   0x00000F00L
19836 #define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK                                                                   0x0000F000L
19837 #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK                                                                  0x00030000L
19838 #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK                                                                     0x000C0000L
19839 #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK                                                                     0x00100000L
19840 #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK                                                                   0xFFE00000L
19841 //GRBM_GFX_INDEX
19842 #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT                                                                 0x0
19843 #define GRBM_GFX_INDEX__SH_INDEX__SHIFT                                                                       0x8
19844 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT                                                                       0x10
19845 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT                                                            0x1d
19846 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT                                                      0x1e
19847 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT                                                            0x1f
19848 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK                                                                   0x000000FFL
19849 #define GRBM_GFX_INDEX__SH_INDEX_MASK                                                                         0x0000FF00L
19850 #define GRBM_GFX_INDEX__SE_INDEX_MASK                                                                         0x00FF0000L
19851 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK                                                              0x20000000L
19852 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK                                                        0x40000000L
19853 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK                                                              0x80000000L
19854 //VGT_GSVS_RING_SIZE
19855 #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT                                                                   0x0
19856 #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK                                                                     0xFFFFFFFFL
19857 //VGT_PRIMITIVE_TYPE
19858 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT                                                                  0x0
19859 #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK                                                                    0x0000003FL
19860 //VGT_INDEX_TYPE
19861 #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT                                                                     0x0
19862 #define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT                                                                     0x8
19863 #define VGT_INDEX_TYPE__INDEX_TYPE_MASK                                                                       0x00000003L
19864 #define VGT_INDEX_TYPE__PRIMGEN_EN_MASK                                                                       0x00000100L
19865 //VGT_STRMOUT_BUFFER_FILLED_SIZE_0
19866 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT                                                         0x0
19867 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK                                                           0xFFFFFFFFL
19868 //VGT_STRMOUT_BUFFER_FILLED_SIZE_1
19869 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT                                                         0x0
19870 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK                                                           0xFFFFFFFFL
19871 //VGT_STRMOUT_BUFFER_FILLED_SIZE_2
19872 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT                                                         0x0
19873 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK                                                           0xFFFFFFFFL
19874 //VGT_STRMOUT_BUFFER_FILLED_SIZE_3
19875 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT                                                         0x0
19876 #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK                                                           0xFFFFFFFFL
19877 //VGT_MAX_VTX_INDX
19878 #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT                                                                     0x0
19879 #define VGT_MAX_VTX_INDX__MAX_INDX_MASK                                                                       0xFFFFFFFFL
19880 //VGT_MIN_VTX_INDX
19881 #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT                                                                     0x0
19882 #define VGT_MIN_VTX_INDX__MIN_INDX_MASK                                                                       0xFFFFFFFFL
19883 //VGT_INDX_OFFSET
19884 #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT                                                                   0x0
19885 #define VGT_INDX_OFFSET__INDX_OFFSET_MASK                                                                     0xFFFFFFFFL
19886 //VGT_MULTI_PRIM_IB_RESET_EN
19887 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT                                                           0x0
19888 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT                                                     0x1
19889 #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK                                                             0x00000001L
19890 #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK                                                       0x00000002L
19891 //VGT_NUM_INDICES
19892 #define VGT_NUM_INDICES__NUM_INDICES__SHIFT                                                                   0x0
19893 #define VGT_NUM_INDICES__NUM_INDICES_MASK                                                                     0xFFFFFFFFL
19894 //VGT_NUM_INSTANCES
19895 #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT                                                               0x0
19896 #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK                                                                 0xFFFFFFFFL
19897 //VGT_TF_RING_SIZE
19898 #define VGT_TF_RING_SIZE__SIZE__SHIFT                                                                         0x0
19899 #define VGT_TF_RING_SIZE__SIZE_MASK                                                                           0x0000FFFFL
19900 //VGT_HS_OFFCHIP_PARAM
19901 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT                                                        0x0
19902 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT                                                      0x9
19903 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK                                                          0x000001FFL
19904 #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK                                                        0x00000600L
19905 //VGT_TF_MEMORY_BASE
19906 #define VGT_TF_MEMORY_BASE__BASE__SHIFT                                                                       0x0
19907 #define VGT_TF_MEMORY_BASE__BASE_MASK                                                                         0xFFFFFFFFL
19908 //VGT_TF_MEMORY_BASE_HI
19909 #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT                                                                 0x0
19910 #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK                                                                   0x000000FFL
19911 //WD_POS_BUF_BASE
19912 #define WD_POS_BUF_BASE__BASE__SHIFT                                                                          0x0
19913 #define WD_POS_BUF_BASE__BASE_MASK                                                                            0xFFFFFFFFL
19914 //WD_POS_BUF_BASE_HI
19915 #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT                                                                    0x0
19916 #define WD_POS_BUF_BASE_HI__BASE_HI_MASK                                                                      0x000000FFL
19917 //WD_CNTL_SB_BUF_BASE
19918 #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT                                                                      0x0
19919 #define WD_CNTL_SB_BUF_BASE__BASE_MASK                                                                        0xFFFFFFFFL
19920 //WD_CNTL_SB_BUF_BASE_HI
19921 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT                                                                0x0
19922 #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK                                                                  0x000000FFL
19923 //WD_INDEX_BUF_BASE
19924 #define WD_INDEX_BUF_BASE__BASE__SHIFT                                                                        0x0
19925 #define WD_INDEX_BUF_BASE__BASE_MASK                                                                          0xFFFFFFFFL
19926 //WD_INDEX_BUF_BASE_HI
19927 #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT                                                                  0x0
19928 #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK                                                                    0x000000FFL
19929 //IA_MULTI_VGT_PARAM
19930 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT                                                             0x0
19931 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT                                                         0x10
19932 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT                                                              0x11
19933 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT                                                         0x12
19934 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT                                                              0x13
19935 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT                                                           0x14
19936 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT                                                          0x15
19937 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT                                                            0x16
19938 #define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT                                                                0x17
19939 #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK                                                               0x0000FFFFL
19940 #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK                                                           0x00010000L
19941 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK                                                                0x00020000L
19942 #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK                                                           0x00040000L
19943 #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK                                                                0x00080000L
19944 #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK                                                             0x00100000L
19945 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK                                                            0x00200000L
19946 #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK                                                              0x00400000L
19947 #define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK                                                                  0x00800000L
19948 //VGT_INSTANCE_BASE_ID
19949 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT                                                         0x0
19950 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK                                                           0xFFFFFFFFL
19951 //PA_SU_LINE_STIPPLE_VALUE
19952 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT                                                   0x0
19953 #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK                                                     0x00FFFFFFL
19954 //PA_SC_LINE_STIPPLE_STATE
19955 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT                                                          0x0
19956 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT                                                        0x8
19957 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK                                                            0x0000000FL
19958 #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK                                                          0x0000FF00L
19959 //PA_SC_SCREEN_EXTENT_MIN_0
19960 #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT                                                                   0x0
19961 #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT                                                                   0x10
19962 #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK                                                                     0x0000FFFFL
19963 #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK                                                                     0xFFFF0000L
19964 //PA_SC_SCREEN_EXTENT_MAX_0
19965 #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT                                                                   0x0
19966 #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT                                                                   0x10
19967 #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK                                                                     0x0000FFFFL
19968 #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK                                                                     0xFFFF0000L
19969 //PA_SC_SCREEN_EXTENT_MIN_1
19970 #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT                                                                   0x0
19971 #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT                                                                   0x10
19972 #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK                                                                     0x0000FFFFL
19973 #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK                                                                     0xFFFF0000L
19974 //PA_SC_SCREEN_EXTENT_MAX_1
19975 #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT                                                                   0x0
19976 #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT                                                                   0x10
19977 #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK                                                                     0x0000FFFFL
19978 #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK                                                                     0xFFFF0000L
19979 //PA_SC_P3D_TRAP_SCREEN_HV_EN
19980 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                              0x0
19981 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                       0x1
19982 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                0x00000001L
19983 #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                         0x00000002L
19984 //PA_SC_P3D_TRAP_SCREEN_H
19985 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                               0x0
19986 #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK                                                                 0x00003FFFL
19987 //PA_SC_P3D_TRAP_SCREEN_V
19988 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                               0x0
19989 #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                 0x00003FFFL
19990 //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE
19991 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                        0x0
19992 #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                          0x0000FFFFL
19993 //PA_SC_P3D_TRAP_SCREEN_COUNT
19994 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                             0x0
19995 #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                               0x0000FFFFL
19996 //PA_SC_HP3D_TRAP_SCREEN_HV_EN
19997 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                             0x0
19998 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                      0x1
19999 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                               0x00000001L
20000 #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                        0x00000002L
20001 //PA_SC_HP3D_TRAP_SCREEN_H
20002 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT                                                              0x0
20003 #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK                                                                0x00003FFFL
20004 //PA_SC_HP3D_TRAP_SCREEN_V
20005 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT                                                              0x0
20006 #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK                                                                0x00003FFFL
20007 //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE
20008 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                       0x0
20009 #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                         0x0000FFFFL
20010 //PA_SC_HP3D_TRAP_SCREEN_COUNT
20011 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                            0x0
20012 #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK                                                              0x0000FFFFL
20013 //PA_SC_TRAP_SCREEN_HV_EN
20014 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT                                                  0x0
20015 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT                                           0x1
20016 #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK                                                    0x00000001L
20017 #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK                                             0x00000002L
20018 //PA_SC_TRAP_SCREEN_H
20019 #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT                                                                   0x0
20020 #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK                                                                     0x00003FFFL
20021 //PA_SC_TRAP_SCREEN_V
20022 #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT                                                                   0x0
20023 #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK                                                                     0x00003FFFL
20024 //PA_SC_TRAP_SCREEN_OCCURRENCE
20025 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT                                                            0x0
20026 #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK                                                              0x0000FFFFL
20027 //PA_SC_TRAP_SCREEN_COUNT
20028 #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT                                                                 0x0
20029 #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK                                                                   0x0000FFFFL
20030 //SQ_THREAD_TRACE_BASE
20031 #define SQ_THREAD_TRACE_BASE__ADDR__SHIFT                                                                     0x0
20032 #define SQ_THREAD_TRACE_BASE__ADDR_MASK                                                                       0xFFFFFFFFL
20033 //SQ_THREAD_TRACE_SIZE
20034 #define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT                                                                     0x0
20035 #define SQ_THREAD_TRACE_SIZE__SIZE_MASK                                                                       0x003FFFFFL
20036 //SQ_THREAD_TRACE_MASK
20037 #define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT                                                                   0x0
20038 #define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT                                                                   0x5
20039 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT                                                             0x7
20040 #define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT                                                                  0x8
20041 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT                                                               0xc
20042 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT                                                             0xe
20043 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT                                                              0xf
20044 #define SQ_THREAD_TRACE_MASK__CU_SEL_MASK                                                                     0x0000001FL
20045 #define SQ_THREAD_TRACE_MASK__SH_SEL_MASK                                                                     0x00000020L
20046 #define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK                                                               0x00000080L
20047 #define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK                                                                    0x00000F00L
20048 #define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK                                                                 0x00003000L
20049 #define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK                                                               0x00004000L
20050 #define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK                                                                0x00008000L
20051 //SQ_THREAD_TRACE_TOKEN_MASK
20052 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT                                                         0x0
20053 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT                                                           0x10
20054 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT                                                  0x18
20055 #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK                                                           0x0000FFFFL
20056 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK                                                             0x00FF0000L
20057 #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK                                                    0x01000000L
20058 //SQ_THREAD_TRACE_PERF_MASK
20059 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT                                                            0x0
20060 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT                                                            0x10
20061 #define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK                                                              0x0000FFFFL
20062 #define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK                                                              0xFFFF0000L
20063 //SQ_THREAD_TRACE_CTRL
20064 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT                                                             0x1f
20065 #define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK                                                               0x80000000L
20066 //SQ_THREAD_TRACE_MODE
20067 #define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT                                                                  0x0
20068 #define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT                                                                  0x3
20069 #define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT                                                                  0x6
20070 #define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT                                                                  0x9
20071 #define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT                                                                  0xc
20072 #define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT                                                                  0xf
20073 #define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT                                                                  0x12
20074 #define SQ_THREAD_TRACE_MODE__MODE__SHIFT                                                                     0x15
20075 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT                                                             0x17
20076 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT                                                             0x19
20077 #define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT                                                               0x1a
20078 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT                                                               0x1b
20079 #define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT                                                                0x1d
20080 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT                                                             0x1e
20081 #define SQ_THREAD_TRACE_MODE__WRAP__SHIFT                                                                     0x1f
20082 #define SQ_THREAD_TRACE_MODE__MASK_PS_MASK                                                                    0x00000007L
20083 #define SQ_THREAD_TRACE_MODE__MASK_VS_MASK                                                                    0x00000038L
20084 #define SQ_THREAD_TRACE_MODE__MASK_GS_MASK                                                                    0x000001C0L
20085 #define SQ_THREAD_TRACE_MODE__MASK_ES_MASK                                                                    0x00000E00L
20086 #define SQ_THREAD_TRACE_MODE__MASK_HS_MASK                                                                    0x00007000L
20087 #define SQ_THREAD_TRACE_MODE__MASK_LS_MASK                                                                    0x00038000L
20088 #define SQ_THREAD_TRACE_MODE__MASK_CS_MASK                                                                    0x001C0000L
20089 #define SQ_THREAD_TRACE_MODE__MODE_MASK                                                                       0x00600000L
20090 #define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK                                                               0x01800000L
20091 #define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK                                                               0x02000000L
20092 #define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK                                                                 0x04000000L
20093 #define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK                                                                 0x18000000L
20094 #define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK                                                                  0x20000000L
20095 #define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK                                                               0x40000000L
20096 #define SQ_THREAD_TRACE_MODE__WRAP_MASK                                                                       0x80000000L
20097 //SQ_THREAD_TRACE_BASE2
20098 #define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT                                                                 0x0
20099 #define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK                                                                   0x0000000FL
20100 //SQ_THREAD_TRACE_TOKEN_MASK2
20101 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT                                                         0x0
20102 #define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK                                                           0xFFFFFFFFL
20103 //SQ_THREAD_TRACE_WPTR
20104 #define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT                                                                     0x0
20105 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT                                                              0x1e
20106 #define SQ_THREAD_TRACE_WPTR__WPTR_MASK                                                                       0x3FFFFFFFL
20107 #define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK                                                                0xC0000000L
20108 //SQ_THREAD_TRACE_STATUS
20109 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT                                                         0x0
20110 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT                                                            0x10
20111 #define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT                                                              0x1c
20112 #define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT                                                                0x1d
20113 #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT                                                                   0x1e
20114 #define SQ_THREAD_TRACE_STATUS__FULL__SHIFT                                                                   0x1f
20115 #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK                                                           0x000003FFL
20116 #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK                                                              0x03FF0000L
20117 #define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK                                                                0x10000000L
20118 #define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK                                                                  0x20000000L
20119 #define SQ_THREAD_TRACE_STATUS__BUSY_MASK                                                                     0x40000000L
20120 #define SQ_THREAD_TRACE_STATUS__FULL_MASK                                                                     0x80000000L
20121 //SQ_THREAD_TRACE_HIWATER
20122 #define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT                                                               0x0
20123 #define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK                                                                 0x00000007L
20124 //SQ_THREAD_TRACE_CNTR
20125 #define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT                                                                     0x0
20126 #define SQ_THREAD_TRACE_CNTR__CNTR_MASK                                                                       0xFFFFFFFFL
20127 //SQ_THREAD_TRACE_USERDATA_0
20128 #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT                                                               0x0
20129 #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK                                                                 0xFFFFFFFFL
20130 //SQ_THREAD_TRACE_USERDATA_1
20131 #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT                                                               0x0
20132 #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK                                                                 0xFFFFFFFFL
20133 //SQ_THREAD_TRACE_USERDATA_2
20134 #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT                                                               0x0
20135 #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK                                                                 0xFFFFFFFFL
20136 //SQ_THREAD_TRACE_USERDATA_3
20137 #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT                                                               0x0
20138 #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK                                                                 0xFFFFFFFFL
20139 //SQC_CACHES
20140 #define SQC_CACHES__TARGET_INST__SHIFT                                                                        0x0
20141 #define SQC_CACHES__TARGET_DATA__SHIFT                                                                        0x1
20142 #define SQC_CACHES__INVALIDATE__SHIFT                                                                         0x2
20143 #define SQC_CACHES__WRITEBACK__SHIFT                                                                          0x3
20144 #define SQC_CACHES__VOL__SHIFT                                                                                0x4
20145 #define SQC_CACHES__COMPLETE__SHIFT                                                                           0x10
20146 #define SQC_CACHES__TARGET_INST_MASK                                                                          0x00000001L
20147 #define SQC_CACHES__TARGET_DATA_MASK                                                                          0x00000002L
20148 #define SQC_CACHES__INVALIDATE_MASK                                                                           0x00000004L
20149 #define SQC_CACHES__WRITEBACK_MASK                                                                            0x00000008L
20150 #define SQC_CACHES__VOL_MASK                                                                                  0x00000010L
20151 #define SQC_CACHES__COMPLETE_MASK                                                                             0x00010000L
20152 //SQC_WRITEBACK
20153 #define SQC_WRITEBACK__DWB__SHIFT                                                                             0x0
20154 #define SQC_WRITEBACK__DIRTY__SHIFT                                                                           0x1
20155 #define SQC_WRITEBACK__DWB_MASK                                                                               0x00000001L
20156 #define SQC_WRITEBACK__DIRTY_MASK                                                                             0x00000002L
20157 //TA_CS_BC_BASE_ADDR
20158 #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT                                                                    0x0
20159 #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK                                                                      0xFFFFFFFFL
20160 //TA_CS_BC_BASE_ADDR_HI
20161 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT                                                                 0x0
20162 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK                                                                   0x000000FFL
20163 //DB_OCCLUSION_COUNT0_LOW
20164 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT                                                             0x0
20165 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20166 //DB_OCCLUSION_COUNT0_HI
20167 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT                                                               0x0
20168 #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20169 //DB_OCCLUSION_COUNT1_LOW
20170 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT                                                             0x0
20171 #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20172 //DB_OCCLUSION_COUNT1_HI
20173 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT                                                               0x0
20174 #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20175 //DB_OCCLUSION_COUNT2_LOW
20176 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT                                                             0x0
20177 #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20178 //DB_OCCLUSION_COUNT2_HI
20179 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT                                                               0x0
20180 #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20181 //DB_OCCLUSION_COUNT3_LOW
20182 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT                                                             0x0
20183 #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK                                                               0xFFFFFFFFL
20184 //DB_OCCLUSION_COUNT3_HI
20185 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT                                                               0x0
20186 #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK                                                                 0x7FFFFFFFL
20187 //DB_ZPASS_COUNT_LOW
20188 #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT                                                                  0x0
20189 #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK                                                                    0xFFFFFFFFL
20190 //DB_ZPASS_COUNT_HI
20191 #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT                                                                    0x0
20192 #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK                                                                      0x7FFFFFFFL
20193 //GDS_RD_ADDR
20194 #define GDS_RD_ADDR__READ_ADDR__SHIFT                                                                         0x0
20195 #define GDS_RD_ADDR__READ_ADDR_MASK                                                                           0xFFFFFFFFL
20196 //GDS_RD_DATA
20197 #define GDS_RD_DATA__READ_DATA__SHIFT                                                                         0x0
20198 #define GDS_RD_DATA__READ_DATA_MASK                                                                           0xFFFFFFFFL
20199 //GDS_RD_BURST_ADDR
20200 #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT                                                                  0x0
20201 #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK                                                                    0xFFFFFFFFL
20202 //GDS_RD_BURST_COUNT
20203 #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT                                                                0x0
20204 #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK                                                                  0xFFFFFFFFL
20205 //GDS_RD_BURST_DATA
20206 #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT                                                                  0x0
20207 #define GDS_RD_BURST_DATA__BURST_DATA_MASK                                                                    0xFFFFFFFFL
20208 //GDS_WR_ADDR
20209 #define GDS_WR_ADDR__WRITE_ADDR__SHIFT                                                                        0x0
20210 #define GDS_WR_ADDR__WRITE_ADDR_MASK                                                                          0xFFFFFFFFL
20211 //GDS_WR_DATA
20212 #define GDS_WR_DATA__WRITE_DATA__SHIFT                                                                        0x0
20213 #define GDS_WR_DATA__WRITE_DATA_MASK                                                                          0xFFFFFFFFL
20214 //GDS_WR_BURST_ADDR
20215 #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT                                                                  0x0
20216 #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK                                                                    0xFFFFFFFFL
20217 //GDS_WR_BURST_DATA
20218 #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT                                                                  0x0
20219 #define GDS_WR_BURST_DATA__WRITE_DATA_MASK                                                                    0xFFFFFFFFL
20220 //GDS_WRITE_COMPLETE
20221 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT                                                             0x0
20222 #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK                                                               0xFFFFFFFFL
20223 //GDS_ATOM_CNTL
20224 #define GDS_ATOM_CNTL__AINC__SHIFT                                                                            0x0
20225 #define GDS_ATOM_CNTL__UNUSED1__SHIFT                                                                         0x6
20226 #define GDS_ATOM_CNTL__DMODE__SHIFT                                                                           0x8
20227 #define GDS_ATOM_CNTL__UNUSED2__SHIFT                                                                         0xa
20228 #define GDS_ATOM_CNTL__AINC_MASK                                                                              0x0000003FL
20229 #define GDS_ATOM_CNTL__UNUSED1_MASK                                                                           0x000000C0L
20230 #define GDS_ATOM_CNTL__DMODE_MASK                                                                             0x00000300L
20231 #define GDS_ATOM_CNTL__UNUSED2_MASK                                                                           0xFFFFFC00L
20232 //GDS_ATOM_COMPLETE
20233 #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT                                                                    0x0
20234 #define GDS_ATOM_COMPLETE__UNUSED__SHIFT                                                                      0x1
20235 #define GDS_ATOM_COMPLETE__COMPLETE_MASK                                                                      0x00000001L
20236 #define GDS_ATOM_COMPLETE__UNUSED_MASK                                                                        0xFFFFFFFEL
20237 //GDS_ATOM_BASE
20238 #define GDS_ATOM_BASE__BASE__SHIFT                                                                            0x0
20239 #define GDS_ATOM_BASE__UNUSED__SHIFT                                                                          0x10
20240 #define GDS_ATOM_BASE__BASE_MASK                                                                              0x0000FFFFL
20241 #define GDS_ATOM_BASE__UNUSED_MASK                                                                            0xFFFF0000L
20242 //GDS_ATOM_SIZE
20243 #define GDS_ATOM_SIZE__SIZE__SHIFT                                                                            0x0
20244 #define GDS_ATOM_SIZE__UNUSED__SHIFT                                                                          0x10
20245 #define GDS_ATOM_SIZE__SIZE_MASK                                                                              0x0000FFFFL
20246 #define GDS_ATOM_SIZE__UNUSED_MASK                                                                            0xFFFF0000L
20247 //GDS_ATOM_OFFSET0
20248 #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT                                                                      0x0
20249 #define GDS_ATOM_OFFSET0__UNUSED__SHIFT                                                                       0x8
20250 #define GDS_ATOM_OFFSET0__OFFSET0_MASK                                                                        0x000000FFL
20251 #define GDS_ATOM_OFFSET0__UNUSED_MASK                                                                         0xFFFFFF00L
20252 //GDS_ATOM_OFFSET1
20253 #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT                                                                      0x0
20254 #define GDS_ATOM_OFFSET1__UNUSED__SHIFT                                                                       0x8
20255 #define GDS_ATOM_OFFSET1__OFFSET1_MASK                                                                        0x000000FFL
20256 #define GDS_ATOM_OFFSET1__UNUSED_MASK                                                                         0xFFFFFF00L
20257 //GDS_ATOM_DST
20258 #define GDS_ATOM_DST__DST__SHIFT                                                                              0x0
20259 #define GDS_ATOM_DST__DST_MASK                                                                                0xFFFFFFFFL
20260 //GDS_ATOM_OP
20261 #define GDS_ATOM_OP__OP__SHIFT                                                                                0x0
20262 #define GDS_ATOM_OP__UNUSED__SHIFT                                                                            0x8
20263 #define GDS_ATOM_OP__OP_MASK                                                                                  0x000000FFL
20264 #define GDS_ATOM_OP__UNUSED_MASK                                                                              0xFFFFFF00L
20265 //GDS_ATOM_SRC0
20266 #define GDS_ATOM_SRC0__DATA__SHIFT                                                                            0x0
20267 #define GDS_ATOM_SRC0__DATA_MASK                                                                              0xFFFFFFFFL
20268 //GDS_ATOM_SRC0_U
20269 #define GDS_ATOM_SRC0_U__DATA__SHIFT                                                                          0x0
20270 #define GDS_ATOM_SRC0_U__DATA_MASK                                                                            0xFFFFFFFFL
20271 //GDS_ATOM_SRC1
20272 #define GDS_ATOM_SRC1__DATA__SHIFT                                                                            0x0
20273 #define GDS_ATOM_SRC1__DATA_MASK                                                                              0xFFFFFFFFL
20274 //GDS_ATOM_SRC1_U
20275 #define GDS_ATOM_SRC1_U__DATA__SHIFT                                                                          0x0
20276 #define GDS_ATOM_SRC1_U__DATA_MASK                                                                            0xFFFFFFFFL
20277 //GDS_ATOM_READ0
20278 #define GDS_ATOM_READ0__DATA__SHIFT                                                                           0x0
20279 #define GDS_ATOM_READ0__DATA_MASK                                                                             0xFFFFFFFFL
20280 //GDS_ATOM_READ0_U
20281 #define GDS_ATOM_READ0_U__DATA__SHIFT                                                                         0x0
20282 #define GDS_ATOM_READ0_U__DATA_MASK                                                                           0xFFFFFFFFL
20283 //GDS_ATOM_READ1
20284 #define GDS_ATOM_READ1__DATA__SHIFT                                                                           0x0
20285 #define GDS_ATOM_READ1__DATA_MASK                                                                             0xFFFFFFFFL
20286 //GDS_ATOM_READ1_U
20287 #define GDS_ATOM_READ1_U__DATA__SHIFT                                                                         0x0
20288 #define GDS_ATOM_READ1_U__DATA_MASK                                                                           0xFFFFFFFFL
20289 //GDS_GWS_RESOURCE_CNTL
20290 #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT                                                                   0x0
20291 #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT                                                                  0x6
20292 #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK                                                                     0x0000003FL
20293 #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK                                                                    0xFFFFFFC0L
20294 //GDS_GWS_RESOURCE
20295 #define GDS_GWS_RESOURCE__FLAG__SHIFT                                                                         0x0
20296 #define GDS_GWS_RESOURCE__COUNTER__SHIFT                                                                      0x1
20297 #define GDS_GWS_RESOURCE__TYPE__SHIFT                                                                         0xd
20298 #define GDS_GWS_RESOURCE__DED__SHIFT                                                                          0xe
20299 #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT                                                                  0xf
20300 #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT                                                                   0x10
20301 #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT                                                                   0x1c
20302 #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT                                                                    0x1d
20303 #define GDS_GWS_RESOURCE__HALTED__SHIFT                                                                       0x1e
20304 #define GDS_GWS_RESOURCE__UNUSED1__SHIFT                                                                      0x1f
20305 #define GDS_GWS_RESOURCE__FLAG_MASK                                                                           0x00000001L
20306 #define GDS_GWS_RESOURCE__COUNTER_MASK                                                                        0x00001FFEL
20307 #define GDS_GWS_RESOURCE__TYPE_MASK                                                                           0x00002000L
20308 #define GDS_GWS_RESOURCE__DED_MASK                                                                            0x00004000L
20309 #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK                                                                    0x00008000L
20310 #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK                                                                     0x0FFF0000L
20311 #define GDS_GWS_RESOURCE__HEAD_VALID_MASK                                                                     0x10000000L
20312 #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK                                                                      0x20000000L
20313 #define GDS_GWS_RESOURCE__HALTED_MASK                                                                         0x40000000L
20314 #define GDS_GWS_RESOURCE__UNUSED1_MASK                                                                        0x80000000L
20315 //GDS_GWS_RESOURCE_CNT
20316 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT                                                             0x0
20317 #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT                                                                   0x10
20318 #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK                                                               0x0000FFFFL
20319 #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK                                                                     0xFFFF0000L
20320 //GDS_OA_CNTL
20321 #define GDS_OA_CNTL__INDEX__SHIFT                                                                             0x0
20322 #define GDS_OA_CNTL__UNUSED__SHIFT                                                                            0x4
20323 #define GDS_OA_CNTL__INDEX_MASK                                                                               0x0000000FL
20324 #define GDS_OA_CNTL__UNUSED_MASK                                                                              0xFFFFFFF0L
20325 //GDS_OA_COUNTER
20326 #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT                                                                0x0
20327 #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK                                                                  0xFFFFFFFFL
20328 //GDS_OA_ADDRESS
20329 #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT                                                                     0x0
20330 #define GDS_OA_ADDRESS__CRAWLER__SHIFT                                                                        0x10
20331 #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT                                                                   0x14
20332 #define GDS_OA_ADDRESS__UNUSED__SHIFT                                                                         0x16
20333 #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT                                                                       0x1e
20334 #define GDS_OA_ADDRESS__ENABLE__SHIFT                                                                         0x1f
20335 #define GDS_OA_ADDRESS__DS_ADDRESS_MASK                                                                       0x0000FFFFL
20336 #define GDS_OA_ADDRESS__CRAWLER_MASK                                                                          0x000F0000L
20337 #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK                                                                     0x00300000L
20338 #define GDS_OA_ADDRESS__UNUSED_MASK                                                                           0x3FC00000L
20339 #define GDS_OA_ADDRESS__NO_ALLOC_MASK                                                                         0x40000000L
20340 #define GDS_OA_ADDRESS__ENABLE_MASK                                                                           0x80000000L
20341 //GDS_OA_INCDEC
20342 #define GDS_OA_INCDEC__VALUE__SHIFT                                                                           0x0
20343 #define GDS_OA_INCDEC__INCDEC__SHIFT                                                                          0x1f
20344 #define GDS_OA_INCDEC__VALUE_MASK                                                                             0x7FFFFFFFL
20345 #define GDS_OA_INCDEC__INCDEC_MASK                                                                            0x80000000L
20346 //GDS_OA_RING_SIZE
20347 #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT                                                                    0x0
20348 #define GDS_OA_RING_SIZE__RING_SIZE_MASK                                                                      0xFFFFFFFFL
20349 //SPI_CONFIG_CNTL
20350 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT                                                            0x0
20351 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT                                                            0x15
20352 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT                                                         0x18
20353 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT                                                         0x19
20354 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT                                                               0x1a
20355 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT                                                              0x1b
20356 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT                                                             0x1c
20357 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT                                                               0x1d
20358 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT                                                          0x1e
20359 #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK                                                              0x001FFFFFL
20360 #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK                                                              0x00E00000L
20361 #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK                                                           0x01000000L
20362 #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK                                                           0x02000000L
20363 #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK                                                                 0x04000000L
20364 #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK                                                                0x08000000L
20365 #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK                                                               0x10000000L
20366 #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK                                                                 0x20000000L
20367 #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK                                                            0xC0000000L
20368 //SPI_CONFIG_CNTL_1
20369 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT                                                              0x0
20370 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT                                                     0x4
20371 #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT                                                         0x5
20372 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT                                                             0x6
20373 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT                                                             0x7
20374 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT                                                   0x8
20375 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT                                                            0x9
20376 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT                                                             0xa
20377 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT                                                        0xe
20378 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT                                                        0xf
20379 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT                                                               0x10
20380 #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK                                                                0x0000000FL
20381 #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK                                                       0x00000010L
20382 #define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK                                                           0x00000020L
20383 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK                                                               0x00000040L
20384 #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK                                                               0x00000080L
20385 #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK                                                     0x00000100L
20386 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK                                                              0x00000200L
20387 #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK                                                               0x00003C00L
20388 #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK                                                          0x00004000L
20389 #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK                                                          0x00008000L
20390 #define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK                                                                 0xFFFF0000L
20391 //SPI_CONFIG_CNTL_2
20392 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT                                    0x0
20393 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT                                      0x4
20394 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK                                      0x0000000FL
20395 #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK                                        0x000000F0L
20396 
20397 
20398 // addressBlock: gc_perfddec
20399 //CPG_PERFCOUNTER1_LO
20400 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20401 #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20402 //CPG_PERFCOUNTER1_HI
20403 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20404 #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20405 //CPG_PERFCOUNTER0_LO
20406 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20407 #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20408 //CPG_PERFCOUNTER0_HI
20409 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20410 #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20411 //CPC_PERFCOUNTER1_LO
20412 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20413 #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20414 //CPC_PERFCOUNTER1_HI
20415 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20416 #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20417 //CPC_PERFCOUNTER0_LO
20418 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20419 #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20420 //CPC_PERFCOUNTER0_HI
20421 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20422 #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20423 //CPF_PERFCOUNTER1_LO
20424 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20425 #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20426 //CPF_PERFCOUNTER1_HI
20427 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20428 #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20429 //CPF_PERFCOUNTER0_LO
20430 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20431 #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20432 //CPF_PERFCOUNTER0_HI
20433 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20434 #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20435 //CPF_LATENCY_STATS_DATA
20436 #define CPF_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
20437 #define CPF_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
20438 //CPG_LATENCY_STATS_DATA
20439 #define CPG_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
20440 #define CPG_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
20441 //CPC_LATENCY_STATS_DATA
20442 #define CPC_LATENCY_STATS_DATA__DATA__SHIFT                                                                   0x0
20443 #define CPC_LATENCY_STATS_DATA__DATA_MASK                                                                     0xFFFFFFFFL
20444 //GRBM_PERFCOUNTER0_LO
20445 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
20446 #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
20447 //GRBM_PERFCOUNTER0_HI
20448 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
20449 #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
20450 //GRBM_PERFCOUNTER1_LO
20451 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                           0x0
20452 #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                             0xFFFFFFFFL
20453 //GRBM_PERFCOUNTER1_HI
20454 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                           0x0
20455 #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                             0xFFFFFFFFL
20456 //GRBM_SE0_PERFCOUNTER_LO
20457 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20458 #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20459 //GRBM_SE0_PERFCOUNTER_HI
20460 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20461 #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20462 //GRBM_SE1_PERFCOUNTER_LO
20463 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20464 #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20465 //GRBM_SE1_PERFCOUNTER_HI
20466 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20467 #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20468 //GRBM_SE2_PERFCOUNTER_LO
20469 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20470 #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20471 //GRBM_SE2_PERFCOUNTER_HI
20472 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20473 #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20474 //GRBM_SE3_PERFCOUNTER_LO
20475 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
20476 #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
20477 //GRBM_SE3_PERFCOUNTER_HI
20478 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
20479 #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
20480 //WD_PERFCOUNTER0_LO
20481 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20482 #define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20483 //WD_PERFCOUNTER0_HI
20484 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20485 #define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20486 //WD_PERFCOUNTER1_LO
20487 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20488 #define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20489 //WD_PERFCOUNTER1_HI
20490 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20491 #define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20492 //WD_PERFCOUNTER2_LO
20493 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20494 #define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20495 //WD_PERFCOUNTER2_HI
20496 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20497 #define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20498 //WD_PERFCOUNTER3_LO
20499 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20500 #define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20501 //WD_PERFCOUNTER3_HI
20502 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20503 #define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20504 //IA_PERFCOUNTER0_LO
20505 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20506 #define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20507 //IA_PERFCOUNTER0_HI
20508 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20509 #define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20510 //IA_PERFCOUNTER1_LO
20511 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20512 #define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20513 //IA_PERFCOUNTER1_HI
20514 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20515 #define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20516 //IA_PERFCOUNTER2_LO
20517 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20518 #define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20519 //IA_PERFCOUNTER2_HI
20520 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20521 #define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20522 //IA_PERFCOUNTER3_LO
20523 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20524 #define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20525 //IA_PERFCOUNTER3_HI
20526 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20527 #define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20528 //VGT_PERFCOUNTER0_LO
20529 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20530 #define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20531 //VGT_PERFCOUNTER0_HI
20532 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20533 #define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20534 //VGT_PERFCOUNTER1_LO
20535 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20536 #define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20537 //VGT_PERFCOUNTER1_HI
20538 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20539 #define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20540 //VGT_PERFCOUNTER2_LO
20541 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20542 #define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20543 //VGT_PERFCOUNTER2_HI
20544 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20545 #define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20546 //VGT_PERFCOUNTER3_LO
20547 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20548 #define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20549 //VGT_PERFCOUNTER3_HI
20550 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20551 #define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20552 //PA_SU_PERFCOUNTER0_LO
20553 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20554 #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20555 //PA_SU_PERFCOUNTER0_HI
20556 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20557 #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20558 //PA_SU_PERFCOUNTER1_LO
20559 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20560 #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20561 //PA_SU_PERFCOUNTER1_HI
20562 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20563 #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20564 //PA_SU_PERFCOUNTER2_LO
20565 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20566 #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20567 //PA_SU_PERFCOUNTER2_HI
20568 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20569 #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20570 //PA_SU_PERFCOUNTER3_LO
20571 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20572 #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20573 //PA_SU_PERFCOUNTER3_HI
20574 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20575 #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0x0000FFFFL
20576 //PA_SC_PERFCOUNTER0_LO
20577 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20578 #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20579 //PA_SC_PERFCOUNTER0_HI
20580 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20581 #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20582 //PA_SC_PERFCOUNTER1_LO
20583 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20584 #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20585 //PA_SC_PERFCOUNTER1_HI
20586 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20587 #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20588 //PA_SC_PERFCOUNTER2_LO
20589 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20590 #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20591 //PA_SC_PERFCOUNTER2_HI
20592 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20593 #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20594 //PA_SC_PERFCOUNTER3_LO
20595 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20596 #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20597 //PA_SC_PERFCOUNTER3_HI
20598 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20599 #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20600 //PA_SC_PERFCOUNTER4_LO
20601 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20602 #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20603 //PA_SC_PERFCOUNTER4_HI
20604 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20605 #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20606 //PA_SC_PERFCOUNTER5_LO
20607 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20608 #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20609 //PA_SC_PERFCOUNTER5_HI
20610 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20611 #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20612 //PA_SC_PERFCOUNTER6_LO
20613 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20614 #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20615 //PA_SC_PERFCOUNTER6_HI
20616 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20617 #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20618 //PA_SC_PERFCOUNTER7_LO
20619 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
20620 #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
20621 //PA_SC_PERFCOUNTER7_HI
20622 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
20623 #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
20624 //SPI_PERFCOUNTER0_HI
20625 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20626 #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20627 //SPI_PERFCOUNTER0_LO
20628 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20629 #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20630 //SPI_PERFCOUNTER1_HI
20631 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20632 #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20633 //SPI_PERFCOUNTER1_LO
20634 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20635 #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20636 //SPI_PERFCOUNTER2_HI
20637 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20638 #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20639 //SPI_PERFCOUNTER2_LO
20640 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20641 #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20642 //SPI_PERFCOUNTER3_HI
20643 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20644 #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20645 //SPI_PERFCOUNTER3_LO
20646 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20647 #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20648 //SPI_PERFCOUNTER4_HI
20649 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20650 #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20651 //SPI_PERFCOUNTER4_LO
20652 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20653 #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20654 //SPI_PERFCOUNTER5_HI
20655 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20656 #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20657 //SPI_PERFCOUNTER5_LO
20658 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20659 #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20660 //SQ_PERFCOUNTER0_LO
20661 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20662 #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20663 //SQ_PERFCOUNTER0_HI
20664 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20665 #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20666 //SQ_PERFCOUNTER1_LO
20667 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20668 #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20669 //SQ_PERFCOUNTER1_HI
20670 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20671 #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20672 //SQ_PERFCOUNTER2_LO
20673 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20674 #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20675 //SQ_PERFCOUNTER2_HI
20676 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20677 #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20678 //SQ_PERFCOUNTER3_LO
20679 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20680 #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20681 //SQ_PERFCOUNTER3_HI
20682 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20683 #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20684 //SQ_PERFCOUNTER4_LO
20685 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20686 #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20687 //SQ_PERFCOUNTER4_HI
20688 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20689 #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20690 //SQ_PERFCOUNTER5_LO
20691 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20692 #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20693 //SQ_PERFCOUNTER5_HI
20694 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20695 #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20696 //SQ_PERFCOUNTER6_LO
20697 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20698 #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20699 //SQ_PERFCOUNTER6_HI
20700 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20701 #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20702 //SQ_PERFCOUNTER7_LO
20703 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20704 #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20705 //SQ_PERFCOUNTER7_HI
20706 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20707 #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20708 //SQ_PERFCOUNTER8_LO
20709 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20710 #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20711 //SQ_PERFCOUNTER8_HI
20712 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20713 #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20714 //SQ_PERFCOUNTER9_LO
20715 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20716 #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20717 //SQ_PERFCOUNTER9_HI
20718 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20719 #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20720 //SQ_PERFCOUNTER10_LO
20721 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20722 #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20723 //SQ_PERFCOUNTER10_HI
20724 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20725 #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20726 //SQ_PERFCOUNTER11_LO
20727 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20728 #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20729 //SQ_PERFCOUNTER11_HI
20730 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20731 #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20732 //SQ_PERFCOUNTER12_LO
20733 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20734 #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20735 //SQ_PERFCOUNTER12_HI
20736 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20737 #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20738 //SQ_PERFCOUNTER13_LO
20739 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20740 #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20741 //SQ_PERFCOUNTER13_HI
20742 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20743 #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20744 //SQ_PERFCOUNTER14_LO
20745 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20746 #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20747 //SQ_PERFCOUNTER14_HI
20748 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20749 #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20750 //SQ_PERFCOUNTER15_LO
20751 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20752 #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20753 //SQ_PERFCOUNTER15_HI
20754 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20755 #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20756 //SX_PERFCOUNTER0_LO
20757 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20758 #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20759 //SX_PERFCOUNTER0_HI
20760 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20761 #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20762 //SX_PERFCOUNTER1_LO
20763 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20764 #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20765 //SX_PERFCOUNTER1_HI
20766 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20767 #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20768 //SX_PERFCOUNTER2_LO
20769 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20770 #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20771 //SX_PERFCOUNTER2_HI
20772 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20773 #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20774 //SX_PERFCOUNTER3_LO
20775 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20776 #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20777 //SX_PERFCOUNTER3_HI
20778 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20779 #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20780 //GDS_PERFCOUNTER0_LO
20781 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20782 #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20783 //GDS_PERFCOUNTER0_HI
20784 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20785 #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20786 //GDS_PERFCOUNTER1_LO
20787 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20788 #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20789 //GDS_PERFCOUNTER1_HI
20790 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20791 #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20792 //GDS_PERFCOUNTER2_LO
20793 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20794 #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20795 //GDS_PERFCOUNTER2_HI
20796 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20797 #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20798 //GDS_PERFCOUNTER3_LO
20799 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20800 #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20801 //GDS_PERFCOUNTER3_HI
20802 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20803 #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20804 //TA_PERFCOUNTER0_LO
20805 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20806 #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20807 //TA_PERFCOUNTER0_HI
20808 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20809 #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20810 //TA_PERFCOUNTER1_LO
20811 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20812 #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20813 //TA_PERFCOUNTER1_HI
20814 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20815 #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20816 //TD_PERFCOUNTER0_LO
20817 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20818 #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20819 //TD_PERFCOUNTER0_HI
20820 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20821 #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20822 //TD_PERFCOUNTER1_LO
20823 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20824 #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20825 //TD_PERFCOUNTER1_HI
20826 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20827 #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20828 //TCP_PERFCOUNTER0_LO
20829 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20830 #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20831 //TCP_PERFCOUNTER0_HI
20832 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20833 #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20834 //TCP_PERFCOUNTER1_LO
20835 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20836 #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20837 //TCP_PERFCOUNTER1_HI
20838 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20839 #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20840 //TCP_PERFCOUNTER2_LO
20841 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20842 #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20843 //TCP_PERFCOUNTER2_HI
20844 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20845 #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20846 //TCP_PERFCOUNTER3_LO
20847 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20848 #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20849 //TCP_PERFCOUNTER3_HI
20850 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20851 #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20852 //TCC_PERFCOUNTER0_LO
20853 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20854 #define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20855 //TCC_PERFCOUNTER0_HI
20856 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20857 #define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20858 //TCC_PERFCOUNTER1_LO
20859 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20860 #define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20861 //TCC_PERFCOUNTER1_HI
20862 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20863 #define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20864 //TCC_PERFCOUNTER2_LO
20865 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20866 #define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20867 //TCC_PERFCOUNTER2_HI
20868 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20869 #define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20870 //TCC_PERFCOUNTER3_LO
20871 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20872 #define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20873 //TCC_PERFCOUNTER3_HI
20874 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20875 #define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20876 //TCA_PERFCOUNTER0_LO
20877 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20878 #define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20879 //TCA_PERFCOUNTER0_HI
20880 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20881 #define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20882 //TCA_PERFCOUNTER1_LO
20883 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20884 #define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20885 //TCA_PERFCOUNTER1_HI
20886 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20887 #define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20888 //TCA_PERFCOUNTER2_LO
20889 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20890 #define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20891 //TCA_PERFCOUNTER2_HI
20892 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20893 #define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20894 //TCA_PERFCOUNTER3_LO
20895 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20896 #define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20897 //TCA_PERFCOUNTER3_HI
20898 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20899 #define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20900 //CB_PERFCOUNTER0_LO
20901 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20902 #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20903 //CB_PERFCOUNTER0_HI
20904 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20905 #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20906 //CB_PERFCOUNTER1_LO
20907 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20908 #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20909 //CB_PERFCOUNTER1_HI
20910 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20911 #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20912 //CB_PERFCOUNTER2_LO
20913 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20914 #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20915 //CB_PERFCOUNTER2_HI
20916 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20917 #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20918 //CB_PERFCOUNTER3_LO
20919 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20920 #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20921 //CB_PERFCOUNTER3_HI
20922 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20923 #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20924 //DB_PERFCOUNTER0_LO
20925 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20926 #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20927 //DB_PERFCOUNTER0_HI
20928 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20929 #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20930 //DB_PERFCOUNTER1_LO
20931 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20932 #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20933 //DB_PERFCOUNTER1_HI
20934 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20935 #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20936 //DB_PERFCOUNTER2_LO
20937 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20938 #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20939 //DB_PERFCOUNTER2_HI
20940 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20941 #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20942 //DB_PERFCOUNTER3_LO
20943 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                             0x0
20944 #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                               0xFFFFFFFFL
20945 //DB_PERFCOUNTER3_HI
20946 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                             0x0
20947 #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                               0xFFFFFFFFL
20948 //RLC_PERFCOUNTER0_LO
20949 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20950 #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20951 //RLC_PERFCOUNTER0_HI
20952 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20953 #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20954 //RLC_PERFCOUNTER1_LO
20955 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20956 #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20957 //RLC_PERFCOUNTER1_HI
20958 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20959 #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20960 //RMI_PERFCOUNTER0_LO
20961 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20962 #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20963 //RMI_PERFCOUNTER0_HI
20964 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20965 #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20966 //RMI_PERFCOUNTER1_LO
20967 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20968 #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20969 //RMI_PERFCOUNTER1_HI
20970 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20971 #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20972 //RMI_PERFCOUNTER2_LO
20973 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20974 #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20975 //RMI_PERFCOUNTER2_HI
20976 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20977 #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20978 //RMI_PERFCOUNTER3_LO
20979 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT                                                            0x0
20980 #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK                                                              0xFFFFFFFFL
20981 //RMI_PERFCOUNTER3_HI
20982 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT                                                            0x0
20983 #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
20984 
20985 
20986 // addressBlock: gc_utcl2_atcl2pfcntrdec
20987 //ATC_L2_PERFCOUNTER_LO
20988 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                              0x0
20989 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                0xFFFFFFFFL
20990 //ATC_L2_PERFCOUNTER_HI
20991 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                              0x0
20992 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                           0x10
20993 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                0x0000FFFFL
20994 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                             0xFFFF0000L
20995 
20996 
20997 // addressBlock: gc_utcl2_vml2prdec
20998 //MC_VM_L2_PERFCOUNTER_LO
20999 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                            0x0
21000 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                              0xFFFFFFFFL
21001 //MC_VM_L2_PERFCOUNTER_HI
21002 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                            0x0
21003 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                         0x10
21004 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                              0x0000FFFFL
21005 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                           0xFFFF0000L
21006 
21007 
21008 // addressBlock: gc_perfsdec
21009 //CPG_PERFCOUNTER1_SELECT
21010 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21011 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21012 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
21013 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21014 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21015 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21016 #define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21017 #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21018 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21019 #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21020 //CPG_PERFCOUNTER0_SELECT1
21021 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
21022 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
21023 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
21024 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
21025 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
21026 #define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
21027 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
21028 #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
21029 //CPG_PERFCOUNTER0_SELECT
21030 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21031 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21032 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
21033 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21034 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21035 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21036 #define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21037 #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21038 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21039 #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21040 //CPC_PERFCOUNTER1_SELECT
21041 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21042 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21043 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
21044 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21045 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21046 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21047 #define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21048 #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21049 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21050 #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21051 //CPC_PERFCOUNTER0_SELECT1
21052 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
21053 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
21054 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
21055 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
21056 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
21057 #define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
21058 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
21059 #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
21060 //CPF_PERFCOUNTER1_SELECT
21061 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21062 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21063 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                              0x14
21064 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21065 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21066 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21067 #define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21068 #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21069 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21070 #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21071 //CPF_PERFCOUNTER0_SELECT1
21072 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT                                                            0x0
21073 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT                                                            0xa
21074 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT                                                           0x18
21075 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT                                                           0x1c
21076 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK                                                              0x000003FFL
21077 #define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK                                                              0x000FFC00L
21078 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK                                                             0x0F000000L
21079 #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK                                                             0xF0000000L
21080 //CPF_PERFCOUNTER0_SELECT
21081 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21082 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21083 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
21084 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21085 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21086 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21087 #define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21088 #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21089 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21090 #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21091 //CP_PERFMON_CNTL
21092 #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                 0x0
21093 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT                                                             0x4
21094 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT                                                           0x8
21095 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                         0xa
21096 #define CP_PERFMON_CNTL__PERFMON_STATE_MASK                                                                   0x0000000FL
21097 #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK                                                               0x000000F0L
21098 #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK                                                             0x00000300L
21099 #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                           0x00000400L
21100 //CPC_PERFCOUNTER0_SELECT
21101 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT                                                             0x0
21102 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT                                                             0xa
21103 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                              0x14
21104 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT                                                            0x18
21105 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT                                                            0x1c
21106 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK                                                               0x000003FFL
21107 #define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK                                                               0x000FFC00L
21108 #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21109 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK                                                              0x0F000000L
21110 #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK                                                              0xF0000000L
21111 //CPF_TC_PERF_COUNTER_WINDOW_SELECT
21112 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
21113 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
21114 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
21115 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x00000007L
21116 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
21117 #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
21118 //CPG_TC_PERF_COUNTER_WINDOW_SELECT
21119 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT                                                       0x0
21120 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT                                                      0x1e
21121 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT                                                      0x1f
21122 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK                                                         0x0000001FL
21123 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK                                                        0x40000000L
21124 #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK                                                        0x80000000L
21125 //CPF_LATENCY_STATS_SELECT
21126 #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
21127 #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
21128 #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
21129 #define CPF_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000000FL
21130 #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
21131 #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
21132 //CPG_LATENCY_STATS_SELECT
21133 #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
21134 #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
21135 #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
21136 #define CPG_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x0000001FL
21137 #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
21138 #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
21139 //CPC_LATENCY_STATS_SELECT
21140 #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT                                                                0x0
21141 #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT                                                                0x1e
21142 #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT                                                               0x1f
21143 #define CPC_LATENCY_STATS_SELECT__INDEX_MASK                                                                  0x00000007L
21144 #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK                                                                  0x40000000L
21145 #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK                                                                 0x80000000L
21146 //CP_DRAW_OBJECT
21147 #define CP_DRAW_OBJECT__OBJECT__SHIFT                                                                         0x0
21148 #define CP_DRAW_OBJECT__OBJECT_MASK                                                                           0xFFFFFFFFL
21149 //CP_DRAW_OBJECT_COUNTER
21150 #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT                                                                  0x0
21151 #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK                                                                    0x0000FFFFL
21152 //CP_DRAW_WINDOW_MASK_HI
21153 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT                                                         0x0
21154 #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK                                                           0xFFFFFFFFL
21155 //CP_DRAW_WINDOW_HI
21156 #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT                                                                   0x0
21157 #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK                                                                     0xFFFFFFFFL
21158 //CP_DRAW_WINDOW_LO
21159 #define CP_DRAW_WINDOW_LO__MIN__SHIFT                                                                         0x0
21160 #define CP_DRAW_WINDOW_LO__MAX__SHIFT                                                                         0x10
21161 #define CP_DRAW_WINDOW_LO__MIN_MASK                                                                           0x0000FFFFL
21162 #define CP_DRAW_WINDOW_LO__MAX_MASK                                                                           0xFFFF0000L
21163 //CP_DRAW_WINDOW_CNTL
21164 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT                                                0x0
21165 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT                                                0x1
21166 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT                                                    0x2
21167 #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT                                                                      0x8
21168 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK                                                  0x00000001L
21169 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK                                                  0x00000002L
21170 #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK                                                      0x00000004L
21171 #define CP_DRAW_WINDOW_CNTL__MODE_MASK                                                                        0x00000100L
21172 //GRBM_PERFCOUNTER0_SELECT
21173 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
21174 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
21175 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
21176 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                           0xc
21177 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
21178 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
21179 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
21180 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
21181 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
21182 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
21183 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
21184 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
21185 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
21186 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x17
21187 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
21188 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
21189 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
21190 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1b
21191 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
21192 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
21193 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
21194 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
21195 #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x0000003FL
21196 #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
21197 #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
21198 #define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                             0x00001000L
21199 #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
21200 #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
21201 #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
21202 #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
21203 #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
21204 #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
21205 #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
21206 #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
21207 #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
21208 #define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK                                              0x00800000L
21209 #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
21210 #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
21211 #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
21212 #define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK                                              0x08000000L
21213 #define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
21214 #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
21215 #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
21216 #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
21217 //GRBM_PERFCOUNTER1_SELECT
21218 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
21219 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xa
21220 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                           0xb
21221 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                           0xc
21222 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                            0xd
21223 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                            0xe
21224 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x10
21225 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x11
21226 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x12
21227 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT                                          0x13
21228 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x14
21229 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                            0x15
21230 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT                                            0x16
21231 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x17
21232 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT                                           0x18
21233 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x19
21234 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1a
21235 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1b
21236 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1c
21237 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT                                         0x1d
21238 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                            0x1e
21239 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1f
21240 #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x0000003FL
21241 #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000400L
21242 #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                             0x00000800L
21243 #define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                             0x00001000L
21244 #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                              0x00002000L
21245 #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                              0x00004000L
21246 #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                             0x00010000L
21247 #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                              0x00020000L
21248 #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                              0x00040000L
21249 #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK                                            0x00080000L
21250 #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                              0x00100000L
21251 #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                              0x00200000L
21252 #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK                                              0x00400000L
21253 #define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK                                              0x00800000L
21254 #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK                                             0x01000000L
21255 #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                             0x02000000L
21256 #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                             0x04000000L
21257 #define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK                                              0x08000000L
21258 #define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK                                              0x10000000L
21259 #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK                                           0x20000000L
21260 #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                              0x40000000L
21261 #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                             0x80000000L
21262 //GRBM_SE0_PERFCOUNTER_SELECT
21263 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21264 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21265 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21266 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21267 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21268 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21269 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21270 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21271 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21272 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21273 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21274 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21275 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21276 #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21277 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21278 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21279 #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21280 #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21281 #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21282 #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21283 #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21284 #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21285 #define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21286 #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21287 #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21288 #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21289 //GRBM_SE1_PERFCOUNTER_SELECT
21290 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21291 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21292 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21293 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21294 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21295 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21296 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21297 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21298 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21299 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21300 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21301 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21302 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21303 #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21304 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21305 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21306 #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21307 #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21308 #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21309 #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21310 #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21311 #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21312 #define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21313 #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21314 #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21315 #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21316 //GRBM_SE2_PERFCOUNTER_SELECT
21317 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21318 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21319 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21320 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21321 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21322 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21323 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21324 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21325 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21326 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21327 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21328 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21329 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21330 #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21331 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21332 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21333 #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21334 #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21335 #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21336 #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21337 #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21338 #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21339 #define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21340 #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21341 #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21342 #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21343 //GRBM_SE3_PERFCOUNTER_SELECT
21344 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT                                                          0x0
21345 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xa
21346 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                        0xb
21347 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                         0xc
21348 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                         0xd
21349 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                        0xf
21350 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x10
21351 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
21352 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                         0x12
21353 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT                                        0x13
21354 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                         0x14
21355 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x15
21356 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT                                        0x16
21357 #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK                                                            0x0000003FL
21358 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000400L
21359 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                          0x00000800L
21360 #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                           0x00001000L
21361 #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                           0x00002000L
21362 #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                          0x00008000L
21363 #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK                                           0x00010000L
21364 #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
21365 #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                           0x00040000L
21366 #define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK                                          0x00080000L
21367 #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                           0x00100000L
21368 #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                          0x00200000L
21369 #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK                                          0x00400000L
21370 //WD_PERFCOUNTER0_SELECT
21371 #define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21372 #define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21373 #define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21374 #define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21375 //WD_PERFCOUNTER1_SELECT
21376 #define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21377 #define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21378 #define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21379 #define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21380 //WD_PERFCOUNTER2_SELECT
21381 #define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
21382 #define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
21383 #define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21384 #define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21385 //WD_PERFCOUNTER3_SELECT
21386 #define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
21387 #define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
21388 #define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21389 #define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21390 //IA_PERFCOUNTER0_SELECT
21391 #define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21392 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
21393 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21394 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
21395 #define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21396 #define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
21397 #define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
21398 #define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21399 #define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21400 #define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21401 //IA_PERFCOUNTER1_SELECT
21402 #define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21403 #define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21404 #define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21405 #define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21406 //IA_PERFCOUNTER2_SELECT
21407 #define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
21408 #define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
21409 #define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21410 #define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21411 //IA_PERFCOUNTER3_SELECT
21412 #define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
21413 #define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
21414 #define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21415 #define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21416 //IA_PERFCOUNTER0_SELECT1
21417 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
21418 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
21419 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
21420 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
21421 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
21422 #define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
21423 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
21424 #define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
21425 //VGT_PERFCOUNTER0_SELECT
21426 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
21427 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
21428 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21429 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
21430 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
21431 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21432 #define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21433 #define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21434 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21435 #define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21436 //VGT_PERFCOUNTER1_SELECT
21437 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
21438 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
21439 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
21440 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
21441 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
21442 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21443 #define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21444 #define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21445 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21446 #define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21447 //VGT_PERFCOUNTER2_SELECT
21448 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
21449 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
21450 #define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21451 #define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21452 //VGT_PERFCOUNTER3_SELECT
21453 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
21454 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
21455 #define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21456 #define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21457 //VGT_PERFCOUNTER0_SELECT1
21458 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21459 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21460 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21461 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21462 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21463 #define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21464 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21465 #define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21466 //VGT_PERFCOUNTER1_SELECT1
21467 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21468 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21469 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21470 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21471 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21472 #define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21473 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21474 #define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21475 //VGT_PERFCOUNTER_SEID_MASK
21476 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT                                               0x0
21477 #define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK                                                 0x000000FFL
21478 //PA_SU_PERFCOUNTER0_SELECT
21479 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
21480 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
21481 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
21482 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21483 #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
21484 #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21485 //PA_SU_PERFCOUNTER0_SELECT1
21486 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
21487 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
21488 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
21489 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
21490 //PA_SU_PERFCOUNTER1_SELECT
21491 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
21492 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                           0xa
21493 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                           0x14
21494 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21495 #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
21496 #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21497 //PA_SU_PERFCOUNTER1_SELECT1
21498 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                          0x0
21499 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                          0xa
21500 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
21501 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
21502 //PA_SU_PERFCOUNTER2_SELECT
21503 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
21504 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                           0x14
21505 #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21506 #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21507 //PA_SU_PERFCOUNTER3_SELECT
21508 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
21509 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                           0x14
21510 #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21511 #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21512 //PA_SC_PERFCOUNTER0_SELECT
21513 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
21514 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                           0xa
21515 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                           0x14
21516 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21517 #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                             0x000FFC00L
21518 #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                             0x00F00000L
21519 //PA_SC_PERFCOUNTER0_SELECT1
21520 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                          0x0
21521 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                          0xa
21522 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                            0x000003FFL
21523 #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                            0x000FFC00L
21524 //PA_SC_PERFCOUNTER1_SELECT
21525 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
21526 #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21527 //PA_SC_PERFCOUNTER2_SELECT
21528 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                            0x0
21529 #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21530 //PA_SC_PERFCOUNTER3_SELECT
21531 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                            0x0
21532 #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21533 //PA_SC_PERFCOUNTER4_SELECT
21534 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                            0x0
21535 #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21536 //PA_SC_PERFCOUNTER5_SELECT
21537 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                            0x0
21538 #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21539 //PA_SC_PERFCOUNTER6_SELECT
21540 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                            0x0
21541 #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21542 //PA_SC_PERFCOUNTER7_SELECT
21543 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                            0x0
21544 #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                              0x000003FFL
21545 //SPI_PERFCOUNTER0_SELECT
21546 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
21547 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
21548 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21549 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
21550 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
21551 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21552 #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21553 #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21554 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21555 #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21556 //SPI_PERFCOUNTER1_SELECT
21557 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
21558 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
21559 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
21560 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
21561 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
21562 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21563 #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21564 #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21565 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21566 #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21567 //SPI_PERFCOUNTER2_SELECT
21568 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
21569 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
21570 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
21571 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
21572 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
21573 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21574 #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21575 #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21576 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21577 #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21578 //SPI_PERFCOUNTER3_SELECT
21579 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
21580 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                             0xa
21581 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
21582 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                            0x18
21583 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
21584 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
21585 #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
21586 #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21587 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
21588 #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21589 //SPI_PERFCOUNTER0_SELECT1
21590 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21591 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21592 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21593 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21594 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21595 #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21596 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21597 #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21598 //SPI_PERFCOUNTER1_SELECT1
21599 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21600 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21601 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21602 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21603 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21604 #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21605 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21606 #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21607 //SPI_PERFCOUNTER2_SELECT1
21608 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21609 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21610 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21611 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21612 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21613 #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21614 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21615 #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21616 //SPI_PERFCOUNTER3_SELECT1
21617 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                            0x0
21618 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                            0xa
21619 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                           0x18
21620 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
21621 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
21622 #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
21623 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
21624 #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
21625 //SPI_PERFCOUNTER4_SELECT
21626 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                              0x0
21627 #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21628 //SPI_PERFCOUNTER5_SELECT
21629 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                              0x0
21630 #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                0x000000FFL
21631 //SPI_PERFCOUNTER_BINS
21632 #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT                                                                 0x0
21633 #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT                                                                 0x4
21634 #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT                                                                 0x8
21635 #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT                                                                 0xc
21636 #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT                                                                 0x10
21637 #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT                                                                 0x14
21638 #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT                                                                 0x18
21639 #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT                                                                 0x1c
21640 #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK                                                                   0x0000000FL
21641 #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK                                                                   0x000000F0L
21642 #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK                                                                   0x00000F00L
21643 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK                                                                   0x0000F000L
21644 #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK                                                                   0x000F0000L
21645 #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK                                                                   0x00F00000L
21646 #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK                                                                   0x0F000000L
21647 #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK                                                                   0xF0000000L
21648 //SQ_PERFCOUNTER0_SELECT
21649 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21650 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21651 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21652 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT                                                               0x14
21653 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT                                                              0x18
21654 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21655 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21656 #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21657 #define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21658 #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21659 #define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21660 #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21661 //SQ_PERFCOUNTER1_SELECT
21662 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21663 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21664 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21665 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT                                                               0x14
21666 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT                                                              0x18
21667 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21668 #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21669 #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21670 #define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21671 #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21672 #define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21673 #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21674 //SQ_PERFCOUNTER2_SELECT
21675 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
21676 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21677 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21678 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT                                                               0x14
21679 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT                                                              0x18
21680 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
21681 #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21682 #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21683 #define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21684 #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21685 #define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21686 #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21687 //SQ_PERFCOUNTER3_SELECT
21688 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
21689 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21690 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21691 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT                                                               0x14
21692 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT                                                              0x18
21693 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
21694 #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21695 #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21696 #define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21697 #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21698 #define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21699 #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21700 //SQ_PERFCOUNTER4_SELECT
21701 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT                                                               0x0
21702 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21703 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21704 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT                                                               0x14
21705 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT                                                              0x18
21706 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT                                                              0x1c
21707 #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21708 #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21709 #define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21710 #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21711 #define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21712 #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21713 //SQ_PERFCOUNTER5_SELECT
21714 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT                                                               0x0
21715 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21716 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21717 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT                                                               0x14
21718 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT                                                              0x18
21719 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT                                                              0x1c
21720 #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21721 #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21722 #define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21723 #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21724 #define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21725 #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21726 //SQ_PERFCOUNTER6_SELECT
21727 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT                                                               0x0
21728 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21729 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21730 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT                                                               0x14
21731 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT                                                              0x18
21732 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT                                                              0x1c
21733 #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21734 #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21735 #define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21736 #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21737 #define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21738 #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21739 //SQ_PERFCOUNTER7_SELECT
21740 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT                                                               0x0
21741 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21742 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21743 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT                                                               0x14
21744 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT                                                              0x18
21745 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT                                                              0x1c
21746 #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21747 #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21748 #define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21749 #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21750 #define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21751 #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21752 //SQ_PERFCOUNTER8_SELECT
21753 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT                                                               0x0
21754 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21755 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21756 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT                                                               0x14
21757 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT                                                              0x18
21758 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT                                                              0x1c
21759 #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21760 #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21761 #define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21762 #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21763 #define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21764 #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21765 //SQ_PERFCOUNTER9_SELECT
21766 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT                                                               0x0
21767 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT                                                          0xc
21768 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT                                                        0x10
21769 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT                                                               0x14
21770 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT                                                              0x18
21771 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT                                                              0x1c
21772 #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
21773 #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK                                                            0x0000F000L
21774 #define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK                                                          0x000F0000L
21775 #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK                                                                 0x00F00000L
21776 #define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK                                                                0x0F000000L
21777 #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21778 //SQ_PERFCOUNTER10_SELECT
21779 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT                                                              0x0
21780 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21781 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21782 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT                                                              0x14
21783 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT                                                             0x18
21784 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT                                                             0x1c
21785 #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21786 #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21787 #define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21788 #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21789 #define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21790 #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21791 //SQ_PERFCOUNTER11_SELECT
21792 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT                                                              0x0
21793 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21794 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21795 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT                                                              0x14
21796 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT                                                             0x18
21797 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT                                                             0x1c
21798 #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21799 #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21800 #define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21801 #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21802 #define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21803 #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21804 //SQ_PERFCOUNTER12_SELECT
21805 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT                                                              0x0
21806 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21807 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21808 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT                                                              0x14
21809 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT                                                             0x18
21810 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT                                                             0x1c
21811 #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21812 #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21813 #define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21814 #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21815 #define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21816 #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21817 //SQ_PERFCOUNTER13_SELECT
21818 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT                                                              0x0
21819 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21820 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21821 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT                                                              0x14
21822 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT                                                             0x18
21823 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT                                                             0x1c
21824 #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21825 #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21826 #define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21827 #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21828 #define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21829 #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21830 //SQ_PERFCOUNTER14_SELECT
21831 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT                                                              0x0
21832 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21833 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21834 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT                                                              0x14
21835 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT                                                             0x18
21836 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT                                                             0x1c
21837 #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21838 #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21839 #define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21840 #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21841 #define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21842 #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21843 //SQ_PERFCOUNTER15_SELECT
21844 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT                                                              0x0
21845 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT                                                         0xc
21846 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT                                                       0x10
21847 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT                                                              0x14
21848 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT                                                             0x18
21849 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT                                                             0x1c
21850 #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK                                                                0x000001FFL
21851 #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK                                                           0x0000F000L
21852 #define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK                                                         0x000F0000L
21853 #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK                                                                0x00F00000L
21854 #define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK                                                               0x0F000000L
21855 #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK                                                               0xF0000000L
21856 //SQ_PERFCOUNTER_CTRL
21857 #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT                                                                     0x0
21858 #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT                                                                     0x1
21859 #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT                                                                     0x2
21860 #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT                                                                     0x3
21861 #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT                                                                     0x4
21862 #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT                                                                     0x5
21863 #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT                                                                     0x6
21864 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT                                                                 0x8
21865 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT                                                             0xd
21866 #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK                                                                       0x00000001L
21867 #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK                                                                       0x00000002L
21868 #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK                                                                       0x00000004L
21869 #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK                                                                       0x00000008L
21870 #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK                                                                       0x00000010L
21871 #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK                                                                       0x00000020L
21872 #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK                                                                       0x00000040L
21873 #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK                                                                   0x00001F00L
21874 #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK                                                               0x00002000L
21875 //SQ_PERFCOUNTER_MASK
21876 #define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT                                                                  0x0
21877 #define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT                                                                  0x10
21878 #define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK                                                                    0x0000FFFFL
21879 #define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK                                                                    0xFFFF0000L
21880 //SQ_PERFCOUNTER_CTRL2
21881 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT                                                                 0x0
21882 #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK                                                                   0x00000001L
21883 //SX_PERFCOUNTER0_SELECT
21884 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21885 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21886 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21887 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21888 #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21889 #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21890 //SX_PERFCOUNTER1_SELECT
21891 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21892 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21893 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
21894 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21895 #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21896 #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21897 //SX_PERFCOUNTER2_SELECT
21898 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21899 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21900 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
21901 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21902 #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21903 #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21904 //SX_PERFCOUNTER3_SELECT
21905 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT                                                     0x0
21906 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                    0xa
21907 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
21908 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK                                                       0x000003FFL
21909 #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK                                                      0x000FFC00L
21910 #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21911 //SX_PERFCOUNTER0_SELECT1
21912 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                   0x0
21913 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                   0xa
21914 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK                                                     0x000003FFL
21915 #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK                                                     0x000FFC00L
21916 //SX_PERFCOUNTER1_SELECT1
21917 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                   0x0
21918 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                   0xa
21919 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK                                                     0x000003FFL
21920 #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK                                                     0x000FFC00L
21921 //GDS_PERFCOUNTER0_SELECT
21922 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21923 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21924 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
21925 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21926 #define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21927 #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21928 //GDS_PERFCOUNTER1_SELECT
21929 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21930 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21931 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
21932 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21933 #define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21934 #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21935 //GDS_PERFCOUNTER2_SELECT
21936 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21937 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21938 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
21939 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21940 #define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21941 #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21942 //GDS_PERFCOUNTER3_SELECT
21943 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
21944 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT                                                   0xa
21945 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
21946 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x000003FFL
21947 #define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK                                                     0x000FFC00L
21948 #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
21949 //GDS_PERFCOUNTER0_SELECT1
21950 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT                                                  0x0
21951 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT                                                  0xa
21952 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK                                                    0x000003FFL
21953 #define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK                                                    0x000FFC00L
21954 //TA_PERFCOUNTER0_SELECT
21955 #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21956 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
21957 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21958 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
21959 #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21960 #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21961 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21962 #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21963 #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21964 #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21965 //TA_PERFCOUNTER0_SELECT1
21966 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
21967 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
21968 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
21969 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
21970 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000000FFL
21971 #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0003FC00L
21972 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
21973 #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
21974 //TA_PERFCOUNTER1_SELECT
21975 #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
21976 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
21977 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
21978 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
21979 #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
21980 #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21981 #define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21982 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21983 #define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21984 #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21985 //TD_PERFCOUNTER0_SELECT
21986 #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
21987 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
21988 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
21989 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
21990 #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
21991 #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
21992 #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
21993 #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
21994 #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
21995 #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
21996 //TD_PERFCOUNTER0_SELECT1
21997 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
21998 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
21999 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22000 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22001 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000000FFL
22002 #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0003FC00L
22003 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22004 #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22005 //TD_PERFCOUNTER1_SELECT
22006 #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
22007 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
22008 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
22009 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
22010 #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
22011 #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000000FFL
22012 #define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x0003FC00L
22013 #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22014 #define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22015 #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22016 //TCP_PERFCOUNTER0_SELECT
22017 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22018 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22019 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22020 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22021 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22022 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22023 #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22024 #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22025 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22026 #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22027 //TCP_PERFCOUNTER0_SELECT1
22028 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22029 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22030 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22031 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22032 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22033 #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22034 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22035 #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22036 //TCP_PERFCOUNTER1_SELECT
22037 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22038 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
22039 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
22040 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
22041 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22042 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22043 #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22044 #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22045 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22046 #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22047 //TCP_PERFCOUNTER1_SELECT1
22048 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22049 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22050 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22051 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22052 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22053 #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22054 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22055 #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22056 //TCP_PERFCOUNTER2_SELECT
22057 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22058 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22059 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22060 #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22061 #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22062 #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22063 //TCP_PERFCOUNTER3_SELECT
22064 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22065 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
22066 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22067 #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22068 #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22069 #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22070 //TCC_PERFCOUNTER0_SELECT
22071 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22072 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22073 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22074 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22075 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22076 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22077 #define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22078 #define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22079 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22080 #define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22081 //TCC_PERFCOUNTER0_SELECT1
22082 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22083 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22084 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22085 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22086 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22087 #define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22088 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22089 #define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22090 //TCC_PERFCOUNTER1_SELECT
22091 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22092 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
22093 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
22094 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
22095 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22096 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22097 #define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22098 #define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22099 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22100 #define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22101 //TCC_PERFCOUNTER1_SELECT1
22102 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22103 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22104 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22105 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22106 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22107 #define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22108 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22109 #define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22110 //TCC_PERFCOUNTER2_SELECT
22111 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22112 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22113 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22114 #define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22115 #define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22116 #define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22117 //TCC_PERFCOUNTER3_SELECT
22118 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22119 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
22120 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22121 #define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22122 #define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22123 #define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22124 //TCA_PERFCOUNTER0_SELECT
22125 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22126 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22127 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22128 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22129 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22130 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22131 #define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22132 #define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22133 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22134 #define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22135 //TCA_PERFCOUNTER0_SELECT1
22136 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22137 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22138 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22139 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22140 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22141 #define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22142 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22143 #define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22144 //TCA_PERFCOUNTER1_SELECT
22145 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22146 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                             0xa
22147 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                             0x14
22148 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                            0x18
22149 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22150 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22151 #define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                               0x000FFC00L
22152 #define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22153 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22154 #define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22155 //TCA_PERFCOUNTER1_SELECT1
22156 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22157 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22158 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                           0x18
22159 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                           0x1c
22160 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                              0x000003FFL
22161 #define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                              0x000FFC00L
22162 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                             0x0F000000L
22163 #define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                             0xF0000000L
22164 //TCA_PERFCOUNTER2_SELECT
22165 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22166 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22167 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22168 #define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22169 #define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22170 #define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22171 //TCA_PERFCOUNTER3_SELECT
22172 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22173 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                             0x14
22174 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22175 #define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000003FFL
22176 #define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22177 #define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22178 //CB_PERFCOUNTER_FILTER
22179 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT                                                        0x0
22180 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT                                                           0x1
22181 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT                                                    0x4
22182 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT                                                       0x5
22183 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT                                                     0xa
22184 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT                                                        0xb
22185 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT                                                       0xc
22186 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT                                                          0xd
22187 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT                                               0x11
22188 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT                                                  0x12
22189 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT                                             0x15
22190 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT                                                0x16
22191 #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK                                                          0x00000001L
22192 #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK                                                             0x0000000EL
22193 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK                                                      0x00000010L
22194 #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK                                                         0x000003E0L
22195 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK                                                       0x00000400L
22196 #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK                                                          0x00000800L
22197 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK                                                         0x00001000L
22198 #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK                                                            0x0000E000L
22199 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK                                                 0x00020000L
22200 #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK                                                    0x001C0000L
22201 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK                                               0x00200000L
22202 #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK                                                  0x00C00000L
22203 //CB_PERFCOUNTER0_SELECT
22204 #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
22205 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
22206 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
22207 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
22208 #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
22209 #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22210 #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x0007FC00L
22211 #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22212 #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22213 #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22214 //CB_PERFCOUNTER0_SELECT1
22215 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
22216 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
22217 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22218 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22219 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000001FFL
22220 #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x0007FC00L
22221 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22222 #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22223 //CB_PERFCOUNTER1_SELECT
22224 #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
22225 #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
22226 #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22227 #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22228 //CB_PERFCOUNTER2_SELECT
22229 #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
22230 #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
22231 #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22232 #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22233 //CB_PERFCOUNTER3_SELECT
22234 #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
22235 #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
22236 #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000001FFL
22237 #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22238 //DB_PERFCOUNTER0_SELECT
22239 #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                               0x0
22240 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                              0xa
22241 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                              0x14
22242 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                             0x18
22243 #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                              0x1c
22244 #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22245 #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22246 #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22247 #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22248 #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22249 //DB_PERFCOUNTER0_SELECT1
22250 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                             0x0
22251 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                             0xa
22252 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22253 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22254 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
22255 #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
22256 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22257 #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22258 //DB_PERFCOUNTER1_SELECT
22259 #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                               0x0
22260 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                              0xa
22261 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                              0x14
22262 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                             0x18
22263 #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                              0x1c
22264 #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22265 #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22266 #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22267 #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22268 #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22269 //DB_PERFCOUNTER1_SELECT1
22270 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                             0x0
22271 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                             0xa
22272 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                            0x18
22273 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                            0x1c
22274 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                               0x000003FFL
22275 #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                               0x000FFC00L
22276 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                              0x0F000000L
22277 #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                              0xF0000000L
22278 //DB_PERFCOUNTER2_SELECT
22279 #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                               0x0
22280 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                              0xa
22281 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                              0x14
22282 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                             0x18
22283 #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                              0x1c
22284 #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22285 #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22286 #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22287 #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22288 #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22289 //DB_PERFCOUNTER3_SELECT
22290 #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                               0x0
22291 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                              0xa
22292 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                              0x14
22293 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                             0x18
22294 #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                              0x1c
22295 #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                 0x000003FFL
22296 #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                                0x000FFC00L
22297 #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                                0x00F00000L
22298 #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                               0x0F000000L
22299 #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                                0xF0000000L
22300 //RLC_SPM_PERFMON_CNTL
22301 #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT                                                                0x0
22302 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT                                                        0xc
22303 #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT                                                                 0xe
22304 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT                                                  0x10
22305 #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK                                                                  0x00000FFFL
22306 #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK                                                          0x00003000L
22307 #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK                                                                   0x0000C000L
22308 #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK                                                    0xFFFF0000L
22309 //RLC_SPM_PERFMON_RING_BASE_LO
22310 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT                                                     0x0
22311 #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK                                                       0xFFFFFFFFL
22312 //RLC_SPM_PERFMON_RING_BASE_HI
22313 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT                                                     0x0
22314 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT                                                         0x10
22315 #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK                                                       0x0000FFFFL
22316 #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK                                                           0xFFFF0000L
22317 //RLC_SPM_PERFMON_RING_SIZE
22318 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT                                                      0x0
22319 #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK                                                        0xFFFFFFFFL
22320 //RLC_SPM_PERFMON_SEGMENT_SIZE
22321 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT                                             0x0
22322 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT                                                        0x8
22323 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT                                                  0xb
22324 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT                                                     0x10
22325 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT                                                     0x15
22326 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT                                                     0x1a
22327 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT                                                         0x1f
22328 #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK                                               0x000000FFL
22329 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK                                                          0x00000700L
22330 #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK                                                    0x0000F800L
22331 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK                                                       0x001F0000L
22332 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK                                                       0x03E00000L
22333 #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK                                                       0x7C000000L
22334 #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK                                                           0x80000000L
22335 //RLC_SPM_SE_MUXSEL_ADDR
22336 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                       0x0
22337 #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                         0xFFFFFFFFL
22338 //RLC_SPM_SE_MUXSEL_DATA
22339 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                       0x0
22340 #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                         0xFFFFFFFFL
22341 //RLC_SPM_CPG_PERFMON_SAMPLE_DELAY
22342 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22343 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22344 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22345 #define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22346 //RLC_SPM_CPC_PERFMON_SAMPLE_DELAY
22347 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22348 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22349 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22350 #define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22351 //RLC_SPM_CPF_PERFMON_SAMPLE_DELAY
22352 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22353 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22354 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22355 #define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22356 //RLC_SPM_CB_PERFMON_SAMPLE_DELAY
22357 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22358 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22359 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22360 #define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22361 //RLC_SPM_DB_PERFMON_SAMPLE_DELAY
22362 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22363 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22364 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22365 #define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22366 //RLC_SPM_PA_PERFMON_SAMPLE_DELAY
22367 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22368 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22369 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22370 #define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22371 //RLC_SPM_GDS_PERFMON_SAMPLE_DELAY
22372 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22373 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22374 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22375 #define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22376 //RLC_SPM_IA_PERFMON_SAMPLE_DELAY
22377 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22378 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22379 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22380 #define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22381 //RLC_SPM_SC_PERFMON_SAMPLE_DELAY
22382 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22383 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22384 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22385 #define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22386 //RLC_SPM_TCC_PERFMON_SAMPLE_DELAY
22387 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22388 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22389 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22390 #define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22391 //RLC_SPM_TCA_PERFMON_SAMPLE_DELAY
22392 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22393 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22394 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22395 #define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22396 //RLC_SPM_TCP_PERFMON_SAMPLE_DELAY
22397 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22398 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22399 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22400 #define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22401 //RLC_SPM_TA_PERFMON_SAMPLE_DELAY
22402 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22403 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22404 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22405 #define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22406 //RLC_SPM_TD_PERFMON_SAMPLE_DELAY
22407 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22408 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22409 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22410 #define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22411 //RLC_SPM_VGT_PERFMON_SAMPLE_DELAY
22412 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22413 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22414 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22415 #define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22416 //RLC_SPM_SPI_PERFMON_SAMPLE_DELAY
22417 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22418 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22419 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22420 #define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22421 //RLC_SPM_SQG_PERFMON_SAMPLE_DELAY
22422 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22423 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22424 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22425 #define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22426 //RLC_SPM_SX_PERFMON_SAMPLE_DELAY
22427 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                          0x0
22428 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                      0x8
22429 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                            0x000000FFL
22430 #define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                        0xFFFFFF00L
22431 //RLC_SPM_GLOBAL_MUXSEL_ADDR
22432 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT                                                   0x0
22433 #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK                                                     0xFFFFFFFFL
22434 //RLC_SPM_GLOBAL_MUXSEL_DATA
22435 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT                                                   0x0
22436 #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK                                                     0xFFFFFFFFL
22437 //RLC_SPM_RING_RDPTR
22438 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT                                                         0x0
22439 #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK                                                           0xFFFFFFFFL
22440 //RLC_SPM_SEGMENT_THRESHOLD
22441 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT                                               0x0
22442 #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK                                                 0xFFFFFFFFL
22443 //RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY
22444 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22445 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22446 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22447 #define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22448 //RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY
22449 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22450 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22451 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22452 #define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22453 //RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY
22454 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22455 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22456 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22457 #define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22458 //RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY
22459 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                        0x0
22460 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                    0x8
22461 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                          0x000000FFL
22462 #define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                      0xFFFFFF00L
22463 //RLC_SPM_RMI_PERFMON_SAMPLE_DELAY
22464 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT                                         0x0
22465 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT                                                     0x8
22466 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK                                           0x000000FFL
22467 #define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK                                                       0xFFFFFF00L
22468 //RLC_PERFMON_CLK_CNTL
22469 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT                                                      0x0
22470 #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK                                                        0x00000001L
22471 //RLC_PERFMON_CNTL
22472 #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                0x0
22473 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                        0xa
22474 #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK                                                                  0x00000007L
22475 #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                          0x00000400L
22476 //RLC_PERFCOUNTER0_SELECT
22477 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
22478 #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x00FFL
22479 //RLC_PERFCOUNTER1_SELECT
22480 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT                                                    0x0
22481 #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK                                                      0x00FFL
22482 //RLC_GPU_IOV_PERF_CNT_CNTL
22483 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT                                                              0x0
22484 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT                                                         0x1
22485 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT                                                               0x2
22486 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT                                                            0x3
22487 #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK                                                                0x00000001L
22488 #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK                                                           0x00000002L
22489 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK                                                                 0x00000004L
22490 #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK                                                              0xFFFFFFF8L
22491 //RLC_GPU_IOV_PERF_CNT_WR_ADDR
22492 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT                                                             0x0
22493 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT                                                           0x4
22494 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT                                                         0x6
22495 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK                                                               0x0000000FL
22496 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK                                                             0x00000030L
22497 #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
22498 //RLC_GPU_IOV_PERF_CNT_WR_DATA
22499 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT                                                             0x0
22500 #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK                                                               0x0000000FL
22501 //RLC_GPU_IOV_PERF_CNT_RD_ADDR
22502 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT                                                             0x0
22503 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT                                                           0x4
22504 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT                                                         0x6
22505 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK                                                               0x0000000FL
22506 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK                                                             0x00000030L
22507 #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK                                                           0xFFFFFFC0L
22508 //RLC_GPU_IOV_PERF_CNT_RD_DATA
22509 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT                                                             0x0
22510 #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK                                                               0x0000000FL
22511 //RMI_PERFCOUNTER0_SELECT
22512 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                              0x0
22513 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                             0xa
22514 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                             0x14
22515 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                            0x18
22516 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                             0x1c
22517 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22518 #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
22519 #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22520 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22521 #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22522 //RMI_PERFCOUNTER0_SELECT1
22523 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22524 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22525 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22526 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22527 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
22528 #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
22529 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22530 #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22531 //RMI_PERFCOUNTER1_SELECT
22532 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
22533 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                             0x1c
22534 #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22535 #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22536 //RMI_PERFCOUNTER2_SELECT
22537 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                              0x0
22538 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                             0xa
22539 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                             0x14
22540 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                            0x18
22541 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                             0x1c
22542 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22543 #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                               0x0007FC00L
22544 #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                               0x00F00000L
22545 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                              0x0F000000L
22546 #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22547 //RMI_PERFCOUNTER2_SELECT1
22548 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                            0x0
22549 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                            0xa
22550 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                           0x18
22551 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                           0x1c
22552 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                              0x000001FFL
22553 #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                              0x0007FC00L
22554 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                             0x0F000000L
22555 #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
22556 //RMI_PERFCOUNTER3_SELECT
22557 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                              0x0
22558 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                             0x1c
22559 #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                                0x000001FFL
22560 #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                               0xF0000000L
22561 //RMI_PERF_COUNTER_CNTL
22562 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT                                                 0x0
22563 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT                                                 0x2
22564 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT                                                          0x4
22565 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT                                                 0x6
22566 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT                                                 0x8
22567 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT                                                        0xa
22568 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT                                                       0xe
22569 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT                                     0x13
22570 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT                                                         0x19
22571 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT                                                       0x1a
22572 #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK                                                   0x00000003L
22573 #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK                                                   0x0000000CL
22574 #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK                                                            0x00000030L
22575 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK                                                   0x000000C0L
22576 #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK                                                   0x00000300L
22577 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK                                                          0x00003C00L
22578 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK                                                         0x0007C000L
22579 #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK                                       0x01F80000L
22580 #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK                                                           0x02000000L
22581 #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK                                                         0x04000000L
22582 
22583 
22584 // addressBlock: gc_utcl2_atcl2pfcntldec
22585 //ATC_L2_PERFCOUNTER0_CFG
22586 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                              0x0
22587 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                          0x8
22588 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                             0x18
22589 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                0x1c
22590 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                 0x1d
22591 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                0x000000FFL
22592 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
22593 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                               0x0F000000L
22594 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                  0x10000000L
22595 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                   0x20000000L
22596 //ATC_L2_PERFCOUNTER1_CFG
22597 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                              0x0
22598 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                          0x8
22599 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                             0x18
22600 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                0x1c
22601 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                 0x1d
22602 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                0x000000FFL
22603 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                            0x0000FF00L
22604 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                               0x0F000000L
22605 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                  0x10000000L
22606 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                   0x20000000L
22607 //ATC_L2_PERFCOUNTER_RSLT_CNTL
22608 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                              0x0
22609 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                    0x8
22610 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                     0x10
22611 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                       0x18
22612 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                        0x19
22613 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                             0x1a
22614 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                0x0000000FL
22615 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                      0x0000FF00L
22616 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                       0x00FF0000L
22617 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                         0x01000000L
22618 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                          0x02000000L
22619 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                               0x04000000L
22620 
22621 
22622 // addressBlock: gc_utcl2_vml2pldec
22623 //MC_VM_L2_PERFCOUNTER0_CFG
22624 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                            0x0
22625 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                        0x8
22626 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                           0x18
22627 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                              0x1c
22628 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                               0x1d
22629 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                              0x000000FFL
22630 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22631 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                             0x0F000000L
22632 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                0x10000000L
22633 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                 0x20000000L
22634 //MC_VM_L2_PERFCOUNTER1_CFG
22635 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                            0x0
22636 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                        0x8
22637 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                           0x18
22638 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                              0x1c
22639 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                               0x1d
22640 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                              0x000000FFL
22641 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22642 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                             0x0F000000L
22643 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                0x10000000L
22644 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                 0x20000000L
22645 //MC_VM_L2_PERFCOUNTER2_CFG
22646 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                            0x0
22647 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                        0x8
22648 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                           0x18
22649 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                              0x1c
22650 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                               0x1d
22651 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                              0x000000FFL
22652 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22653 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                             0x0F000000L
22654 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                0x10000000L
22655 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                 0x20000000L
22656 //MC_VM_L2_PERFCOUNTER3_CFG
22657 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                            0x0
22658 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                        0x8
22659 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                           0x18
22660 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                              0x1c
22661 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                               0x1d
22662 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                              0x000000FFL
22663 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22664 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                             0x0F000000L
22665 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                0x10000000L
22666 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                 0x20000000L
22667 //MC_VM_L2_PERFCOUNTER4_CFG
22668 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                            0x0
22669 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                        0x8
22670 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                           0x18
22671 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                              0x1c
22672 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                               0x1d
22673 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                              0x000000FFL
22674 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22675 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                             0x0F000000L
22676 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                                0x10000000L
22677 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                                 0x20000000L
22678 //MC_VM_L2_PERFCOUNTER5_CFG
22679 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                            0x0
22680 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                        0x8
22681 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                           0x18
22682 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                              0x1c
22683 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                               0x1d
22684 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                              0x000000FFL
22685 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22686 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                             0x0F000000L
22687 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                                0x10000000L
22688 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                                 0x20000000L
22689 //MC_VM_L2_PERFCOUNTER6_CFG
22690 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                            0x0
22691 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                        0x8
22692 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                           0x18
22693 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                              0x1c
22694 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                               0x1d
22695 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                              0x000000FFL
22696 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22697 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                             0x0F000000L
22698 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                                0x10000000L
22699 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                                 0x20000000L
22700 //MC_VM_L2_PERFCOUNTER7_CFG
22701 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                            0x0
22702 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                        0x8
22703 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                           0x18
22704 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                              0x1c
22705 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                               0x1d
22706 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                              0x000000FFL
22707 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                          0x0000FF00L
22708 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                             0x0F000000L
22709 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                                0x10000000L
22710 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                                 0x20000000L
22711 //MC_VM_L2_PERFCOUNTER_RSLT_CNTL
22712 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                            0x0
22713 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                  0x8
22714 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                   0x10
22715 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                     0x18
22716 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                      0x19
22717 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                           0x1a
22718 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                              0x0000000FL
22719 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                    0x0000FF00L
22720 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                     0x00FF0000L
22721 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                       0x01000000L
22722 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                        0x02000000L
22723 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                             0x04000000L
22724 
22725 
22726 // addressBlock: gc_rlcpdec
22727 //RLC_CNTL
22728 #define RLC_CNTL__RLC_ENABLE_F32__SHIFT                                                                       0x0
22729 #define RLC_CNTL__FORCE_RETRY__SHIFT                                                                          0x1
22730 #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT                                                                   0x2
22731 #define RLC_CNTL__RLC_STEP_F32__SHIFT                                                                         0x3
22732 #define RLC_CNTL__RESERVED__SHIFT                                                                             0x4
22733 #define RLC_CNTL__RLC_ENABLE_F32_MASK                                                                         0x00000001L
22734 #define RLC_CNTL__FORCE_RETRY_MASK                                                                            0x00000002L
22735 #define RLC_CNTL__READ_CACHE_DISABLE_MASK                                                                     0x00000004L
22736 #define RLC_CNTL__RLC_STEP_F32_MASK                                                                           0x00000008L
22737 #define RLC_CNTL__RESERVED_MASK                                                                               0xFFFFFFF0L
22738 //RLC_STAT
22739 #define RLC_STAT__RLC_BUSY__SHIFT                                                                             0x0
22740 #define RLC_STAT__RLC_GPM_BUSY__SHIFT                                                                         0x1
22741 #define RLC_STAT__RLC_SPM_BUSY__SHIFT                                                                         0x2
22742 #define RLC_STAT__RLC_SRM_BUSY__SHIFT                                                                         0x3
22743 #define RLC_STAT__MC_BUSY__SHIFT                                                                              0x4
22744 #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT                                                                    0x5
22745 #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT                                                                    0x6
22746 #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT                                                                    0x7
22747 #define RLC_STAT__RESERVED__SHIFT                                                                             0x8
22748 #define RLC_STAT__RLC_BUSY_MASK                                                                               0x00000001L
22749 #define RLC_STAT__RLC_GPM_BUSY_MASK                                                                           0x00000002L
22750 #define RLC_STAT__RLC_SPM_BUSY_MASK                                                                           0x00000004L
22751 #define RLC_STAT__RLC_SRM_BUSY_MASK                                                                           0x00000008L
22752 #define RLC_STAT__MC_BUSY_MASK                                                                                0x00000010L
22753 #define RLC_STAT__RLC_THREAD_0_BUSY_MASK                                                                      0x00000020L
22754 #define RLC_STAT__RLC_THREAD_1_BUSY_MASK                                                                      0x00000040L
22755 #define RLC_STAT__RLC_THREAD_2_BUSY_MASK                                                                      0x00000080L
22756 #define RLC_STAT__RESERVED_MASK                                                                               0xFFFFFF00L
22757 //RLC_SAFE_MODE
22758 #define RLC_SAFE_MODE__CMD__SHIFT                                                                             0x0
22759 #define RLC_SAFE_MODE__MESSAGE__SHIFT                                                                         0x1
22760 #define RLC_SAFE_MODE__RESERVED1__SHIFT                                                                       0x5
22761 #define RLC_SAFE_MODE__RESPONSE__SHIFT                                                                        0x8
22762 #define RLC_SAFE_MODE__RESERVED__SHIFT                                                                        0xc
22763 #define RLC_SAFE_MODE__CMD_MASK                                                                               0x00000001L
22764 #define RLC_SAFE_MODE__MESSAGE_MASK                                                                           0x0000001EL
22765 #define RLC_SAFE_MODE__RESERVED1_MASK                                                                         0x000000E0L
22766 #define RLC_SAFE_MODE__RESPONSE_MASK                                                                          0x00000F00L
22767 #define RLC_SAFE_MODE__RESERVED_MASK                                                                          0xFFFFF000L
22768 //RLC_MEM_SLP_CNTL
22769 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT                                                                0x0
22770 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT                                                                0x1
22771 #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
22772 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT                                                      0x7
22773 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT                                                          0x8
22774 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT                                                         0x10
22775 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
22776 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK                                                                  0x00000001L
22777 #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK                                                                  0x00000002L
22778 #define RLC_MEM_SLP_CNTL__RESERVED_MASK                                                                       0x0000007CL
22779 #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK                                                        0x00000080L
22780 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK                                                            0x0000FF00L
22781 #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK                                                           0x00FF0000L
22782 #define RLC_MEM_SLP_CNTL__RESERVED1_MASK                                                                      0xFF000000L
22783 //SMU_RLC_RESPONSE
22784 #define SMU_RLC_RESPONSE__RESP__SHIFT                                                                         0x0
22785 #define SMU_RLC_RESPONSE__RESP_MASK                                                                           0xFFFFFFFFL
22786 //RLC_RLCV_SAFE_MODE
22787 #define RLC_RLCV_SAFE_MODE__CMD__SHIFT                                                                        0x0
22788 #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT                                                                    0x1
22789 #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT                                                                  0x5
22790 #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT                                                                   0x8
22791 #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT                                                                   0xc
22792 #define RLC_RLCV_SAFE_MODE__CMD_MASK                                                                          0x00000001L
22793 #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK                                                                      0x0000001EL
22794 #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK                                                                    0x000000E0L
22795 #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK                                                                     0x00000F00L
22796 #define RLC_RLCV_SAFE_MODE__RESERVED_MASK                                                                     0xFFFFF000L
22797 //RLC_SMU_SAFE_MODE
22798 #define RLC_SMU_SAFE_MODE__CMD__SHIFT                                                                         0x0
22799 #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT                                                                     0x1
22800 #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT                                                                   0x5
22801 #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT                                                                    0x8
22802 #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT                                                                    0xc
22803 #define RLC_SMU_SAFE_MODE__CMD_MASK                                                                           0x00000001L
22804 #define RLC_SMU_SAFE_MODE__MESSAGE_MASK                                                                       0x0000001EL
22805 #define RLC_SMU_SAFE_MODE__RESERVED1_MASK                                                                     0x000000E0L
22806 #define RLC_SMU_SAFE_MODE__RESPONSE_MASK                                                                      0x00000F00L
22807 #define RLC_SMU_SAFE_MODE__RESERVED_MASK                                                                      0xFFFFF000L
22808 //RLC_RLCV_COMMAND
22809 #define RLC_RLCV_COMMAND__CMD__SHIFT                                                                          0x0
22810 #define RLC_RLCV_COMMAND__RESERVED__SHIFT                                                                     0x4
22811 #define RLC_RLCV_COMMAND__CMD_MASK                                                                            0x0000000FL
22812 #define RLC_RLCV_COMMAND__RESERVED_MASK                                                                       0xFFFFFFF0L
22813 //RLC_REFCLOCK_TIMESTAMP_LSB
22814 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT                                                      0x0
22815 #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK                                                        0xFFFFFFFFL
22816 //RLC_REFCLOCK_TIMESTAMP_MSB
22817 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT                                                      0x0
22818 #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK                                                        0xFFFFFFFFL
22819 //RLC_GPM_TIMER_INT_0
22820 #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT                                                                     0x0
22821 #define RLC_GPM_TIMER_INT_0__TIMER_MASK                                                                       0xFFFFFFFFL
22822 //RLC_GPM_TIMER_INT_1
22823 #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT                                                                     0x0
22824 #define RLC_GPM_TIMER_INT_1__TIMER_MASK                                                                       0xFFFFFFFFL
22825 //RLC_GPM_TIMER_INT_2
22826 #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT                                                                     0x0
22827 #define RLC_GPM_TIMER_INT_2__TIMER_MASK                                                                       0xFFFFFFFFL
22828 //RLC_GPM_TIMER_CTRL
22829 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                 0x0
22830 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT                                                                 0x1
22831 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT                                                                 0x2
22832 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT                                                                 0x3
22833 #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT                                                                   0x4
22834 #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK                                                                   0x00000001L
22835 #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK                                                                   0x00000002L
22836 #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK                                                                   0x00000004L
22837 #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK                                                                   0x00000008L
22838 #define RLC_GPM_TIMER_CTRL__RESERVED_MASK                                                                     0xFFFFFFF0L
22839 //RLC_LB_CNTR_MAX
22840 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT                                                                   0x0
22841 #define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK                                                                     0xFFFFFFFFL
22842 //RLC_GPM_TIMER_STAT
22843 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT                                                               0x0
22844 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT                                                               0x1
22845 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT                                                               0x2
22846 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT                                                               0x3
22847 #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT                                                                   0x4
22848 #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK                                                                 0x00000001L
22849 #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK                                                                 0x00000002L
22850 #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK                                                                 0x00000004L
22851 #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK                                                                 0x00000008L
22852 #define RLC_GPM_TIMER_STAT__RESERVED_MASK                                                                     0xFFFFFFF0L
22853 //RLC_GPM_TIMER_INT_3
22854 #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT                                                                     0x0
22855 #define RLC_GPM_TIMER_INT_3__TIMER_MASK                                                                       0xFFFFFFFFL
22856 //RLC_SERDES_WR_NONCU_MASTER_MASK_1
22857 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT                                            0x0
22858 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT                                            0x10
22859 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT                                        0x11
22860 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT                                           0x12
22861 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT                                                  0x13
22862 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT                                          0x14
22863 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT                                          0x15
22864 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT                                          0x16
22865 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT                                          0x17
22866 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT                                            0x18
22867 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT                                                    0x19
22868 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK                                              0x0000FFFFL
22869 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK                                              0x00010000L
22870 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK                                          0x00020000L
22871 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK                                             0x00040000L
22872 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK                                                    0x00080000L
22873 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK                                            0x00100000L
22874 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK                                            0x00200000L
22875 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK                                            0x00400000L
22876 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK                                            0x00800000L
22877 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK                                              0x01000000L
22878 #define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK                                                      0xFE000000L
22879 //RLC_SERDES_NONCU_MASTER_BUSY_1
22880 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT                                               0x0
22881 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT                                               0x10
22882 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT                                           0x11
22883 #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT                                              0x12
22884 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT                                                     0x13
22885 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT                                             0x14
22886 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT                                             0x15
22887 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT                                             0x16
22888 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT                                             0x17
22889 #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT                                               0x18
22890 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT                                                       0x19
22891 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK                                                 0x0000FFFFL
22892 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK                                                 0x00010000L
22893 #define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK                                             0x00020000L
22894 #define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK                                                0x00040000L
22895 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK                                                       0x00080000L
22896 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK                                               0x00100000L
22897 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK                                               0x00200000L
22898 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK                                               0x00400000L
22899 #define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK                                               0x00800000L
22900 #define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK                                                 0x01000000L
22901 #define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK                                                         0xFE000000L
22902 //RLC_INT_STAT
22903 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT                                                               0x0
22904 #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT                                                               0x8
22905 #define RLC_INT_STAT__RESERVED__SHIFT                                                                         0x9
22906 #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK                                                                 0x000000FFL
22907 #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK                                                                 0x00000100L
22908 #define RLC_INT_STAT__RESERVED_MASK                                                                           0xFFFFFE00L
22909 //RLC_LB_CNTL
22910 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT                                                               0x0
22911 #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT                                                                    0x1
22912 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT                                                                0x2
22913 #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT                                                                    0x3
22914 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT                                                             0x4
22915 #define RLC_LB_CNTL__RESERVED__SHIFT                                                                          0xc
22916 #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK                                                                 0x00000001L
22917 #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK                                                                      0x00000002L
22918 #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK                                                                  0x00000004L
22919 #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK                                                                      0x00000008L
22920 #define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK                                                               0x00000FF0L
22921 #define RLC_LB_CNTL__RESERVED_MASK                                                                            0xFFFFF000L
22922 //RLC_MGCG_CTRL
22923 #define RLC_MGCG_CTRL__MGCG_EN__SHIFT                                                                         0x0
22924 #define RLC_MGCG_CTRL__SILICON_EN__SHIFT                                                                      0x1
22925 #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT                                                                   0x2
22926 #define RLC_MGCG_CTRL__ON_DELAY__SHIFT                                                                        0x3
22927 #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT                                                                  0x7
22928 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT                                                            0xf
22929 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT                                                            0x10
22930 #define RLC_MGCG_CTRL__SPARE__SHIFT                                                                           0x11
22931 #define RLC_MGCG_CTRL__MGCG_EN_MASK                                                                           0x00000001L
22932 #define RLC_MGCG_CTRL__SILICON_EN_MASK                                                                        0x00000002L
22933 #define RLC_MGCG_CTRL__SIMULATION_EN_MASK                                                                     0x00000004L
22934 #define RLC_MGCG_CTRL__ON_DELAY_MASK                                                                          0x00000078L
22935 #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK                                                                    0x00007F80L
22936 #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK                                                              0x00008000L
22937 #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK                                                              0x00010000L
22938 #define RLC_MGCG_CTRL__SPARE_MASK                                                                             0xFFFE0000L
22939 //RLC_LB_CNTR_INIT
22940 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT                                                                 0x0
22941 #define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK                                                                   0xFFFFFFFFL
22942 //RLC_LOAD_BALANCE_CNTR
22943 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT                                                   0x0
22944 #define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK                                                     0xFFFFFFFFL
22945 //RLC_JUMP_TABLE_RESTORE
22946 #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT                                                                   0x0
22947 #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK                                                                     0xFFFFFFFFL
22948 //RLC_PG_DELAY_2
22949 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT                                                           0x0
22950 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT                                                               0x8
22951 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT                                                            0x10
22952 #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK                                                             0x000000FFL
22953 #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK                                                                 0x0000FF00L
22954 #define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK                                                              0xFFFF0000L
22955 //RLC_GPU_CLOCK_COUNT_LSB
22956 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT                                                        0x0
22957 #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK                                                          0xFFFFFFFFL
22958 //RLC_GPU_CLOCK_COUNT_MSB
22959 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT                                                        0x0
22960 #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK                                                          0xFFFFFFFFL
22961 //RLC_CAPTURE_GPU_CLOCK_COUNT
22962 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT                                                           0x0
22963 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT                                                          0x1
22964 #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK                                                             0x00000001L
22965 #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK                                                            0xFFFFFFFEL
22966 //RLC_UCODE_CNTL
22967 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT                                                                0x0
22968 #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK                                                                  0xFFFFFFFFL
22969 //RLC_GPM_THREAD_RESET
22970 #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT                                                            0x0
22971 #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT                                                            0x1
22972 #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT                                                            0x2
22973 #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT                                                            0x3
22974 #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT                                                                 0x4
22975 #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK                                                              0x00000001L
22976 #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK                                                              0x00000002L
22977 #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK                                                              0x00000004L
22978 #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK                                                              0x00000008L
22979 #define RLC_GPM_THREAD_RESET__RESERVED_MASK                                                                   0xFFFFFFF0L
22980 //RLC_GPM_CP_DMA_COMPLETE_T0
22981 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT                                                               0x0
22982 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT                                                           0x1
22983 #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK                                                                 0x00000001L
22984 #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK                                                             0xFFFFFFFEL
22985 //RLC_GPM_CP_DMA_COMPLETE_T1
22986 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT                                                               0x0
22987 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT                                                           0x1
22988 #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK                                                                 0x00000001L
22989 #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK                                                             0xFFFFFFFEL
22990 //RLC_FIREWALL_VIOLATION
22991 #define RLC_FIREWALL_VIOLATION__ADDR__SHIFT                                                                   0x0
22992 #define RLC_FIREWALL_VIOLATION__ADDR_MASK                                                                     0xFFFFFFFFL
22993 //RLC_GPM_STAT
22994 #define RLC_GPM_STAT__RLC_BUSY__SHIFT                                                                         0x0
22995 #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT                                                                 0x1
22996 #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT                                                                 0x2
22997 #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT                                                                    0x3
22998 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT                                                        0x4
22999 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT                                                        0x5
23000 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT                                                        0x6
23001 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT                                                         0x7
23002 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT                                                         0x8
23003 #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT                                                                 0x9
23004 #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT                                                              0xa
23005 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                0xb
23006 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT                                                  0xc
23007 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT                                                            0xd
23008 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT                                                          0xe
23009 #define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT                                                               0xf
23010 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT                                                             0x10
23011 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT                                                              0x11
23012 #define RLC_GPM_STAT__CMP_power_status__SHIFT                                                                 0x12
23013 #define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT                                                                 0x13
23014 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT                                                              0x14
23015 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT                                                             0x15
23016 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT                                                                0x16
23017 #define RLC_GPM_STAT__RESERVED__SHIFT                                                                         0x17
23018 #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT                                                                  0x18
23019 #define RLC_GPM_STAT__RLC_BUSY_MASK                                                                           0x00000001L
23020 #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK                                                                   0x00000002L
23021 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK                                                                   0x00000004L
23022 #define RLC_GPM_STAT__GFX_LS_STATUS_MASK                                                                      0x00000008L
23023 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK                                                          0x00000010L
23024 #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK                                                          0x00000020L
23025 #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK                                                          0x00000040L
23026 #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK                                                           0x00000080L
23027 #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK                                                           0x00000100L
23028 #define RLC_GPM_STAT__SAVING_REGISTERS_MASK                                                                   0x00000200L
23029 #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK                                                                0x00000400L
23030 #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK                                                  0x00000800L
23031 #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK                                                    0x00001000L
23032 #define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK                                                              0x00002000L
23033 #define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK                                                            0x00004000L
23034 #define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK                                                                 0x00008000L
23035 #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK                                                               0x00010000L
23036 #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK                                                                0x00020000L
23037 #define RLC_GPM_STAT__CMP_power_status_MASK                                                                   0x00040000L
23038 #define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK                                                                   0x00080000L
23039 #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK                                                                0x00100000L
23040 #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK                                                               0x00200000L
23041 #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK                                                                  0x00400000L
23042 #define RLC_GPM_STAT__RESERVED_MASK                                                                           0x00800000L
23043 #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK                                                                    0xFF000000L
23044 //RLC_GPU_CLOCK_32_RES_SEL
23045 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT                                                              0x0
23046 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT                                                             0x6
23047 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK                                                                0x0000003FL
23048 #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK                                                               0xFFFFFFC0L
23049 //RLC_GPU_CLOCK_32
23050 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT                                                                 0x0
23051 #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK                                                                   0xFFFFFFFFL
23052 //RLC_PG_CNTL
23053 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT                                                           0x0
23054 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT                                                              0x1
23055 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT                                                              0x2
23056 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT                                                           0x3
23057 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT                                                            0x4
23058 #define RLC_PG_CNTL__RESERVED__SHIFT                                                                          0x5
23059 #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT                                                                       0xe
23060 #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT                                                                     0xf
23061 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT                                                             0x10
23062 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT                                                     0x11
23063 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT                                                     0x12
23064 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT                                                              0x13
23065 #define RLC_PG_CNTL__RESERVED1__SHIFT                                                                         0x14
23066 #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK                                                             0x00000001L
23067 #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK                                                                0x00000002L
23068 #define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK                                                                0x00000004L
23069 #define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK                                                             0x00000008L
23070 #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK                                                              0x00000010L
23071 #define RLC_PG_CNTL__RESERVED_MASK                                                                            0x00003FE0L
23072 #define RLC_PG_CNTL__PG_OVERRIDE_MASK                                                                         0x00004000L
23073 #define RLC_PG_CNTL__CP_PG_DISABLE_MASK                                                                       0x00008000L
23074 #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK                                                               0x00010000L
23075 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK                                                       0x00020000L
23076 #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK                                                       0x00040000L
23077 #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK                                                                0x00080000L
23078 #define RLC_PG_CNTL__RESERVED1_MASK                                                                           0x00F00000L
23079 //RLC_GPM_THREAD_PRIORITY
23080 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT                                                      0x0
23081 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT                                                      0x8
23082 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT                                                      0x10
23083 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT                                                      0x18
23084 #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK                                                        0x000000FFL
23085 #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK                                                        0x0000FF00L
23086 #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK                                                        0x00FF0000L
23087 #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK                                                        0xFF000000L
23088 //RLC_GPM_THREAD_ENABLE
23089 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT                                                          0x0
23090 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT                                                          0x1
23091 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT                                                          0x2
23092 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT                                                          0x3
23093 #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT                                                                0x4
23094 #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK                                                            0x00000001L
23095 #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK                                                            0x00000002L
23096 #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK                                                            0x00000004L
23097 #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK                                                            0x00000008L
23098 #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK                                                                  0xFFFFFFF0L
23099 //RLC_CGTT_MGCG_OVERRIDE
23100 #define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT                                                 0x0
23101 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT                                                 0x1
23102 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT                                                    0x2
23103 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT                                                    0x3
23104 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT                                                    0x4
23105 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT                                                0x5
23106 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT                                                    0x6
23107 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT                                                0x7
23108 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT                                                               0x8
23109 #define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK                                                   0x00000001L
23110 #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK                                                   0x00000002L
23111 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK                                                      0x00000004L
23112 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK                                                      0x00000008L
23113 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK                                                      0x00000010L
23114 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK                                                  0x00000020L
23115 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK                                                      0x00000040L
23116 #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK                                                  0x00000080L
23117 #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK                                                                 0xFFFFFF00L
23118 //RLC_CGCG_CGLS_CTRL
23119 #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT                                                                    0x0
23120 #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT                                                                    0x1
23121 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                   0x2
23122 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                    0x8
23123 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT                                                            0x1b
23124 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT                                                              0x1c
23125 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT                                                                 0x1d
23126 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT                                                             0x1f
23127 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK                                                                      0x00000001L
23128 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK                                                                      0x00000002L
23129 #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK                                                     0x000000FCL
23130 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK                                                      0x07FFFF00L
23131 #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK                                                              0x08000000L
23132 #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK                                                                0x10000000L
23133 #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK                                                                   0x60000000L
23134 #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK                                                               0x80000000L
23135 //RLC_CGCG_RAMP_CTRL
23136 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT                                                        0x0
23137 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT                                                         0x4
23138 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT                                                          0x8
23139 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT                                                           0xc
23140 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT                                                             0x10
23141 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT                                                            0x1c
23142 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK                                                          0x0000000FL
23143 #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK                                                           0x000000F0L
23144 #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK                                                            0x00000F00L
23145 #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK                                                             0x0000F000L
23146 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK                                                               0x0FFF0000L
23147 #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK                                                              0xF0000000L
23148 //RLC_DYN_PG_STATUS
23149 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT                                                           0x0
23150 #define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK                                                             0xFFFFFFFFL
23151 //RLC_DYN_PG_REQUEST
23152 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT                                                         0x0
23153 #define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK                                                           0xFFFFFFFFL
23154 //RLC_PG_DELAY
23155 #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT                                                                   0x0
23156 #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT                                                                 0x8
23157 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT                                                              0x10
23158 #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT                                                                  0x18
23159 #define RLC_PG_DELAY__POWER_UP_DELAY_MASK                                                                     0x000000FFL
23160 #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK                                                                   0x0000FF00L
23161 #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK                                                                0x00FF0000L
23162 #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK                                                                    0xFF000000L
23163 //RLC_CU_STATUS
23164 #define RLC_CU_STATUS__WORK_PENDING__SHIFT                                                                    0x0
23165 #define RLC_CU_STATUS__WORK_PENDING_MASK                                                                      0xFFFFFFFFL
23166 //RLC_LB_INIT_CU_MASK
23167 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT                                                              0x0
23168 #define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK                                                                0xFFFFFFFFL
23169 //RLC_LB_ALWAYS_ACTIVE_CU_MASK
23170 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT                                            0x0
23171 #define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK                                              0xFFFFFFFFL
23172 //RLC_LB_PARAMS
23173 #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT                                                                   0x0
23174 #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT                                                                    0x1
23175 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT                                                                 0x8
23176 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT                                                         0x10
23177 #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK                                                                     0x00000001L
23178 #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK                                                                      0x000000FEL
23179 #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK                                                                   0x0000FF00L
23180 #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK                                                           0xFFFF0000L
23181 //RLC_THREAD1_DELAY
23182 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT                                                               0x0
23183 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT                                                       0x8
23184 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT                                                       0x10
23185 #define RLC_THREAD1_DELAY__SPARE__SHIFT                                                                       0x18
23186 #define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK                                                                 0x000000FFL
23187 #define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK                                                         0x0000FF00L
23188 #define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK                                                         0x00FF0000L
23189 #define RLC_THREAD1_DELAY__SPARE_MASK                                                                         0xFF000000L
23190 //RLC_PG_ALWAYS_ON_CU_MASK
23191 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT                                                          0x0
23192 #define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK                                                            0xFFFFFFFFL
23193 //RLC_MAX_PG_CU
23194 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT                                                               0x0
23195 #define RLC_MAX_PG_CU__SPARE__SHIFT                                                                           0x8
23196 #define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK                                                                 0x000000FFL
23197 #define RLC_MAX_PG_CU__SPARE_MASK                                                                             0xFFFFFF00L
23198 //RLC_AUTO_PG_CTRL
23199 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT                                                                   0x0
23200 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT                                                0x1
23201 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT                                                              0x2
23202 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT                                             0x3
23203 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT                                             0x13
23204 #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK                                                                     0x00000001L
23205 #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK                                                  0x00000002L
23206 #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK                                                                0x00000004L
23207 #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK                                               0x0007FFF8L
23208 #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK                                               0xFFF80000L
23209 //RLC_SMU_GRBM_REG_SAVE_CTRL
23210 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT                                                0x0
23211 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT                                                              0x1
23212 #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK                                                  0x00000001L
23213 #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK                                                                0xFFFFFFFEL
23214 //RLC_SERDES_RD_MASTER_INDEX
23215 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT                                                              0x0
23216 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT                                                              0x4
23217 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT                                                              0x6
23218 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT                                                        0x9
23219 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT                                                           0xc
23220 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT                                                             0xd
23221 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT                                                        0x11
23222 #define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT                                                              0x13
23223 #define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK                                                                0x0000000FL
23224 #define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK                                                                0x00000030L
23225 #define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK                                                                0x000001C0L
23226 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK                                                          0x00000E00L
23227 #define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK                                                             0x00001000L
23228 #define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK                                                               0x0001E000L
23229 #define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK                                                          0x00060000L
23230 #define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK                                                                0xFFF80000L
23231 //RLC_SERDES_RD_DATA_0
23232 #define RLC_SERDES_RD_DATA_0__DATA__SHIFT                                                                     0x0
23233 #define RLC_SERDES_RD_DATA_0__DATA_MASK                                                                       0xFFFFFFFFL
23234 //RLC_SERDES_RD_DATA_1
23235 #define RLC_SERDES_RD_DATA_1__DATA__SHIFT                                                                     0x0
23236 #define RLC_SERDES_RD_DATA_1__DATA_MASK                                                                       0xFFFFFFFFL
23237 //RLC_SERDES_RD_DATA_2
23238 #define RLC_SERDES_RD_DATA_2__DATA__SHIFT                                                                     0x0
23239 #define RLC_SERDES_RD_DATA_2__DATA_MASK                                                                       0xFFFFFFFFL
23240 //RLC_SERDES_WR_CU_MASTER_MASK
23241 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT                                                      0x0
23242 #define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK                                                        0xFFFFFFFFL
23243 //RLC_SERDES_WR_NONCU_MASTER_MASK
23244 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT                                                0x0
23245 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT                                                0x10
23246 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT                                            0x11
23247 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT                                               0x12
23248 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT                                               0x13
23249 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT                                            0x14
23250 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT                                            0x15
23251 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT                                            0x16
23252 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT                                            0x17
23253 #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT                                              0x18
23254 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT                                               0x19
23255 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT                                                      0x1a
23256 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK                                                  0x0000FFFFL
23257 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK                                                  0x00010000L
23258 #define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK                                              0x00020000L
23259 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK                                                 0x00040000L
23260 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK                                                 0x00080000L
23261 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK                                              0x00100000L
23262 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK                                              0x00200000L
23263 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK                                              0x00400000L
23264 #define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK                                              0x00800000L
23265 #define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK                                                0x01000000L
23266 #define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK                                                 0x02000000L
23267 #define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK                                                        0xFC000000L
23268 //RLC_SERDES_WR_CTRL
23269 #define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT                                                                   0x0
23270 #define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT                                                                 0x8
23271 #define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT                                                                   0x9
23272 #define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT                                                                  0xa
23273 #define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT                                                                  0xb
23274 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT                                                              0xc
23275 #define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT                                                               0xd
23276 #define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT                                                               0xe
23277 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT                                                               0xf
23278 #define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT                                                                   0x10
23279 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT                                                              0x1a
23280 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT                                                              0x1b
23281 #define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT                                                                   0x1c
23282 #define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK                                                                     0x000000FFL
23283 #define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK                                                                   0x00000100L
23284 #define RLC_SERDES_WR_CTRL__POWER_UP_MASK                                                                     0x00000200L
23285 #define RLC_SERDES_WR_CTRL__P1_SELECT_MASK                                                                    0x00000400L
23286 #define RLC_SERDES_WR_CTRL__P2_SELECT_MASK                                                                    0x00000800L
23287 #define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK                                                                0x00001000L
23288 #define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK                                                                 0x00002000L
23289 #define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK                                                                 0x00004000L
23290 #define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK                                                                 0x00008000L
23291 #define RLC_SERDES_WR_CTRL__BPM_DATA_MASK                                                                     0x03FF0000L
23292 #define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK                                                                0x04000000L
23293 #define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK                                                                0x08000000L
23294 #define RLC_SERDES_WR_CTRL__REG_ADDR_MASK                                                                     0xF0000000L
23295 //RLC_SERDES_WR_DATA
23296 #define RLC_SERDES_WR_DATA__DATA__SHIFT                                                                       0x0
23297 #define RLC_SERDES_WR_DATA__DATA_MASK                                                                         0xFFFFFFFFL
23298 //RLC_SERDES_CU_MASTER_BUSY
23299 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT                                                           0x0
23300 #define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK                                                             0xFFFFFFFFL
23301 //RLC_SERDES_NONCU_MASTER_BUSY
23302 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT                                                   0x0
23303 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT                                                   0x10
23304 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT                                               0x11
23305 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT                                                  0x12
23306 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT                                                  0x13
23307 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT                                               0x14
23308 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT                                               0x15
23309 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT                                               0x16
23310 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT                                               0x17
23311 #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT                                                 0x18
23312 #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT                                                  0x19
23313 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT                                                         0x1a
23314 #define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK                                                     0x0000FFFFL
23315 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK                                                     0x00010000L
23316 #define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK                                                 0x00020000L
23317 #define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK                                                    0x00040000L
23318 #define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK                                                    0x00080000L
23319 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK                                                 0x00100000L
23320 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK                                                 0x00200000L
23321 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK                                                 0x00400000L
23322 #define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK                                                 0x00800000L
23323 #define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK                                                   0x01000000L
23324 #define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK                                                    0x02000000L
23325 #define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK                                                           0xFC000000L
23326 //RLC_GPM_GENERAL_0
23327 #define RLC_GPM_GENERAL_0__DATA__SHIFT                                                                        0x0
23328 #define RLC_GPM_GENERAL_0__DATA_MASK                                                                          0xFFFFFFFFL
23329 //RLC_GPM_GENERAL_1
23330 #define RLC_GPM_GENERAL_1__DATA__SHIFT                                                                        0x0
23331 #define RLC_GPM_GENERAL_1__DATA_MASK                                                                          0xFFFFFFFFL
23332 //RLC_GPM_GENERAL_2
23333 #define RLC_GPM_GENERAL_2__DATA__SHIFT                                                                        0x0
23334 #define RLC_GPM_GENERAL_2__DATA_MASK                                                                          0xFFFFFFFFL
23335 //RLC_GPM_GENERAL_3
23336 #define RLC_GPM_GENERAL_3__DATA__SHIFT                                                                        0x0
23337 #define RLC_GPM_GENERAL_3__DATA_MASK                                                                          0xFFFFFFFFL
23338 //RLC_GPM_GENERAL_4
23339 #define RLC_GPM_GENERAL_4__DATA__SHIFT                                                                        0x0
23340 #define RLC_GPM_GENERAL_4__DATA_MASK                                                                          0xFFFFFFFFL
23341 //RLC_GPM_GENERAL_5
23342 #define RLC_GPM_GENERAL_5__DATA__SHIFT                                                                        0x0
23343 #define RLC_GPM_GENERAL_5__DATA_MASK                                                                          0xFFFFFFFFL
23344 //RLC_GPM_GENERAL_6
23345 #define RLC_GPM_GENERAL_6__DATA__SHIFT                                                                        0x0
23346 #define RLC_GPM_GENERAL_6__DATA_MASK                                                                          0xFFFFFFFFL
23347 //RLC_GPM_GENERAL_7
23348 #define RLC_GPM_GENERAL_7__DATA__SHIFT                                                                        0x0
23349 #define RLC_GPM_GENERAL_7__DATA_MASK                                                                          0xFFFFFFFFL
23350 //RLC_GPM_SCRATCH_ADDR
23351 #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT                                                                     0x0
23352 #define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT                                                                 0x9
23353 #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK                                                                       0x000001FFL
23354 #define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK                                                                   0xFFFFFE00L
23355 //RLC_GPM_SCRATCH_DATA
23356 #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT                                                                     0x0
23357 #define RLC_GPM_SCRATCH_DATA__DATA_MASK                                                                       0xFFFFFFFFL
23358 //RLC_STATIC_PG_STATUS
23359 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT                                                        0x0
23360 #define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK                                                          0xFFFFFFFFL
23361 //RLC_SPM_MC_CNTL
23362 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT                                                                  0x0
23363 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT                                                                0x4
23364 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT                                                             0x5
23365 #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT                                                                   0x6
23366 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT                                                            0x7
23367 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT                                                                 0x8
23368 #define RLC_SPM_MC_CNTL__RESERVED__SHIFT                                                                      0xa
23369 #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK                                                                    0x0000000FL
23370 #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK                                                                  0x00000010L
23371 #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK                                                               0x00000020L
23372 #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK                                                                     0x00000040L
23373 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK                                                              0x00000080L
23374 #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK                                                                   0x00000300L
23375 #define RLC_SPM_MC_CNTL__RESERVED_MASK                                                                        0xFFFFFC00L
23376 //RLC_SPM_INT_CNTL
23377 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT                                                             0x0
23378 #define RLC_SPM_INT_CNTL__RESERVED__SHIFT                                                                     0x1
23379 #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK                                                               0x00000001L
23380 #define RLC_SPM_INT_CNTL__RESERVED_MASK                                                                       0xFFFFFFFEL
23381 //RLC_SPM_INT_STATUS
23382 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT                                                         0x0
23383 #define RLC_SPM_INT_STATUS__RESERVED__SHIFT                                                                   0x1
23384 #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK                                                           0x00000001L
23385 #define RLC_SPM_INT_STATUS__RESERVED_MASK                                                                     0xFFFFFFFEL
23386 //RLC_SMU_MESSAGE
23387 #define RLC_SMU_MESSAGE__CMD__SHIFT                                                                           0x0
23388 #define RLC_SMU_MESSAGE__CMD_MASK                                                                             0xFFFFFFFFL
23389 //RLC_GPM_LOG_SIZE
23390 #define RLC_GPM_LOG_SIZE__SIZE__SHIFT                                                                         0x0
23391 #define RLC_GPM_LOG_SIZE__SIZE_MASK                                                                           0xFFFFFFFFL
23392 //RLC_PG_DELAY_3
23393 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT                                                        0x0
23394 #define RLC_PG_DELAY_3__RESERVED__SHIFT                                                                       0x8
23395 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK                                                          0x000000FFL
23396 #define RLC_PG_DELAY_3__RESERVED_MASK                                                                         0xFFFFFF00L
23397 //RLC_GPR_REG1
23398 #define RLC_GPR_REG1__DATA__SHIFT                                                                             0x0
23399 #define RLC_GPR_REG1__DATA_MASK                                                                               0xFFFFFFFFL
23400 //RLC_GPR_REG2
23401 #define RLC_GPR_REG2__DATA__SHIFT                                                                             0x0
23402 #define RLC_GPR_REG2__DATA_MASK                                                                               0xFFFFFFFFL
23403 //RLC_GPM_LOG_CONT
23404 #define RLC_GPM_LOG_CONT__CONT__SHIFT                                                                         0x0
23405 #define RLC_GPM_LOG_CONT__CONT_MASK                                                                           0xFFFFFFFFL
23406 //RLC_GPM_INT_DISABLE_TH0
23407 #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT                                                               0x0
23408 #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK                                                                 0xFFFFFFFFL
23409 //RLC_GPM_INT_DISABLE_TH1
23410 #define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT                                                               0x0
23411 #define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK                                                                 0xFFFFFFFFL
23412 //RLC_GPM_INT_FORCE_TH0
23413 #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT                                                                   0x0
23414 #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK                                                                     0xFFFFFFFFL
23415 //RLC_GPM_INT_FORCE_TH1
23416 #define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT                                                                   0x0
23417 #define RLC_GPM_INT_FORCE_TH1__FORCE_MASK                                                                     0xFFFFFFFFL
23418 //RLC_SRM_CNTL
23419 #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT                                                                       0x0
23420 #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT                                                                   0x1
23421 #define RLC_SRM_CNTL__RESERVED__SHIFT                                                                         0x2
23422 #define RLC_SRM_CNTL__SRM_ENABLE_MASK                                                                         0x00000001L
23423 #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK                                                                     0x00000002L
23424 #define RLC_SRM_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
23425 //RLC_SRM_ARAM_ADDR
23426 #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT                                                                        0x0
23427 #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT                                                                    0xc
23428 #define RLC_SRM_ARAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
23429 #define RLC_SRM_ARAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
23430 //RLC_SRM_ARAM_DATA
23431 #define RLC_SRM_ARAM_DATA__DATA__SHIFT                                                                        0x0
23432 #define RLC_SRM_ARAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
23433 //RLC_SRM_DRAM_ADDR
23434 #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT                                                                        0x0
23435 #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT                                                                    0xc
23436 #define RLC_SRM_DRAM_ADDR__ADDR_MASK                                                                          0x00000FFFL
23437 #define RLC_SRM_DRAM_ADDR__RESERVED_MASK                                                                      0xFFFFF000L
23438 //RLC_SRM_DRAM_DATA
23439 #define RLC_SRM_DRAM_DATA__DATA__SHIFT                                                                        0x0
23440 #define RLC_SRM_DRAM_DATA__DATA_MASK                                                                          0xFFFFFFFFL
23441 //RLC_SRM_GPM_COMMAND
23442 #define RLC_SRM_GPM_COMMAND__OP__SHIFT                                                                        0x0
23443 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT                                                                0x1
23444 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT                                                            0x2
23445 #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT                                                                      0x5
23446 #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT                                                              0x11
23447 #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT                                                                 0x1d
23448 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT                                                               0x1f
23449 #define RLC_SRM_GPM_COMMAND__OP_MASK                                                                          0x00000001L
23450 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK                                                                  0x00000002L
23451 #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK                                                              0x0000001CL
23452 #define RLC_SRM_GPM_COMMAND__SIZE_MASK                                                                        0x0001FFE0L
23453 #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK                                                                0x1FFE0000L
23454 #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK                                                                   0x60000000L
23455 #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK                                                                 0x80000000L
23456 //RLC_SRM_GPM_COMMAND_STATUS
23457 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                         0x0
23458 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT                                                          0x1
23459 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT                                                           0x2
23460 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK                                                           0x00000001L
23461 #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK                                                            0x00000002L
23462 #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK                                                             0xFFFFFFFCL
23463 //RLC_SRM_RLCV_COMMAND
23464 #define RLC_SRM_RLCV_COMMAND__OP__SHIFT                                                                       0x0
23465 #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT                                                                 0x1
23466 #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT                                                                     0x4
23467 #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT                                                             0x10
23468 #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT                                                                0x1c
23469 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT                                                              0x1f
23470 #define RLC_SRM_RLCV_COMMAND__OP_MASK                                                                         0x00000001L
23471 #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK                                                                   0x0000000EL
23472 #define RLC_SRM_RLCV_COMMAND__SIZE_MASK                                                                       0x0000FFF0L
23473 #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK                                                               0x0FFF0000L
23474 #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK                                                                  0x70000000L
23475 #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK                                                                0x80000000L
23476 //RLC_SRM_RLCV_COMMAND_STATUS
23477 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT                                                        0x0
23478 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT                                                         0x1
23479 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT                                                          0x2
23480 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK                                                          0x00000001L
23481 #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK                                                           0x00000002L
23482 #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK                                                            0xFFFFFFFCL
23483 //RLC_SRM_INDEX_CNTL_ADDR_0
23484 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT                                                             0x0
23485 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT                                                            0x10
23486 #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK                                                               0x0000FFFFL
23487 #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK                                                              0xFFFF0000L
23488 //RLC_SRM_INDEX_CNTL_ADDR_1
23489 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT                                                             0x0
23490 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT                                                            0x10
23491 #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK                                                               0x0000FFFFL
23492 #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK                                                              0xFFFF0000L
23493 //RLC_SRM_INDEX_CNTL_ADDR_2
23494 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT                                                             0x0
23495 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT                                                            0x10
23496 #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK                                                               0x0000FFFFL
23497 #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK                                                              0xFFFF0000L
23498 //RLC_SRM_INDEX_CNTL_ADDR_3
23499 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT                                                             0x0
23500 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT                                                            0x10
23501 #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK                                                               0x0000FFFFL
23502 #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK                                                              0xFFFF0000L
23503 //RLC_SRM_INDEX_CNTL_ADDR_4
23504 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT                                                             0x0
23505 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT                                                            0x10
23506 #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK                                                               0x0000FFFFL
23507 #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK                                                              0xFFFF0000L
23508 //RLC_SRM_INDEX_CNTL_ADDR_5
23509 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT                                                             0x0
23510 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT                                                            0x10
23511 #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK                                                               0x0000FFFFL
23512 #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK                                                              0xFFFF0000L
23513 //RLC_SRM_INDEX_CNTL_ADDR_6
23514 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT                                                             0x0
23515 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT                                                            0x10
23516 #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK                                                               0x0000FFFFL
23517 #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK                                                              0xFFFF0000L
23518 //RLC_SRM_INDEX_CNTL_ADDR_7
23519 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT                                                             0x0
23520 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT                                                            0x10
23521 #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK                                                               0x0000FFFFL
23522 #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK                                                              0xFFFF0000L
23523 //RLC_SRM_INDEX_CNTL_DATA_0
23524 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT                                                                0x0
23525 #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK                                                                  0xFFFFFFFFL
23526 //RLC_SRM_INDEX_CNTL_DATA_1
23527 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT                                                                0x0
23528 #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK                                                                  0xFFFFFFFFL
23529 //RLC_SRM_INDEX_CNTL_DATA_2
23530 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT                                                                0x0
23531 #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK                                                                  0xFFFFFFFFL
23532 //RLC_SRM_INDEX_CNTL_DATA_3
23533 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT                                                                0x0
23534 #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK                                                                  0xFFFFFFFFL
23535 //RLC_SRM_INDEX_CNTL_DATA_4
23536 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT                                                                0x0
23537 #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK                                                                  0xFFFFFFFFL
23538 //RLC_SRM_INDEX_CNTL_DATA_5
23539 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT                                                                0x0
23540 #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK                                                                  0xFFFFFFFFL
23541 //RLC_SRM_INDEX_CNTL_DATA_6
23542 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT                                                                0x0
23543 #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK                                                                  0xFFFFFFFFL
23544 //RLC_SRM_INDEX_CNTL_DATA_7
23545 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT                                                                0x0
23546 #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK                                                                  0xFFFFFFFFL
23547 //RLC_SRM_STAT
23548 #define RLC_SRM_STAT__SRM_BUSY__SHIFT                                                                         0x0
23549 #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT                                                                   0x1
23550 #define RLC_SRM_STAT__RESERVED__SHIFT                                                                         0x2
23551 #define RLC_SRM_STAT__SRM_BUSY_MASK                                                                           0x00000001L
23552 #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK                                                                     0x00000002L
23553 #define RLC_SRM_STAT__RESERVED_MASK                                                                           0xFFFFFFFCL
23554 //RLC_SRM_GPM_ABORT
23555 #define RLC_SRM_GPM_ABORT__ABORT__SHIFT                                                                       0x0
23556 #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT                                                                    0x1
23557 #define RLC_SRM_GPM_ABORT__ABORT_MASK                                                                         0x00000001L
23558 #define RLC_SRM_GPM_ABORT__RESERVED_MASK                                                                      0xFFFFFFFEL
23559 //RLC_CSIB_ADDR_LO
23560 #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT                                                                      0x0
23561 #define RLC_CSIB_ADDR_LO__ADDRESS_MASK                                                                        0xFFFFFFFFL
23562 //RLC_CSIB_ADDR_HI
23563 #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT                                                                      0x0
23564 #define RLC_CSIB_ADDR_HI__ADDRESS_MASK                                                                        0x0000FFFFL
23565 //RLC_CSIB_LENGTH
23566 #define RLC_CSIB_LENGTH__LENGTH__SHIFT                                                                        0x0
23567 #define RLC_CSIB_LENGTH__LENGTH_MASK                                                                          0xFFFFFFFFL
23568 //RLC_SMU_COMMAND
23569 #define RLC_SMU_COMMAND__CMD__SHIFT                                                                           0x0
23570 #define RLC_SMU_COMMAND__CMD_MASK                                                                             0xFFFFFFFFL
23571 //RLC_CP_SCHEDULERS
23572 #define RLC_CP_SCHEDULERS__scheduler0__SHIFT                                                                  0x0
23573 #define RLC_CP_SCHEDULERS__scheduler1__SHIFT                                                                  0x8
23574 #define RLC_CP_SCHEDULERS__scheduler2__SHIFT                                                                  0x10
23575 #define RLC_CP_SCHEDULERS__scheduler3__SHIFT                                                                  0x18
23576 #define RLC_CP_SCHEDULERS__scheduler0_MASK                                                                    0x000000FFL
23577 #define RLC_CP_SCHEDULERS__scheduler1_MASK                                                                    0x0000FF00L
23578 #define RLC_CP_SCHEDULERS__scheduler2_MASK                                                                    0x00FF0000L
23579 #define RLC_CP_SCHEDULERS__scheduler3_MASK                                                                    0xFF000000L
23580 //RLC_SMU_ARGUMENT_1
23581 #define RLC_SMU_ARGUMENT_1__ARG__SHIFT                                                                        0x0
23582 #define RLC_SMU_ARGUMENT_1__ARG_MASK                                                                          0xFFFFFFFFL
23583 //RLC_SMU_ARGUMENT_2
23584 #define RLC_SMU_ARGUMENT_2__ARG__SHIFT                                                                        0x0
23585 #define RLC_SMU_ARGUMENT_2__ARG_MASK                                                                          0xFFFFFFFFL
23586 //RLC_GPM_GENERAL_8
23587 #define RLC_GPM_GENERAL_8__DATA__SHIFT                                                                        0x0
23588 #define RLC_GPM_GENERAL_8__DATA_MASK                                                                          0xFFFFFFFFL
23589 //RLC_GPM_GENERAL_9
23590 #define RLC_GPM_GENERAL_9__DATA__SHIFT                                                                        0x0
23591 #define RLC_GPM_GENERAL_9__DATA_MASK                                                                          0xFFFFFFFFL
23592 //RLC_GPM_GENERAL_10
23593 #define RLC_GPM_GENERAL_10__DATA__SHIFT                                                                       0x0
23594 #define RLC_GPM_GENERAL_10__DATA_MASK                                                                         0xFFFFFFFFL
23595 //RLC_GPM_GENERAL_11
23596 #define RLC_GPM_GENERAL_11__DATA__SHIFT                                                                       0x0
23597 #define RLC_GPM_GENERAL_11__DATA_MASK                                                                         0xFFFFFFFFL
23598 //RLC_GPM_GENERAL_12
23599 #define RLC_GPM_GENERAL_12__DATA__SHIFT                                                                       0x0
23600 #define RLC_GPM_GENERAL_12__DATA_MASK                                                                         0xFFFFFFFFL
23601 //RLC_GPM_UTCL1_CNTL_0
23602 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
23603 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT                                                                0x18
23604 #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT                                                                   0x19
23605 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT                                                               0x1a
23606 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
23607 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT                                                              0x1c
23608 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT                                                      0x1d
23609 #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT                                                                 0x1e
23610 #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
23611 #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK                                                                  0x01000000L
23612 #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK                                                                     0x02000000L
23613 #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK                                                                 0x04000000L
23614 #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
23615 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK                                                                0x10000000L
23616 #define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK                                                        0x20000000L
23617 #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK                                                                   0xC0000000L
23618 //RLC_GPM_UTCL1_CNTL_1
23619 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
23620 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT                                                                0x18
23621 #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT                                                                   0x19
23622 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT                                                               0x1a
23623 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
23624 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT                                                              0x1c
23625 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT                                                      0x1d
23626 #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT                                                                 0x1e
23627 #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
23628 #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK                                                                  0x01000000L
23629 #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK                                                                     0x02000000L
23630 #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK                                                                 0x04000000L
23631 #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
23632 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK                                                                0x10000000L
23633 #define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK                                                        0x20000000L
23634 #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK                                                                   0xC0000000L
23635 //RLC_GPM_UTCL1_CNTL_2
23636 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT                                                     0x0
23637 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT                                                                0x18
23638 #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT                                                                   0x19
23639 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT                                                               0x1a
23640 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT                                                          0x1b
23641 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT                                                              0x1c
23642 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT                                                      0x1d
23643 #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT                                                                 0x1e
23644 #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK                                                       0x000FFFFFL
23645 #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK                                                                  0x01000000L
23646 #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK                                                                     0x02000000L
23647 #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK                                                                 0x04000000L
23648 #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK                                                            0x08000000L
23649 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK                                                                0x10000000L
23650 #define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK                                                        0x20000000L
23651 #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK                                                                   0xC0000000L
23652 //RLC_SPM_UTCL1_CNTL
23653 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                       0x0
23654 #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT                                                                  0x18
23655 #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT                                                                     0x19
23656 #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT                                                                 0x1a
23657 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                            0x1b
23658 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                                0x1c
23659 #define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                        0x1d
23660 #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT                                                                   0x1e
23661 #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                         0x000FFFFFL
23662 #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK                                                                    0x01000000L
23663 #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK                                                                       0x02000000L
23664 #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK                                                                   0x04000000L
23665 #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                              0x08000000L
23666 #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK                                                                  0x10000000L
23667 #define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                          0x20000000L
23668 #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK                                                                     0xC0000000L
23669 //RLC_UTCL1_STATUS_2
23670 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT                                                         0x0
23671 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT                                                         0x1
23672 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT                                                         0x2
23673 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT                                                             0x3
23674 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT                                                       0x4
23675 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT                                                 0x5
23676 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT                                                 0x6
23677 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT                                                 0x7
23678 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT                                                     0x8
23679 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT                                               0x9
23680 #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT                                                                   0xa
23681 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK                                                           0x00000001L
23682 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK                                                           0x00000002L
23683 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK                                                           0x00000004L
23684 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK                                                               0x00000008L
23685 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK                                                         0x00000010L
23686 #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK                                                   0x00000020L
23687 #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK                                                   0x00000040L
23688 #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK                                                   0x00000080L
23689 #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK                                                       0x00000100L
23690 #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK                                                 0x00000200L
23691 #define RLC_UTCL1_STATUS_2__RESERVED_MASK                                                                     0xFFFFFC00L
23692 //RLC_LB_THR_CONFIG_2
23693 #define RLC_LB_THR_CONFIG_2__DATA__SHIFT                                                                      0x0
23694 #define RLC_LB_THR_CONFIG_2__DATA_MASK                                                                        0xFFFFFFFFL
23695 //RLC_LB_THR_CONFIG_3
23696 #define RLC_LB_THR_CONFIG_3__DATA__SHIFT                                                                      0x0
23697 #define RLC_LB_THR_CONFIG_3__DATA_MASK                                                                        0xFFFFFFFFL
23698 //RLC_LB_THR_CONFIG_4
23699 #define RLC_LB_THR_CONFIG_4__DATA__SHIFT                                                                      0x0
23700 #define RLC_LB_THR_CONFIG_4__DATA_MASK                                                                        0xFFFFFFFFL
23701 //RLC_SPM_UTCL1_ERROR_1
23702 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT                                                     0x0
23703 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                                 0x2
23704 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                             0x6
23705 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK                                                       0x00000003L
23706 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK                                                   0x0000003CL
23707 #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                               0x000003C0L
23708 //RLC_SPM_UTCL1_ERROR_2
23709 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                             0x0
23710 #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                               0xFFFFFFFFL
23711 //RLC_GPM_UTCL1_TH0_ERROR_1
23712 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
23713 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
23714 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
23715 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
23716 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
23717 #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
23718 //RLC_LB_THR_CONFIG_1
23719 #define RLC_LB_THR_CONFIG_1__DATA__SHIFT                                                                      0x0
23720 #define RLC_LB_THR_CONFIG_1__DATA_MASK                                                                        0xFFFFFFFFL
23721 //RLC_GPM_UTCL1_TH0_ERROR_2
23722 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
23723 #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
23724 //RLC_GPM_UTCL1_TH1_ERROR_1
23725 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
23726 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
23727 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
23728 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
23729 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
23730 #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
23731 //RLC_GPM_UTCL1_TH1_ERROR_2
23732 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
23733 #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
23734 //RLC_GPM_UTCL1_TH2_ERROR_1
23735 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT                                                 0x0
23736 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT                                             0x2
23737 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT                                         0x6
23738 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK                                                   0x00000003L
23739 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK                                               0x0000003CL
23740 #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK                                           0x000003C0L
23741 //RLC_GPM_UTCL1_TH2_ERROR_2
23742 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT                                         0x0
23743 #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK                                           0xFFFFFFFFL
23744 //RLC_CGCG_CGLS_CTRL_3D
23745 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT                                                                 0x0
23746 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT                                                                 0x1
23747 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT                                                0x2
23748 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT                                                 0x8
23749 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT                                                         0x1b
23750 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT                                                           0x1c
23751 #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT                                                              0x1d
23752 #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT                                                          0x1f
23753 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK                                                                   0x00000001L
23754 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK                                                                   0x00000002L
23755 #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK                                                  0x000000FCL
23756 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK                                                   0x07FFFF00L
23757 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK                                                           0x08000000L
23758 #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK                                                             0x10000000L
23759 #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK                                                                0x60000000L
23760 #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK                                                            0x80000000L
23761 //RLC_CGCG_RAMP_CTRL_3D
23762 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT                                                     0x0
23763 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT                                                      0x4
23764 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT                                                       0x8
23765 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT                                                        0xc
23766 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT                                                          0x10
23767 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT                                                         0x1c
23768 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK                                                       0x0000000FL
23769 #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK                                                        0x000000F0L
23770 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK                                                         0x00000F00L
23771 #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK                                                          0x0000F000L
23772 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK                                                            0x0FFF0000L
23773 #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK                                                           0xF0000000L
23774 //RLC_SEMAPHORE_0
23775 #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT                                                                     0x0
23776 #define RLC_SEMAPHORE_0__RESERVED__SHIFT                                                                      0x5
23777 #define RLC_SEMAPHORE_0__CLIENT_ID_MASK                                                                       0x0000001FL
23778 #define RLC_SEMAPHORE_0__RESERVED_MASK                                                                        0xFFFFFFE0L
23779 //RLC_SEMAPHORE_1
23780 #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT                                                                     0x0
23781 #define RLC_SEMAPHORE_1__RESERVED__SHIFT                                                                      0x5
23782 #define RLC_SEMAPHORE_1__CLIENT_ID_MASK                                                                       0x0000001FL
23783 #define RLC_SEMAPHORE_1__RESERVED_MASK                                                                        0xFFFFFFE0L
23784 //RLC_CP_EOF_INT
23785 #define RLC_CP_EOF_INT__INTERRUPT__SHIFT                                                                      0x0
23786 #define RLC_CP_EOF_INT__RESERVED__SHIFT                                                                       0x1
23787 #define RLC_CP_EOF_INT__INTERRUPT_MASK                                                                        0x00000001L
23788 #define RLC_CP_EOF_INT__RESERVED_MASK                                                                         0xFFFFFFFEL
23789 //RLC_CP_EOF_INT_CNT
23790 #define RLC_CP_EOF_INT_CNT__CNT__SHIFT                                                                        0x0
23791 #define RLC_CP_EOF_INT_CNT__CNT_MASK                                                                          0xFFFFFFFFL
23792 //RLC_SPARE_INT
23793 #define RLC_SPARE_INT__INTERRUPT__SHIFT                                                                       0x0
23794 #define RLC_SPARE_INT__RESERVED__SHIFT                                                                        0x1
23795 #define RLC_SPARE_INT__INTERRUPT_MASK                                                                         0x00000001L
23796 #define RLC_SPARE_INT__RESERVED_MASK                                                                          0xFFFFFFFEL
23797 //RLC_PREWALKER_UTCL1_CNTL
23798 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT                                                 0x0
23799 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT                                                            0x18
23800 #define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT                                                               0x19
23801 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT                                                           0x1a
23802 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT                                                      0x1b
23803 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT                                                          0x1c
23804 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT                                                  0x1d
23805 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT                                                             0x1e
23806 #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK                                                   0x000FFFFFL
23807 #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK                                                              0x01000000L
23808 #define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK                                                                 0x02000000L
23809 #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK                                                             0x04000000L
23810 #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK                                                        0x08000000L
23811 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK                                                            0x10000000L
23812 #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK                                                    0x20000000L
23813 #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK                                                               0xC0000000L
23814 //RLC_PREWALKER_UTCL1_TRIG
23815 #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT                                                                0x0
23816 #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT                                                                 0x1
23817 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT                                                           0x5
23818 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT                                                            0x6
23819 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT                                                           0x7
23820 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT                                                            0x8
23821 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT                                                             0x9
23822 #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT                                                                0x1f
23823 #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK                                                                  0x00000001L
23824 #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK                                                                   0x0000001EL
23825 #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK                                                             0x00000020L
23826 #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK                                                              0x00000040L
23827 #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK                                                             0x00000080L
23828 #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK                                                              0x00000100L
23829 #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK                                                               0x7FFFFE00L
23830 #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK                                                                  0x80000000L
23831 //RLC_PREWALKER_UTCL1_ADDR_LSB
23832 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT                                                         0x0
23833 #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK                                                           0xFFFFFFFFL
23834 //RLC_PREWALKER_UTCL1_ADDR_MSB
23835 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT                                                         0x0
23836 #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK                                                           0x0000FFFFL
23837 //RLC_PREWALKER_UTCL1_SIZE_LSB
23838 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT                                                         0x0
23839 #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK                                                           0xFFFFFFFFL
23840 //RLC_PREWALKER_UTCL1_SIZE_MSB
23841 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT                                                         0x0
23842 #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK                                                           0x00000003L
23843 //RLC_DSM_TRIG
23844 //RLC_UTCL1_STATUS
23845 #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT                                                               0x0
23846 #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT                                                               0x1
23847 #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT                                                                 0x2
23848 #define RLC_UTCL1_STATUS__RESERVED__SHIFT                                                                     0x3
23849 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT                                                                0x8
23850 #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT                                                                   0xe
23851 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT                                                                0x10
23852 #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT                                                                   0x16
23853 #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT                                                                  0x18
23854 #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT                                                                   0x1e
23855 #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK                                                                 0x00000001L
23856 #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK                                                                 0x00000002L
23857 #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK                                                                   0x00000004L
23858 #define RLC_UTCL1_STATUS__RESERVED_MASK                                                                       0x000000F8L
23859 #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK                                                                  0x00003F00L
23860 #define RLC_UTCL1_STATUS__RESERVED_1_MASK                                                                     0x0000C000L
23861 #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK                                                                  0x003F0000L
23862 #define RLC_UTCL1_STATUS__RESERVED_2_MASK                                                                     0x00C00000L
23863 #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK                                                                    0x3F000000L
23864 #define RLC_UTCL1_STATUS__RESERVED_3_MASK                                                                     0xC0000000L
23865 //RLC_R2I_CNTL_0
23866 #define RLC_R2I_CNTL_0__Data__SHIFT                                                                           0x0
23867 #define RLC_R2I_CNTL_0__Data_MASK                                                                             0xFFFFFFFFL
23868 //RLC_R2I_CNTL_1
23869 #define RLC_R2I_CNTL_1__Data__SHIFT                                                                           0x0
23870 #define RLC_R2I_CNTL_1__Data_MASK                                                                             0xFFFFFFFFL
23871 //RLC_R2I_CNTL_2
23872 #define RLC_R2I_CNTL_2__Data__SHIFT                                                                           0x0
23873 #define RLC_R2I_CNTL_2__Data_MASK                                                                             0xFFFFFFFFL
23874 //RLC_R2I_CNTL_3
23875 #define RLC_R2I_CNTL_3__Data__SHIFT                                                                           0x0
23876 #define RLC_R2I_CNTL_3__Data_MASK                                                                             0xFFFFFFFFL
23877 //RLC_UTCL2_CNTL
23878 #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT                                                              0x0
23879 #define RLC_UTCL2_CNTL__RESERVED__SHIFT                                                                       0x1
23880 #define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK                                                                0x00000001L
23881 #define RLC_UTCL2_CNTL__RESERVED_MASK                                                                         0xFFFFFFFEL
23882 //RLC_LBPW_CU_STAT
23883 #define RLC_LBPW_CU_STAT__MAX_CU__SHIFT                                                                       0x0
23884 #define RLC_LBPW_CU_STAT__ON_CU__SHIFT                                                                        0x10
23885 #define RLC_LBPW_CU_STAT__MAX_CU_MASK                                                                         0x0000FFFFL
23886 #define RLC_LBPW_CU_STAT__ON_CU_MASK                                                                          0xFFFF0000L
23887 //RLC_DS_CNTL
23888 #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT                                                          0x0
23889 #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT                                                           0x1
23890 #define RLC_DS_CNTL__RESRVED__SHIFT                                                                           0x2
23891 #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT                                                          0x10
23892 #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT                                                           0x11
23893 #define RLC_DS_CNTL__RESRVED_1__SHIFT                                                                         0x12
23894 #define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK                                                            0x00000001L
23895 #define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK                                                             0x00000002L
23896 #define RLC_DS_CNTL__RESRVED_MASK                                                                             0x0000FFFCL
23897 #define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK                                                            0x00010000L
23898 #define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK                                                             0x00020000L
23899 #define RLC_DS_CNTL__RESRVED_1_MASK                                                                           0xFFFC0000L
23900 //RLC_RLCV_SPARE_INT
23901 #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT                                                                  0x0
23902 #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT                                                                   0x1
23903 #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK                                                                    0x00000001L
23904 #define RLC_RLCV_SPARE_INT__RESERVED_MASK                                                                     0xFFFFFFFEL
23905 
23906 
23907 // addressBlock: gc_pwrdec
23908 //CGTS_SM_CTRL_REG
23909 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT                                                                 0x0
23910 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT                                                                0x4
23911 #define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT                                                                 0xc
23912 #define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT                                                                    0x10
23913 #define CGTS_SM_CTRL_REG__SM_MODE__SHIFT                                                                      0x11
23914 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT                                                               0x14
23915 #define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT                                                                     0x15
23916 #define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT                                                                  0x16
23917 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT                                                            0x17
23918 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT                                                               0x18
23919 #define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK                                                                   0x0000000FL
23920 #define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK                                                                  0x00000FF0L
23921 #define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK                                                                   0x00001000L
23922 #define CGTS_SM_CTRL_REG__BASE_MODE_MASK                                                                      0x00010000L
23923 #define CGTS_SM_CTRL_REG__SM_MODE_MASK                                                                        0x000E0000L
23924 #define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK                                                                 0x00100000L
23925 #define CGTS_SM_CTRL_REG__OVERRIDE_MASK                                                                       0x00200000L
23926 #define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK                                                                    0x00400000L
23927 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK                                                              0x00800000L
23928 #define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK                                                                 0xFF000000L
23929 //CGTS_RD_CTRL_REG
23930 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT                                                                  0x0
23931 #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT                                                                  0x8
23932 #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK                                                                    0x0000001FL
23933 #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK                                                                    0x00001F00L
23934 //CGTS_RD_REG
23935 #define CGTS_RD_REG__READ_DATA__SHIFT                                                                         0x0
23936 #define CGTS_RD_REG__READ_DATA_MASK                                                                           0x00003FFFL
23937 //CGTS_TCC_DISABLE
23938 #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT                                                                  0x10
23939 #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK                                                                    0xFFFF0000L
23940 //CGTS_USER_TCC_DISABLE
23941 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT                                                             0x10
23942 #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK                                                               0xFFFF0000L
23943 //CGTS_CU0_SP0_CTRL_REG
23944 #define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
23945 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
23946 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
23947 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
23948 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
23949 #define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
23950 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
23951 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
23952 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
23953 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
23954 #define CGTS_CU0_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
23955 #define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
23956 #define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
23957 #define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
23958 #define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
23959 #define CGTS_CU0_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
23960 #define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
23961 #define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
23962 #define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
23963 #define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
23964 //CGTS_CU0_LDS_SQ_CTRL_REG
23965 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
23966 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
23967 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
23968 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
23969 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
23970 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
23971 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
23972 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
23973 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
23974 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
23975 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
23976 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
23977 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
23978 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
23979 #define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
23980 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
23981 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
23982 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
23983 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
23984 #define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
23985 //CGTS_CU0_TA_SQC_CTRL_REG
23986 #define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
23987 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
23988 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
23989 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
23990 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
23991 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
23992 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
23993 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
23994 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
23995 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
23996 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
23997 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
23998 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
23999 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24000 #define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24001 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24002 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24003 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24004 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24005 #define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24006 //CGTS_CU0_SP1_CTRL_REG
24007 #define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24008 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24009 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24010 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24011 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24012 #define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24013 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24014 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24015 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24016 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24017 #define CGTS_CU0_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24018 #define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24019 #define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24020 #define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24021 #define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24022 #define CGTS_CU0_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24023 #define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24024 #define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24025 #define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24026 #define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24027 //CGTS_CU0_TD_TCP_CTRL_REG
24028 #define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24029 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24030 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24031 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24032 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24033 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24034 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24035 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24036 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24037 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24038 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24039 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24040 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24041 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24042 #define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24043 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24044 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24045 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24046 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24047 #define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24048 //CGTS_CU1_SP0_CTRL_REG
24049 #define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24050 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24051 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24052 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24053 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24054 #define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24055 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24056 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24057 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24058 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24059 #define CGTS_CU1_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24060 #define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24061 #define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24062 #define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24063 #define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24064 #define CGTS_CU1_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24065 #define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24066 #define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24067 #define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24068 #define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24069 //CGTS_CU1_LDS_SQ_CTRL_REG
24070 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24071 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24072 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24073 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24074 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24075 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24076 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24077 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24078 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24079 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24080 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24081 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24082 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24083 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24084 #define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24085 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24086 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24087 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24088 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24089 #define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24090 //CGTS_CU1_TA_SQC_CTRL_REG
24091 #define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24092 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24093 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24094 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24095 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24096 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24097 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24098 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24099 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24100 #define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24101 //CGTS_CU1_SP1_CTRL_REG
24102 #define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24103 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24104 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24105 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24106 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24107 #define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24108 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24109 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24110 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24111 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24112 #define CGTS_CU1_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24113 #define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24114 #define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24115 #define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24116 #define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24117 #define CGTS_CU1_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24118 #define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24119 #define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24120 #define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24121 #define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24122 //CGTS_CU1_TD_TCP_CTRL_REG
24123 #define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24124 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24125 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24126 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24127 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24128 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24129 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24130 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24131 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24132 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24133 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24134 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24135 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24136 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24137 #define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24138 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24139 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24140 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24141 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24142 #define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24143 //CGTS_CU2_SP0_CTRL_REG
24144 #define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24145 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24146 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24147 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24148 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24149 #define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24150 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24151 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24152 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24153 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24154 #define CGTS_CU2_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24155 #define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24156 #define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24157 #define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24158 #define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24159 #define CGTS_CU2_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24160 #define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24161 #define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24162 #define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24163 #define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24164 //CGTS_CU2_LDS_SQ_CTRL_REG
24165 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24166 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24167 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24168 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24169 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24170 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24171 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24172 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24173 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24174 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24175 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24176 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24177 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24178 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24179 #define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24180 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24181 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24182 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24183 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24184 #define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24185 //CGTS_CU2_TA_SQC_CTRL_REG
24186 #define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24187 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24188 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24189 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24190 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24191 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24192 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24193 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24194 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24195 #define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24196 //CGTS_CU2_SP1_CTRL_REG
24197 #define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24198 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24199 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24200 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24201 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24202 #define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24203 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24204 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24205 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24206 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24207 #define CGTS_CU2_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24208 #define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24209 #define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24210 #define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24211 #define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24212 #define CGTS_CU2_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24213 #define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24214 #define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24215 #define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24216 #define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24217 //CGTS_CU2_TD_TCP_CTRL_REG
24218 #define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24219 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24220 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24221 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24222 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24223 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24224 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24225 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24226 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24227 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24228 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24229 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24230 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24231 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24232 #define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24233 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24234 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24235 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24236 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24237 #define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24238 //CGTS_CU3_SP0_CTRL_REG
24239 #define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24240 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24241 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24242 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24243 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24244 #define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24245 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24246 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24247 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24248 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24249 #define CGTS_CU3_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24250 #define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24251 #define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24252 #define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24253 #define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24254 #define CGTS_CU3_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24255 #define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24256 #define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24257 #define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24258 #define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24259 //CGTS_CU3_LDS_SQ_CTRL_REG
24260 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24261 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24262 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24263 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24264 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24265 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24266 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24267 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24268 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24269 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24270 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24271 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24272 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24273 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24274 #define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24275 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24276 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24277 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24278 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24279 #define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24280 //CGTS_CU3_TA_SQC_CTRL_REG
24281 #define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24282 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24283 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24284 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24285 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24286 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
24287 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
24288 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
24289 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
24290 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24291 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24292 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24293 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24294 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24295 #define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24296 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24297 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24298 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24299 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24300 #define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24301 //CGTS_CU3_SP1_CTRL_REG
24302 #define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24303 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24304 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24305 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24306 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24307 #define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24308 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24309 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24310 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24311 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24312 #define CGTS_CU3_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24313 #define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24314 #define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24315 #define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24316 #define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24317 #define CGTS_CU3_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24318 #define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24319 #define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24320 #define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24321 #define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24322 //CGTS_CU3_TD_TCP_CTRL_REG
24323 #define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24324 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24325 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24326 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24327 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24328 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24329 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24330 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24331 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24332 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24333 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24334 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24335 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24336 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24337 #define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24338 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24339 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24340 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24341 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24342 #define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24343 //CGTS_CU4_SP0_CTRL_REG
24344 #define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24345 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24346 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24347 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24348 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24349 #define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24350 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24351 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24352 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24353 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24354 #define CGTS_CU4_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24355 #define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24356 #define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24357 #define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24358 #define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24359 #define CGTS_CU4_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24360 #define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24361 #define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24362 #define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24363 #define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24364 //CGTS_CU4_LDS_SQ_CTRL_REG
24365 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24366 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24367 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24368 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24369 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24370 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24371 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24372 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24373 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24374 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24375 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24376 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24377 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24378 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24379 #define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24380 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24381 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24382 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24383 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24384 #define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24385 //CGTS_CU4_TA_SQC_CTRL_REG
24386 #define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24387 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24388 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24389 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24390 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24391 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24392 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24393 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24394 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24395 #define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24396 //CGTS_CU4_SP1_CTRL_REG
24397 #define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24398 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24399 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24400 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24401 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24402 #define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24403 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24404 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24405 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24406 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24407 #define CGTS_CU4_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24408 #define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24409 #define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24410 #define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24411 #define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24412 #define CGTS_CU4_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24413 #define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24414 #define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24415 #define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24416 #define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24417 //CGTS_CU4_TD_TCP_CTRL_REG
24418 #define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24419 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24420 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24421 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24422 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24423 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24424 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24425 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24426 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24427 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24428 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24429 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24430 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24431 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24432 #define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24433 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24434 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24435 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24436 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24437 #define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24438 //CGTS_CU5_SP0_CTRL_REG
24439 #define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24440 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24441 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24442 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24443 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24444 #define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24445 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24446 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24447 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24448 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24449 #define CGTS_CU5_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24450 #define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24451 #define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24452 #define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24453 #define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24454 #define CGTS_CU5_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24455 #define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24456 #define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24457 #define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24458 #define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24459 //CGTS_CU5_LDS_SQ_CTRL_REG
24460 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24461 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24462 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24463 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24464 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24465 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24466 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24467 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24468 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24469 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24470 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24471 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24472 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24473 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24474 #define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24475 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24476 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24477 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24478 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24479 #define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24480 //CGTS_CU5_TA_SQC_CTRL_REG
24481 #define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24482 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24483 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24484 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24485 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24486 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24487 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24488 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24489 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24490 #define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24491 //CGTS_CU5_SP1_CTRL_REG
24492 #define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24493 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24494 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24495 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24496 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24497 #define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24498 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24499 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24500 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24501 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24502 #define CGTS_CU5_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24503 #define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24504 #define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24505 #define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24506 #define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24507 #define CGTS_CU5_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24508 #define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24509 #define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24510 #define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24511 #define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24512 //CGTS_CU5_TD_TCP_CTRL_REG
24513 #define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24514 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24515 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24516 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24517 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24518 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24519 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24520 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24521 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24522 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24523 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24524 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24525 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24526 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24527 #define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24528 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24529 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24530 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24531 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24532 #define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24533 //CGTS_CU6_SP0_CTRL_REG
24534 #define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24535 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24536 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24537 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24538 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24539 #define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24540 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24541 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24542 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24543 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24544 #define CGTS_CU6_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24545 #define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24546 #define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24547 #define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24548 #define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24549 #define CGTS_CU6_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24550 #define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24551 #define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24552 #define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24553 #define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24554 //CGTS_CU6_LDS_SQ_CTRL_REG
24555 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24556 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24557 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24558 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24559 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24560 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24561 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24562 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24563 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24564 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24565 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24566 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24567 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24568 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24569 #define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24570 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24571 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24572 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24573 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24574 #define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24575 //CGTS_CU6_TA_SQC_CTRL_REG
24576 #define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24577 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24578 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24579 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24580 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24581 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
24582 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
24583 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
24584 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
24585 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24586 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24587 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24588 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24589 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24590 #define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24591 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24592 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24593 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24594 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24595 #define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24596 //CGTS_CU6_SP1_CTRL_REG
24597 #define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24598 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24599 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24600 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24601 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24602 #define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24603 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24604 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24605 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24606 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24607 #define CGTS_CU6_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24608 #define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24609 #define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24610 #define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24611 #define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24612 #define CGTS_CU6_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24613 #define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24614 #define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24615 #define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24616 #define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24617 //CGTS_CU6_TD_TCP_CTRL_REG
24618 #define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24619 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24620 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24621 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24622 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24623 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24624 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24625 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24626 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24627 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24628 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24629 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24630 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24631 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24632 #define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24633 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24634 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24635 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24636 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24637 #define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24638 //CGTS_CU7_SP0_CTRL_REG
24639 #define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24640 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24641 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24642 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24643 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24644 #define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24645 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24646 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24647 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24648 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24649 #define CGTS_CU7_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24650 #define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24651 #define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24652 #define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24653 #define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24654 #define CGTS_CU7_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24655 #define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24656 #define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24657 #define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24658 #define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24659 //CGTS_CU7_LDS_SQ_CTRL_REG
24660 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24661 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24662 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24663 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24664 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24665 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24666 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24667 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24668 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24669 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24670 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24671 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24672 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24673 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24674 #define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24675 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24676 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24677 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24678 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24679 #define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24680 //CGTS_CU7_TA_SQC_CTRL_REG
24681 #define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24682 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24683 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24684 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24685 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24686 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24687 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24688 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24689 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24690 #define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24691 //CGTS_CU7_SP1_CTRL_REG
24692 #define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24693 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24694 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24695 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24696 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24697 #define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24698 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24699 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24700 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24701 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24702 #define CGTS_CU7_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24703 #define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24704 #define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24705 #define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24706 #define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24707 #define CGTS_CU7_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24708 #define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24709 #define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24710 #define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24711 #define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24712 //CGTS_CU7_TD_TCP_CTRL_REG
24713 #define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24714 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24715 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24716 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24717 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24718 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24719 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24720 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24721 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24722 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24723 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24724 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24725 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24726 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24727 #define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24728 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24729 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24730 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24731 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24732 #define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24733 //CGTS_CU8_SP0_CTRL_REG
24734 #define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24735 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24736 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24737 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24738 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24739 #define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24740 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24741 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24742 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24743 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24744 #define CGTS_CU8_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24745 #define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24746 #define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24747 #define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24748 #define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24749 #define CGTS_CU8_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24750 #define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24751 #define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24752 #define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24753 #define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24754 //CGTS_CU8_LDS_SQ_CTRL_REG
24755 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24756 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24757 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24758 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24759 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24760 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24761 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24762 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24763 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24764 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24765 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24766 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24767 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24768 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24769 #define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24770 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24771 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24772 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24773 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24774 #define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24775 //CGTS_CU8_TA_SQC_CTRL_REG
24776 #define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24777 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24778 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24779 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24780 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24781 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24782 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24783 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24784 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24785 #define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24786 //CGTS_CU8_SP1_CTRL_REG
24787 #define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24788 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24789 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24790 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24791 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24792 #define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24793 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24794 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24795 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24796 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24797 #define CGTS_CU8_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24798 #define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24799 #define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24800 #define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24801 #define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24802 #define CGTS_CU8_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24803 #define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24804 #define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24805 #define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24806 #define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24807 //CGTS_CU8_TD_TCP_CTRL_REG
24808 #define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24809 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24810 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24811 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24812 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24813 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24814 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24815 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24816 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24817 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24818 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24819 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24820 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24821 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24822 #define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24823 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24824 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24825 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24826 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24827 #define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24828 //CGTS_CU9_SP0_CTRL_REG
24829 #define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT                                                                    0x0
24830 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                           0x7
24831 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                      0x8
24832 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                        0xa
24833 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24834 #define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT                                                                    0x10
24835 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                           0x17
24836 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                      0x18
24837 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                        0x1a
24838 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24839 #define CGTS_CU9_SP0_CTRL_REG__SP00_MASK                                                                      0x0000007FL
24840 #define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                             0x00000080L
24841 #define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                        0x00000300L
24842 #define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                          0x00000400L
24843 #define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24844 #define CGTS_CU9_SP0_CTRL_REG__SP01_MASK                                                                      0x007F0000L
24845 #define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                             0x00800000L
24846 #define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                        0x03000000L
24847 #define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                          0x04000000L
24848 #define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24849 //CGTS_CU9_LDS_SQ_CTRL_REG
24850 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                  0x0
24851 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                         0x7
24852 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                    0x8
24853 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                      0xa
24854 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24855 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                   0x10
24856 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                          0x17
24857 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                     0x18
24858 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                       0x1a
24859 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24860 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK                                                                    0x0000007FL
24861 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                           0x00000080L
24862 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                      0x00000300L
24863 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                        0x00000400L
24864 #define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24865 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK                                                                     0x007F0000L
24866 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                            0x00800000L
24867 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                       0x03000000L
24868 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                         0x04000000L
24869 #define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24870 //CGTS_CU9_TA_SQC_CTRL_REG
24871 #define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT                                                                   0x0
24872 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                          0x7
24873 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                     0x8
24874 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                       0xa
24875 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24876 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT                                                                  0x10
24877 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                         0x17
24878 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                    0x18
24879 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                      0x1a
24880 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24881 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK                                                                     0x0000007FL
24882 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                            0x00000080L
24883 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                       0x00000300L
24884 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                         0x00000400L
24885 #define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24886 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK                                                                    0x007F0000L
24887 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                           0x00800000L
24888 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                      0x03000000L
24889 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                        0x04000000L
24890 #define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24891 //CGTS_CU9_SP1_CTRL_REG
24892 #define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT                                                                    0x0
24893 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                           0x7
24894 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                      0x8
24895 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                        0xa
24896 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                  0xb
24897 #define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT                                                                    0x10
24898 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                           0x17
24899 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                      0x18
24900 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                        0x1a
24901 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                  0x1b
24902 #define CGTS_CU9_SP1_CTRL_REG__SP10_MASK                                                                      0x0000007FL
24903 #define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                             0x00000080L
24904 #define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                        0x00000300L
24905 #define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                          0x00000400L
24906 #define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                    0x00000800L
24907 #define CGTS_CU9_SP1_CTRL_REG__SP11_MASK                                                                      0x007F0000L
24908 #define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                             0x00800000L
24909 #define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                        0x03000000L
24910 #define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                          0x04000000L
24911 #define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                    0x08000000L
24912 //CGTS_CU9_TD_TCP_CTRL_REG
24913 #define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT                                                                   0x0
24914 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                          0x7
24915 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                     0x8
24916 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                       0xa
24917 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24918 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                 0x10
24919 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                        0x17
24920 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                   0x18
24921 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                     0x1a
24922 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
24923 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK                                                                     0x0000007FL
24924 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                            0x00000080L
24925 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                       0x00000300L
24926 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                         0x00000400L
24927 #define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24928 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK                                                                   0x007F0000L
24929 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                          0x00800000L
24930 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                     0x03000000L
24931 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                       0x04000000L
24932 #define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
24933 //CGTS_CU10_SP0_CTRL_REG
24934 #define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
24935 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
24936 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
24937 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
24938 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24939 #define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
24940 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
24941 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
24942 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
24943 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24944 #define CGTS_CU10_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
24945 #define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
24946 #define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
24947 #define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
24948 #define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
24949 #define CGTS_CU10_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
24950 #define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
24951 #define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
24952 #define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
24953 #define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
24954 //CGTS_CU10_LDS_SQ_CTRL_REG
24955 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
24956 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
24957 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
24958 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
24959 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
24960 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
24961 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
24962 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
24963 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
24964 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
24965 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
24966 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
24967 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
24968 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
24969 #define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
24970 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
24971 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
24972 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
24973 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
24974 #define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
24975 //CGTS_CU10_TA_SQC_CTRL_REG
24976 #define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
24977 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
24978 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
24979 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
24980 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
24981 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
24982 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
24983 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
24984 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
24985 #define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
24986 //CGTS_CU10_SP1_CTRL_REG
24987 #define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
24988 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
24989 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
24990 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
24991 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
24992 #define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
24993 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
24994 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
24995 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
24996 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
24997 #define CGTS_CU10_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
24998 #define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
24999 #define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25000 #define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25001 #define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25002 #define CGTS_CU10_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25003 #define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25004 #define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25005 #define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25006 #define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25007 //CGTS_CU10_TD_TCP_CTRL_REG
25008 #define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25009 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25010 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25011 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25012 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25013 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25014 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25015 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25016 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25017 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25018 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25019 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25020 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25021 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25022 #define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25023 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25024 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25025 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25026 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25027 #define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25028 //CGTS_CU11_SP0_CTRL_REG
25029 #define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25030 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25031 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25032 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25033 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25034 #define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25035 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25036 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25037 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25038 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25039 #define CGTS_CU11_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25040 #define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25041 #define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25042 #define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25043 #define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25044 #define CGTS_CU11_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25045 #define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25046 #define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25047 #define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25048 #define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25049 //CGTS_CU11_LDS_SQ_CTRL_REG
25050 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25051 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25052 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25053 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25054 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25055 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25056 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25057 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25058 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25059 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25060 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25061 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25062 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25063 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25064 #define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25065 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25066 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25067 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25068 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25069 #define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25070 //CGTS_CU11_TA_SQC_CTRL_REG
25071 #define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25072 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25073 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25074 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25075 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25076 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25077 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25078 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25079 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25080 #define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25081 //CGTS_CU11_SP1_CTRL_REG
25082 #define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25083 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25084 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25085 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25086 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25087 #define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25088 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25089 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25090 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25091 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25092 #define CGTS_CU11_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25093 #define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25094 #define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25095 #define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25096 #define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25097 #define CGTS_CU11_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25098 #define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25099 #define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25100 #define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25101 #define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25102 //CGTS_CU11_TD_TCP_CTRL_REG
25103 #define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25104 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25105 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25106 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25107 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25108 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25109 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25110 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25111 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25112 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25113 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25114 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25115 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25116 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25117 #define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25118 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25119 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25120 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25121 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25122 #define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25123 //CGTS_CU12_SP0_CTRL_REG
25124 #define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25125 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25126 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25127 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25128 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25129 #define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25130 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25131 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25132 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25133 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25134 #define CGTS_CU12_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25135 #define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25136 #define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25137 #define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25138 #define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25139 #define CGTS_CU12_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25140 #define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25141 #define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25142 #define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25143 #define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25144 //CGTS_CU12_LDS_SQ_CTRL_REG
25145 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25146 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25147 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25148 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25149 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25150 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25151 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25152 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25153 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25154 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25155 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25156 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25157 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25158 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25159 #define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25160 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25161 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25162 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25163 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25164 #define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25165 //CGTS_CU12_TA_SQC_CTRL_REG
25166 #define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25167 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25168 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25169 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25170 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25171 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
25172 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
25173 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
25174 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
25175 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
25176 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25177 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25178 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25179 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25180 #define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25181 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
25182 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
25183 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
25184 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
25185 #define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
25186 //CGTS_CU12_SP1_CTRL_REG
25187 #define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25188 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25189 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25190 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25191 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25192 #define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25193 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25194 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25195 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25196 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25197 #define CGTS_CU12_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25198 #define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25199 #define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25200 #define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25201 #define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25202 #define CGTS_CU12_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25203 #define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25204 #define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25205 #define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25206 #define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25207 //CGTS_CU12_TD_TCP_CTRL_REG
25208 #define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25209 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25210 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25211 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25212 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25213 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25214 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25215 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25216 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25217 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25218 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25219 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25220 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25221 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25222 #define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25223 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25224 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25225 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25226 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25227 #define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25228 //CGTS_CU13_SP0_CTRL_REG
25229 #define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25230 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25231 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25232 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25233 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25234 #define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25235 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25236 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25237 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25238 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25239 #define CGTS_CU13_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25240 #define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25241 #define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25242 #define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25243 #define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25244 #define CGTS_CU13_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25245 #define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25246 #define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25247 #define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25248 #define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25249 //CGTS_CU13_LDS_SQ_CTRL_REG
25250 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25251 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25252 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25253 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25254 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25255 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25256 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25257 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25258 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25259 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25260 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25261 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25262 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25263 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25264 #define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25265 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25266 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25267 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25268 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25269 #define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25270 //CGTS_CU13_TA_SQC_CTRL_REG
25271 #define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25272 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25273 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25274 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25275 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25276 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25277 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25278 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25279 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25280 #define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25281 //CGTS_CU13_SP1_CTRL_REG
25282 #define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25283 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25284 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25285 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25286 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25287 #define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25288 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25289 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25290 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25291 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25292 #define CGTS_CU13_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25293 #define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25294 #define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25295 #define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25296 #define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25297 #define CGTS_CU13_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25298 #define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25299 #define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25300 #define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25301 #define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25302 //CGTS_CU13_TD_TCP_CTRL_REG
25303 #define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25304 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25305 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25306 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25307 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25308 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25309 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25310 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25311 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25312 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25313 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25314 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25315 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25316 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25317 #define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25318 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25319 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25320 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25321 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25322 #define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25323 //CGTS_CU14_SP0_CTRL_REG
25324 #define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25325 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25326 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25327 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25328 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25329 #define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25330 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25331 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25332 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25333 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25334 #define CGTS_CU14_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25335 #define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25336 #define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25337 #define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25338 #define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25339 #define CGTS_CU14_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25340 #define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25341 #define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25342 #define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25343 #define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25344 //CGTS_CU14_LDS_SQ_CTRL_REG
25345 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25346 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25347 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25348 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25349 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25350 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25351 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25352 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25353 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25354 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25355 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25356 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25357 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25358 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25359 #define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25360 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25361 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25362 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25363 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25364 #define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25365 //CGTS_CU14_TA_SQC_CTRL_REG
25366 #define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25367 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25368 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25369 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25370 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25371 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25372 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25373 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25374 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25375 #define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25376 //CGTS_CU14_SP1_CTRL_REG
25377 #define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25378 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25379 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25380 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25381 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25382 #define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25383 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25384 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25385 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25386 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25387 #define CGTS_CU14_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25388 #define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25389 #define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25390 #define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25391 #define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25392 #define CGTS_CU14_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25393 #define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25394 #define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25395 #define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25396 #define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25397 //CGTS_CU14_TD_TCP_CTRL_REG
25398 #define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25399 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25400 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25401 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25402 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25403 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25404 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25405 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25406 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25407 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25408 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25409 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25410 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25411 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25412 #define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25413 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25414 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25415 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25416 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25417 #define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25418 //CGTS_CU15_SP0_CTRL_REG
25419 #define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT                                                                   0x0
25420 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT                                                          0x7
25421 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT                                                     0x8
25422 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT                                                       0xa
25423 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25424 #define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT                                                                   0x10
25425 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT                                                          0x17
25426 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT                                                     0x18
25427 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT                                                       0x1a
25428 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25429 #define CGTS_CU15_SP0_CTRL_REG__SP00_MASK                                                                     0x0000007FL
25430 #define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK                                                            0x00000080L
25431 #define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK                                                       0x00000300L
25432 #define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK                                                         0x00000400L
25433 #define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25434 #define CGTS_CU15_SP0_CTRL_REG__SP01_MASK                                                                     0x007F0000L
25435 #define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK                                                            0x00800000L
25436 #define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK                                                       0x03000000L
25437 #define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK                                                         0x04000000L
25438 #define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25439 //CGTS_CU15_LDS_SQ_CTRL_REG
25440 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT                                                                 0x0
25441 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT                                                        0x7
25442 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT                                                   0x8
25443 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT                                                     0xa
25444 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT                                               0xb
25445 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT                                                                  0x10
25446 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT                                                         0x17
25447 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT                                                    0x18
25448 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT                                                      0x1a
25449 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT                                                0x1b
25450 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK                                                                   0x0000007FL
25451 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK                                                          0x00000080L
25452 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK                                                     0x00000300L
25453 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK                                                       0x00000400L
25454 #define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK                                                 0x00000800L
25455 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK                                                                    0x007F0000L
25456 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK                                                           0x00800000L
25457 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK                                                      0x03000000L
25458 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK                                                        0x04000000L
25459 #define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK                                                  0x08000000L
25460 //CGTS_CU15_TA_SQC_CTRL_REG
25461 #define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT                                                                  0x0
25462 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT                                                         0x7
25463 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT                                                    0x8
25464 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT                                                      0xa
25465 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25466 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT                                                                 0x10
25467 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT                                                        0x17
25468 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT                                                   0x18
25469 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT                                                     0x1a
25470 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT                                               0x1b
25471 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK                                                                    0x0000007FL
25472 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK                                                           0x00000080L
25473 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK                                                      0x00000300L
25474 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK                                                        0x00000400L
25475 #define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25476 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK                                                                   0x007F0000L
25477 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK                                                          0x00800000L
25478 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK                                                     0x03000000L
25479 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK                                                       0x04000000L
25480 #define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK                                                 0x08000000L
25481 //CGTS_CU15_SP1_CTRL_REG
25482 #define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT                                                                   0x0
25483 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT                                                          0x7
25484 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT                                                     0x8
25485 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT                                                       0xa
25486 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25487 #define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT                                                                   0x10
25488 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT                                                          0x17
25489 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT                                                     0x18
25490 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT                                                       0x1a
25491 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT                                                 0x1b
25492 #define CGTS_CU15_SP1_CTRL_REG__SP10_MASK                                                                     0x0000007FL
25493 #define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK                                                            0x00000080L
25494 #define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK                                                       0x00000300L
25495 #define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK                                                         0x00000400L
25496 #define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25497 #define CGTS_CU15_SP1_CTRL_REG__SP11_MASK                                                                     0x007F0000L
25498 #define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK                                                            0x00800000L
25499 #define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK                                                       0x03000000L
25500 #define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK                                                         0x04000000L
25501 #define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK                                                   0x08000000L
25502 //CGTS_CU15_TD_TCP_CTRL_REG
25503 #define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT                                                                  0x0
25504 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT                                                         0x7
25505 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT                                                    0x8
25506 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT                                                      0xa
25507 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25508 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT                                                                0x10
25509 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT                                                       0x17
25510 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT                                                  0x18
25511 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT                                                    0x1a
25512 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT                                              0x1b
25513 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK                                                                    0x0000007FL
25514 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK                                                           0x00000080L
25515 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK                                                      0x00000300L
25516 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK                                                        0x00000400L
25517 #define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25518 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK                                                                  0x007F0000L
25519 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK                                                         0x00800000L
25520 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK                                                    0x03000000L
25521 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK                                                      0x04000000L
25522 #define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK                                                0x08000000L
25523 //CGTS_CU0_TCPI_CTRL_REG
25524 #define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25525 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25526 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25527 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25528 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25529 #define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25530 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25531 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25532 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25533 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25534 #define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25535 #define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25536 //CGTS_CU1_TCPI_CTRL_REG
25537 #define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25538 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25539 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25540 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25541 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25542 #define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25543 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25544 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25545 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25546 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25547 #define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25548 #define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25549 //CGTS_CU2_TCPI_CTRL_REG
25550 #define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25551 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25552 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25553 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25554 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25555 #define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25556 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25557 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25558 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25559 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25560 #define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25561 #define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25562 //CGTS_CU3_TCPI_CTRL_REG
25563 #define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25564 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25565 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25566 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25567 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25568 #define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25569 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25570 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25571 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25572 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25573 #define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25574 #define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25575 //CGTS_CU4_TCPI_CTRL_REG
25576 #define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25577 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25578 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25579 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25580 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25581 #define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25582 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25583 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25584 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25585 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25586 #define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25587 #define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25588 //CGTS_CU5_TCPI_CTRL_REG
25589 #define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25590 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25591 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25592 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25593 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25594 #define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25595 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25596 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25597 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25598 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25599 #define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25600 #define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25601 //CGTS_CU6_TCPI_CTRL_REG
25602 #define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25603 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25604 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25605 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25606 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25607 #define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25608 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25609 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25610 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25611 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25612 #define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25613 #define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25614 //CGTS_CU7_TCPI_CTRL_REG
25615 #define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25616 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25617 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25618 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25619 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25620 #define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25621 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25622 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25623 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25624 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25625 #define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25626 #define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25627 //CGTS_CU8_TCPI_CTRL_REG
25628 #define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25629 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25630 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25631 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25632 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25633 #define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25634 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25635 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25636 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25637 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25638 #define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25639 #define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25640 //CGTS_CU9_TCPI_CTRL_REG
25641 #define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT                                                                   0x0
25642 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                          0x7
25643 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                     0x8
25644 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                       0xa
25645 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                 0xb
25646 #define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT                                                               0xc
25647 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK                                                                     0x0000007FL
25648 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                            0x00000080L
25649 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                       0x00000300L
25650 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                         0x00000400L
25651 #define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                   0x00000800L
25652 #define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK                                                                 0xFFFFF000L
25653 //CGTS_CU10_TCPI_CTRL_REG
25654 #define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25655 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25656 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25657 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25658 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25659 #define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25660 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25661 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25662 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25663 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25664 #define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25665 #define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25666 //CGTS_CU11_TCPI_CTRL_REG
25667 #define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25668 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25669 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25670 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25671 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25672 #define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25673 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25674 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25675 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25676 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25677 #define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25678 #define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25679 //CGTS_CU12_TCPI_CTRL_REG
25680 #define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25681 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25682 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25683 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25684 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25685 #define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25686 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25687 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25688 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25689 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25690 #define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25691 #define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25692 //CGTS_CU13_TCPI_CTRL_REG
25693 #define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25694 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25695 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25696 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25697 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25698 #define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25699 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25700 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25701 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25702 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25703 #define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25704 #define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25705 //CGTS_CU14_TCPI_CTRL_REG
25706 #define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25707 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25708 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25709 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25710 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25711 #define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25712 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25713 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25714 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25715 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25716 #define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25717 #define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25718 //CGTS_CU15_TCPI_CTRL_REG
25719 #define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT                                                                  0x0
25720 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT                                                         0x7
25721 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT                                                    0x8
25722 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT                                                      0xa
25723 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT                                                0xb
25724 #define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT                                                              0xc
25725 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK                                                                    0x0000007FL
25726 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK                                                           0x00000080L
25727 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK                                                      0x00000300L
25728 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK                                                        0x00000400L
25729 #define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK                                                  0x00000800L
25730 #define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK                                                                0xFFFFF000L
25731 //CGTT_SPI_CLK_CTRL
25732 #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
25733 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
25734 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                            0x12
25735 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                            0x18
25736 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT                                                         0x1a
25737 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT                                                               0x1b
25738 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT                                                               0x1c
25739 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT                                                               0x1d
25740 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT                                                               0x1e
25741 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
25742 #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
25743 #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25744 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                              0x00FC0000L
25745 #define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                              0x01000000L
25746 #define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK                                                           0x04000000L
25747 #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK                                                                 0x08000000L
25748 #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK                                                                 0x10000000L
25749 #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK                                                                 0x20000000L
25750 #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK                                                                 0x40000000L
25751 #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
25752 //CGTT_PC_CLK_CTRL
25753 #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25754 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25755 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT                                                             0x12
25756 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT                                                             0x18
25757 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT                                                     0x19
25758 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT                                                      0x1a
25759 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                               0x1b
25760 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                               0x1c
25761 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                               0x1d
25762 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                               0x1e
25763 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
25764 #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25765 #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25766 #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK                                                               0x00FC0000L
25767 #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK                                                               0x01000000L
25768 #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK                                                       0x02000000L
25769 #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK                                                        0x04000000L
25770 #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                 0x08000000L
25771 #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                 0x10000000L
25772 #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                 0x20000000L
25773 #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                 0x40000000L
25774 #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
25775 //CGTT_BCI_CLK_CTRL
25776 #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
25777 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
25778 #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT                                                                    0xc
25779 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
25780 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
25781 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
25782 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
25783 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
25784 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
25785 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
25786 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
25787 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT                                                              0x18
25788 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT                                                              0x19
25789 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT                                                              0x1a
25790 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT                                                              0x1b
25791 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT                                                              0x1c
25792 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT                                                              0x1d
25793 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT                                                              0x1e
25794 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
25795 #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
25796 #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25797 #define CGTT_BCI_CLK_CTRL__RESERVED_MASK                                                                      0x0000F000L
25798 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
25799 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
25800 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
25801 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
25802 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
25803 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
25804 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
25805 #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
25806 #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK                                                                0x01000000L
25807 #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK                                                                0x02000000L
25808 #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK                                                                0x04000000L
25809 #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK                                                                0x08000000L
25810 #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK                                                                0x10000000L
25811 #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK                                                                0x20000000L
25812 #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK                                                                0x40000000L
25813 #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
25814 //CGTT_VGT_CLK_CTRL
25815 #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
25816 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
25817 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT                                                                 0xf
25818 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT                                                                  0x10
25819 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
25820 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
25821 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
25822 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
25823 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
25824 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
25825 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
25826 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT                                                              0x18
25827 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                              0x19
25828 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x1a
25829 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                            0x1b
25830 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                               0x1c
25831 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT                                                                 0x1d
25832 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
25833 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
25834 #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
25835 #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25836 #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK                                                                   0x00008000L
25837 #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK                                                                    0x00010000L
25838 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
25839 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
25840 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
25841 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
25842 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
25843 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
25844 #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
25845 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK                                                                0x01000000L
25846 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                0x02000000L
25847 #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x04000000L
25848 #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                              0x08000000L
25849 #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK                                                                 0x10000000L
25850 #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK                                                                   0x20000000L
25851 #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
25852 #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
25853 //CGTT_IA_CLK_CTRL
25854 #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25855 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25856 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
25857 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
25858 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
25859 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
25860 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
25861 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
25862 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
25863 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
25864 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
25865 #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0x19
25866 #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT                                                                   0x1a
25867 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
25868 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
25869 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                               0x1d
25870 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
25871 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
25872 #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25873 #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25874 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
25875 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
25876 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
25877 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
25878 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
25879 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
25880 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
25881 #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
25882 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
25883 #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x02000000L
25884 #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK                                                                     0x04000000L
25885 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
25886 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
25887 #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                 0x20000000L
25888 #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
25889 #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
25890 //CGTT_WD_CLK_CTRL
25891 #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25892 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25893 #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT                                                                  0xf
25894 #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT                                                                   0x10
25895 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
25896 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
25897 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
25898 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
25899 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
25900 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
25901 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
25902 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT                                                               0x19
25903 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x1a
25904 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                             0x1b
25905 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT                                                                0x1c
25906 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1d
25907 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                          0x1e
25908 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
25909 #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25910 #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25911 #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK                                                                    0x00008000L
25912 #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK                                                                     0x00010000L
25913 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
25914 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
25915 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
25916 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
25917 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
25918 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
25919 #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
25920 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK                                                                 0x02000000L
25921 #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x04000000L
25922 #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                               0x08000000L
25923 #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK                                                                  0x10000000L
25924 #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x20000000L
25925 #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                            0x40000000L
25926 #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
25927 //CGTT_PA_CLK_CTRL
25928 #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
25929 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
25930 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
25931 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
25932 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
25933 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
25934 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
25935 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
25936 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
25937 #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT                                                                 0x17
25938 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                               0x18
25939 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                               0x19
25940 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                               0x1a
25941 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                               0x1b
25942 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                               0x1c
25943 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT                                                              0x1d
25944 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT                                                              0x1e
25945 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT                                                             0x1f
25946 #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
25947 #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
25948 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
25949 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
25950 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
25951 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
25952 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
25953 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
25954 #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
25955 #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK                                                                   0x00800000L
25956 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                 0x01000000L
25957 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                 0x02000000L
25958 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                 0x04000000L
25959 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                 0x08000000L
25960 #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                 0x10000000L
25961 #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK                                                                0x20000000L
25962 #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK                                                                0x40000000L
25963 #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK                                                               0x80000000L
25964 //CGTT_SC_CLK_CTRL0
25965 #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
25966 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
25967 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT                                              0x10
25968 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x11
25969 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x12
25970 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x13
25971 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x14
25972 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x15
25973 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x16
25974 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT                                                      0x17
25975 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT                                                    0x18
25976 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x19
25977 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1a
25978 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1b
25979 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1c
25980 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1d
25981 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1e
25982 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT                                                            0x1f
25983 #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
25984 #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
25985 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK                                                0x00010000L
25986 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00020000L
25987 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00040000L
25988 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00080000L
25989 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00100000L
25990 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00200000L
25991 #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00400000L
25992 #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK                                                        0x00800000L
25993 #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK                                                      0x01000000L
25994 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x02000000L
25995 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x04000000L
25996 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x08000000L
25997 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x10000000L
25998 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x20000000L
25999 #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x40000000L
26000 #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK                                                              0x80000000L
26001 //CGTT_SC_CLK_CTRL1
26002 #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
26003 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
26004 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT                                              0x11
26005 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT                                              0x12
26006 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT                                     0x13
26007 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT                                           0x14
26008 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT                                            0x15
26009 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT                                                      0x16
26010 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT                                                    0x19
26011 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT                                                    0x1a
26012 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT                                           0x1b
26013 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT                                                 0x1c
26014 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT                                                  0x1d
26015 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT                                                            0x1e
26016 #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
26017 #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26018 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK                                                0x00020000L
26019 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK                                                0x00040000L
26020 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK                                       0x00080000L
26021 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK                                             0x00100000L
26022 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK                                              0x00200000L
26023 #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK                                                        0x00400000L
26024 #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK                                                      0x02000000L
26025 #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK                                                      0x04000000L
26026 #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK                                             0x08000000L
26027 #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK                                                   0x10000000L
26028 #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK                                                    0x20000000L
26029 #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK                                                              0x40000000L
26030 //CGTT_SQ_CLK_CTRL
26031 #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
26032 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
26033 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
26034 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
26035 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
26036 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
26037 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
26038 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
26039 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
26040 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
26041 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                             0x1d
26042 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                                0x1e
26043 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                 0x1f
26044 #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
26045 #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
26046 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
26047 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
26048 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
26049 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
26050 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
26051 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
26052 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
26053 #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
26054 #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                               0x20000000L
26055 #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x40000000L
26056 #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
26057 //CGTT_SQG_CLK_CTRL
26058 #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26059 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26060 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26061 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26062 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26063 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26064 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26065 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26066 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26067 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26068 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT                                                             0x1c
26069 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT                                                            0x1d
26070 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT                                                               0x1e
26071 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                                0x1f
26072 #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26073 #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26074 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26075 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26076 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26077 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26078 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26079 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26080 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26081 #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26082 #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK                                                               0x10000000L
26083 #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK                                                              0x20000000L
26084 #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK                                                                 0x40000000L
26085 #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK                                                                  0x80000000L
26086 //SQ_ALU_CLK_CTRL
26087 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
26088 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
26089 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
26090 #define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
26091 //SQ_TEX_CLK_CTRL
26092 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
26093 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
26094 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
26095 #define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
26096 //SQ_LDS_CLK_CTRL
26097 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT                                                               0x0
26098 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT                                                               0x10
26099 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK                                                                 0x0000FFFFL
26100 #define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK                                                                 0xFFFF0000L
26101 //SQ_POWER_THROTTLE
26102 #define SQ_POWER_THROTTLE__MIN_POWER__SHIFT                                                                   0x0
26103 #define SQ_POWER_THROTTLE__MAX_POWER__SHIFT                                                                   0x10
26104 #define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT                                                                0x1e
26105 #define SQ_POWER_THROTTLE__MIN_POWER_MASK                                                                     0x00003FFFL
26106 #define SQ_POWER_THROTTLE__MAX_POWER_MASK                                                                     0x3FFF0000L
26107 #define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK                                                                  0xC0000000L
26108 //SQ_POWER_THROTTLE2
26109 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT                                                            0x0
26110 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                   0x10
26111 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                   0x1b
26112 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT                                                              0x1f
26113 #define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK                                                              0x00003FFFL
26114 #define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK                                                     0x03FF0000L
26115 #define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK                                                     0x78000000L
26116 #define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK                                                                0x80000000L
26117 //CGTT_SX_CLK_CTRL0
26118 #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT                                                                    0x0
26119 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT                                                              0x4
26120 #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT                                                                    0xc
26121 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26122 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26123 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26124 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26125 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26126 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26127 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26128 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26129 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT                                                              0x18
26130 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT                                                              0x19
26131 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26132 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26133 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26134 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26135 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26136 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26137 #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK                                                                      0x0000000FL
26138 #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26139 #define CGTT_SX_CLK_CTRL0__RESERVED_MASK                                                                      0x0000F000L
26140 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26141 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26142 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26143 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26144 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26145 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26146 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26147 #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26148 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26149 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26150 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26151 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26152 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26153 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26154 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26155 #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26156 //CGTT_SX_CLK_CTRL1
26157 #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT                                                                    0x0
26158 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT                                                              0x4
26159 #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT                                                                    0xc
26160 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26161 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26162 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26163 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26164 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26165 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26166 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26167 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26168 #define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT                                                                      0x18
26169 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT                                                              0x19
26170 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26171 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26172 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26173 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26174 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26175 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26176 #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK                                                                      0x0000000FL
26177 #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26178 #define CGTT_SX_CLK_CTRL1__RESERVED_MASK                                                                      0x0000F000L
26179 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26180 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26181 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26182 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26183 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26184 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26185 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26186 #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26187 #define CGTT_SX_CLK_CTRL1__DBG_EN_MASK                                                                        0x01000000L
26188 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26189 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26190 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26191 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26192 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26193 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26194 #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26195 //CGTT_SX_CLK_CTRL2
26196 #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT                                                                    0x0
26197 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT                                                              0x4
26198 #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT                                                                    0xd
26199 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26200 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26201 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26202 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26203 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26204 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26205 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26206 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26207 #define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT                                                                      0x18
26208 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT                                                              0x19
26209 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26210 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26211 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26212 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26213 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26214 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26215 #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK                                                                      0x0000000FL
26216 #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26217 #define CGTT_SX_CLK_CTRL2__RESERVED_MASK                                                                      0x0000E000L
26218 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26219 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26220 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26221 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26222 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26223 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26224 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26225 #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26226 #define CGTT_SX_CLK_CTRL2__DBG_EN_MASK                                                                        0x01000000L
26227 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26228 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26229 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26230 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26231 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26232 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26233 #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26234 //CGTT_SX_CLK_CTRL3
26235 #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT                                                                    0x0
26236 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT                                                              0x4
26237 #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT                                                                    0xd
26238 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26239 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26240 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26241 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26242 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26243 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26244 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26245 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26246 #define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT                                                                      0x18
26247 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT                                                              0x19
26248 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26249 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26250 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26251 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26252 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26253 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26254 #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK                                                                      0x0000000FL
26255 #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26256 #define CGTT_SX_CLK_CTRL3__RESERVED_MASK                                                                      0x0000E000L
26257 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26258 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26259 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26260 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26261 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26262 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26263 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26264 #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26265 #define CGTT_SX_CLK_CTRL3__DBG_EN_MASK                                                                        0x01000000L
26266 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26267 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26268 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26269 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26270 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26271 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26272 #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26273 //CGTT_SX_CLK_CTRL4
26274 #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT                                                                    0x0
26275 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT                                                              0x4
26276 #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT                                                                    0xc
26277 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26278 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26279 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26280 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26281 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26282 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26283 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26284 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26285 #define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT                                                                      0x18
26286 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT                                                              0x19
26287 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26288 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26289 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26290 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26291 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26292 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26293 #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK                                                                      0x0000000FL
26294 #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26295 #define CGTT_SX_CLK_CTRL4__RESERVED_MASK                                                                      0x0000F000L
26296 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26297 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26298 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26299 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26300 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26301 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26302 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26303 #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26304 #define CGTT_SX_CLK_CTRL4__DBG_EN_MASK                                                                        0x01000000L
26305 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26306 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26307 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26308 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26309 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26310 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26311 #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26312 //TD_CGTT_CTRL
26313 #define TD_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
26314 #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
26315 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                             0x10
26316 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                             0x11
26317 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                             0x12
26318 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                             0x13
26319 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                             0x14
26320 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                             0x15
26321 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                             0x16
26322 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                             0x17
26323 #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
26324 #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
26325 #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
26326 #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
26327 #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
26328 #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
26329 #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
26330 #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
26331 #define TD_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
26332 #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
26333 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                               0x00010000L
26334 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                               0x00020000L
26335 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                               0x00040000L
26336 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                               0x00080000L
26337 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                               0x00100000L
26338 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                               0x00200000L
26339 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                               0x00400000L
26340 #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                               0x00800000L
26341 #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
26342 #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
26343 #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
26344 #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
26345 #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
26346 #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
26347 #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
26348 #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
26349 //TA_CGTT_CTRL
26350 #define TA_CGTT_CTRL__ON_DELAY__SHIFT                                                                         0x0
26351 #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT                                                                   0x4
26352 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                             0x10
26353 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                             0x11
26354 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                             0x12
26355 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                             0x13
26356 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                             0x14
26357 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                             0x15
26358 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                             0x16
26359 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                             0x17
26360 #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT                                                                   0x18
26361 #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT                                                                   0x19
26362 #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT                                                                   0x1a
26363 #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT                                                                   0x1b
26364 #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT                                                                   0x1c
26365 #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT                                                                   0x1d
26366 #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT                                                                   0x1e
26367 #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT                                                                   0x1f
26368 #define TA_CGTT_CTRL__ON_DELAY_MASK                                                                           0x0000000FL
26369 #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK                                                                     0x00000FF0L
26370 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                               0x00010000L
26371 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                               0x00020000L
26372 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                               0x00040000L
26373 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                               0x00080000L
26374 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                               0x00100000L
26375 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                               0x00200000L
26376 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                               0x00400000L
26377 #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                               0x00800000L
26378 #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK                                                                     0x01000000L
26379 #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK                                                                     0x02000000L
26380 #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK                                                                     0x04000000L
26381 #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK                                                                     0x08000000L
26382 #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK                                                                     0x10000000L
26383 #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK                                                                     0x20000000L
26384 #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK                                                                     0x40000000L
26385 #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK                                                                     0x80000000L
26386 //CGTT_TCPI_CLK_CTRL
26387 #define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26388 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26389 #define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT                                                                      0xc
26390 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26391 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26392 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26393 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26394 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26395 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26396 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26397 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26398 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26399 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26400 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26401 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26402 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26403 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26404 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26405 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26406 #define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26407 #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26408 #define CGTT_TCPI_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
26409 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26410 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26411 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26412 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26413 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26414 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26415 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26416 #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26417 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26418 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26419 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26420 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26421 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26422 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26423 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26424 #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26425 //CGTT_TCI_CLK_CTRL
26426 #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26427 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26428 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26429 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26430 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26431 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26432 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26433 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26434 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26435 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26436 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
26437 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
26438 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26439 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26440 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26441 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26442 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26443 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26444 #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26445 #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26446 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26447 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26448 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26449 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26450 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26451 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26452 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26453 #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26454 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26455 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26456 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26457 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26458 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26459 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26460 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26461 #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26462 //CGTT_GDS_CLK_CTRL
26463 #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26464 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26465 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26466 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26467 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26468 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26469 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26470 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26471 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26472 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26473 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
26474 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
26475 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26476 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26477 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26478 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26479 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26480 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26481 #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26482 #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26483 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26484 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26485 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26486 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26487 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26488 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26489 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26490 #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26491 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26492 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26493 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26494 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26495 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26496 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26497 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26498 #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26499 //DB_CGTT_CLK_CTRL_0
26500 #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT                                                                   0x0
26501 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT                                                             0x4
26502 #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT                                                                   0xc
26503 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26504 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26505 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26506 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26507 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26508 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26509 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26510 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26511 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT                                                             0x18
26512 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT                                                             0x19
26513 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26514 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26515 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26516 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26517 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26518 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26519 #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK                                                                     0x0000000FL
26520 #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26521 #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK                                                                     0x0000F000L
26522 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26523 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26524 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26525 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26526 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26527 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26528 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26529 #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26530 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26531 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26532 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26533 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26534 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26535 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26536 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26537 #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26538 //CB_CGTT_SCLK_CTRL
26539 #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26540 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26541 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26542 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26543 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26544 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26545 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26546 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26547 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26548 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26549 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                              0x18
26550 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                              0x19
26551 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                              0x1a
26552 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                              0x1b
26553 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                              0x1c
26554 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                              0x1d
26555 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                              0x1e
26556 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                              0x1f
26557 #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26558 #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26559 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26560 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26561 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26562 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26563 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26564 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26565 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26566 #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26567 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                                0x01000000L
26568 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                                0x02000000L
26569 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                                0x04000000L
26570 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                                0x08000000L
26571 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                                0x10000000L
26572 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                                0x20000000L
26573 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                                0x40000000L
26574 #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                                0x80000000L
26575 //TCC_CGTT_SCLK_CTRL
26576 #define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26577 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26578 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26579 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26580 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26581 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26582 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26583 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26584 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26585 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26586 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26587 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26588 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26589 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26590 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26591 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26592 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26593 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26594 #define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26595 #define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26596 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26597 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26598 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26599 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26600 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26601 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26602 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26603 #define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26604 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26605 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26606 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26607 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26608 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26609 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26610 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26611 #define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26612 //TCA_CGTT_SCLK_CTRL
26613 #define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26614 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26615 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26616 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26617 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26618 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26619 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26620 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26621 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26622 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26623 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26624 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26625 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26626 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26627 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26628 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26629 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26630 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26631 #define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26632 #define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26633 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26634 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26635 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26636 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26637 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26638 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26639 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26640 #define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26641 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26642 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26643 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26644 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26645 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26646 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26647 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26648 #define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26649 //CGTT_CP_CLK_CTRL
26650 #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
26651 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
26652 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                                0xf
26653 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                         0x10
26654 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                         0x11
26655 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                         0x12
26656 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                         0x13
26657 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                         0x14
26658 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                         0x15
26659 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                         0x16
26660 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                         0x17
26661 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                        0x1d
26662 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                            0x1e
26663 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                            0x1f
26664 #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK                                                                       0x0000000FL
26665 #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                 0x00000FF0L
26666 #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                  0x00008000L
26667 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                           0x00010000L
26668 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                           0x00020000L
26669 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                           0x00040000L
26670 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                           0x00080000L
26671 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                           0x00100000L
26672 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                           0x00200000L
26673 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                           0x00400000L
26674 #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                           0x00800000L
26675 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                          0x20000000L
26676 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                              0x40000000L
26677 #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                              0x80000000L
26678 //CGTT_CPF_CLK_CTRL
26679 #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26680 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26681 #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
26682 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26683 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26684 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26685 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26686 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26687 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26688 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26689 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26690 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1d
26691 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
26692 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
26693 #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26694 #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26695 #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
26696 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26697 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26698 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26699 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26700 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26701 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26702 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26703 #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26704 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x20000000L
26705 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
26706 #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
26707 //CGTT_CPC_CLK_CTRL
26708 #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26709 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26710 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                               0xf
26711 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26712 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26713 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26714 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26715 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26716 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26717 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26718 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26719 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT                                                       0x1d
26720 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
26721 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
26722 #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26723 #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26724 #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK                                                                 0x00008000L
26725 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26726 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26727 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26728 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26729 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26730 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26731 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26732 #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26733 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK                                                         0x20000000L
26734 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
26735 #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
26736 //CGTT_RLC_CLK_CTRL
26737 #define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT                                                                    0x0
26738 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                              0x4
26739 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                        0x10
26740 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                        0x11
26741 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                        0x12
26742 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                        0x13
26743 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                        0x14
26744 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                        0x15
26745 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                        0x16
26746 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                        0x17
26747 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT                                                           0x1e
26748 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT                                                           0x1f
26749 #define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK                                                                      0x0000000FL
26750 #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                0x00000FF0L
26751 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                          0x00010000L
26752 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                          0x00020000L
26753 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                          0x00040000L
26754 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                          0x00080000L
26755 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                          0x00100000L
26756 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                          0x00200000L
26757 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                          0x00400000L
26758 #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                          0x00800000L
26759 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK                                                             0x40000000L
26760 #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK                                                             0x80000000L
26761 //RLC_GFX_RM_CNTL
26762 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT                                                              0x0
26763 #define RLC_GFX_RM_CNTL__RESERVED__SHIFT                                                                      0x1
26764 #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK                                                                0x00000001L
26765 #define RLC_GFX_RM_CNTL__RESERVED_MASK                                                                        0xFFFFFFFEL
26766 //RMI_CGTT_SCLK_CTRL
26767 #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26768 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26769 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26770 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26771 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26772 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26773 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26774 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26775 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26776 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26777 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26778 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26779 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26780 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26781 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26782 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26783 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26784 #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26785 #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26786 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26787 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26788 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26789 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26790 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26791 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26792 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26793 #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26794 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26795 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26796 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26797 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26798 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26799 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26800 #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26801 //CGTT_TCPF_CLK_CTRL
26802 #define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26803 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26804 #define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT                                                                      0xc
26805 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT                                                       0x10
26806 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                       0x11
26807 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                       0x12
26808 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                       0x13
26809 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                       0x14
26810 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                       0x15
26811 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                       0x16
26812 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                       0x17
26813 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                             0x18
26814 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                             0x19
26815 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                             0x1a
26816 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                             0x1b
26817 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                             0x1c
26818 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                             0x1d
26819 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                             0x1e
26820 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                             0x1f
26821 #define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26822 #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26823 #define CGTT_TCPF_CLK_CTRL__SPARE_MASK                                                                        0x0000F000L
26824 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK                                                         0x00010000L
26825 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                         0x00020000L
26826 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                         0x00040000L
26827 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                         0x00080000L
26828 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                         0x00100000L
26829 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                         0x00200000L
26830 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                         0x00400000L
26831 #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                         0x00800000L
26832 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                               0x01000000L
26833 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                               0x02000000L
26834 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                               0x04000000L
26835 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                               0x08000000L
26836 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                               0x10000000L
26837 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                               0x20000000L
26838 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                               0x40000000L
26839 #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                               0x80000000L
26840 
26841 
26842 // addressBlock: gc_ea_pwrdec
26843 //GCEA_CGTT_CLK_CTRL
26844 #define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                   0x0
26845 #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                             0x4
26846 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                        0x16
26847 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                       0x1e
26848 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                     0x1f
26849 #define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                     0x0000000FL
26850 #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                               0x00000FF0L
26851 #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                          0x00400000L
26852 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                         0x40000000L
26853 #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                       0x80000000L
26854 
26855 
26856 // addressBlock: gc_utcl2_vmsharedhvdec
26857 //MC_VM_FB_SIZE_OFFSET_VF0
26858 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                                           0x0
26859 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                                         0x10
26860 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26861 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26862 //MC_VM_FB_SIZE_OFFSET_VF1
26863 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                                           0x0
26864 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                                         0x10
26865 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26866 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26867 //MC_VM_FB_SIZE_OFFSET_VF2
26868 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                                           0x0
26869 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                                         0x10
26870 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26871 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26872 //MC_VM_FB_SIZE_OFFSET_VF3
26873 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                                           0x0
26874 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                                         0x10
26875 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26876 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26877 //MC_VM_FB_SIZE_OFFSET_VF4
26878 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                                           0x0
26879 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                                         0x10
26880 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26881 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26882 //MC_VM_FB_SIZE_OFFSET_VF5
26883 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                                           0x0
26884 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                                         0x10
26885 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26886 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26887 //MC_VM_FB_SIZE_OFFSET_VF6
26888 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                                           0x0
26889 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                                         0x10
26890 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26891 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26892 //MC_VM_FB_SIZE_OFFSET_VF7
26893 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                                           0x0
26894 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                                         0x10
26895 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26896 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26897 //MC_VM_FB_SIZE_OFFSET_VF8
26898 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                                           0x0
26899 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                                         0x10
26900 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26901 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26902 //MC_VM_FB_SIZE_OFFSET_VF9
26903 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                                           0x0
26904 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                                         0x10
26905 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                             0x0000FFFFL
26906 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                                           0xFFFF0000L
26907 //MC_VM_FB_SIZE_OFFSET_VF10
26908 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                                          0x0
26909 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                                        0x10
26910 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26911 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26912 //MC_VM_FB_SIZE_OFFSET_VF11
26913 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                                          0x0
26914 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                                        0x10
26915 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26916 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26917 //MC_VM_FB_SIZE_OFFSET_VF12
26918 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                                          0x0
26919 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                                        0x10
26920 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26921 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26922 //MC_VM_FB_SIZE_OFFSET_VF13
26923 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                                          0x0
26924 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                                        0x10
26925 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26926 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26927 //MC_VM_FB_SIZE_OFFSET_VF14
26928 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                                          0x0
26929 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                                        0x10
26930 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26931 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26932 //MC_VM_FB_SIZE_OFFSET_VF15
26933 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                                          0x0
26934 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                                        0x10
26935 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                            0x0000FFFFL
26936 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                                          0xFFFF0000L
26937 //VM_IOMMU_MMIO_CNTRL_1
26938 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                                 0x8
26939 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                                   0x00000100L
26940 //MC_VM_MARC_BASE_LO_0
26941 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                                           0xc
26942 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                             0xFFFFF000L
26943 //MC_VM_MARC_BASE_LO_1
26944 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                                           0xc
26945 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                             0xFFFFF000L
26946 //MC_VM_MARC_BASE_LO_2
26947 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                                           0xc
26948 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                             0xFFFFF000L
26949 //MC_VM_MARC_BASE_LO_3
26950 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                                           0xc
26951 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                             0xFFFFF000L
26952 //MC_VM_MARC_BASE_HI_0
26953 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                                           0x0
26954 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                             0x000FFFFFL
26955 //MC_VM_MARC_BASE_HI_1
26956 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                                           0x0
26957 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                             0x000FFFFFL
26958 //MC_VM_MARC_BASE_HI_2
26959 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                                           0x0
26960 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                             0x000FFFFFL
26961 //MC_VM_MARC_BASE_HI_3
26962 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                                           0x0
26963 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                             0x000FFFFFL
26964 //MC_VM_MARC_RELOC_LO_0
26965 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                                           0x0
26966 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                                         0x1
26967 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                                         0xc
26968 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                             0x00000001L
26969 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                                           0x00000002L
26970 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                                           0xFFFFF000L
26971 //MC_VM_MARC_RELOC_LO_1
26972 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                                           0x0
26973 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                                         0x1
26974 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                                         0xc
26975 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                             0x00000001L
26976 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                                           0x00000002L
26977 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                                           0xFFFFF000L
26978 //MC_VM_MARC_RELOC_LO_2
26979 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                                           0x0
26980 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                                         0x1
26981 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                                         0xc
26982 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                             0x00000001L
26983 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                                           0x00000002L
26984 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                                           0xFFFFF000L
26985 //MC_VM_MARC_RELOC_LO_3
26986 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                                           0x0
26987 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                                         0x1
26988 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                                         0xc
26989 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                             0x00000001L
26990 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                                           0x00000002L
26991 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                                           0xFFFFF000L
26992 //MC_VM_MARC_RELOC_HI_0
26993 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                                         0x0
26994 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                                           0x000FFFFFL
26995 //MC_VM_MARC_RELOC_HI_1
26996 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                                         0x0
26997 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                                           0x000FFFFFL
26998 //MC_VM_MARC_RELOC_HI_2
26999 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                                         0x0
27000 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                                           0x000FFFFFL
27001 //MC_VM_MARC_RELOC_HI_3
27002 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                                         0x0
27003 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                                           0x000FFFFFL
27004 //MC_VM_MARC_LEN_LO_0
27005 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                             0xc
27006 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                               0xFFFFF000L
27007 //MC_VM_MARC_LEN_LO_1
27008 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                             0xc
27009 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                               0xFFFFF000L
27010 //MC_VM_MARC_LEN_LO_2
27011 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                             0xc
27012 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                               0xFFFFF000L
27013 //MC_VM_MARC_LEN_LO_3
27014 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                             0xc
27015 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                               0xFFFFF000L
27016 //MC_VM_MARC_LEN_HI_0
27017 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                             0x0
27018 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                               0x000FFFFFL
27019 //MC_VM_MARC_LEN_HI_1
27020 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                             0x0
27021 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                               0x000FFFFFL
27022 //MC_VM_MARC_LEN_HI_2
27023 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                             0x0
27024 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                               0x000FFFFFL
27025 //MC_VM_MARC_LEN_HI_3
27026 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                             0x0
27027 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                               0x000FFFFFL
27028 //VM_IOMMU_CONTROL_REGISTER
27029 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                             0x0
27030 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                               0x00000001L
27031 //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
27032 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                  0xd
27033 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                    0x00002000L
27034 //VM_PCIE_ATS_CNTL
27035 #define VM_PCIE_ATS_CNTL__STU__SHIFT                                                                          0x10
27036 #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                   0x1f
27037 #define VM_PCIE_ATS_CNTL__STU_MASK                                                                            0x001F0000L
27038 #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                     0x80000000L
27039 //VM_PCIE_ATS_CNTL_VF_0
27040 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                              0x1f
27041 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                                0x80000000L
27042 //VM_PCIE_ATS_CNTL_VF_1
27043 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                              0x1f
27044 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                                0x80000000L
27045 //VM_PCIE_ATS_CNTL_VF_2
27046 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                              0x1f
27047 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                                0x80000000L
27048 //VM_PCIE_ATS_CNTL_VF_3
27049 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                              0x1f
27050 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                                0x80000000L
27051 //VM_PCIE_ATS_CNTL_VF_4
27052 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                              0x1f
27053 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                                0x80000000L
27054 //VM_PCIE_ATS_CNTL_VF_5
27055 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                              0x1f
27056 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                                0x80000000L
27057 //VM_PCIE_ATS_CNTL_VF_6
27058 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                              0x1f
27059 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                                0x80000000L
27060 //VM_PCIE_ATS_CNTL_VF_7
27061 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                              0x1f
27062 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                                0x80000000L
27063 //VM_PCIE_ATS_CNTL_VF_8
27064 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                              0x1f
27065 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                                0x80000000L
27066 //VM_PCIE_ATS_CNTL_VF_9
27067 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                              0x1f
27068 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                                0x80000000L
27069 //VM_PCIE_ATS_CNTL_VF_10
27070 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                             0x1f
27071 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                               0x80000000L
27072 //VM_PCIE_ATS_CNTL_VF_11
27073 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                             0x1f
27074 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                               0x80000000L
27075 //VM_PCIE_ATS_CNTL_VF_12
27076 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                             0x1f
27077 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                               0x80000000L
27078 //VM_PCIE_ATS_CNTL_VF_13
27079 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                             0x1f
27080 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                               0x80000000L
27081 //VM_PCIE_ATS_CNTL_VF_14
27082 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                             0x1f
27083 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                               0x80000000L
27084 //VM_PCIE_ATS_CNTL_VF_15
27085 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                             0x1f
27086 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                               0x80000000L
27087 //UTCL2_CGTT_CLK_CTRL
27088 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
27089 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
27090 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                                       0xc
27091 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                             0xf
27092 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                       0x10
27093 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                             0x18
27094 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
27095 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
27096 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                                         0x00007000L
27097 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                               0x00008000L
27098 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                         0x00FF0000L
27099 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                               0xFF000000L
27100 
27101 
27102 // addressBlock: gc_hypdec
27103 //CP_HYP_PFP_UCODE_ADDR
27104 #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
27105 #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x00003FFFL
27106 //CP_PFP_UCODE_ADDR
27107 #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                  0x0
27108 #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK                                                                    0x00003FFFL
27109 //CP_HYP_PFP_UCODE_DATA
27110 #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
27111 #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
27112 //CP_PFP_UCODE_DATA
27113 #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT                                                                  0x0
27114 #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK                                                                    0xFFFFFFFFL
27115 //CP_HYP_ME_UCODE_ADDR
27116 #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
27117 #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x00001FFFL
27118 //CP_ME_RAM_RADDR
27119 #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT                                                                  0x0
27120 #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK                                                                    0x00001FFFL
27121 //CP_ME_RAM_WADDR
27122 #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT                                                                  0x0
27123 #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK                                                                    0x00001FFFL
27124 //CP_HYP_ME_UCODE_DATA
27125 #define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
27126 #define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
27127 //CP_ME_RAM_DATA
27128 #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT                                                                    0x0
27129 #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK                                                                      0xFFFFFFFFL
27130 //CP_CE_UCODE_ADDR
27131 #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                   0x0
27132 #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                     0x00000FFFL
27133 //CP_HYP_CE_UCODE_ADDR
27134 #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT                                                               0x0
27135 #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK                                                                 0x00000FFFL
27136 //CP_CE_UCODE_DATA
27137 #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                                   0x0
27138 #define CP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                     0xFFFFFFFFL
27139 //CP_HYP_CE_UCODE_DATA
27140 #define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT                                                               0x0
27141 #define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK                                                                 0xFFFFFFFFL
27142 //CP_HYP_MEC1_UCODE_ADDR
27143 #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
27144 #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x0001FFFFL
27145 //CP_MEC_ME1_UCODE_ADDR
27146 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
27147 #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x0001FFFFL
27148 //CP_HYP_MEC1_UCODE_DATA
27149 #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
27150 #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
27151 //CP_MEC_ME1_UCODE_DATA
27152 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
27153 #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
27154 //CP_HYP_MEC2_UCODE_ADDR
27155 #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
27156 #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x0001FFFFL
27157 //CP_MEC_ME2_UCODE_ADDR
27158 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT                                                              0x0
27159 #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK                                                                0x0001FFFFL
27160 //CP_HYP_MEC2_UCODE_DATA
27161 #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
27162 #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
27163 //CP_MEC_ME2_UCODE_DATA
27164 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT                                                              0x0
27165 #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK                                                                0xFFFFFFFFL
27166 //RLC_GPM_UCODE_ADDR
27167 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                 0x0
27168 #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT                                                                   0xe
27169 #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK                                                                   0x00003FFFL
27170 #define RLC_GPM_UCODE_ADDR__RESERVED_MASK                                                                     0xFFFFC000L
27171 //RLC_GPM_UCODE_DATA
27172 #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT                                                                 0x0
27173 #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK                                                                   0xFFFFFFFFL
27174 //GRBM_GFX_INDEX_SR_SELECT
27175 #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT                                                                0x0
27176 #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK                                                                  0x00000007L
27177 //GRBM_GFX_INDEX_SR_DATA
27178 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT                                                         0x0
27179 #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT                                                               0x8
27180 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT                                                               0x10
27181 #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT                                                    0x1d
27182 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT                                              0x1e
27183 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT                                                    0x1f
27184 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK                                                           0x000000FFL
27185 #define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK                                                                 0x0000FF00L
27186 #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK                                                                 0x00FF0000L
27187 #define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK                                                      0x20000000L
27188 #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK                                                0x40000000L
27189 #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK                                                      0x80000000L
27190 //GRBM_GFX_CNTL_SR_SELECT
27191 #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT                                                                 0x0
27192 #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK                                                                   0x00000007L
27193 //GRBM_GFX_CNTL_SR_DATA
27194 #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT                                                                  0x0
27195 #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT                                                                    0x2
27196 #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT                                                                    0x4
27197 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT                                                                 0x8
27198 #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK                                                                    0x00000003L
27199 #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK                                                                      0x0000000CL
27200 #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK                                                                      0x000000F0L
27201 #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK                                                                   0x00000700L
27202 //GRBM_CAM_INDEX
27203 #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT                                                                      0x0
27204 #define GRBM_CAM_INDEX__CAM_INDEX_MASK                                                                        0x00000007L
27205 //GRBM_HYP_CAM_INDEX
27206 #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT                                                                  0x0
27207 #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK                                                                    0x00000007L
27208 //GRBM_CAM_DATA
27209 #define GRBM_CAM_DATA__CAM_ADDR__SHIFT                                                                        0x0
27210 #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT                                                                   0x10
27211 #define GRBM_CAM_DATA__CAM_ADDR_MASK                                                                          0x0000FFFFL
27212 #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK                                                                     0xFFFF0000L
27213 //GRBM_HYP_CAM_DATA
27214 #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT                                                                    0x0
27215 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT                                                               0x10
27216 #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK                                                                      0x0000FFFFL
27217 #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK                                                                 0xFFFF0000L
27218 //RLC_GPU_IOV_VF_ENABLE
27219 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT                                                               0x0
27220 #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT                                                                0x1
27221 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT                                                                  0x10
27222 #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK                                                                 0x00000001L
27223 #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK                                                                  0x0000FFFEL
27224 #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK                                                                    0xFFFF0000L
27225 //RLC_GPU_IOV_CFG_REG6
27226 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT                                                               0x0
27227 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT                                                           0x7
27228 #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT                                                                 0x8
27229 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT                                                             0xa
27230 #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK                                                                 0x0000007FL
27231 #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK                                                             0x00000080L
27232 #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK                                                                   0x00000300L
27233 #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK                                                               0xFFFFFC00L
27234 //RLC_GPU_IOV_CFG_REG8
27235 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT                                                           0x0
27236 #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK                                                             0xFFFFFFFFL
27237 //RLC_RLCV_TIMER_INT_0
27238 #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT                                                                    0x0
27239 #define RLC_RLCV_TIMER_INT_0__TIMER_MASK                                                                      0xFFFFFFFFL
27240 //RLC_RLCV_TIMER_CTRL
27241 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT                                                                0x0
27242 #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT                                                                  0x1
27243 #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK                                                                  0x00000001L
27244 #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK                                                                    0xFFFFFFFEL
27245 //RLC_RLCV_TIMER_STAT
27246 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT                                                              0x0
27247 #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT                                                                  0x1
27248 #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK                                                                0x00000001L
27249 #define RLC_RLCV_TIMER_STAT__RESERVED_MASK                                                                    0xFFFFFFFEL
27250 //RLC_GPU_IOV_VF_DOORBELL_STATUS
27251 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT                                             0x0
27252 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT                                                       0x10
27253 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT                                             0x1f
27254 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK                                               0x0000FFFFL
27255 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK                                                         0x7FFF0000L
27256 #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK                                               0x80000000L
27257 //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET
27258 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT                                     0x0
27259 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT                                                   0x10
27260 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT                                     0x1f
27261 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK                                       0x0000FFFFL
27262 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK                                                     0x7FFF0000L
27263 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK                                       0x80000000L
27264 //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR
27265 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT                                     0x0
27266 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT                                                   0x10
27267 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT                                     0x1f
27268 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK                                       0x0000FFFFL
27269 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK                                                     0x7FFF0000L
27270 #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK                                       0x80000000L
27271 //RLC_GPU_IOV_VF_MASK
27272 #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT                                                                   0x0
27273 #define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT                                                                  0x10
27274 #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK                                                                     0x0000FFFFL
27275 #define RLC_GPU_IOV_VF_MASK__RESERVED_MASK                                                                    0xFFFF0000L
27276 //RLC_HYP_SEMAPHORE_2
27277 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT                                                                 0x0
27278 #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT                                                                  0x5
27279 #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK                                                                   0x0000001FL
27280 #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK                                                                    0xFFFFFFE0L
27281 //RLC_HYP_SEMAPHORE_3
27282 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT                                                                 0x0
27283 #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT                                                                  0x5
27284 #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK                                                                   0x0000001FL
27285 #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK                                                                    0xFFFFFFE0L
27286 //RLC_CLK_CNTL
27287 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT                                                                 0x0
27288 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT                                                                 0x1
27289 #define RLC_CLK_CNTL__RESERVED__SHIFT                                                                         0x2
27290 #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK                                                                   0x00000001L
27291 #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK                                                                   0x00000002L
27292 #define RLC_CLK_CNTL__RESERVED_MASK                                                                           0xFFFFFFFCL
27293 //RLC_GPU_IOV_SCH_BLOCK
27294 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT                                                            0x0
27295 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT                                                           0x4
27296 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT                                                          0x8
27297 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT                                                                0x10
27298 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK                                                              0x0000000FL
27299 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK                                                             0x000000F0L
27300 #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK                                                            0x00007F00L
27301 #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK                                                                  0x7FFF0000L
27302 //RLC_GPU_IOV_CFG_REG1
27303 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT                                                                 0x0
27304 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT                                                              0x4
27305 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT                                                      0x5
27306 #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT                                                                 0x6
27307 #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT                                                                   0x8
27308 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT                                                              0x10
27309 #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT                                                                0x18
27310 #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK                                                                   0x0000000FL
27311 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK                                                                0x00000010L
27312 #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK                                                        0x00000020L
27313 #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK                                                                   0x000000C0L
27314 #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK                                                                     0x0000FF00L
27315 #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK                                                                0x00FF0000L
27316 #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK                                                                  0xFF000000L
27317 //RLC_GPU_IOV_CFG_REG2
27318 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT                                                               0x0
27319 #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT                                                                 0x4
27320 #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK                                                                 0x0000000FL
27321 #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK                                                                   0xFFFFFFF0L
27322 //RLC_GPU_IOV_VM_BUSY_STATUS
27323 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                     0x0
27324 #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                       0xFFFFFFFFL
27325 //RLC_GPU_IOV_SCH_0
27326 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT                                                            0x0
27327 #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK                                                              0xFFFFFFFFL
27328 //RLC_GPU_IOV_ACTIVE_FCN_ID
27329 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT                                                               0x0
27330 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT                                                            0x4
27331 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT                                                               0x1f
27332 #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK                                                                 0x0000000FL
27333 #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK                                                              0x7FFFFFF0L
27334 #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK                                                                 0x80000000L
27335 //RLC_GPU_IOV_SCH_3
27336 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT                                                             0x0
27337 #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK                                                               0xFFFFFFFFL
27338 //RLC_GPU_IOV_SCH_1
27339 #define RLC_GPU_IOV_SCH_1__DATA__SHIFT                                                                        0x0
27340 #define RLC_GPU_IOV_SCH_1__DATA_MASK                                                                          0xFFFFFFFFL
27341 //RLC_GPU_IOV_SCH_2
27342 #define RLC_GPU_IOV_SCH_2__DATA__SHIFT                                                                        0x0
27343 #define RLC_GPU_IOV_SCH_2__DATA_MASK                                                                          0xFFFFFFFFL
27344 //RLC_GPU_IOV_UCODE_ADDR
27345 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT                                                             0x0
27346 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT                                                               0xc
27347 #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK                                                               0x00000FFFL
27348 #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK                                                                 0xFFFFF000L
27349 //RLC_GPU_IOV_UCODE_DATA
27350 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT                                                             0x0
27351 #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK                                                               0xFFFFFFFFL
27352 //RLC_GPU_IOV_SCRATCH_ADDR
27353 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT                                                                 0x0
27354 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT                                                             0x9
27355 #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK                                                                   0x000001FFL
27356 #define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK                                                               0xFFFFFE00L
27357 //RLC_GPU_IOV_SCRATCH_DATA
27358 #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT                                                                 0x0
27359 #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK                                                                   0xFFFFFFFFL
27360 //RLC_GPU_IOV_F32_CNTL
27361 #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT                                                                   0x0
27362 #define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT                                                                 0x1
27363 #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK                                                                     0x00000001L
27364 #define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK                                                                   0xFFFFFFFEL
27365 //RLC_GPU_IOV_F32_RESET
27366 #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT                                                                   0x0
27367 #define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT                                                                0x1
27368 #define RLC_GPU_IOV_F32_RESET__RESET_MASK                                                                     0x00000001L
27369 #define RLC_GPU_IOV_F32_RESET__RESERVED_MASK                                                                  0xFFFFFFFEL
27370 //RLC_GPU_IOV_SDMA0_STATUS
27371 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT                                                            0x0
27372 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT                                                             0x1
27373 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT                                                                0x8
27374 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT                                                            0x9
27375 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
27376 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT                                                            0xd
27377 #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK                                                              0x00000001L
27378 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK                                                               0x000000FEL
27379 #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK                                                                  0x00000100L
27380 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK                                                              0x00000E00L
27381 #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK                                                               0x00001000L
27382 #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
27383 //RLC_GPU_IOV_SDMA1_STATUS
27384 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT                                                            0x0
27385 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT                                                             0x1
27386 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT                                                                0x8
27387 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT                                                            0x9
27388 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT                                                             0xc
27389 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT                                                            0xd
27390 #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK                                                              0x00000001L
27391 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK                                                               0x000000FEL
27392 #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK                                                                  0x00000100L
27393 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK                                                              0x00000E00L
27394 #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK                                                               0x00001000L
27395 #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK                                                              0xFFFFE000L
27396 //RLC_GPU_IOV_SMU_RESPONSE
27397 #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT                                                                 0x0
27398 #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
27399 //RLC_GPU_IOV_VIRT_RESET_REQ
27400 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT                                                             0x0
27401 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT                                                           0x10
27402 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT                                                        0x1f
27403 #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK                                                               0x0000FFFFL
27404 #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK                                                             0x7FFF0000L
27405 #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK                                                          0x80000000L
27406 //RLC_GPU_IOV_RLC_RESPONSE
27407 #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT                                                                 0x0
27408 #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK                                                                   0xFFFFFFFFL
27409 //RLC_GPU_IOV_INT_DISABLE
27410 #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT                                                               0x0
27411 #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK                                                                 0xFFFFFFFFL
27412 //RLC_GPU_IOV_INT_FORCE
27413 #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT                                                                   0x0
27414 #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK                                                                     0xFFFFFFFFL
27415 //RLC_GPU_IOV_SDMA0_BUSY_STATUS
27416 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
27417 #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
27418 //RLC_GPU_IOV_SDMA1_BUSY_STATUS
27419 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT                                                  0x0
27420 #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK                                                    0xFFFFFFFFL
27421 
27422 
27423 // addressBlock: gccacind
27424 //GC_CAC_CNTL
27425 #define GC_CAC_CNTL__CAC_ENABLE__SHIFT                                                                        0x0
27426 #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
27427 #define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT                                                                      0x11
27428 #define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT                                                                     0x17
27429 #define GC_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x1f
27430 #define GC_CAC_CNTL__CAC_ENABLE_MASK                                                                          0x00000001L
27431 #define GC_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
27432 #define GC_CAC_CNTL__CAC_BLOCK_ID_MASK                                                                        0x007E0000L
27433 #define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK                                                                       0x7F800000L
27434 #define GC_CAC_CNTL__UNUSED_0_MASK                                                                            0x80000000L
27435 //GC_CAC_OVR_SEL
27436 #define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
27437 #define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
27438 //GC_CAC_OVR_VAL
27439 #define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
27440 #define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
27441 //GC_CAC_WEIGHT_BCI_0
27442 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT                                                           0x0
27443 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT                                                           0x10
27444 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK                                                             0x0000FFFFL
27445 #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK                                                             0xFFFF0000L
27446 //GC_CAC_WEIGHT_CB_0
27447 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT                                                             0x0
27448 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT                                                             0x10
27449 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK                                                               0x0000FFFFL
27450 #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK                                                               0xFFFF0000L
27451 //GC_CAC_WEIGHT_CB_1
27452 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT                                                             0x0
27453 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT                                                             0x10
27454 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK                                                               0x0000FFFFL
27455 #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK                                                               0xFFFF0000L
27456 //GC_CAC_WEIGHT_CBR_0
27457 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT                                                           0x0
27458 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT                                                           0x10
27459 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK                                                             0x0000FFFFL
27460 #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK                                                             0xFFFF0000L
27461 //GC_CAC_WEIGHT_CBR_1
27462 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT                                                           0x0
27463 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT                                                           0x10
27464 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK                                                             0x0000FFFFL
27465 #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK                                                             0xFFFF0000L
27466 //GC_CAC_WEIGHT_CP_0
27467 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT                                                             0x0
27468 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT                                                             0x10
27469 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK                                                               0x0000FFFFL
27470 #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK                                                               0xFFFF0000L
27471 //GC_CAC_WEIGHT_CP_1
27472 #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT                                                             0x0
27473 #define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT                                                                   0x10
27474 #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK                                                               0x0000FFFFL
27475 #define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK                                                                     0xFFFF0000L
27476 //GC_CAC_WEIGHT_DB_0
27477 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT                                                             0x0
27478 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT                                                             0x10
27479 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK                                                               0x0000FFFFL
27480 #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK                                                               0xFFFF0000L
27481 //GC_CAC_WEIGHT_DB_1
27482 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT                                                             0x0
27483 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT                                                             0x10
27484 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK                                                               0x0000FFFFL
27485 #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK                                                               0xFFFF0000L
27486 //GC_CAC_WEIGHT_DBR_0
27487 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT                                                           0x0
27488 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT                                                           0x10
27489 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK                                                             0x0000FFFFL
27490 #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK                                                             0xFFFF0000L
27491 //GC_CAC_WEIGHT_DBR_1
27492 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT                                                           0x0
27493 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT                                                           0x10
27494 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK                                                             0x0000FFFFL
27495 #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK                                                             0xFFFF0000L
27496 //GC_CAC_WEIGHT_GDS_0
27497 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT                                                           0x0
27498 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT                                                           0x10
27499 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK                                                             0x0000FFFFL
27500 #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK                                                             0xFFFF0000L
27501 //GC_CAC_WEIGHT_GDS_1
27502 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT                                                           0x0
27503 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT                                                           0x10
27504 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK                                                             0x0000FFFFL
27505 #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK                                                             0xFFFF0000L
27506 //GC_CAC_WEIGHT_IA_0
27507 #define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT                                                             0x0
27508 #define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT                                                                   0x10
27509 #define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK                                                               0x0000FFFFL
27510 #define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27511 //GC_CAC_WEIGHT_LDS_0
27512 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT                                                           0x0
27513 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT                                                           0x10
27514 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK                                                             0x0000FFFFL
27515 #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK                                                             0xFFFF0000L
27516 //GC_CAC_WEIGHT_LDS_1
27517 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT                                                           0x0
27518 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT                                                           0x10
27519 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK                                                             0x0000FFFFL
27520 #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK                                                             0xFFFF0000L
27521 //GC_CAC_WEIGHT_PA_0
27522 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT                                                             0x0
27523 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT                                                             0x10
27524 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK                                                               0x0000FFFFL
27525 #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK                                                               0xFFFF0000L
27526 //GC_CAC_WEIGHT_PC_0
27527 #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT                                                             0x0
27528 #define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT                                                                   0x10
27529 #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK                                                               0x0000FFFFL
27530 #define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27531 //GC_CAC_WEIGHT_SC_0
27532 #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT                                                             0x0
27533 #define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT                                                                   0x10
27534 #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK                                                               0x0000FFFFL
27535 #define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27536 //GC_CAC_WEIGHT_SPI_0
27537 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT                                                           0x0
27538 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT                                                           0x10
27539 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK                                                             0x0000FFFFL
27540 #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK                                                             0xFFFF0000L
27541 //GC_CAC_WEIGHT_SPI_1
27542 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT                                                           0x0
27543 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT                                                           0x10
27544 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK                                                             0x0000FFFFL
27545 #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK                                                             0xFFFF0000L
27546 //GC_CAC_WEIGHT_SPI_2
27547 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT                                                           0x0
27548 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT                                                           0x10
27549 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK                                                             0x0000FFFFL
27550 #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK                                                             0xFFFF0000L
27551 //GC_CAC_WEIGHT_SQ_0
27552 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT                                                             0x0
27553 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT                                                             0x10
27554 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK                                                               0x0000FFFFL
27555 #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK                                                               0xFFFF0000L
27556 //GC_CAC_WEIGHT_SQ_1
27557 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT                                                             0x0
27558 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT                                                             0x10
27559 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK                                                               0x0000FFFFL
27560 #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK                                                               0xFFFF0000L
27561 //GC_CAC_WEIGHT_SQ_2
27562 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT                                                             0x0
27563 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT                                                             0x10
27564 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK                                                               0x0000FFFFL
27565 #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK                                                               0xFFFF0000L
27566 //GC_CAC_WEIGHT_SQ_3
27567 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT                                                             0x0
27568 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT                                                             0x10
27569 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK                                                               0x0000FFFFL
27570 #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK                                                               0xFFFF0000L
27571 //GC_CAC_WEIGHT_SQ_4
27572 #define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT                                                             0x0
27573 #define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT                                                                   0x10
27574 #define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK                                                               0x0000FFFFL
27575 #define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK                                                                     0xFFFF0000L
27576 //GC_CAC_WEIGHT_SX_0
27577 #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT                                                             0x0
27578 #define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT                                                                   0x10
27579 #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK                                                               0x0000FFFFL
27580 #define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27581 //GC_CAC_WEIGHT_SXRB_0
27582 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT                                                         0x0
27583 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT                                                         0x10
27584 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK                                                           0x0000FFFFL
27585 #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK                                                           0xFFFF0000L
27586 //GC_CAC_WEIGHT_TA_0
27587 #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT                                                             0x0
27588 #define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT                                                                   0x10
27589 #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK                                                               0x0000FFFFL
27590 #define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27591 //GC_CAC_WEIGHT_TCC_0
27592 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT                                                           0x0
27593 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT                                                           0x10
27594 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK                                                             0x0000FFFFL
27595 #define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK                                                             0xFFFF0000L
27596 //GC_CAC_WEIGHT_TCC_1
27597 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT                                                           0x0
27598 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT                                                           0x10
27599 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK                                                             0x0000FFFFL
27600 #define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK                                                             0xFFFF0000L
27601 //GC_CAC_WEIGHT_TCC_2
27602 #define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT                                                           0x0
27603 #define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT                                                                  0x10
27604 #define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK                                                             0x0000FFFFL
27605 #define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK                                                                    0xFFFF0000L
27606 //GC_CAC_WEIGHT_TCP_0
27607 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT                                                           0x0
27608 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT                                                           0x10
27609 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK                                                             0x0000FFFFL
27610 #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK                                                             0xFFFF0000L
27611 //GC_CAC_WEIGHT_TCP_1
27612 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT                                                           0x0
27613 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT                                                           0x10
27614 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK                                                             0x0000FFFFL
27615 #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK                                                             0xFFFF0000L
27616 //GC_CAC_WEIGHT_TCP_2
27617 #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT                                                           0x0
27618 #define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT                                                                  0x10
27619 #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK                                                             0x0000FFFFL
27620 #define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK                                                                    0xFFFF0000L
27621 //GC_CAC_WEIGHT_TD_0
27622 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT                                                             0x0
27623 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT                                                             0x10
27624 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK                                                               0x0000FFFFL
27625 #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK                                                               0xFFFF0000L
27626 //GC_CAC_WEIGHT_TD_1
27627 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT                                                             0x0
27628 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT                                                             0x10
27629 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK                                                               0x0000FFFFL
27630 #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK                                                               0xFFFF0000L
27631 //GC_CAC_WEIGHT_TD_2
27632 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT                                                             0x0
27633 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT                                                             0x10
27634 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK                                                               0x0000FFFFL
27635 #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK                                                               0xFFFF0000L
27636 //GC_CAC_WEIGHT_VGT_0
27637 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT                                                           0x0
27638 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT                                                           0x10
27639 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK                                                             0x0000FFFFL
27640 #define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK                                                             0xFFFF0000L
27641 //GC_CAC_WEIGHT_VGT_1
27642 #define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT                                                           0x0
27643 #define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT                                                                  0x10
27644 #define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK                                                             0x0000FFFFL
27645 #define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK                                                                    0xFFFF0000L
27646 //GC_CAC_WEIGHT_WD_0
27647 #define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT                                                             0x0
27648 #define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT                                                                   0x10
27649 #define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK                                                               0x0000FFFFL
27650 #define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK                                                                     0xFFFF0000L
27651 //GC_CAC_WEIGHT_CU_0
27652 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT                                                             0x0
27653 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT                                                             0x10
27654 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK                                                               0x0000FFFFL
27655 #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK                                                               0xFFFF0000L
27656 //GC_CAC_WEIGHT_CU_1
27657 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT                                                             0x0
27658 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT                                                             0x10
27659 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK                                                               0x0000FFFFL
27660 #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK                                                               0xFFFF0000L
27661 //GC_CAC_WEIGHT_CU_2
27662 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT                                                             0x0
27663 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT                                                             0x10
27664 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK                                                               0x0000FFFFL
27665 #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK                                                               0xFFFF0000L
27666 //GC_CAC_WEIGHT_CU_3
27667 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT                                                             0x0
27668 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT                                                             0x10
27669 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK                                                               0x0000FFFFL
27670 #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK                                                               0xFFFF0000L
27671 //GC_CAC_WEIGHT_CU_4
27672 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT                                                             0x0
27673 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT                                                             0x10
27674 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK                                                               0x0000FFFFL
27675 #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK                                                               0xFFFF0000L
27676 //GC_CAC_WEIGHT_CU_5
27677 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT                                                            0x0
27678 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT                                                            0x10
27679 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK                                                              0x0000FFFFL
27680 #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK                                                              0xFFFF0000L
27681 //GC_CAC_WEIGHT_CU_6
27682 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT                                                            0x0
27683 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT                                                            0x10
27684 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK                                                              0x0000FFFFL
27685 #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK                                                              0xFFFF0000L
27686 //GC_CAC_WEIGHT_CU_7
27687 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT                                                            0x0
27688 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT                                                            0x10
27689 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK                                                              0x0000FFFFL
27690 #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK                                                              0xFFFF0000L
27691 //GC_CAC_ACC_BCI0
27692 #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27693 #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27694 //GC_CAC_ACC_CB0
27695 #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27696 #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27697 //GC_CAC_ACC_CB1
27698 #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27699 #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27700 //GC_CAC_ACC_CB2
27701 #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27702 #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27703 //GC_CAC_ACC_CB3
27704 #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27705 #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27706 //GC_CAC_ACC_CBR0
27707 #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27708 #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27709 //GC_CAC_ACC_CBR1
27710 #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27711 #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27712 //GC_CAC_ACC_CBR2
27713 #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27714 #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27715 //GC_CAC_ACC_CBR3
27716 #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27717 #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27718 //GC_CAC_ACC_CP0
27719 #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27720 #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27721 //GC_CAC_ACC_CP1
27722 #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27723 #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27724 //GC_CAC_ACC_CP2
27725 #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27726 #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27727 //GC_CAC_ACC_DB0
27728 #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27729 #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27730 //GC_CAC_ACC_DB1
27731 #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27732 #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27733 //GC_CAC_ACC_DB2
27734 #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27735 #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27736 //GC_CAC_ACC_DB3
27737 #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27738 #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27739 //GC_CAC_ACC_DBR0
27740 #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27741 #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27742 //GC_CAC_ACC_DBR1
27743 #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27744 #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27745 //GC_CAC_ACC_DBR2
27746 #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27747 #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27748 //GC_CAC_ACC_DBR3
27749 #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27750 #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27751 //GC_CAC_ACC_GDS0
27752 #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27753 #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27754 //GC_CAC_ACC_GDS1
27755 #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27756 #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27757 //GC_CAC_ACC_GDS2
27758 #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27759 #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27760 //GC_CAC_ACC_GDS3
27761 #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27762 #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27763 //GC_CAC_ACC_IA0
27764 #define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27765 #define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27766 //GC_CAC_ACC_LDS0
27767 #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27768 #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27769 //GC_CAC_ACC_LDS1
27770 #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27771 #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27772 //GC_CAC_ACC_LDS2
27773 #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27774 #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27775 //GC_CAC_ACC_LDS3
27776 #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27777 #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27778 //GC_CAC_ACC_PA0
27779 #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27780 #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27781 //GC_CAC_ACC_PA1
27782 #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27783 #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27784 //GC_CAC_ACC_PC0
27785 #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27786 #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27787 //GC_CAC_ACC_SC0
27788 #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27789 #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27790 //GC_CAC_ACC_SPI0
27791 #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27792 #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27793 //GC_CAC_ACC_SPI1
27794 #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27795 #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27796 //GC_CAC_ACC_SPI2
27797 #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27798 #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27799 //GC_CAC_ACC_SPI3
27800 #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27801 #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27802 //GC_CAC_ACC_SPI4
27803 #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT                                                              0x0
27804 #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27805 //GC_CAC_ACC_SPI5
27806 #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT                                                              0x0
27807 #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27808 //GC_CAC_WEIGHT_UTCL2_ATCL2_0
27809 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT                                           0x0
27810 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT                                           0x10
27811 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK                                             0x0000FFFFL
27812 #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK                                             0xFFFF0000L
27813 //GC_CAC_ACC_EA0
27814 #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27815 #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27816 //GC_CAC_ACC_EA1
27817 #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT                                                               0x0
27818 #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27819 //GC_CAC_ACC_EA2
27820 #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT                                                               0x0
27821 #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27822 //GC_CAC_ACC_EA3
27823 #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT                                                               0x0
27824 #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27825 //GC_CAC_ACC_UTCL2_ATCL20
27826 #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT                                                      0x0
27827 #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27828 //GC_CAC_OVRD_EA
27829 #define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT                                                                   0x0
27830 #define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT                                                                    0x6
27831 #define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK                                                                     0x0000003FL
27832 #define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK                                                                      0x00000FC0L
27833 //GC_CAC_OVRD_UTCL2_ATCL2
27834 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT                                                          0x0
27835 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT                                                           0x5
27836 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK                                                            0x0000001FL
27837 #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK                                                             0x000003E0L
27838 //GC_CAC_WEIGHT_EA_0
27839 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT                                                             0x0
27840 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT                                                             0x10
27841 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK                                                               0x0000FFFFL
27842 #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK                                                               0xFFFF0000L
27843 //GC_CAC_WEIGHT_EA_1
27844 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT                                                             0x0
27845 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT                                                             0x10
27846 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK                                                               0x0000FFFFL
27847 #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK                                                               0xFFFF0000L
27848 //GC_CAC_WEIGHT_RMI_0
27849 #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT                                                           0x0
27850 #define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT                                                                    0x10
27851 #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK                                                             0x0000FFFFL
27852 #define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK                                                                      0xFFFF0000L
27853 //GC_CAC_ACC_RMI0
27854 #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27855 #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27856 //GC_CAC_OVRD_RMI
27857 #define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT                                                                  0x0
27858 #define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT                                                                   0x1
27859 #define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK                                                                    0x00000001L
27860 #define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK                                                                     0x00000002L
27861 //GC_CAC_WEIGHT_UTCL2_ATCL2_1
27862 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT                                           0x0
27863 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT                                           0x10
27864 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK                                             0x0000FFFFL
27865 #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK                                             0xFFFF0000L
27866 //GC_CAC_ACC_UTCL2_ATCL21
27867 #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT                                                      0x0
27868 #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27869 //GC_CAC_ACC_UTCL2_ATCL22
27870 #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT                                                      0x0
27871 #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27872 //GC_CAC_ACC_UTCL2_ATCL23
27873 #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT                                                      0x0
27874 #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
27875 //GC_CAC_ACC_EA4
27876 #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT                                                               0x0
27877 #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27878 //GC_CAC_ACC_EA5
27879 #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT                                                               0x0
27880 #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27881 //GC_CAC_WEIGHT_EA_2
27882 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT                                                             0x0
27883 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT                                                             0x10
27884 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK                                                               0x0000FFFFL
27885 #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK                                                               0xFFFF0000L
27886 //GC_CAC_ACC_SQ0_LOWER
27887 #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27888 #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27889 //GC_CAC_ACC_SQ0_UPPER
27890 #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27891 #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT                                                                 0x8
27892 #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27893 #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27894 //GC_CAC_ACC_SQ1_LOWER
27895 #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27896 #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27897 //GC_CAC_ACC_SQ1_UPPER
27898 #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27899 #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT                                                                 0x8
27900 #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27901 #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27902 //GC_CAC_ACC_SQ2_LOWER
27903 #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27904 #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27905 //GC_CAC_ACC_SQ2_UPPER
27906 #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27907 #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT                                                                 0x8
27908 #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27909 #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27910 //GC_CAC_ACC_SQ3_LOWER
27911 #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27912 #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27913 //GC_CAC_ACC_SQ3_UPPER
27914 #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27915 #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT                                                                 0x8
27916 #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27917 #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27918 //GC_CAC_ACC_SQ4_LOWER
27919 #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27920 #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27921 //GC_CAC_ACC_SQ4_UPPER
27922 #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27923 #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT                                                                 0x8
27924 #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27925 #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27926 //GC_CAC_ACC_SQ5_LOWER
27927 #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27928 #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27929 //GC_CAC_ACC_SQ5_UPPER
27930 #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27931 #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT                                                                 0x8
27932 #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27933 #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27934 //GC_CAC_ACC_SQ6_LOWER
27935 #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27936 #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27937 //GC_CAC_ACC_SQ6_UPPER
27938 #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27939 #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT                                                                 0x8
27940 #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27941 #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27942 //GC_CAC_ACC_SQ7_LOWER
27943 #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27944 #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27945 //GC_CAC_ACC_SQ7_UPPER
27946 #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27947 #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT                                                                 0x8
27948 #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27949 #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27950 //GC_CAC_ACC_SQ8_LOWER
27951 #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT                                                         0x0
27952 #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK                                                           0xFFFFFFFFL
27953 //GC_CAC_ACC_SQ8_UPPER
27954 #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT                                                        0x0
27955 #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT                                                                 0x8
27956 #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK                                                          0x000000FFL
27957 #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK                                                                   0xFFFFFF00L
27958 //GC_CAC_ACC_SX0
27959 #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27960 #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27961 //GC_CAC_ACC_SXRB0
27962 #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT                                                             0x0
27963 #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
27964 //GC_CAC_ACC_SXRB1
27965 #define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT                                                             0x0
27966 #define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK                                                               0xFFFFFFFFL
27967 //GC_CAC_ACC_TA0
27968 #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT                                                               0x0
27969 #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
27970 //GC_CAC_ACC_TCC0
27971 #define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27972 #define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27973 //GC_CAC_ACC_TCC1
27974 #define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27975 #define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27976 //GC_CAC_ACC_TCC2
27977 #define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27978 #define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27979 //GC_CAC_ACC_TCC3
27980 #define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27981 #define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27982 //GC_CAC_ACC_TCC4
27983 #define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT                                                              0x0
27984 #define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27985 //GC_CAC_ACC_TCP0
27986 #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT                                                              0x0
27987 #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27988 //GC_CAC_ACC_TCP1
27989 #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT                                                              0x0
27990 #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27991 //GC_CAC_ACC_TCP2
27992 #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT                                                              0x0
27993 #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27994 //GC_CAC_ACC_TCP3
27995 #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT                                                              0x0
27996 #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
27997 //GC_CAC_ACC_TCP4
27998 #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT                                                              0x0
27999 #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28000 //GC_CAC_ACC_TD0
28001 #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT                                                               0x0
28002 #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28003 //GC_CAC_ACC_TD1
28004 #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT                                                               0x0
28005 #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28006 //GC_CAC_ACC_TD2
28007 #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT                                                               0x0
28008 #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28009 //GC_CAC_ACC_TD3
28010 #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT                                                               0x0
28011 #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28012 //GC_CAC_ACC_TD4
28013 #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT                                                               0x0
28014 #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28015 //GC_CAC_ACC_TD5
28016 #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT                                                               0x0
28017 #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28018 //GC_CAC_ACC_VGT0
28019 #define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT                                                              0x0
28020 #define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28021 //GC_CAC_ACC_VGT1
28022 #define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT                                                              0x0
28023 #define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28024 //GC_CAC_ACC_VGT2
28025 #define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT                                                              0x0
28026 #define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28027 //GC_CAC_ACC_WD0
28028 #define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT                                                               0x0
28029 #define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28030 //GC_CAC_ACC_CU0
28031 #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT                                                               0x0
28032 #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28033 //GC_CAC_ACC_CU1
28034 #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT                                                               0x0
28035 #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28036 //GC_CAC_ACC_CU2
28037 #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT                                                               0x0
28038 #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28039 //GC_CAC_ACC_CU3
28040 #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT                                                               0x0
28041 #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28042 //GC_CAC_ACC_CU4
28043 #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT                                                               0x0
28044 #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28045 //GC_CAC_ACC_CU5
28046 #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT                                                               0x0
28047 #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28048 //GC_CAC_ACC_CU6
28049 #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT                                                               0x0
28050 #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28051 //GC_CAC_ACC_CU7
28052 #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT                                                               0x0
28053 #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28054 //GC_CAC_ACC_CU8
28055 #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT                                                               0x0
28056 #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28057 //GC_CAC_ACC_CU9
28058 #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT                                                               0x0
28059 #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK                                                                 0xFFFFFFFFL
28060 //GC_CAC_ACC_CU10
28061 #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT                                                              0x0
28062 #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28063 //GC_CAC_ACC_CU11
28064 #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT                                                              0x0
28065 #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28066 //GC_CAC_ACC_CU12
28067 #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT                                                              0x0
28068 #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28069 //GC_CAC_ACC_CU13
28070 #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT                                                              0x0
28071 #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28072 //GC_CAC_ACC_CU14
28073 #define GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT                                                              0x0
28074 #define GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28075 //GC_CAC_ACC_CU15
28076 #define GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT                                                              0x0
28077 #define GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28078 //GC_CAC_OVRD_BCI
28079 #define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT                                                                  0x0
28080 #define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT                                                                   0x2
28081 #define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK                                                                    0x00000003L
28082 #define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK                                                                     0x0000000CL
28083 //GC_CAC_OVRD_CB
28084 #define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT                                                                   0x0
28085 #define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT                                                                    0x4
28086 #define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK                                                                     0x0000000FL
28087 #define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK                                                                      0x000000F0L
28088 //GC_CAC_OVRD_CBR
28089 #define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT                                                                  0x0
28090 #define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT                                                                   0x4
28091 #define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK                                                                    0x0000000FL
28092 #define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK                                                                     0x000000F0L
28093 //GC_CAC_OVRD_CP
28094 #define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT                                                                   0x0
28095 #define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT                                                                    0x3
28096 #define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK                                                                     0x00000007L
28097 #define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK                                                                      0x00000038L
28098 //GC_CAC_OVRD_DB
28099 #define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT                                                                   0x0
28100 #define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT                                                                    0x4
28101 #define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK                                                                     0x0000000FL
28102 #define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK                                                                      0x000000F0L
28103 //GC_CAC_OVRD_DBR
28104 #define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT                                                                  0x0
28105 #define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT                                                                   0x4
28106 #define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK                                                                    0x0000000FL
28107 #define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK                                                                     0x000000F0L
28108 //GC_CAC_OVRD_GDS
28109 #define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT                                                                  0x0
28110 #define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT                                                                   0x4
28111 #define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK                                                                    0x0000000FL
28112 #define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK                                                                     0x000000F0L
28113 //GC_CAC_OVRD_IA
28114 #define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT                                                                   0x0
28115 #define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT                                                                    0x1
28116 #define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK                                                                     0x00000001L
28117 #define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK                                                                      0x00000002L
28118 //GC_CAC_OVRD_LDS
28119 #define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT                                                                  0x0
28120 #define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT                                                                   0x4
28121 #define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK                                                                    0x0000000FL
28122 #define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK                                                                     0x000000F0L
28123 //GC_CAC_OVRD_PA
28124 #define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT                                                                   0x0
28125 #define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT                                                                    0x2
28126 #define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK                                                                     0x00000003L
28127 #define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK                                                                      0x0000000CL
28128 //GC_CAC_OVRD_PC
28129 #define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT                                                                   0x0
28130 #define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT                                                                    0x1
28131 #define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK                                                                     0x00000001L
28132 #define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK                                                                      0x00000002L
28133 //GC_CAC_OVRD_SC
28134 #define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT                                                                   0x0
28135 #define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT                                                                    0x1
28136 #define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK                                                                     0x00000001L
28137 #define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK                                                                      0x00000002L
28138 //GC_CAC_OVRD_SPI
28139 #define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT                                                                  0x0
28140 #define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT                                                                   0x6
28141 #define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK                                                                    0x0000003FL
28142 #define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK                                                                     0x00000FC0L
28143 //GC_CAC_OVRD_CU
28144 #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT                                                                   0x0
28145 #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT                                                                    0x1
28146 #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK                                                                     0x00000001L
28147 #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK                                                                      0x00000002L
28148 //GC_CAC_OVRD_SQ
28149 #define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT                                                                   0x0
28150 #define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT                                                                    0x9
28151 #define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK                                                                     0x000001FFL
28152 #define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK                                                                      0x0003FE00L
28153 //GC_CAC_OVRD_SX
28154 #define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT                                                                   0x0
28155 #define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT                                                                    0x1
28156 #define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK                                                                     0x00000001L
28157 #define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK                                                                      0x00000002L
28158 //GC_CAC_OVRD_SXRB
28159 #define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT                                                                 0x0
28160 #define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT                                                                  0x1
28161 #define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK                                                                   0x00000001L
28162 #define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK                                                                    0x00000002L
28163 //GC_CAC_OVRD_TA
28164 #define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT                                                                   0x0
28165 #define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT                                                                    0x1
28166 #define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK                                                                     0x00000001L
28167 #define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK                                                                      0x00000002L
28168 //GC_CAC_OVRD_TCC
28169 #define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT                                                                  0x0
28170 #define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT                                                                   0x5
28171 #define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK                                                                    0x0000001FL
28172 #define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK                                                                     0x000003E0L
28173 //GC_CAC_OVRD_TCP
28174 #define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT                                                                  0x0
28175 #define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT                                                                   0x5
28176 #define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK                                                                    0x0000001FL
28177 #define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK                                                                     0x000003E0L
28178 //GC_CAC_OVRD_TD
28179 #define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT                                                                   0x0
28180 #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT                                                                    0x6
28181 #define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK                                                                     0x0000003FL
28182 #define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK                                                                      0x00000FC0L
28183 //GC_CAC_OVRD_VGT
28184 #define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT                                                                  0x0
28185 #define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT                                                                   0x3
28186 #define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK                                                                    0x00000007L
28187 #define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK                                                                     0x00000038L
28188 //GC_CAC_OVRD_WD
28189 #define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT                                                                   0x0
28190 #define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT                                                                    0x1
28191 #define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK                                                                     0x00000001L
28192 #define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK                                                                      0x00000002L
28193 //GC_CAC_ACC_BCI1
28194 #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT                                                              0x0
28195 #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK                                                                0xFFFFFFFFL
28196 //GC_CAC_WEIGHT_UTCL2_ATCL2_2
28197 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT                                           0x0
28198 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT                                           0x10
28199 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK                                             0x0000FFFFL
28200 #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK                                             0xFFFF0000L
28201 //GC_CAC_WEIGHT_UTCL2_ROUTER_0
28202 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT                                         0x0
28203 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT                                         0x10
28204 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK                                           0x0000FFFFL
28205 #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK                                           0xFFFF0000L
28206 //GC_CAC_WEIGHT_UTCL2_ROUTER_1
28207 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT                                         0x0
28208 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT                                         0x10
28209 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK                                           0x0000FFFFL
28210 #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK                                           0xFFFF0000L
28211 //GC_CAC_WEIGHT_UTCL2_ROUTER_2
28212 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT                                         0x0
28213 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT                                         0x10
28214 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK                                           0x0000FFFFL
28215 #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK                                           0xFFFF0000L
28216 //GC_CAC_WEIGHT_UTCL2_ROUTER_3
28217 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT                                         0x0
28218 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT                                         0x10
28219 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK                                           0x0000FFFFL
28220 #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK                                           0xFFFF0000L
28221 //GC_CAC_WEIGHT_UTCL2_ROUTER_4
28222 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT                                         0x0
28223 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT                                         0x10
28224 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK                                           0x0000FFFFL
28225 #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK                                           0xFFFF0000L
28226 //GC_CAC_WEIGHT_UTCL2_VML2_0
28227 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT                                             0x0
28228 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT                                             0x10
28229 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK                                               0x0000FFFFL
28230 #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK                                               0xFFFF0000L
28231 //GC_CAC_WEIGHT_UTCL2_VML2_1
28232 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT                                             0x0
28233 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT                                             0x10
28234 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK                                               0x0000FFFFL
28235 #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK                                               0xFFFF0000L
28236 //GC_CAC_WEIGHT_UTCL2_VML2_2
28237 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT                                             0x0
28238 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT                                             0x10
28239 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK                                               0x0000FFFFL
28240 #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK                                               0xFFFF0000L
28241 //GC_CAC_ACC_UTCL2_ATCL24
28242 #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT                                                      0x0
28243 #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK                                                        0xFFFFFFFFL
28244 //GC_CAC_ACC_UTCL2_ROUTER0
28245 #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
28246 #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28247 //GC_CAC_ACC_UTCL2_ROUTER1
28248 #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
28249 #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28250 //GC_CAC_ACC_UTCL2_ROUTER2
28251 #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
28252 #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28253 //GC_CAC_ACC_UTCL2_ROUTER3
28254 #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
28255 #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28256 //GC_CAC_ACC_UTCL2_ROUTER4
28257 #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
28258 #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28259 //GC_CAC_ACC_UTCL2_ROUTER5
28260 #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT                                                     0x0
28261 #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28262 //GC_CAC_ACC_UTCL2_ROUTER6
28263 #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT                                                     0x0
28264 #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28265 //GC_CAC_ACC_UTCL2_ROUTER7
28266 #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT                                                     0x0
28267 #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28268 //GC_CAC_ACC_UTCL2_ROUTER8
28269 #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT                                                     0x0
28270 #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28271 //GC_CAC_ACC_UTCL2_ROUTER9
28272 #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT                                                     0x0
28273 #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28274 //GC_CAC_ACC_UTCL2_VML20
28275 #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT                                                       0x0
28276 #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28277 //GC_CAC_ACC_UTCL2_VML21
28278 #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT                                                       0x0
28279 #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28280 //GC_CAC_ACC_UTCL2_VML22
28281 #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT                                                       0x0
28282 #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28283 //GC_CAC_ACC_UTCL2_VML23
28284 #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT                                                       0x0
28285 #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28286 //GC_CAC_ACC_UTCL2_VML24
28287 #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT                                                       0x0
28288 #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK                                                         0xFFFFFFFFL
28289 //GC_CAC_OVRD_UTCL2_ROUTER
28290 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT                                                         0x0
28291 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT                                                          0xa
28292 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK                                                           0x000003FFL
28293 #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK                                                            0x000FFC00L
28294 //GC_CAC_OVRD_UTCL2_VML2
28295 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT                                                           0x0
28296 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT                                                            0x5
28297 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK                                                             0x0000001FL
28298 #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK                                                              0x000003E0L
28299 //GC_CAC_WEIGHT_UTCL2_WALKER_0
28300 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT                                         0x0
28301 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT                                         0x10
28302 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK                                           0x0000FFFFL
28303 #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK                                           0xFFFF0000L
28304 //GC_CAC_WEIGHT_UTCL2_WALKER_1
28305 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT                                         0x0
28306 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT                                         0x10
28307 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK                                           0x0000FFFFL
28308 #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK                                           0xFFFF0000L
28309 //GC_CAC_WEIGHT_UTCL2_WALKER_2
28310 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT                                         0x0
28311 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT                                         0x10
28312 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK                                           0x0000FFFFL
28313 #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK                                           0xFFFF0000L
28314 //GC_CAC_ACC_UTCL2_WALKER0
28315 #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT                                                     0x0
28316 #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28317 //GC_CAC_ACC_UTCL2_WALKER1
28318 #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT                                                     0x0
28319 #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28320 //GC_CAC_ACC_UTCL2_WALKER2
28321 #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT                                                     0x0
28322 #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28323 //GC_CAC_ACC_UTCL2_WALKER3
28324 #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT                                                     0x0
28325 #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28326 //GC_CAC_ACC_UTCL2_WALKER4
28327 #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT                                                     0x0
28328 #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK                                                       0xFFFFFFFFL
28329 //GC_CAC_OVRD_UTCL2_WALKER
28330 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT                                                         0x0
28331 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT                                                          0x5
28332 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK                                                           0x0000001FL
28333 #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK                                                            0x000003E0L
28334 
28335 
28336 // addressBlock: secacind
28337 //SE_CAC_CNTL
28338 #define SE_CAC_CNTL__CAC_ENABLE__SHIFT                                                                        0x0
28339 #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT                                                                     0x1
28340 #define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT                                                                      0x11
28341 #define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT                                                                     0x17
28342 #define SE_CAC_CNTL__UNUSED_0__SHIFT                                                                          0x1f
28343 #define SE_CAC_CNTL__CAC_ENABLE_MASK                                                                          0x00000001L
28344 #define SE_CAC_CNTL__CAC_THRESHOLD_MASK                                                                       0x0001FFFEL
28345 #define SE_CAC_CNTL__CAC_BLOCK_ID_MASK                                                                        0x007E0000L
28346 #define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK                                                                       0x7F800000L
28347 #define SE_CAC_CNTL__UNUSED_0_MASK                                                                            0x80000000L
28348 //SE_CAC_OVR_SEL
28349 #define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT                                                                    0x0
28350 #define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK                                                                      0xFFFFFFFFL
28351 //SE_CAC_OVR_VAL
28352 #define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT                                                                    0x0
28353 #define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK                                                                      0xFFFFFFFFL
28354 
28355 
28356 // addressBlock: sqind
28357 //SQ_DEBUG_STS_GLOBAL
28358 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL
28359 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000
28360 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L
28361 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008
28362 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000L
28363 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x00000018
28364 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0x00ff0000L
28365 #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x00000010
28366 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0x0000000fL
28367 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x00000000
28368 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x000000f0L
28369 #define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x00000004
28370 #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L
28371 #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000
28372 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L
28373 #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001
28374 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0x0000fff0L
28375 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x00000004
28376 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0x0fff0000L
28377 #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x00000010
28378 
28379 //SQ_DEBUG_STS_LOCAL
28380 #define SQ_DEBUG_STS_LOCAL__BUSY_MASK                                                                         0x00000001L
28381 #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT                                                                       0x00000000
28382 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK                                                                   0x000003f0L
28383 #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT                                                                 0x00000004
28384 //SQ_WAVE_MODE
28385 #define SQ_WAVE_MODE__FP_ROUND__SHIFT                                                                         0x0
28386 #define SQ_WAVE_MODE__FP_DENORM__SHIFT                                                                        0x4
28387 #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT                                                                       0x8
28388 #define SQ_WAVE_MODE__IEEE__SHIFT                                                                             0x9
28389 #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT                                                                      0xa
28390 #define SQ_WAVE_MODE__DEBUG_EN__SHIFT                                                                         0xb
28391 #define SQ_WAVE_MODE__EXCP_EN__SHIFT                                                                          0xc
28392 #define SQ_WAVE_MODE__FP16_OVFL__SHIFT                                                                        0x17
28393 #define SQ_WAVE_MODE__POPS_PACKER0__SHIFT                                                                     0x18
28394 #define SQ_WAVE_MODE__POPS_PACKER1__SHIFT                                                                     0x19
28395 #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT                                                                     0x1a
28396 #define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT                                                                       0x1b
28397 #define SQ_WAVE_MODE__VSKIP__SHIFT                                                                            0x1c
28398 #define SQ_WAVE_MODE__CSP__SHIFT                                                                              0x1d
28399 #define SQ_WAVE_MODE__FP_ROUND_MASK                                                                           0x0000000FL
28400 #define SQ_WAVE_MODE__FP_DENORM_MASK                                                                          0x000000F0L
28401 #define SQ_WAVE_MODE__DX10_CLAMP_MASK                                                                         0x00000100L
28402 #define SQ_WAVE_MODE__IEEE_MASK                                                                               0x00000200L
28403 #define SQ_WAVE_MODE__LOD_CLAMPED_MASK                                                                        0x00000400L
28404 #define SQ_WAVE_MODE__DEBUG_EN_MASK                                                                           0x00000800L
28405 #define SQ_WAVE_MODE__EXCP_EN_MASK                                                                            0x001FF000L
28406 #define SQ_WAVE_MODE__FP16_OVFL_MASK                                                                          0x00800000L
28407 #define SQ_WAVE_MODE__POPS_PACKER0_MASK                                                                       0x01000000L
28408 #define SQ_WAVE_MODE__POPS_PACKER1_MASK                                                                       0x02000000L
28409 #define SQ_WAVE_MODE__DISABLE_PERF_MASK                                                                       0x04000000L
28410 #define SQ_WAVE_MODE__GPR_IDX_EN_MASK                                                                         0x08000000L
28411 #define SQ_WAVE_MODE__VSKIP_MASK                                                                              0x10000000L
28412 #define SQ_WAVE_MODE__CSP_MASK                                                                                0xE0000000L
28413 //SQ_WAVE_STATUS
28414 #define SQ_WAVE_STATUS__SCC__SHIFT                                                                            0x0
28415 #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT                                                                       0x1
28416 #define SQ_WAVE_STATUS__USER_PRIO__SHIFT                                                                      0x3
28417 #define SQ_WAVE_STATUS__PRIV__SHIFT                                                                           0x5
28418 #define SQ_WAVE_STATUS__TRAP_EN__SHIFT                                                                        0x6
28419 #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT                                                                      0x7
28420 #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT                                                                     0x8
28421 #define SQ_WAVE_STATUS__EXECZ__SHIFT                                                                          0x9
28422 #define SQ_WAVE_STATUS__VCCZ__SHIFT                                                                           0xa
28423 #define SQ_WAVE_STATUS__IN_TG__SHIFT                                                                          0xb
28424 #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT                                                                     0xc
28425 #define SQ_WAVE_STATUS__HALT__SHIFT                                                                           0xd
28426 #define SQ_WAVE_STATUS__TRAP__SHIFT                                                                           0xe
28427 #define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT                                                                   0xf
28428 #define SQ_WAVE_STATUS__VALID__SHIFT                                                                          0x10
28429 #define SQ_WAVE_STATUS__ECC_ERR__SHIFT                                                                        0x11
28430 #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT                                                                    0x12
28431 #define SQ_WAVE_STATUS__PERF_EN__SHIFT                                                                        0x13
28432 #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT                                                                  0x14
28433 #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT                                                                   0x15
28434 #define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT                                                                   0x16
28435 #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT                                                                     0x17
28436 #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT                                                                    0x1b
28437 #define SQ_WAVE_STATUS__SCC_MASK                                                                              0x00000001L
28438 #define SQ_WAVE_STATUS__SPI_PRIO_MASK                                                                         0x00000006L
28439 #define SQ_WAVE_STATUS__USER_PRIO_MASK                                                                        0x00000018L
28440 #define SQ_WAVE_STATUS__PRIV_MASK                                                                             0x00000020L
28441 #define SQ_WAVE_STATUS__TRAP_EN_MASK                                                                          0x00000040L
28442 #define SQ_WAVE_STATUS__TTRACE_EN_MASK                                                                        0x00000080L
28443 #define SQ_WAVE_STATUS__EXPORT_RDY_MASK                                                                       0x00000100L
28444 #define SQ_WAVE_STATUS__EXECZ_MASK                                                                            0x00000200L
28445 #define SQ_WAVE_STATUS__VCCZ_MASK                                                                             0x00000400L
28446 #define SQ_WAVE_STATUS__IN_TG_MASK                                                                            0x00000800L
28447 #define SQ_WAVE_STATUS__IN_BARRIER_MASK                                                                       0x00001000L
28448 #define SQ_WAVE_STATUS__HALT_MASK                                                                             0x00002000L
28449 #define SQ_WAVE_STATUS__TRAP_MASK                                                                             0x00004000L
28450 #define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK                                                                     0x00008000L
28451 #define SQ_WAVE_STATUS__VALID_MASK                                                                            0x00010000L
28452 #define SQ_WAVE_STATUS__ECC_ERR_MASK                                                                          0x00020000L
28453 #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK                                                                      0x00040000L
28454 #define SQ_WAVE_STATUS__PERF_EN_MASK                                                                          0x00080000L
28455 #define SQ_WAVE_STATUS__COND_DBG_USER_MASK                                                                    0x00100000L
28456 #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK                                                                     0x00200000L
28457 #define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK                                                                     0x00400000L
28458 #define SQ_WAVE_STATUS__FATAL_HALT_MASK                                                                       0x00800000L
28459 #define SQ_WAVE_STATUS__MUST_EXPORT_MASK                                                                      0x08000000L
28460 //SQ_WAVE_TRAPSTS
28461 #define SQ_WAVE_TRAPSTS__EXCP__SHIFT                                                                          0x0
28462 #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT                                                                       0xa
28463 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT                                                                  0xb
28464 #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT                                                                       0xc
28465 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT                                                                    0x10
28466 #define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT                                                                   0x1c
28467 #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT                                                                       0x1d
28468 #define SQ_WAVE_TRAPSTS__EXCP_MASK                                                                            0x000001FFL
28469 #define SQ_WAVE_TRAPSTS__SAVECTX_MASK                                                                         0x00000400L
28470 #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK                                                                    0x00000800L
28471 #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK                                                                         0x00007000L
28472 #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK                                                                      0x003F0000L
28473 #define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK                                                                     0x10000000L
28474 #define SQ_WAVE_TRAPSTS__DP_RATE_MASK                                                                         0xE0000000L
28475 //SQ_WAVE_HW_ID
28476 #define SQ_WAVE_HW_ID__WAVE_ID__SHIFT                                                                         0x0
28477 #define SQ_WAVE_HW_ID__SIMD_ID__SHIFT                                                                         0x4
28478 #define SQ_WAVE_HW_ID__PIPE_ID__SHIFT                                                                         0x6
28479 #define SQ_WAVE_HW_ID__CU_ID__SHIFT                                                                           0x8
28480 #define SQ_WAVE_HW_ID__SH_ID__SHIFT                                                                           0xc
28481 #define SQ_WAVE_HW_ID__SE_ID__SHIFT                                                                           0xd
28482 #define SQ_WAVE_HW_ID__TG_ID__SHIFT                                                                           0x10
28483 #define SQ_WAVE_HW_ID__VM_ID__SHIFT                                                                           0x14
28484 #define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT                                                                        0x18
28485 #define SQ_WAVE_HW_ID__STATE_ID__SHIFT                                                                        0x1b
28486 #define SQ_WAVE_HW_ID__ME_ID__SHIFT                                                                           0x1e
28487 #define SQ_WAVE_HW_ID__WAVE_ID_MASK                                                                           0x0000000FL
28488 #define SQ_WAVE_HW_ID__SIMD_ID_MASK                                                                           0x00000030L
28489 #define SQ_WAVE_HW_ID__PIPE_ID_MASK                                                                           0x000000C0L
28490 #define SQ_WAVE_HW_ID__CU_ID_MASK                                                                             0x00000F00L
28491 #define SQ_WAVE_HW_ID__SH_ID_MASK                                                                             0x00001000L
28492 #define SQ_WAVE_HW_ID__SE_ID_MASK                                                                             0x00006000L
28493 #define SQ_WAVE_HW_ID__TG_ID_MASK                                                                             0x000F0000L
28494 #define SQ_WAVE_HW_ID__VM_ID_MASK                                                                             0x00F00000L
28495 #define SQ_WAVE_HW_ID__QUEUE_ID_MASK                                                                          0x07000000L
28496 #define SQ_WAVE_HW_ID__STATE_ID_MASK                                                                          0x38000000L
28497 #define SQ_WAVE_HW_ID__ME_ID_MASK                                                                             0xC0000000L
28498 //SQ_WAVE_GPR_ALLOC
28499 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT                                                                   0x0
28500 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT                                                                   0x8
28501 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT                                                                   0x10
28502 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT                                                                   0x18
28503 #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK                                                                     0x0000003FL
28504 #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK                                                                     0x00003F00L
28505 #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK                                                                     0x003F0000L
28506 #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK                                                                     0x0F000000L
28507 //SQ_WAVE_LDS_ALLOC
28508 #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT                                                                    0x0
28509 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT                                                                    0xc
28510 #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK                                                                      0x000000FFL
28511 #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK                                                                      0x001FF000L
28512 //SQ_WAVE_IB_STS
28513 #define SQ_WAVE_IB_STS__VM_CNT__SHIFT                                                                         0x0
28514 #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT                                                                        0x4
28515 #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT                                                                       0x8
28516 #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT                                                                       0xc
28517 #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT                                                                   0xf
28518 #define SQ_WAVE_IB_STS__RCNT__SHIFT                                                                           0x10
28519 #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT                                                                      0x16
28520 #define SQ_WAVE_IB_STS__VM_CNT_MASK                                                                           0x0000000FL
28521 #define SQ_WAVE_IB_STS__EXP_CNT_MASK                                                                          0x00000070L
28522 #define SQ_WAVE_IB_STS__LGKM_CNT_MASK                                                                         0x00000F00L
28523 #define SQ_WAVE_IB_STS__VALU_CNT_MASK                                                                         0x00007000L
28524 #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK                                                                     0x00008000L
28525 #define SQ_WAVE_IB_STS__RCNT_MASK                                                                             0x001F0000L
28526 #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK                                                                        0x00C00000L
28527 //SQ_WAVE_PC_LO
28528 #define SQ_WAVE_PC_LO__PC_LO__SHIFT                                                                           0x0
28529 #define SQ_WAVE_PC_LO__PC_LO_MASK                                                                             0xFFFFFFFFL
28530 //SQ_WAVE_PC_HI
28531 #define SQ_WAVE_PC_HI__PC_HI__SHIFT                                                                           0x0
28532 #define SQ_WAVE_PC_HI__PC_HI_MASK                                                                             0x0000FFFFL
28533 //SQ_WAVE_INST_DW0
28534 #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT                                                                     0x0
28535 #define SQ_WAVE_INST_DW0__INST_DW0_MASK                                                                       0xFFFFFFFFL
28536 //SQ_WAVE_INST_DW1
28537 #define SQ_WAVE_INST_DW1__INST_DW1__SHIFT                                                                     0x0
28538 #define SQ_WAVE_INST_DW1__INST_DW1_MASK                                                                       0xFFFFFFFFL
28539 //SQ_WAVE_IB_DBG0
28540 #define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT                                                                       0x0
28541 #define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT                                                                    0x3
28542 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT                                                                  0x4
28543 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT                                                               0x5
28544 #define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT                                                                     0x8
28545 #define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT                                                                     0xa
28546 #define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT                                                                   0x10
28547 #define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT                                                                        0x18
28548 #define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT                                                                        0x1a
28549 #define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT                                                                       0x1b
28550 #define SQ_WAVE_IB_DBG0__KILL__SHIFT                                                                          0x1d
28551 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT                                                              0x1e
28552 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT                                                            0x1f
28553 #define SQ_WAVE_IB_DBG0__IBUF_ST_MASK                                                                         0x00000007L
28554 #define SQ_WAVE_IB_DBG0__PC_INVALID_MASK                                                                      0x00000008L
28555 #define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK                                                                    0x00000010L
28556 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK                                                                 0x000000E0L
28557 #define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK                                                                       0x00000300L
28558 #define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK                                                                       0x00000C00L
28559 #define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK                                                                     0x000F0000L
28560 #define SQ_WAVE_IB_DBG0__ECC_ST_MASK                                                                          0x03000000L
28561 #define SQ_WAVE_IB_DBG0__IS_HYB_MASK                                                                          0x04000000L
28562 #define SQ_WAVE_IB_DBG0__HYB_CNT_MASK                                                                         0x18000000L
28563 #define SQ_WAVE_IB_DBG0__KILL_MASK                                                                            0x20000000L
28564 #define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK                                                                0x40000000L
28565 #define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK                                                              0x80000000L
28566 //SQ_WAVE_IB_DBG1
28567 #define SQ_WAVE_IB_DBG1__IXNACK__SHIFT                                                                        0x0
28568 #define SQ_WAVE_IB_DBG1__XNACK__SHIFT                                                                         0x1
28569 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT                                                                 0x2
28570 #define SQ_WAVE_IB_DBG1__XCNT__SHIFT                                                                          0x4
28571 #define SQ_WAVE_IB_DBG1__QCNT__SHIFT                                                                          0xb
28572 #define SQ_WAVE_IB_DBG1__RCNT__SHIFT                                                                          0x12
28573 #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT                                                                      0x19
28574 #define SQ_WAVE_IB_DBG1__IXNACK_MASK                                                                          0x00000001L
28575 #define SQ_WAVE_IB_DBG1__XNACK_MASK                                                                           0x00000002L
28576 #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK                                                                   0x00000004L
28577 #define SQ_WAVE_IB_DBG1__XCNT_MASK                                                                            0x000001F0L
28578 #define SQ_WAVE_IB_DBG1__QCNT_MASK                                                                            0x0000F800L
28579 #define SQ_WAVE_IB_DBG1__RCNT_MASK                                                                            0x007C0000L
28580 #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK                                                                        0xFE000000L
28581 //SQ_WAVE_FLUSH_IB
28582 #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT                                                                       0x0
28583 #define SQ_WAVE_FLUSH_IB__UNUSED_MASK                                                                         0xFFFFFFFFL
28584 //SQ_WAVE_TTMP0
28585 #define SQ_WAVE_TTMP0__DATA__SHIFT                                                                            0x0
28586 #define SQ_WAVE_TTMP0__DATA_MASK                                                                              0xFFFFFFFFL
28587 //SQ_WAVE_TTMP1
28588 #define SQ_WAVE_TTMP1__DATA__SHIFT                                                                            0x0
28589 #define SQ_WAVE_TTMP1__DATA_MASK                                                                              0xFFFFFFFFL
28590 //SQ_WAVE_TTMP2
28591 #define SQ_WAVE_TTMP2__DATA__SHIFT                                                                            0x0
28592 #define SQ_WAVE_TTMP2__DATA_MASK                                                                              0xFFFFFFFFL
28593 //SQ_WAVE_TTMP3
28594 #define SQ_WAVE_TTMP3__DATA__SHIFT                                                                            0x0
28595 #define SQ_WAVE_TTMP3__DATA_MASK                                                                              0xFFFFFFFFL
28596 //SQ_WAVE_TTMP4
28597 #define SQ_WAVE_TTMP4__DATA__SHIFT                                                                            0x0
28598 #define SQ_WAVE_TTMP4__DATA_MASK                                                                              0xFFFFFFFFL
28599 //SQ_WAVE_TTMP5
28600 #define SQ_WAVE_TTMP5__DATA__SHIFT                                                                            0x0
28601 #define SQ_WAVE_TTMP5__DATA_MASK                                                                              0xFFFFFFFFL
28602 //SQ_WAVE_TTMP6
28603 #define SQ_WAVE_TTMP6__DATA__SHIFT                                                                            0x0
28604 #define SQ_WAVE_TTMP6__DATA_MASK                                                                              0xFFFFFFFFL
28605 //SQ_WAVE_TTMP7
28606 #define SQ_WAVE_TTMP7__DATA__SHIFT                                                                            0x0
28607 #define SQ_WAVE_TTMP7__DATA_MASK                                                                              0xFFFFFFFFL
28608 //SQ_WAVE_TTMP8
28609 #define SQ_WAVE_TTMP8__DATA__SHIFT                                                                            0x0
28610 #define SQ_WAVE_TTMP8__DATA_MASK                                                                              0xFFFFFFFFL
28611 //SQ_WAVE_TTMP9
28612 #define SQ_WAVE_TTMP9__DATA__SHIFT                                                                            0x0
28613 #define SQ_WAVE_TTMP9__DATA_MASK                                                                              0xFFFFFFFFL
28614 //SQ_WAVE_TTMP10
28615 #define SQ_WAVE_TTMP10__DATA__SHIFT                                                                           0x0
28616 #define SQ_WAVE_TTMP10__DATA_MASK                                                                             0xFFFFFFFFL
28617 //SQ_WAVE_TTMP11
28618 #define SQ_WAVE_TTMP11__DATA__SHIFT                                                                           0x0
28619 #define SQ_WAVE_TTMP11__DATA_MASK                                                                             0xFFFFFFFFL
28620 //SQ_WAVE_TTMP12
28621 #define SQ_WAVE_TTMP12__DATA__SHIFT                                                                           0x0
28622 #define SQ_WAVE_TTMP12__DATA_MASK                                                                             0xFFFFFFFFL
28623 //SQ_WAVE_TTMP13
28624 #define SQ_WAVE_TTMP13__DATA__SHIFT                                                                           0x0
28625 #define SQ_WAVE_TTMP13__DATA_MASK                                                                             0xFFFFFFFFL
28626 //SQ_WAVE_TTMP14
28627 #define SQ_WAVE_TTMP14__DATA__SHIFT                                                                           0x0
28628 #define SQ_WAVE_TTMP14__DATA_MASK                                                                             0xFFFFFFFFL
28629 //SQ_WAVE_TTMP15
28630 #define SQ_WAVE_TTMP15__DATA__SHIFT                                                                           0x0
28631 #define SQ_WAVE_TTMP15__DATA_MASK                                                                             0xFFFFFFFFL
28632 //SQ_WAVE_M0
28633 #define SQ_WAVE_M0__M0__SHIFT                                                                                 0x0
28634 #define SQ_WAVE_M0__M0_MASK                                                                                   0xFFFFFFFFL
28635 //SQ_WAVE_EXEC_LO
28636 #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT                                                                       0x0
28637 #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK                                                                         0xFFFFFFFFL
28638 //SQ_WAVE_EXEC_HI
28639 #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT                                                                       0x0
28640 #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK                                                                         0xFFFFFFFFL
28641 //SQ_INTERRUPT_WORD_AUTO_CTXID
28642 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT                                                     0x0
28643 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT                                                              0x1
28644 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT                                            0x2
28645 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT                                                    0x3
28646 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT                                                    0x4
28647 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT                                                0x5
28648 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT                                                0x6
28649 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT                                                   0x7
28650 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT                                           0x8
28651 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT                                                            0x18
28652 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT                                                         0x1a
28653 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK                                                       0x0000001L
28654 #define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK                                                                0x0000002L
28655 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK                                              0x0000004L
28656 #define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK                                                      0x0000008L
28657 #define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK                                                      0x0000010L
28658 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK                                                  0x0000020L
28659 #define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK                                                  0x0000040L
28660 #define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK                                                     0x0000080L
28661 #define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK                                             0x0000100L
28662 #define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK                                                              0x3000000L
28663 #define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK                                                           0xC000000L
28664 //SQ_INTERRUPT_WORD_AUTO_HI
28665 #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT                                                               0x8
28666 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT                                                            0xa
28667 #define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK                                                                 0x300L
28668 #define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK                                                              0xC00L
28669 //SQ_INTERRUPT_WORD_AUTO_LO
28670 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT                                                        0x0
28671 #define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT                                                                 0x1
28672 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT                                               0x2
28673 #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT                                                       0x3
28674 #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT                                                       0x4
28675 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT                                                   0x5
28676 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT                                                   0x6
28677 #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT                                                      0x7
28678 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT                                              0x8
28679 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK                                                          0x001L
28680 #define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK                                                                   0x002L
28681 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK                                                 0x004L
28682 #define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK                                                         0x008L
28683 #define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK                                                         0x010L
28684 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK                                                     0x020L
28685 #define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK                                                     0x040L
28686 #define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK                                                        0x080L
28687 #define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK                                                0x100L
28688 //SQ_INTERRUPT_WORD_CMN_CTXID
28689 #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT                                                             0x18
28690 #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT                                                          0x1a
28691 #define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK                                                               0x3000000L
28692 #define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK                                                            0xC000000L
28693 //SQ_INTERRUPT_WORD_CMN_HI
28694 #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT                                                                0x8
28695 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT                                                             0xa
28696 #define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK                                                                  0x300L
28697 #define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK                                                               0xC00L
28698 //SQ_INTERRUPT_WORD_WAVE_CTXID
28699 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT                                                             0x0
28700 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT                                                            0xc
28701 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT                                                             0xd
28702 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT                                                          0xe
28703 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT                                                          0x12
28704 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT                                                            0x14
28705 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT                                                            0x18
28706 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT                                                         0x1a
28707 #define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK                                                               0x0000FFFL
28708 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK                                                              0x0001000L
28709 #define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK                                                               0x0002000L
28710 #define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK                                                            0x003C000L
28711 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK                                                            0x00C0000L
28712 #define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK                                                              0x0F00000L
28713 #define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK                                                              0x3000000L
28714 #define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK                                                           0xC000000L
28715 //SQ_INTERRUPT_WORD_WAVE_HI
28716 #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT                                                               0x0
28717 #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT                                                               0x4
28718 #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT                                                               0x8
28719 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT                                                            0xa
28720 #define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK                                                                 0x00FL
28721 #define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK                                                                 0x0F0L
28722 #define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK                                                                 0x300L
28723 #define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK                                                              0xC00L
28724 //SQ_INTERRUPT_WORD_WAVE_LO
28725 #define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT                                                                0x0
28726 #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT                                                               0x18
28727 #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT                                                                0x19
28728 #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT                                                             0x1a
28729 #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT                                                             0x1e
28730 #define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK                                                                  0x00FFFFFFL
28731 #define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK                                                                 0x01000000L
28732 #define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK                                                                  0x02000000L
28733 #define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK                                                               0x3C000000L
28734 #define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK                                                               0xC0000000L
28735 
28736 
28737 // addressBlock: didtind
28738 //DIDT_SQ_CTRL0
28739 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
28740 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
28741 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
28742 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
28743 #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
28744 #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
28745 #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
28746 #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
28747 #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
28748 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
28749 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
28750 #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT                                                                        0x1b
28751 #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
28752 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
28753 #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
28754 #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
28755 #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
28756 #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
28757 #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
28758 #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
28759 #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
28760 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
28761 #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
28762 #define DIDT_SQ_CTRL0__UNUSED_0_MASK                                                                          0xF8000000L
28763 //DIDT_SQ_CTRL1
28764 #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT                                                                       0x0
28765 #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT                                                                       0x10
28766 #define DIDT_SQ_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
28767 #define DIDT_SQ_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
28768 //DIDT_SQ_CTRL2
28769 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
28770 #define DIDT_SQ_CTRL2__UNUSED_0__SHIFT                                                                        0xe
28771 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
28772 #define DIDT_SQ_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
28773 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
28774 #define DIDT_SQ_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
28775 #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
28776 #define DIDT_SQ_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
28777 #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
28778 #define DIDT_SQ_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
28779 #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
28780 #define DIDT_SQ_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
28781 //DIDT_SQ_STALL_CTRL
28782 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
28783 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
28784 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
28785 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
28786 #define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT                                                                   0x18
28787 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
28788 #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
28789 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
28790 #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
28791 #define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK                                                                     0xFF000000L
28792 //DIDT_SQ_TUNING_CTRL
28793 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
28794 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
28795 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
28796 #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
28797 //DIDT_SQ_STALL_AUTO_RELEASE_CTRL
28798 #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
28799 #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
28800 //DIDT_SQ_CTRL3
28801 #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
28802 #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
28803 #define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
28804 #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
28805 #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
28806 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
28807 #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
28808 #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
28809 #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
28810 #define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
28811 #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
28812 #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
28813 #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
28814 #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
28815 #define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
28816 #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
28817 #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
28818 #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
28819 #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
28820 #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
28821 #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
28822 #define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
28823 #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
28824 #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
28825 //DIDT_SQ_STALL_PATTERN_1_2
28826 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
28827 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                            0xf
28828 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
28829 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                            0x1f
28830 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
28831 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK                                                              0x00008000L
28832 #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
28833 #define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK                                                              0x80000000L
28834 //DIDT_SQ_STALL_PATTERN_3_4
28835 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
28836 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                            0xf
28837 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
28838 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                            0x1f
28839 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
28840 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK                                                              0x00008000L
28841 #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
28842 #define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK                                                              0x80000000L
28843 //DIDT_SQ_STALL_PATTERN_5_6
28844 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
28845 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                            0xf
28846 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
28847 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                            0x1f
28848 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
28849 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK                                                              0x00008000L
28850 #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
28851 #define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK                                                              0x80000000L
28852 //DIDT_SQ_STALL_PATTERN_7
28853 #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
28854 #define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT                                                              0xf
28855 #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
28856 #define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK                                                                0xFFFF8000L
28857 //DIDT_SQ_WEIGHT0_3
28858 #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
28859 #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
28860 #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
28861 #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
28862 #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
28863 #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
28864 #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
28865 #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
28866 //DIDT_SQ_WEIGHT4_7
28867 #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
28868 #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
28869 #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
28870 #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
28871 #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
28872 #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
28873 #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
28874 #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
28875 //DIDT_SQ_WEIGHT8_11
28876 #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
28877 #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
28878 #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
28879 #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
28880 #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
28881 #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
28882 #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
28883 #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
28884 //DIDT_SQ_EDC_CTRL
28885 #define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
28886 #define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
28887 #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
28888 #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
28889 #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
28890 #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
28891 #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
28892 #define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
28893 #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
28894 #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
28895 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
28896 #define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT                                                                     0x17
28897 #define DIDT_SQ_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
28898 #define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
28899 #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
28900 #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
28901 #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
28902 #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
28903 #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
28904 #define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
28905 #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
28906 #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
28907 #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
28908 #define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK                                                                       0xFF800000L
28909 //DIDT_SQ_EDC_THRESHOLD
28910 #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
28911 #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
28912 //DIDT_SQ_EDC_STALL_PATTERN_1_2
28913 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
28914 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                        0xf
28915 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
28916 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                        0x1f
28917 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
28918 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                          0x00008000L
28919 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
28920 #define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                          0x80000000L
28921 //DIDT_SQ_EDC_STALL_PATTERN_3_4
28922 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
28923 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                        0xf
28924 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
28925 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                        0x1f
28926 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
28927 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                          0x00008000L
28928 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
28929 #define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                          0x80000000L
28930 //DIDT_SQ_EDC_STALL_PATTERN_5_6
28931 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
28932 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                        0xf
28933 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
28934 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                        0x1f
28935 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
28936 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                          0x00008000L
28937 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
28938 #define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                          0x80000000L
28939 //DIDT_SQ_EDC_STALL_PATTERN_7
28940 #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
28941 #define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                          0xf
28942 #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
28943 #define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                            0xFFFF8000L
28944 //DIDT_SQ_EDC_STATUS
28945 #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
28946 #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
28947 #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
28948 #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
28949 //DIDT_SQ_EDC_STALL_DELAY_1
28950 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT                                                 0x0
28951 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT                                                 0x8
28952 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT                                                 0x10
28953 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT                                                 0x18
28954 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK                                                   0x000000FFL
28955 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK                                                   0x0000FF00L
28956 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK                                                   0x00FF0000L
28957 #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK                                                   0xFF000000L
28958 //DIDT_SQ_EDC_STALL_DELAY_2
28959 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT                                                 0x0
28960 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT                                                 0x8
28961 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT                                                 0x10
28962 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT                                                 0x18
28963 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK                                                   0x000000FFL
28964 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK                                                   0x0000FF00L
28965 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK                                                   0x00FF0000L
28966 #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK                                                   0xFF000000L
28967 //DIDT_SQ_EDC_STALL_DELAY_3
28968 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT                                                 0x0
28969 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT                                                 0x8
28970 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT                                                0x10
28971 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT                                                0x18
28972 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK                                                   0x000000FFL
28973 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK                                                   0x0000FF00L
28974 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK                                                  0x00FF0000L
28975 #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK                                                  0xFF000000L
28976 //DIDT_SQ_EDC_STALL_DELAY_4
28977 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT                                                0x0
28978 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT                                                0x8
28979 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT                                                0x10
28980 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT                                                0x18
28981 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK                                                  0x000000FFL
28982 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13_MASK                                                  0x0000FF00L
28983 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK                                                  0x00FF0000L
28984 #define DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK                                                  0xFF000000L
28985 //DIDT_SQ_EDC_OVERFLOW
28986 #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
28987 #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
28988 #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
28989 #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
28990 //DIDT_SQ_EDC_ROLLING_POWER_DELTA
28991 #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
28992 #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
28993 //DIDT_DB_CTRL0
28994 #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
28995 #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
28996 #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
28997 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
28998 #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
28999 #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
29000 #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
29001 #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
29002 #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
29003 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
29004 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
29005 #define DIDT_DB_CTRL0__UNUSED_0__SHIFT                                                                        0x1b
29006 #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
29007 #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
29008 #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
29009 #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
29010 #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
29011 #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
29012 #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
29013 #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
29014 #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
29015 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
29016 #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
29017 #define DIDT_DB_CTRL0__UNUSED_0_MASK                                                                          0xF8000000L
29018 //DIDT_DB_CTRL1
29019 #define DIDT_DB_CTRL1__MIN_POWER__SHIFT                                                                       0x0
29020 #define DIDT_DB_CTRL1__MAX_POWER__SHIFT                                                                       0x10
29021 #define DIDT_DB_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
29022 #define DIDT_DB_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
29023 //DIDT_DB_CTRL2
29024 #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
29025 #define DIDT_DB_CTRL2__UNUSED_0__SHIFT                                                                        0xe
29026 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
29027 #define DIDT_DB_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
29028 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
29029 #define DIDT_DB_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
29030 #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
29031 #define DIDT_DB_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
29032 #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
29033 #define DIDT_DB_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
29034 #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
29035 #define DIDT_DB_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
29036 //DIDT_DB_STALL_CTRL
29037 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
29038 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
29039 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
29040 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
29041 #define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT                                                                   0x18
29042 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
29043 #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
29044 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
29045 #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
29046 #define DIDT_DB_STALL_CTRL__UNUSED_0_MASK                                                                     0xFF000000L
29047 //DIDT_DB_TUNING_CTRL
29048 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
29049 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
29050 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
29051 #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
29052 //DIDT_DB_STALL_AUTO_RELEASE_CTRL
29053 #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
29054 #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
29055 //DIDT_DB_CTRL3
29056 #define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
29057 #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
29058 #define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
29059 #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
29060 #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
29061 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
29062 #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
29063 #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
29064 #define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
29065 #define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
29066 #define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
29067 #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
29068 #define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
29069 #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
29070 #define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
29071 #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
29072 #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
29073 #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
29074 #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
29075 #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
29076 #define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
29077 #define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
29078 #define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
29079 #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
29080 //DIDT_DB_STALL_PATTERN_1_2
29081 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
29082 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                            0xf
29083 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
29084 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                            0x1f
29085 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
29086 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK                                                              0x00008000L
29087 #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
29088 #define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK                                                              0x80000000L
29089 //DIDT_DB_STALL_PATTERN_3_4
29090 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
29091 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                            0xf
29092 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
29093 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                            0x1f
29094 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
29095 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK                                                              0x00008000L
29096 #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
29097 #define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK                                                              0x80000000L
29098 //DIDT_DB_STALL_PATTERN_5_6
29099 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
29100 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                            0xf
29101 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
29102 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                            0x1f
29103 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
29104 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK                                                              0x00008000L
29105 #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
29106 #define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK                                                              0x80000000L
29107 //DIDT_DB_STALL_PATTERN_7
29108 #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
29109 #define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT                                                              0xf
29110 #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
29111 #define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK                                                                0xFFFF8000L
29112 //DIDT_DB_WEIGHT0_3
29113 #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
29114 #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
29115 #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
29116 #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
29117 #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
29118 #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
29119 #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
29120 #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
29121 //DIDT_DB_WEIGHT4_7
29122 #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
29123 #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
29124 #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
29125 #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
29126 #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
29127 #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
29128 #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
29129 #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
29130 //DIDT_DB_WEIGHT8_11
29131 #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
29132 #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
29133 #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
29134 #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
29135 #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
29136 #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
29137 #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
29138 #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
29139 //DIDT_DB_EDC_CTRL
29140 #define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
29141 #define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
29142 #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
29143 #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
29144 #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
29145 #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
29146 #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
29147 #define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
29148 #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
29149 #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
29150 #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
29151 #define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT                                                                     0x17
29152 #define DIDT_DB_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
29153 #define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
29154 #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
29155 #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
29156 #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
29157 #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
29158 #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
29159 #define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
29160 #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
29161 #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
29162 #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
29163 #define DIDT_DB_EDC_CTRL__UNUSED_0_MASK                                                                       0xFF800000L
29164 //DIDT_DB_EDC_THRESHOLD
29165 #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
29166 #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
29167 //DIDT_DB_EDC_STALL_PATTERN_1_2
29168 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
29169 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                        0xf
29170 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
29171 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                        0x1f
29172 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
29173 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                          0x00008000L
29174 #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
29175 #define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                          0x80000000L
29176 //DIDT_DB_EDC_STALL_PATTERN_3_4
29177 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
29178 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                        0xf
29179 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
29180 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                        0x1f
29181 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
29182 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                          0x00008000L
29183 #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
29184 #define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                          0x80000000L
29185 //DIDT_DB_EDC_STALL_PATTERN_5_6
29186 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
29187 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                        0xf
29188 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
29189 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                        0x1f
29190 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
29191 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                          0x00008000L
29192 #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
29193 #define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                          0x80000000L
29194 //DIDT_DB_EDC_STALL_PATTERN_7
29195 #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
29196 #define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                          0xf
29197 #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
29198 #define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                            0xFFFF8000L
29199 //DIDT_DB_EDC_STATUS
29200 #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
29201 #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
29202 #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
29203 #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
29204 //DIDT_DB_EDC_STALL_DELAY_1
29205 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT                                                 0x0
29206 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT                                                 0x6
29207 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT                                                 0xc
29208 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT                                                 0x12
29209 #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                              0x18
29210 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK                                                   0x0000003FL
29211 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK                                                   0x00000FC0L
29212 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK                                                   0x0003F000L
29213 #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK                                                   0x00FC0000L
29214 #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK                                                                0xFF000000L
29215 //DIDT_DB_EDC_OVERFLOW
29216 #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
29217 #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
29218 #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
29219 #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
29220 //DIDT_DB_EDC_ROLLING_POWER_DELTA
29221 #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
29222 #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
29223 //DIDT_TD_CTRL0
29224 #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT                                                                    0x0
29225 #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT                                                                    0x1
29226 #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT                                                                   0x3
29227 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                            0x4
29228 #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                              0x5
29229 #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                             0x6
29230 #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                      0x7
29231 #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                         0x8
29232 #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                                0x18
29233 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                             0x19
29234 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                  0x1a
29235 #define DIDT_TD_CTRL0__UNUSED_0__SHIFT                                                                        0x1b
29236 #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK                                                                      0x00000001L
29237 #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK                                                                      0x00000006L
29238 #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK                                                                     0x00000008L
29239 #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                              0x00000010L
29240 #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                                0x00000020L
29241 #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                               0x00000040L
29242 #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                        0x00000080L
29243 #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                           0x00FFFF00L
29244 #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                  0x01000000L
29245 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                               0x02000000L
29246 #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                    0x04000000L
29247 #define DIDT_TD_CTRL0__UNUSED_0_MASK                                                                          0xF8000000L
29248 //DIDT_TD_CTRL1
29249 #define DIDT_TD_CTRL1__MIN_POWER__SHIFT                                                                       0x0
29250 #define DIDT_TD_CTRL1__MAX_POWER__SHIFT                                                                       0x10
29251 #define DIDT_TD_CTRL1__MIN_POWER_MASK                                                                         0x0000FFFFL
29252 #define DIDT_TD_CTRL1__MAX_POWER_MASK                                                                         0xFFFF0000L
29253 //DIDT_TD_CTRL2
29254 #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT                                                                 0x0
29255 #define DIDT_TD_CTRL2__UNUSED_0__SHIFT                                                                        0xe
29256 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                        0x10
29257 #define DIDT_TD_CTRL2__UNUSED_1__SHIFT                                                                        0x1a
29258 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                        0x1b
29259 #define DIDT_TD_CTRL2__UNUSED_2__SHIFT                                                                        0x1f
29260 #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK                                                                   0x00003FFFL
29261 #define DIDT_TD_CTRL2__UNUSED_0_MASK                                                                          0x0000C000L
29262 #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                          0x03FF0000L
29263 #define DIDT_TD_CTRL2__UNUSED_1_MASK                                                                          0x04000000L
29264 #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                          0x78000000L
29265 #define DIDT_TD_CTRL2__UNUSED_2_MASK                                                                          0x80000000L
29266 //DIDT_TD_STALL_CTRL
29267 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                        0x0
29268 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                        0x6
29269 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                 0xc
29270 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                 0x12
29271 #define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT                                                                   0x18
29272 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                          0x0000003FL
29273 #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                          0x00000FC0L
29274 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                   0x0003F000L
29275 #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                   0x00FC0000L
29276 #define DIDT_TD_STALL_CTRL__UNUSED_0_MASK                                                                     0xFF000000L
29277 //DIDT_TD_TUNING_CTRL
29278 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                        0x0
29279 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                        0xe
29280 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                          0x00003FFFL
29281 #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                          0x0FFFC000L
29282 //DIDT_TD_STALL_AUTO_RELEASE_CTRL
29283 #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                  0x0
29284 #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                    0x00FFFFFFL
29285 //DIDT_TD_CTRL3
29286 #define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                  0x0
29287 #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                         0x1
29288 #define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT                                                                 0x2
29289 #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                    0x4
29290 #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                         0x9
29291 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                     0xe
29292 #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x16
29293 #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                           0x17
29294 #define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT                                                                0x18
29295 #define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT                                                                  0x19
29296 #define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT                                                                0x1b
29297 #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                             0x1c
29298 #define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK                                                                    0x00000001L
29299 #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                           0x00000002L
29300 #define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK                                                                   0x0000000CL
29301 #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                      0x000001F0L
29302 #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                           0x00003E00L
29303 #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                       0x003FC000L
29304 #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                             0x00400000L
29305 #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                             0x00800000L
29306 #define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK                                                                  0x01000000L
29307 #define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK                                                                    0x06000000L
29308 #define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK                                                                  0x08000000L
29309 #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                               0x10000000L
29310 //DIDT_TD_STALL_PATTERN_1_2
29311 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                                0x0
29312 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                            0xf
29313 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                                0x10
29314 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                            0x1f
29315 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                  0x00007FFFL
29316 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK                                                              0x00008000L
29317 #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                  0x7FFF0000L
29318 #define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK                                                              0x80000000L
29319 //DIDT_TD_STALL_PATTERN_3_4
29320 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                                0x0
29321 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                            0xf
29322 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                                0x10
29323 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                            0x1f
29324 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                  0x00007FFFL
29325 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK                                                              0x00008000L
29326 #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                  0x7FFF0000L
29327 #define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK                                                              0x80000000L
29328 //DIDT_TD_STALL_PATTERN_5_6
29329 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                                0x0
29330 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                            0xf
29331 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                                0x10
29332 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                            0x1f
29333 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                  0x00007FFFL
29334 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK                                                              0x00008000L
29335 #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                  0x7FFF0000L
29336 #define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK                                                              0x80000000L
29337 //DIDT_TD_STALL_PATTERN_7
29338 #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                  0x0
29339 #define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT                                                              0xf
29340 #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                    0x00007FFFL
29341 #define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK                                                                0xFFFF8000L
29342 //DIDT_TD_WEIGHT0_3
29343 #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT                                                                     0x0
29344 #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT                                                                     0x8
29345 #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT                                                                     0x10
29346 #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT                                                                     0x18
29347 #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK                                                                       0x000000FFL
29348 #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK                                                                       0x0000FF00L
29349 #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK                                                                       0x00FF0000L
29350 #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK                                                                       0xFF000000L
29351 //DIDT_TD_WEIGHT4_7
29352 #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT                                                                     0x0
29353 #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT                                                                     0x8
29354 #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT                                                                     0x10
29355 #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT                                                                     0x18
29356 #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK                                                                       0x000000FFL
29357 #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK                                                                       0x0000FF00L
29358 #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK                                                                       0x00FF0000L
29359 #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK                                                                       0xFF000000L
29360 //DIDT_TD_WEIGHT8_11
29361 #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT                                                                    0x0
29362 #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT                                                                    0x8
29363 #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT                                                                   0x10
29364 #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT                                                                   0x18
29365 #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK                                                                      0x000000FFL
29366 #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK                                                                      0x0000FF00L
29367 #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK                                                                     0x00FF0000L
29368 #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK                                                                     0xFF000000L
29369 //DIDT_TD_EDC_CTRL
29370 #define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT                                                                       0x0
29371 #define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT                                                                   0x1
29372 #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                          0x2
29373 #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                              0x3
29374 #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                  0x4
29375 #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                   0x9
29376 #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                     0x11
29377 #define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT                                                                    0x12
29378 #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                          0x13
29379 #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                         0x15
29380 #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                         0x16
29381 #define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT                                                                     0x17
29382 #define DIDT_TD_EDC_CTRL__EDC_EN_MASK                                                                         0x00000001L
29383 #define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK                                                                     0x00000002L
29384 #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                            0x00000004L
29385 #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK                                                                0x00000008L
29386 #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                    0x000001F0L
29387 #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                     0x0001FE00L
29388 #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                       0x00020000L
29389 #define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK                                                                      0x00040000L
29390 #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                            0x00180000L
29391 #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                           0x00200000L
29392 #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                           0x00400000L
29393 #define DIDT_TD_EDC_CTRL__UNUSED_0_MASK                                                                       0xFF800000L
29394 //DIDT_TD_EDC_THRESHOLD
29395 #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                           0x0
29396 #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                             0xFFFFFFFFL
29397 //DIDT_TD_EDC_STALL_PATTERN_1_2
29398 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                             0x0
29399 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                        0xf
29400 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                             0x10
29401 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                        0x1f
29402 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                               0x00007FFFL
29403 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                          0x00008000L
29404 #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                               0x7FFF0000L
29405 #define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                          0x80000000L
29406 //DIDT_TD_EDC_STALL_PATTERN_3_4
29407 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                             0x0
29408 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                        0xf
29409 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                             0x10
29410 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                        0x1f
29411 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                               0x00007FFFL
29412 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                          0x00008000L
29413 #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                               0x7FFF0000L
29414 #define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                          0x80000000L
29415 //DIDT_TD_EDC_STALL_PATTERN_5_6
29416 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                             0x0
29417 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                        0xf
29418 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                             0x10
29419 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                        0x1f
29420 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                               0x00007FFFL
29421 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                          0x00008000L
29422 #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                               0x7FFF0000L
29423 #define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                          0x80000000L
29424 //DIDT_TD_EDC_STALL_PATTERN_7
29425 #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                               0x0
29426 #define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                          0xf
29427 #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                 0x00007FFFL
29428 #define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                            0xFFFF8000L
29429 //DIDT_TD_EDC_STATUS
29430 #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                              0x0
29431 #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                         0x1
29432 #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK                                                                0x00000001L
29433 #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                           0x0000000EL
29434 //DIDT_TD_EDC_STALL_DELAY_1
29435 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT                                                 0x0
29436 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT                                                 0x8
29437 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT                                                 0x10
29438 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT                                                 0x18
29439 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK                                                   0x000000FFL
29440 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK                                                   0x0000FF00L
29441 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK                                                   0x00FF0000L
29442 #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK                                                   0xFF000000L
29443 //DIDT_TD_EDC_STALL_DELAY_2
29444 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT                                                 0x0
29445 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT                                                 0x8
29446 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT                                                 0x10
29447 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT                                                 0x18
29448 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK                                                   0x000000FFL
29449 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK                                                   0x0000FF00L
29450 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK                                                   0x00FF0000L
29451 #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK                                                   0xFF000000L
29452 //DIDT_TD_EDC_STALL_DELAY_3
29453 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT                                                 0x0
29454 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT                                                 0x8
29455 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT                                                0x10
29456 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11__SHIFT                                                0x18
29457 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK                                                   0x000000FFL
29458 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK                                                   0x0000FF00L
29459 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK                                                  0x00FF0000L
29460 #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD11_MASK                                                  0xFF000000L
29461 //DIDT_TD_EDC_STALL_DELAY_4
29462 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12__SHIFT                                                0x0
29463 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13__SHIFT                                                0x8
29464 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14__SHIFT                                                0x10
29465 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15__SHIFT                                                0x18
29466 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD12_MASK                                                  0x000000FFL
29467 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD13_MASK                                                  0x0000FF00L
29468 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD14_MASK                                                  0x00FF0000L
29469 #define DIDT_TD_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TD15_MASK                                                  0xFF000000L
29470 //DIDT_TD_EDC_OVERFLOW
29471 #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                         0x0
29472 #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                      0x1
29473 #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                           0x00000001L
29474 #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                        0x0001FFFEL
29475 //DIDT_TD_EDC_ROLLING_POWER_DELTA
29476 #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                       0x0
29477 #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                         0xFFFFFFFFL
29478 //DIDT_TCP_CTRL0
29479 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT                                                                   0x0
29480 #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
29481 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT                                                                  0x3
29482 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                           0x4
29483 #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                             0x5
29484 #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                            0x6
29485 #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                     0x7
29486 #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                        0x8
29487 #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                               0x18
29488 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                            0x19
29489 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                 0x1a
29490 #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT                                                                       0x1b
29491 #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK                                                                     0x00000001L
29492 #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK                                                                     0x00000006L
29493 #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK                                                                    0x00000008L
29494 #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                             0x00000010L
29495 #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                               0x00000020L
29496 #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                              0x00000040L
29497 #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                       0x00000080L
29498 #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                          0x00FFFF00L
29499 #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                 0x01000000L
29500 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                              0x02000000L
29501 #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                   0x04000000L
29502 #define DIDT_TCP_CTRL0__UNUSED_0_MASK                                                                         0xF8000000L
29503 //DIDT_TCP_CTRL1
29504 #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT                                                                      0x0
29505 #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT                                                                      0x10
29506 #define DIDT_TCP_CTRL1__MIN_POWER_MASK                                                                        0x0000FFFFL
29507 #define DIDT_TCP_CTRL1__MAX_POWER_MASK                                                                        0xFFFF0000L
29508 //DIDT_TCP_CTRL2
29509 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT                                                                0x0
29510 #define DIDT_TCP_CTRL2__UNUSED_0__SHIFT                                                                       0xe
29511 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                       0x10
29512 #define DIDT_TCP_CTRL2__UNUSED_1__SHIFT                                                                       0x1a
29513 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                       0x1b
29514 #define DIDT_TCP_CTRL2__UNUSED_2__SHIFT                                                                       0x1f
29515 #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK                                                                  0x00003FFFL
29516 #define DIDT_TCP_CTRL2__UNUSED_0_MASK                                                                         0x0000C000L
29517 #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                         0x03FF0000L
29518 #define DIDT_TCP_CTRL2__UNUSED_1_MASK                                                                         0x04000000L
29519 #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                         0x78000000L
29520 #define DIDT_TCP_CTRL2__UNUSED_2_MASK                                                                         0x80000000L
29521 //DIDT_TCP_STALL_CTRL
29522 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                       0x0
29523 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                       0x6
29524 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                0xc
29525 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                0x12
29526 #define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT                                                                  0x18
29527 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                         0x0000003FL
29528 #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                         0x00000FC0L
29529 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                  0x0003F000L
29530 #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                  0x00FC0000L
29531 #define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK                                                                    0xFF000000L
29532 //DIDT_TCP_TUNING_CTRL
29533 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                       0x0
29534 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                       0xe
29535 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                         0x00003FFFL
29536 #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                         0x0FFFC000L
29537 //DIDT_TCP_STALL_AUTO_RELEASE_CTRL
29538 #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                 0x0
29539 #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                   0x00FFFFFFL
29540 //DIDT_TCP_CTRL3
29541 #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                 0x0
29542 #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                        0x1
29543 #define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT                                                                0x2
29544 #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                   0x4
29545 #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                        0x9
29546 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                    0xe
29547 #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x16
29548 #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x17
29549 #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT                                                               0x18
29550 #define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT                                                                 0x19
29551 #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT                                                               0x1b
29552 #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                            0x1c
29553 #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK                                                                   0x00000001L
29554 #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                          0x00000002L
29555 #define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK                                                                  0x0000000CL
29556 #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                     0x000001F0L
29557 #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                          0x00003E00L
29558 #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                      0x003FC000L
29559 #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                            0x00400000L
29560 #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                            0x00800000L
29561 #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK                                                                 0x01000000L
29562 #define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK                                                                   0x06000000L
29563 #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK                                                                 0x08000000L
29564 #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                              0x10000000L
29565 //DIDT_TCP_STALL_PATTERN_1_2
29566 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                               0x0
29567 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                           0xf
29568 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                               0x10
29569 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                           0x1f
29570 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                 0x00007FFFL
29571 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK                                                             0x00008000L
29572 #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
29573 #define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK                                                             0x80000000L
29574 //DIDT_TCP_STALL_PATTERN_3_4
29575 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                               0x0
29576 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                           0xf
29577 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                               0x10
29578 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                           0x1f
29579 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                 0x00007FFFL
29580 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK                                                             0x00008000L
29581 #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
29582 #define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK                                                             0x80000000L
29583 //DIDT_TCP_STALL_PATTERN_5_6
29584 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                               0x0
29585 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                           0xf
29586 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                               0x10
29587 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                           0x1f
29588 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                 0x00007FFFL
29589 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK                                                             0x00008000L
29590 #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
29591 #define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK                                                             0x80000000L
29592 //DIDT_TCP_STALL_PATTERN_7
29593 #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                 0x0
29594 #define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT                                                             0xf
29595 #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                   0x00007FFFL
29596 #define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK                                                               0xFFFF8000L
29597 //DIDT_TCP_WEIGHT0_3
29598 #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT                                                                    0x0
29599 #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT                                                                    0x8
29600 #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT                                                                    0x10
29601 #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT                                                                    0x18
29602 #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK                                                                      0x000000FFL
29603 #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK                                                                      0x0000FF00L
29604 #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK                                                                      0x00FF0000L
29605 #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK                                                                      0xFF000000L
29606 //DIDT_TCP_WEIGHT4_7
29607 #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT                                                                    0x0
29608 #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT                                                                    0x8
29609 #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT                                                                    0x10
29610 #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT                                                                    0x18
29611 #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK                                                                      0x000000FFL
29612 #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK                                                                      0x0000FF00L
29613 #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK                                                                      0x00FF0000L
29614 #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK                                                                      0xFF000000L
29615 //DIDT_TCP_WEIGHT8_11
29616 #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT                                                                   0x0
29617 #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT                                                                   0x8
29618 #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT                                                                  0x10
29619 #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT                                                                  0x18
29620 #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK                                                                     0x000000FFL
29621 #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK                                                                     0x0000FF00L
29622 #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK                                                                    0x00FF0000L
29623 #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK                                                                    0xFF000000L
29624 //DIDT_TCP_EDC_CTRL
29625 #define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT                                                                      0x0
29626 #define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT                                                                  0x1
29627 #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                         0x2
29628 #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                             0x3
29629 #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                 0x4
29630 #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                  0x9
29631 #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                    0x11
29632 #define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT                                                                   0x12
29633 #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                         0x13
29634 #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                        0x15
29635 #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                        0x16
29636 #define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT                                                                    0x17
29637 #define DIDT_TCP_EDC_CTRL__EDC_EN_MASK                                                                        0x00000001L
29638 #define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK                                                                    0x00000002L
29639 #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                           0x00000004L
29640 #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK                                                               0x00000008L
29641 #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                   0x000001F0L
29642 #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                    0x0001FE00L
29643 #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                      0x00020000L
29644 #define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK                                                                     0x00040000L
29645 #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                           0x00180000L
29646 #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                          0x00200000L
29647 #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                          0x00400000L
29648 #define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK                                                                      0xFF800000L
29649 //DIDT_TCP_EDC_THRESHOLD
29650 #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                          0x0
29651 #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                            0xFFFFFFFFL
29652 //DIDT_TCP_EDC_STALL_PATTERN_1_2
29653 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                            0x0
29654 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                       0xf
29655 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                            0x10
29656 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                       0x1f
29657 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                              0x00007FFFL
29658 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                         0x00008000L
29659 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                              0x7FFF0000L
29660 #define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                         0x80000000L
29661 //DIDT_TCP_EDC_STALL_PATTERN_3_4
29662 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                            0x0
29663 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                       0xf
29664 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                            0x10
29665 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                       0x1f
29666 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                              0x00007FFFL
29667 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                         0x00008000L
29668 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                              0x7FFF0000L
29669 #define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                         0x80000000L
29670 //DIDT_TCP_EDC_STALL_PATTERN_5_6
29671 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                            0x0
29672 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                       0xf
29673 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                            0x10
29674 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                       0x1f
29675 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                              0x00007FFFL
29676 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                         0x00008000L
29677 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                              0x7FFF0000L
29678 #define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                         0x80000000L
29679 //DIDT_TCP_EDC_STALL_PATTERN_7
29680 #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                              0x0
29681 #define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                         0xf
29682 #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                0x00007FFFL
29683 #define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                           0xFFFF8000L
29684 //DIDT_TCP_EDC_STATUS
29685 #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                             0x0
29686 #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                        0x1
29687 #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK                                                               0x00000001L
29688 #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                          0x0000000EL
29689 //DIDT_TCP_EDC_STALL_DELAY_1
29690 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT                                               0x0
29691 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT                                               0x8
29692 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT                                               0x10
29693 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT                                               0x18
29694 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK                                                 0x000000FFL
29695 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK                                                 0x0000FF00L
29696 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK                                                 0x00FF0000L
29697 #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK                                                 0xFF000000L
29698 //DIDT_TCP_EDC_STALL_DELAY_2
29699 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT                                               0x0
29700 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT                                               0x8
29701 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT                                               0x10
29702 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT                                               0x18
29703 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK                                                 0x000000FFL
29704 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK                                                 0x0000FF00L
29705 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK                                                 0x00FF0000L
29706 #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK                                                 0xFF000000L
29707 //DIDT_TCP_EDC_STALL_DELAY_3
29708 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT                                               0x0
29709 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT                                               0x8
29710 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT                                              0x10
29711 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11__SHIFT                                              0x18
29712 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK                                                 0x000000FFL
29713 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK                                                 0x0000FF00L
29714 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK                                                0x00FF0000L
29715 #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP11_MASK                                                0xFF000000L
29716 //DIDT_TCP_EDC_STALL_DELAY_4
29717 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12__SHIFT                                              0x0
29718 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13__SHIFT                                              0x8
29719 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14__SHIFT                                              0x10
29720 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15__SHIFT                                              0x18
29721 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP12_MASK                                                0x000000FFL
29722 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP13_MASK                                                0x0000FF00L
29723 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP14_MASK                                                0x00FF0000L
29724 #define DIDT_TCP_EDC_STALL_DELAY_4__EDC_STALL_DELAY_TCP15_MASK                                                0xFF000000L
29725 //DIDT_TCP_EDC_OVERFLOW
29726 #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                        0x0
29727 #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                     0x1
29728 #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                          0x00000001L
29729 #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                       0x0001FFFEL
29730 //DIDT_TCP_EDC_ROLLING_POWER_DELTA
29731 #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                      0x0
29732 #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                        0xFFFFFFFFL
29733 //DIDT_DBR_CTRL0
29734 #define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT                                                                   0x0
29735 #define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT                                                                   0x1
29736 #define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT                                                                  0x3
29737 #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT                                                           0x4
29738 #define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT                                                             0x5
29739 #define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT                                                            0x6
29740 #define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT                                                     0x7
29741 #define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT                                                        0x8
29742 #define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT                                                               0x18
29743 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT                                                            0x19
29744 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT                                                 0x1a
29745 #define DIDT_DBR_CTRL0__UNUSED_0__SHIFT                                                                       0x1b
29746 #define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK                                                                     0x00000001L
29747 #define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK                                                                     0x00000006L
29748 #define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK                                                                    0x00000008L
29749 #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK                                                             0x00000010L
29750 #define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK                                                               0x00000020L
29751 #define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK                                                              0x00000040L
29752 #define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK                                                       0x00000080L
29753 #define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK                                                          0x00FFFF00L
29754 #define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK                                                                 0x01000000L
29755 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK                                                              0x02000000L
29756 #define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK                                                   0x04000000L
29757 #define DIDT_DBR_CTRL0__UNUSED_0_MASK                                                                         0xF8000000L
29758 //DIDT_DBR_CTRL1
29759 #define DIDT_DBR_CTRL1__MIN_POWER__SHIFT                                                                      0x0
29760 #define DIDT_DBR_CTRL1__MAX_POWER__SHIFT                                                                      0x10
29761 #define DIDT_DBR_CTRL1__MIN_POWER_MASK                                                                        0x0000FFFFL
29762 #define DIDT_DBR_CTRL1__MAX_POWER_MASK                                                                        0xFFFF0000L
29763 //DIDT_DBR_CTRL2
29764 #define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT                                                                0x0
29765 #define DIDT_DBR_CTRL2__UNUSED_0__SHIFT                                                                       0xe
29766 #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT                                                       0x10
29767 #define DIDT_DBR_CTRL2__UNUSED_1__SHIFT                                                                       0x1a
29768 #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT                                                       0x1b
29769 #define DIDT_DBR_CTRL2__UNUSED_2__SHIFT                                                                       0x1f
29770 #define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK                                                                  0x00003FFFL
29771 #define DIDT_DBR_CTRL2__UNUSED_0_MASK                                                                         0x0000C000L
29772 #define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK                                                         0x03FF0000L
29773 #define DIDT_DBR_CTRL2__UNUSED_1_MASK                                                                         0x04000000L
29774 #define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK                                                         0x78000000L
29775 #define DIDT_DBR_CTRL2__UNUSED_2_MASK                                                                         0x80000000L
29776 //DIDT_DBR_STALL_CTRL
29777 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT                                                       0x0
29778 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT                                                       0x6
29779 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT                                                0xc
29780 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT                                                0x12
29781 #define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT                                                                  0x18
29782 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK                                                         0x0000003FL
29783 #define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK                                                         0x00000FC0L
29784 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK                                                  0x0003F000L
29785 #define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK                                                  0x00FC0000L
29786 #define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK                                                                    0xFF000000L
29787 //DIDT_DBR_TUNING_CTRL
29788 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT                                                       0x0
29789 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT                                                       0xe
29790 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK                                                         0x00003FFFL
29791 #define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK                                                         0x0FFFC000L
29792 //DIDT_DBR_STALL_AUTO_RELEASE_CTRL
29793 #define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT                                 0x0
29794 #define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK                                   0x00FFFFFFL
29795 //DIDT_DBR_CTRL3
29796 #define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT                                                                 0x0
29797 #define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT                                                        0x1
29798 #define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT                                                                0x2
29799 #define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                   0x4
29800 #define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT                                                        0x9
29801 #define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT                                                    0xe
29802 #define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x16
29803 #define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT                                                          0x17
29804 #define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT                                                               0x18
29805 #define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT                                                                 0x19
29806 #define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT                                                               0x1b
29807 #define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT                                                            0x1c
29808 #define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK                                                                   0x00000001L
29809 #define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK                                                          0x00000002L
29810 #define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK                                                                  0x0000000CL
29811 #define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK                                                     0x000001F0L
29812 #define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK                                                          0x00003E00L
29813 #define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK                                                      0x003FC000L
29814 #define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK                                                            0x00400000L
29815 #define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK                                                            0x00800000L
29816 #define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK                                                                 0x01000000L
29817 #define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK                                                                   0x06000000L
29818 #define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK                                                                 0x08000000L
29819 #define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK                                                              0x10000000L
29820 //DIDT_DBR_STALL_PATTERN_1_2
29821 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT                                               0x0
29822 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                           0xf
29823 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT                                               0x10
29824 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                           0x1f
29825 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK                                                 0x00007FFFL
29826 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK                                                             0x00008000L
29827 #define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK                                                 0x7FFF0000L
29828 #define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK                                                             0x80000000L
29829 //DIDT_DBR_STALL_PATTERN_3_4
29830 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT                                               0x0
29831 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                           0xf
29832 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT                                               0x10
29833 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                           0x1f
29834 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK                                                 0x00007FFFL
29835 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK                                                             0x00008000L
29836 #define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK                                                 0x7FFF0000L
29837 #define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK                                                             0x80000000L
29838 //DIDT_DBR_STALL_PATTERN_5_6
29839 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT                                               0x0
29840 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                           0xf
29841 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT                                               0x10
29842 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                           0x1f
29843 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK                                                 0x00007FFFL
29844 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK                                                             0x00008000L
29845 #define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK                                                 0x7FFF0000L
29846 #define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK                                                             0x80000000L
29847 //DIDT_DBR_STALL_PATTERN_7
29848 #define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT                                                 0x0
29849 #define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT                                                             0xf
29850 #define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK                                                   0x00007FFFL
29851 #define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK                                                               0xFFFF8000L
29852 //DIDT_DBR_WEIGHT0_3
29853 #define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT                                                                    0x0
29854 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT                                                                    0x8
29855 #define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT                                                                    0x10
29856 #define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT                                                                    0x18
29857 #define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK                                                                      0x000000FFL
29858 #define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK                                                                      0x0000FF00L
29859 #define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK                                                                      0x00FF0000L
29860 #define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK                                                                      0xFF000000L
29861 //DIDT_DBR_WEIGHT4_7
29862 #define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT                                                                    0x0
29863 #define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT                                                                    0x8
29864 #define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT                                                                    0x10
29865 #define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT                                                                    0x18
29866 #define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK                                                                      0x000000FFL
29867 #define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK                                                                      0x0000FF00L
29868 #define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK                                                                      0x00FF0000L
29869 #define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK                                                                      0xFF000000L
29870 //DIDT_DBR_WEIGHT8_11
29871 #define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT                                                                   0x0
29872 #define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT                                                                   0x8
29873 #define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT                                                                  0x10
29874 #define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT                                                                  0x18
29875 #define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK                                                                     0x000000FFL
29876 #define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK                                                                     0x0000FF00L
29877 #define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK                                                                    0x00FF0000L
29878 #define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK                                                                    0xFF000000L
29879 //DIDT_DBR_EDC_CTRL
29880 #define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT                                                                      0x0
29881 #define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT                                                                  0x1
29882 #define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT                                                         0x2
29883 #define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT                                                             0x3
29884 #define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT                                                 0x4
29885 #define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT                                                  0x9
29886 #define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT                                                    0x11
29887 #define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT                                                                   0x12
29888 #define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT                                                         0x13
29889 #define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT                                                        0x15
29890 #define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT                                                        0x16
29891 #define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT                                                                    0x17
29892 #define DIDT_DBR_EDC_CTRL__EDC_EN_MASK                                                                        0x00000001L
29893 #define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK                                                                    0x00000002L
29894 #define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK                                                           0x00000004L
29895 #define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK                                                               0x00000008L
29896 #define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK                                                   0x000001F0L
29897 #define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK                                                    0x0001FE00L
29898 #define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK                                                      0x00020000L
29899 #define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK                                                                     0x00040000L
29900 #define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK                                                           0x00180000L
29901 #define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK                                                          0x00200000L
29902 #define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK                                                          0x00400000L
29903 #define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK                                                                      0xFF800000L
29904 //DIDT_DBR_EDC_THRESHOLD
29905 #define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT                                                          0x0
29906 #define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK                                                            0xFFFFFFFFL
29907 //DIDT_DBR_EDC_STALL_PATTERN_1_2
29908 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT                                            0x0
29909 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT                                                       0xf
29910 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT                                            0x10
29911 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT                                                       0x1f
29912 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK                                              0x00007FFFL
29913 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK                                                         0x00008000L
29914 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK                                              0x7FFF0000L
29915 #define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK                                                         0x80000000L
29916 //DIDT_DBR_EDC_STALL_PATTERN_3_4
29917 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT                                            0x0
29918 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT                                                       0xf
29919 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT                                            0x10
29920 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT                                                       0x1f
29921 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK                                              0x00007FFFL
29922 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK                                                         0x00008000L
29923 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK                                              0x7FFF0000L
29924 #define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK                                                         0x80000000L
29925 //DIDT_DBR_EDC_STALL_PATTERN_5_6
29926 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT                                            0x0
29927 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT                                                       0xf
29928 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT                                            0x10
29929 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT                                                       0x1f
29930 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK                                              0x00007FFFL
29931 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK                                                         0x00008000L
29932 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK                                              0x7FFF0000L
29933 #define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK                                                         0x80000000L
29934 //DIDT_DBR_EDC_STALL_PATTERN_7
29935 #define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT                                              0x0
29936 #define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT                                                         0xf
29937 #define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK                                                0x00007FFFL
29938 #define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK                                                           0xFFFF8000L
29939 //DIDT_DBR_EDC_STATUS
29940 #define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT                                                             0x0
29941 #define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT                                                        0x1
29942 #define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT                                                                  0x4
29943 #define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK                                                               0x00000001L
29944 #define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK                                                          0x0000000EL
29945 #define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK                                                                    0xFFFFFFF0L
29946 //DIDT_DBR_EDC_STALL_DELAY_1
29947 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT                                               0x0
29948 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1__SHIFT                                               0x3
29949 #define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT                                                             0x6
29950 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK                                                 0x00000007L
29951 #define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR1_MASK                                                 0x00000038L
29952 #define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK                                                               0xFFFFFFC0L
29953 //DIDT_DBR_EDC_OVERFLOW
29954 #define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT                                        0x0
29955 #define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT                                     0x1
29956 #define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK                                          0x00000001L
29957 #define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK                                       0x0001FFFEL
29958 //DIDT_DBR_EDC_ROLLING_POWER_DELTA
29959 #define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT                                      0x0
29960 #define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK                                        0xFFFFFFFFL
29961 //DIDT_SQ_STALL_EVENT_COUNTER
29962 #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
29963 #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
29964 //DIDT_DB_STALL_EVENT_COUNTER
29965 #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
29966 #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
29967 //DIDT_TD_STALL_EVENT_COUNTER
29968 #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                          0x0
29969 #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                            0xFFFFFFFFL
29970 //DIDT_TCP_STALL_EVENT_COUNTER
29971 #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
29972 #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
29973 //DIDT_DBR_STALL_EVENT_COUNTER
29974 #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
29975 #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
29976 
29977 //TA_EDC_CNT
29978 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT                                                              0x0
29979 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT                                                              0x2
29980 #define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT                                                              0x4
29981 #define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT                                                              0x6
29982 #define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT                                                              0x8
29983 #define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT                                                              0xa
29984 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK                                                                0x00000003L
29985 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK                                                                0x0000000CL
29986 #define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK                                                                0x00000030L
29987 #define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK                                                                0x000000C0L
29988 #define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK                                                                0x00000300L
29989 #define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK                                                                0x00000C00L
29990 
29991 //TCI_EDC_CNT
29992 #define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT                                                               0x0
29993 #define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK                                                                 0x00000003L
29994 
29995 //TCP_EDC_CNT_NEW
29996 #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT                                                           0x0
29997 #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT                                                           0x2
29998 #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT                                                           0x4
29999 #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT                                                           0x6
30000 #define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT                                                            0x8
30001 #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT                                                             0xa
30002 #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT                                                             0xc
30003 #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT                                                              0xe
30004 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT                                                        0x10
30005 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT                                                        0x12
30006 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT                                                        0x14
30007 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT                                                        0x16
30008 #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK                                                             0x00000003L
30009 #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK                                                             0x0000000CL
30010 #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK                                                             0x00000030L
30011 #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK                                                             0x000000C0L
30012 #define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK                                                              0x00000300L
30013 #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK                                                               0x00000C00L
30014 #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK                                                               0x00003000L
30015 #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK                                                                0x0000C000L
30016 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK                                                          0x00030000L
30017 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK                                                          0x000C0000L
30018 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK                                                          0x00300000L
30019 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK                                                          0x00C00000L
30020 
30021 //TD_EDC_CNT
30022 #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT                                                               0x0
30023 #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT                                                               0x2
30024 #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT                                                               0x4
30025 #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT                                                               0x6
30026 #define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT                                                                  0x8
30027 #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK                                                                 0x00000003L
30028 #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK                                                                 0x0000000CL
30029 #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK                                                                 0x00000030L
30030 #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK                                                                 0x000000C0L
30031 #define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK                                                                    0x00000300L
30032 
30033 #endif
30034