1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Microchip KSZ8XXX series register definitions 4 * 5 * The base for these definitions is KSZ8795 but unless indicated 6 * differently by their prefix, they apply to all KSZ8 series 7 * devices. Registers and masks that do change are defined in 8 * dedicated structures in ksz_common.c. 9 * 10 * Copyright (c) 2017 Microchip Technology Inc. 11 * Tristram Ha <Tristram.Ha@microchip.com> 12 */ 13 14 #ifndef __KSZ8_REG_H 15 #define __KSZ8_REG_H 16 17 #define KS_PORT_M 0x1F 18 19 #define KS_PRIO_M 0x3 20 #define KS_PRIO_S 2 21 22 #define SW_REVISION_M 0x0E 23 #define SW_REVISION_S 1 24 25 #define KSZ8863_REG_SW_RESET 0x43 26 27 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4) 28 #define KSZ8863_PCS_RESET BIT(0) 29 30 #define KSZ88X3_REG_FVID_AND_HOST_MODE 0xC6 31 #define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3) 32 33 #define REG_SW_CTRL_0 0x02 34 35 #define SW_NEW_BACKOFF BIT(7) 36 #define SW_GLOBAL_RESET BIT(6) 37 #define SW_FLUSH_DYN_MAC_TABLE BIT(5) 38 #define SW_FLUSH_STA_MAC_TABLE BIT(4) 39 #define SW_LINK_AUTO_AGING BIT(0) 40 41 #define REG_SW_CTRL_1 0x03 42 43 #define SW_HUGE_PACKET BIT(6) 44 #define SW_TX_FLOW_CTRL_DISABLE BIT(5) 45 #define SW_RX_FLOW_CTRL_DISABLE BIT(4) 46 #define SW_CHECK_LENGTH BIT(3) 47 #define SW_AGING_ENABLE BIT(2) 48 #define SW_FAST_AGING BIT(1) 49 #define SW_AGGR_BACKOFF BIT(0) 50 51 #define REG_SW_CTRL_2 0x04 52 53 #define UNICAST_VLAN_BOUNDARY BIT(7) 54 #define SW_BACK_PRESSURE BIT(5) 55 #define FAIR_FLOW_CTRL BIT(4) 56 #define NO_EXC_COLLISION_DROP BIT(3) 57 #define SW_LEGAL_PACKET_DISABLE BIT(1) 58 59 #define KSZ8863_HUGE_PACKET_ENABLE BIT(2) 60 #define KSZ8863_LEGAL_PACKET_ENABLE BIT(1) 61 62 #define REG_SW_CTRL_3 0x05 63 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) 64 65 #define SW_VLAN_ENABLE BIT(7) 66 #define SW_IGMP_SNOOP BIT(6) 67 #define SW_MIRROR_RX_TX BIT(0) 68 69 #define REG_SW_CTRL_4 0x06 70 71 #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7) 72 #define SW_HALF_DUPLEX BIT(6) 73 #define SW_FLOW_CTRL BIT(5) 74 #define SW_10_MBIT BIT(4) 75 #define SW_REPLACE_VID BIT(3) 76 77 #define REG_SW_CTRL_5 0x07 78 79 #define REG_SW_CTRL_6 0x08 80 81 #define SW_MIB_COUNTER_FLUSH BIT(7) 82 #define SW_MIB_COUNTER_FREEZE BIT(6) 83 #define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M 84 85 #define REG_SW_CTRL_9 0x0B 86 87 #define SPI_CLK_125_MHZ 0x80 88 #define SPI_CLK_62_5_MHZ 0x40 89 #define SPI_CLK_31_25_MHZ 0x00 90 91 #define SW_LED_MODE_M 0x3 92 #define SW_LED_MODE_S 4 93 #define SW_LED_LINK_ACT_SPEED 0 94 #define SW_LED_LINK_ACT 1 95 #define SW_LED_LINK_ACT_DUPLEX 2 96 #define SW_LED_LINK_DUPLEX 3 97 98 #define REG_SW_CTRL_10 0x0C 99 100 #define SW_PASS_PAUSE BIT(0) 101 102 #define REG_SW_CTRL_11 0x0D 103 104 #define REG_POWER_MANAGEMENT_1 0x0E 105 106 #define SW_PLL_POWER_DOWN BIT(5) 107 #define SW_POWER_MANAGEMENT_MODE_M 0x3 108 #define SW_POWER_MANAGEMENT_MODE_S 3 109 #define SW_POWER_NORMAL 0 110 #define SW_ENERGY_DETECTION 1 111 #define SW_SOFTWARE_POWER_DOWN 2 112 113 #define REG_POWER_MANAGEMENT_2 0x0F 114 115 #define REG_PORT_1_CTRL_0 0x10 116 #define REG_PORT_2_CTRL_0 0x20 117 #define REG_PORT_3_CTRL_0 0x30 118 #define REG_PORT_4_CTRL_0 0x40 119 #define REG_PORT_5_CTRL_0 0x50 120 121 #define PORT_BROADCAST_STORM BIT(7) 122 #define PORT_DIFFSERV_ENABLE BIT(6) 123 #define PORT_802_1P_ENABLE BIT(5) 124 #define PORT_BASED_PRIO_S 3 125 #define PORT_BASED_PRIO_M KS_PRIO_M 126 #define PORT_BASED_PRIO_0 0 127 #define PORT_BASED_PRIO_1 1 128 #define PORT_BASED_PRIO_2 2 129 #define PORT_BASED_PRIO_3 3 130 #define PORT_INSERT_TAG BIT(2) 131 #define PORT_REMOVE_TAG BIT(1) 132 #define KSZ8795_PORT_2QUEUE_SPLIT_EN BIT(0) 133 #define KSZ8873_PORT_4QUEUE_SPLIT_EN BIT(0) 134 135 #define REG_PORT_1_CTRL_1 0x11 136 #define REG_PORT_2_CTRL_1 0x21 137 #define REG_PORT_3_CTRL_1 0x31 138 #define REG_PORT_4_CTRL_1 0x41 139 #define REG_PORT_5_CTRL_1 0x51 140 141 #define PORT_MIRROR_SNIFFER BIT(7) 142 #define PORT_MIRROR_RX BIT(6) 143 #define PORT_MIRROR_TX BIT(5) 144 #define PORT_VLAN_MEMBERSHIP KS_PORT_M 145 146 #define REG_PORT_1_CTRL_2 0x12 147 #define REG_PORT_2_CTRL_2 0x22 148 #define REG_PORT_3_CTRL_2 0x32 149 #define REG_PORT_4_CTRL_2 0x42 150 #define REG_PORT_5_CTRL_2 0x52 151 152 #define KSZ8873_PORT_2QUEUE_SPLIT_EN BIT(7) 153 #define PORT_INGRESS_FILTER BIT(6) 154 #define PORT_DISCARD_NON_VID BIT(5) 155 #define PORT_FORCE_FLOW_CTRL BIT(4) 156 #define PORT_BACK_PRESSURE BIT(3) 157 158 #define REG_PORT_1_CTRL_3 0x13 159 #define REG_PORT_2_CTRL_3 0x23 160 #define REG_PORT_3_CTRL_3 0x33 161 #define REG_PORT_4_CTRL_3 0x43 162 #define REG_PORT_5_CTRL_3 0x53 163 #define REG_PORT_1_CTRL_4 0x14 164 #define REG_PORT_2_CTRL_4 0x24 165 #define REG_PORT_3_CTRL_4 0x34 166 #define REG_PORT_4_CTRL_4 0x44 167 #define REG_PORT_5_CTRL_4 0x54 168 169 #define PORT_DEFAULT_VID 0x0001 170 171 #define REG_PORT_1_CTRL_5 0x15 172 #define REG_PORT_2_CTRL_5 0x25 173 #define REG_PORT_3_CTRL_5 0x35 174 #define REG_PORT_4_CTRL_5 0x45 175 #define REG_PORT_5_CTRL_5 0x55 176 177 #define PORT_ACL_ENABLE BIT(2) 178 #define PORT_AUTHEN_MODE 0x3 179 #define PORT_AUTHEN_PASS 0 180 #define PORT_AUTHEN_BLOCK 1 181 #define PORT_AUTHEN_TRAP 2 182 183 #define REG_PORT_5_CTRL_6 0x56 184 185 #define PORT_MII_INTERNAL_CLOCK BIT(7) 186 #define PORT_GMII_MAC_MODE BIT(2) 187 188 #define REG_PORT_1_CTRL_7 0x17 189 #define REG_PORT_2_CTRL_7 0x27 190 #define REG_PORT_3_CTRL_7 0x37 191 #define REG_PORT_4_CTRL_7 0x47 192 193 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5) 194 #define PORT_AUTO_NEG_SYM_PAUSE BIT(4) 195 #define PORT_AUTO_NEG_100BTX_FD BIT(3) 196 #define PORT_AUTO_NEG_100BTX BIT(2) 197 #define PORT_AUTO_NEG_10BT_FD BIT(1) 198 #define PORT_AUTO_NEG_10BT BIT(0) 199 200 #define REG_PORT_1_STATUS_0 0x18 201 #define REG_PORT_2_STATUS_0 0x28 202 #define REG_PORT_3_STATUS_0 0x38 203 #define REG_PORT_4_STATUS_0 0x48 204 205 /* For KSZ8765. */ 206 #define PORT_REMOTE_ASYM_PAUSE BIT(5) 207 #define PORT_REMOTE_SYM_PAUSE BIT(4) 208 #define PORT_REMOTE_100BTX_FD BIT(3) 209 #define PORT_REMOTE_100BTX BIT(2) 210 #define PORT_REMOTE_10BT_FD BIT(1) 211 #define PORT_REMOTE_10BT BIT(0) 212 213 #define REG_PORT_1_STATUS_1 0x19 214 #define REG_PORT_2_STATUS_1 0x29 215 #define REG_PORT_3_STATUS_1 0x39 216 #define REG_PORT_4_STATUS_1 0x49 217 218 #define PORT_HP_MDIX BIT(7) 219 #define PORT_REVERSED_POLARITY BIT(5) 220 #define PORT_TX_FLOW_CTRL BIT(4) 221 #define PORT_RX_FLOW_CTRL BIT(3) 222 #define PORT_STAT_SPEED_100MBIT BIT(2) 223 #define PORT_STAT_FULL_DUPLEX BIT(1) 224 225 #define PORT_REMOTE_FAULT BIT(0) 226 227 #define REG_PORT_1_LINK_MD_CTRL 0x1A 228 #define REG_PORT_2_LINK_MD_CTRL 0x2A 229 #define REG_PORT_3_LINK_MD_CTRL 0x3A 230 #define REG_PORT_4_LINK_MD_CTRL 0x4A 231 232 #define PORT_CABLE_10M_SHORT BIT(7) 233 #define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5) 234 #define PORT_CABLE_DIAG_RESULT_S 5 235 #define PORT_CABLE_STAT_NORMAL 0 236 #define PORT_CABLE_STAT_OPEN 1 237 #define PORT_CABLE_STAT_SHORT 2 238 #define PORT_CABLE_STAT_FAILED 3 239 #define PORT_START_CABLE_DIAG BIT(4) 240 #define PORT_FORCE_LINK BIT(3) 241 #define PORT_POWER_SAVING BIT(2) 242 #define PORT_PHY_REMOTE_LOOPBACK BIT(1) 243 #define PORT_CABLE_FAULT_COUNTER_H 0x01 244 245 #define REG_PORT_1_LINK_MD_RESULT 0x1B 246 #define REG_PORT_2_LINK_MD_RESULT 0x2B 247 #define REG_PORT_3_LINK_MD_RESULT 0x3B 248 #define REG_PORT_4_LINK_MD_RESULT 0x4B 249 250 #define PORT_CABLE_FAULT_COUNTER_L 0xFF 251 #define PORT_CABLE_FAULT_COUNTER 0x1FF 252 253 #define REG_PORT_1_CTRL_9 0x1C 254 #define REG_PORT_2_CTRL_9 0x2C 255 #define REG_PORT_3_CTRL_9 0x3C 256 #define REG_PORT_4_CTRL_9 0x4C 257 258 #define PORT_AUTO_NEG_ENABLE BIT(7) 259 #define PORT_AUTO_NEG_DISABLE BIT(7) 260 #define PORT_FORCE_100_MBIT BIT(6) 261 #define PORT_FORCE_FULL_DUPLEX BIT(5) 262 263 #define REG_PORT_1_CTRL_10 0x1D 264 #define REG_PORT_2_CTRL_10 0x2D 265 #define REG_PORT_3_CTRL_10 0x3D 266 #define REG_PORT_4_CTRL_10 0x4D 267 268 #define PORT_LED_OFF BIT(7) 269 #define PORT_TX_DISABLE BIT(6) 270 #define PORT_AUTO_NEG_RESTART BIT(5) 271 #define PORT_POWER_DOWN BIT(3) 272 #define PORT_AUTO_MDIX_DISABLE BIT(2) 273 #define PORT_FORCE_MDIX BIT(1) 274 #define PORT_MAC_LOOPBACK BIT(0) 275 #define KSZ8873_PORT_PHY_LOOPBACK BIT(0) 276 277 #define REG_PORT_1_STATUS_2 0x1E 278 #define REG_PORT_2_STATUS_2 0x2E 279 #define REG_PORT_3_STATUS_2 0x3E 280 #define REG_PORT_4_STATUS_2 0x4E 281 282 #define PORT_MDIX_STATUS BIT(7) 283 #define PORT_AUTO_NEG_COMPLETE BIT(6) 284 #define PORT_STAT_LINK_GOOD BIT(5) 285 286 #define REG_PORT_1_STATUS_3 0x1F 287 #define REG_PORT_2_STATUS_3 0x2F 288 #define REG_PORT_3_STATUS_3 0x3F 289 #define REG_PORT_4_STATUS_3 0x4F 290 291 #define PORT_PHY_LOOPBACK BIT(7) 292 #define PORT_PHY_ISOLATE BIT(5) 293 #define PORT_PHY_SOFT_RESET BIT(4) 294 #define PORT_PHY_FORCE_LINK BIT(3) 295 #define PORT_PHY_MODE_M 0x7 296 #define PHY_MODE_IN_AUTO_NEG 1 297 #define PHY_MODE_10BT_HALF 2 298 #define PHY_MODE_100BT_HALF 3 299 #define PHY_MODE_10BT_FULL 5 300 #define PHY_MODE_100BT_FULL 6 301 #define PHY_MODE_ISOLDATE 7 302 303 #define REG_PORT_CTRL_0 0x00 304 #define REG_PORT_CTRL_1 0x01 305 #define REG_PORT_CTRL_2 0x02 306 #define REG_PORT_CTRL_VID 0x03 307 308 #define REG_PORT_CTRL_5 0x05 309 310 #define REG_PORT_STATUS_1 0x09 311 #define REG_PORT_LINK_MD_CTRL 0x0A 312 #define REG_PORT_LINK_MD_RESULT 0x0B 313 #define REG_PORT_CTRL_9 0x0C 314 #define REG_PORT_CTRL_10 0x0D 315 #define REG_PORT_STATUS_3 0x0F 316 317 #define REG_PORT_CTRL_12 0xA0 318 #define REG_PORT_CTRL_13 0xA1 319 #define REG_PORT_RATE_CTRL_3 0xA2 320 #define REG_PORT_RATE_CTRL_2 0xA3 321 #define REG_PORT_RATE_CTRL_1 0xA4 322 #define REG_PORT_RATE_CTRL_0 0xA5 323 #define REG_PORT_RATE_LIMIT 0xA6 324 #define REG_PORT_IN_RATE_0 0xA7 325 #define REG_PORT_IN_RATE_1 0xA8 326 #define REG_PORT_IN_RATE_2 0xA9 327 #define REG_PORT_IN_RATE_3 0xAA 328 #define REG_PORT_OUT_RATE_0 0xAB 329 #define REG_PORT_OUT_RATE_1 0xAC 330 #define REG_PORT_OUT_RATE_2 0xAD 331 #define REG_PORT_OUT_RATE_3 0xAE 332 333 #define PORT_CTRL_ADDR(port, addr) \ 334 ((addr) + REG_PORT_1_CTRL_0 + (port) * \ 335 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0)) 336 337 #define TABLE_EXT_SELECT_S 5 338 #define TABLE_EEE_V 1 339 #define TABLE_ACL_V 2 340 #define TABLE_PME_V 4 341 #define TABLE_LINK_MD_V 5 342 #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S) 343 #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S) 344 #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S) 345 #define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S) 346 #define TABLE_READ BIT(4) 347 #define TABLE_SELECT_S 2 348 #define TABLE_STATIC_MAC_V 0 349 #define TABLE_VLAN_V 1 350 #define TABLE_DYNAMIC_MAC_V 2 351 #define TABLE_MIB_V 3 352 #define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S) 353 #define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S) 354 #define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S) 355 #define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S) 356 357 #define REG_IND_CTRL_1 0x6F 358 359 #define TABLE_ENTRY_MASK 0x03FF 360 #define TABLE_EXT_ENTRY_MASK 0x0FFF 361 362 #define REG_IND_DATA_5 0x73 363 #define REG_IND_DATA_2 0x76 364 #define REG_IND_DATA_1 0x77 365 #define REG_IND_DATA_0 0x78 366 367 #define REG_INT_STATUS 0x7C 368 #define REG_INT_ENABLE 0x7D 369 370 #define INT_PME BIT(4) 371 372 #define REG_ACL_INT_STATUS 0x7E 373 #define REG_ACL_INT_ENABLE 0x7F 374 375 #define INT_PORT_5 BIT(4) 376 #define INT_PORT_4 BIT(3) 377 #define INT_PORT_3 BIT(2) 378 #define INT_PORT_2 BIT(1) 379 #define INT_PORT_1 BIT(0) 380 381 #define INT_PORT_ALL \ 382 (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1) 383 384 #define REG_SW_CTRL_12 0x80 385 #define REG_SW_CTRL_13 0x81 386 387 #define SWITCH_802_1P_MASK 3 388 #define SWITCH_802_1P_BASE 3 389 #define SWITCH_802_1P_SHIFT 2 390 391 #define SW_802_1P_MAP_M KS_PRIO_M 392 #define SW_802_1P_MAP_S KS_PRIO_S 393 394 #define REG_SWITCH_CTRL_14 0x82 395 396 #define SW_PRIO_MAPPING_M KS_PRIO_M 397 #define SW_PRIO_MAPPING_S 6 398 #define SW_PRIO_MAP_3_HI 0 399 #define SW_PRIO_MAP_2_HI 2 400 #define SW_PRIO_MAP_0_LO 3 401 402 #define REG_SW_CTRL_15 0x83 403 #define REG_SW_CTRL_16 0x84 404 #define REG_SW_CTRL_17 0x85 405 #define REG_SW_CTRL_18 0x86 406 407 #define SW_SELF_ADDR_FILTER_ENABLE BIT(6) 408 409 #define REG_SW_UNK_UCAST_CTRL 0x83 410 #define REG_SW_UNK_MCAST_CTRL 0x84 411 #define REG_SW_UNK_VID_CTRL 0x85 412 #define REG_SW_UNK_IP_MCAST_CTRL 0x86 413 414 #define SW_UNK_FWD_ENABLE BIT(5) 415 #define SW_UNK_FWD_MAP KS_PORT_M 416 417 #define REG_SW_CTRL_19 0x87 418 419 #define SW_IN_RATE_LIMIT_PERIOD_M 0x3 420 #define SW_IN_RATE_LIMIT_PERIOD_S 4 421 #define SW_IN_RATE_LIMIT_16_MS 0 422 #define SW_IN_RATE_LIMIT_64_MS 1 423 #define SW_IN_RATE_LIMIT_256_MS 2 424 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) 425 #define SW_INS_TAG_ENABLE BIT(2) 426 427 #define REG_TOS_PRIO_CTRL_0 0x90 428 #define REG_TOS_PRIO_CTRL_1 0x91 429 #define REG_TOS_PRIO_CTRL_2 0x92 430 #define REG_TOS_PRIO_CTRL_3 0x93 431 #define REG_TOS_PRIO_CTRL_4 0x94 432 #define REG_TOS_PRIO_CTRL_5 0x95 433 #define REG_TOS_PRIO_CTRL_6 0x96 434 #define REG_TOS_PRIO_CTRL_7 0x97 435 #define REG_TOS_PRIO_CTRL_8 0x98 436 #define REG_TOS_PRIO_CTRL_9 0x99 437 #define REG_TOS_PRIO_CTRL_10 0x9A 438 #define REG_TOS_PRIO_CTRL_11 0x9B 439 #define REG_TOS_PRIO_CTRL_12 0x9C 440 #define REG_TOS_PRIO_CTRL_13 0x9D 441 #define REG_TOS_PRIO_CTRL_14 0x9E 442 #define REG_TOS_PRIO_CTRL_15 0x9F 443 444 #define TOS_PRIO_M KS_PRIO_M 445 #define TOS_PRIO_S KS_PRIO_S 446 447 #define REG_SW_CTRL_21 0xA4 448 449 #define SW_IPV6_MLD_OPTION BIT(3) 450 #define SW_IPV6_MLD_SNOOP BIT(2) 451 452 #define REG_PORT_1_CTRL_12 0xB0 453 #define REG_PORT_2_CTRL_12 0xC0 454 #define REG_PORT_3_CTRL_12 0xD0 455 #define REG_PORT_4_CTRL_12 0xE0 456 #define REG_PORT_5_CTRL_12 0xF0 457 458 #define PORT_PASS_ALL BIT(6) 459 #define PORT_INS_TAG_FOR_PORT_5_S 3 460 #define PORT_INS_TAG_FOR_PORT_5 BIT(3) 461 #define PORT_INS_TAG_FOR_PORT_4 BIT(2) 462 #define PORT_INS_TAG_FOR_PORT_3 BIT(1) 463 #define PORT_INS_TAG_FOR_PORT_2 BIT(0) 464 465 #define REG_PORT_1_CTRL_13 0xB1 466 #define REG_PORT_2_CTRL_13 0xC1 467 #define REG_PORT_3_CTRL_13 0xD1 468 #define REG_PORT_4_CTRL_13 0xE1 469 #define REG_PORT_5_CTRL_13 0xF1 470 471 #define KSZ8795_PORT_4QUEUE_SPLIT_EN BIT(1) 472 #define PORT_DROP_TAG BIT(0) 473 474 #define REG_PORT_1_CTRL_14 0xB2 475 #define REG_PORT_2_CTRL_14 0xC2 476 #define REG_PORT_3_CTRL_14 0xD2 477 #define REG_PORT_4_CTRL_14 0xE2 478 #define REG_PORT_5_CTRL_14 0xF2 479 #define REG_PORT_1_CTRL_15 0xB3 480 #define REG_PORT_2_CTRL_15 0xC3 481 #define REG_PORT_3_CTRL_15 0xD3 482 #define REG_PORT_4_CTRL_15 0xE3 483 #define REG_PORT_5_CTRL_15 0xF3 484 #define REG_PORT_1_CTRL_16 0xB4 485 #define REG_PORT_2_CTRL_16 0xC4 486 #define REG_PORT_3_CTRL_16 0xD4 487 #define REG_PORT_4_CTRL_16 0xE4 488 #define REG_PORT_5_CTRL_16 0xF4 489 #define REG_PORT_1_CTRL_17 0xB5 490 #define REG_PORT_2_CTRL_17 0xC5 491 #define REG_PORT_3_CTRL_17 0xD5 492 #define REG_PORT_4_CTRL_17 0xE5 493 #define REG_PORT_5_CTRL_17 0xF5 494 495 #define REG_PORT_1_RATE_CTRL_3 0xB2 496 #define REG_PORT_1_RATE_CTRL_2 0xB3 497 #define REG_PORT_1_RATE_CTRL_1 0xB4 498 #define REG_PORT_1_RATE_CTRL_0 0xB5 499 #define REG_PORT_2_RATE_CTRL_3 0xC2 500 #define REG_PORT_2_RATE_CTRL_2 0xC3 501 #define REG_PORT_2_RATE_CTRL_1 0xC4 502 #define REG_PORT_2_RATE_CTRL_0 0xC5 503 #define REG_PORT_3_RATE_CTRL_3 0xD2 504 #define REG_PORT_3_RATE_CTRL_2 0xD3 505 #define REG_PORT_3_RATE_CTRL_1 0xD4 506 #define REG_PORT_3_RATE_CTRL_0 0xD5 507 #define REG_PORT_4_RATE_CTRL_3 0xE2 508 #define REG_PORT_4_RATE_CTRL_2 0xE3 509 #define REG_PORT_4_RATE_CTRL_1 0xE4 510 #define REG_PORT_4_RATE_CTRL_0 0xE5 511 #define REG_PORT_5_RATE_CTRL_3 0xF2 512 #define REG_PORT_5_RATE_CTRL_2 0xF3 513 #define REG_PORT_5_RATE_CTRL_1 0xF4 514 #define REG_PORT_5_RATE_CTRL_0 0xF5 515 516 #define RATE_CTRL_ENABLE BIT(7) 517 #define RATE_RATIO_M (BIT(7) - 1) 518 519 #define PORT_OUT_RATE_ENABLE BIT(7) 520 521 #define REG_PORT_1_RATE_LIMIT 0xB6 522 #define REG_PORT_2_RATE_LIMIT 0xC6 523 #define REG_PORT_3_RATE_LIMIT 0xD6 524 #define REG_PORT_4_RATE_LIMIT 0xE6 525 #define REG_PORT_5_RATE_LIMIT 0xF6 526 527 #define PORT_IN_PORT_BASED_S 6 528 #define PORT_RATE_PACKET_BASED_S 5 529 #define PORT_IN_FLOW_CTRL_S 4 530 #define PORT_IN_LIMIT_MODE_M 0x3 531 #define PORT_IN_LIMIT_MODE_S 2 532 #define PORT_COUNT_IFG_S 1 533 #define PORT_COUNT_PREAMBLE_S 0 534 #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S) 535 #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S) 536 #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S) 537 #define PORT_IN_ALL 0 538 #define PORT_IN_UNICAST 1 539 #define PORT_IN_MULTICAST 2 540 #define PORT_IN_BROADCAST 3 541 #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S) 542 #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S) 543 544 #define REG_PORT_1_IN_RATE_0 0xB7 545 #define REG_PORT_2_IN_RATE_0 0xC7 546 #define REG_PORT_3_IN_RATE_0 0xD7 547 #define REG_PORT_4_IN_RATE_0 0xE7 548 #define REG_PORT_5_IN_RATE_0 0xF7 549 #define REG_PORT_1_IN_RATE_1 0xB8 550 #define REG_PORT_2_IN_RATE_1 0xC8 551 #define REG_PORT_3_IN_RATE_1 0xD8 552 #define REG_PORT_4_IN_RATE_1 0xE8 553 #define REG_PORT_5_IN_RATE_1 0xF8 554 #define REG_PORT_1_IN_RATE_2 0xB9 555 #define REG_PORT_2_IN_RATE_2 0xC9 556 #define REG_PORT_3_IN_RATE_2 0xD9 557 #define REG_PORT_4_IN_RATE_2 0xE9 558 #define REG_PORT_5_IN_RATE_2 0xF9 559 #define REG_PORT_1_IN_RATE_3 0xBA 560 #define REG_PORT_2_IN_RATE_3 0xCA 561 #define REG_PORT_3_IN_RATE_3 0xDA 562 #define REG_PORT_4_IN_RATE_3 0xEA 563 #define REG_PORT_5_IN_RATE_3 0xFA 564 565 #define PORT_IN_RATE_ENABLE BIT(7) 566 #define PORT_RATE_LIMIT_M (BIT(7) - 1) 567 568 #define REG_PORT_1_OUT_RATE_0 0xBB 569 #define REG_PORT_2_OUT_RATE_0 0xCB 570 #define REG_PORT_3_OUT_RATE_0 0xDB 571 #define REG_PORT_4_OUT_RATE_0 0xEB 572 #define REG_PORT_5_OUT_RATE_0 0xFB 573 #define REG_PORT_1_OUT_RATE_1 0xBC 574 #define REG_PORT_2_OUT_RATE_1 0xCC 575 #define REG_PORT_3_OUT_RATE_1 0xDC 576 #define REG_PORT_4_OUT_RATE_1 0xEC 577 #define REG_PORT_5_OUT_RATE_1 0xFC 578 #define REG_PORT_1_OUT_RATE_2 0xBD 579 #define REG_PORT_2_OUT_RATE_2 0xCD 580 #define REG_PORT_3_OUT_RATE_2 0xDD 581 #define REG_PORT_4_OUT_RATE_2 0xED 582 #define REG_PORT_5_OUT_RATE_2 0xFD 583 #define REG_PORT_1_OUT_RATE_3 0xBE 584 #define REG_PORT_2_OUT_RATE_3 0xCE 585 #define REG_PORT_3_OUT_RATE_3 0xDE 586 #define REG_PORT_4_OUT_RATE_3 0xEE 587 #define REG_PORT_5_OUT_RATE_3 0xFE 588 589 /* 88x3 specific */ 590 591 #define REG_SW_INSERT_SRC_PVID 0xC2 592 593 /* PME */ 594 595 #define SW_PME_OUTPUT_ENABLE BIT(1) 596 #define SW_PME_ACTIVE_HIGH BIT(0) 597 598 #define PORT_MAGIC_PACKET_DETECT BIT(2) 599 #define PORT_LINK_UP_DETECT BIT(1) 600 #define PORT_ENERGY_DETECT BIT(0) 601 602 /* ACL */ 603 604 #define ACL_FIRST_RULE_M 0xF 605 606 #define ACL_MODE_M 0x3 607 #define ACL_MODE_S 4 608 #define ACL_MODE_DISABLE 0 609 #define ACL_MODE_LAYER_2 1 610 #define ACL_MODE_LAYER_3 2 611 #define ACL_MODE_LAYER_4 3 612 #define ACL_ENABLE_M 0x3 613 #define ACL_ENABLE_S 2 614 #define ACL_ENABLE_2_COUNT 0 615 #define ACL_ENABLE_2_TYPE 1 616 #define ACL_ENABLE_2_MAC 2 617 #define ACL_ENABLE_2_BOTH 3 618 #define ACL_ENABLE_3_IP 1 619 #define ACL_ENABLE_3_SRC_DST_COMP 2 620 #define ACL_ENABLE_4_PROTOCOL 0 621 #define ACL_ENABLE_4_TCP_PORT_COMP 1 622 #define ACL_ENABLE_4_UDP_PORT_COMP 2 623 #define ACL_ENABLE_4_TCP_SEQN_COMP 3 624 #define ACL_SRC BIT(1) 625 #define ACL_EQUAL BIT(0) 626 627 #define ACL_MAX_PORT 0xFFFF 628 629 #define ACL_MIN_PORT 0xFFFF 630 #define ACL_IP_ADDR 0xFFFFFFFF 631 #define ACL_TCP_SEQNUM 0xFFFFFFFF 632 633 #define ACL_RESERVED 0xF8 634 #define ACL_PORT_MODE_M 0x3 635 #define ACL_PORT_MODE_S 1 636 #define ACL_PORT_MODE_DISABLE 0 637 #define ACL_PORT_MODE_EITHER 1 638 #define ACL_PORT_MODE_IN_RANGE 2 639 #define ACL_PORT_MODE_OUT_OF_RANGE 3 640 641 #define ACL_TCP_FLAG_ENABLE BIT(0) 642 643 #define ACL_TCP_FLAG_M 0xFF 644 645 #define ACL_TCP_FLAG 0xFF 646 #define ACL_ETH_TYPE 0xFFFF 647 #define ACL_IP_M 0xFFFFFFFF 648 649 #define ACL_PRIO_MODE_M 0x3 650 #define ACL_PRIO_MODE_S 6 651 #define ACL_PRIO_MODE_DISABLE 0 652 #define ACL_PRIO_MODE_HIGHER 1 653 #define ACL_PRIO_MODE_LOWER 2 654 #define ACL_PRIO_MODE_REPLACE 3 655 #define ACL_PRIO_M 0x7 656 #define ACL_PRIO_S 3 657 #define ACL_VLAN_PRIO_REPLACE BIT(2) 658 #define ACL_VLAN_PRIO_M 0x7 659 #define ACL_VLAN_PRIO_HI_M 0x3 660 661 #define ACL_VLAN_PRIO_LO_M 0x8 662 #define ACL_VLAN_PRIO_S 7 663 #define ACL_MAP_MODE_M 0x3 664 #define ACL_MAP_MODE_S 5 665 #define ACL_MAP_MODE_DISABLE 0 666 #define ACL_MAP_MODE_OR 1 667 #define ACL_MAP_MODE_AND 2 668 #define ACL_MAP_MODE_REPLACE 3 669 #define ACL_MAP_PORT_M 0x1F 670 671 #define ACL_CNT_M (BIT(11) - 1) 672 #define ACL_CNT_S 5 673 #define ACL_MSEC_UNIT BIT(4) 674 #define ACL_INTR_MODE BIT(3) 675 676 #define REG_PORT_ACL_BYTE_EN_MSB 0x10 677 678 #define ACL_BYTE_EN_MSB_M 0x3F 679 680 #define REG_PORT_ACL_BYTE_EN_LSB 0x11 681 682 #define ACL_ACTION_START 0xA 683 #define ACL_ACTION_LEN 2 684 #define ACL_INTR_CNT_START 0xB 685 #define ACL_RULESET_START 0xC 686 #define ACL_RULESET_LEN 2 687 #define ACL_TABLE_LEN 14 688 689 #define ACL_ACTION_ENABLE 0x000C 690 #define ACL_MATCH_ENABLE 0x1FF0 691 #define ACL_RULESET_ENABLE 0x2003 692 #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF) 693 #define ACL_MODE_ENABLE (0x10 << 8) 694 695 #define REG_PORT_ACL_CTRL_0 0x12 696 697 #define PORT_ACL_WRITE_DONE BIT(6) 698 #define PORT_ACL_READ_DONE BIT(5) 699 #define PORT_ACL_WRITE BIT(4) 700 #define PORT_ACL_INDEX_M 0xF 701 702 #define REG_PORT_ACL_CTRL_1 0x13 703 704 #define PORT_ACL_FORCE_DLR_MISS BIT(0) 705 706 #define KSZ8795_ID_HI 0x0022 707 #define KSZ8795_ID_LO 0x1550 708 #define KSZ8863_ID_LO 0x1430 709 710 #define PHY_REG_LINK_MD 0x1D 711 712 #define PHY_START_CABLE_DIAG BIT(15) 713 #define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13) 714 #define PHY_CABLE_DIAG_RESULT 0x6000 715 #define PHY_CABLE_STAT_NORMAL 0x0000 716 #define PHY_CABLE_STAT_OPEN 0x2000 717 #define PHY_CABLE_STAT_SHORT 0x4000 718 #define PHY_CABLE_STAT_FAILED 0x6000 719 #define PHY_CABLE_10M_SHORT BIT(12) 720 #define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0) 721 722 #define PHY_REG_PHY_CTRL 0x1F 723 724 #define PHY_MODE_M 0x7 725 #define PHY_MODE_S 8 726 #define PHY_STAT_REVERSED_POLARITY BIT(5) 727 #define PHY_STAT_MDIX BIT(4) 728 #define PHY_FORCE_LINK BIT(3) 729 #define PHY_POWER_SAVING_ENABLE BIT(2) 730 #define PHY_REMOTE_LOOPBACK BIT(1) 731 732 /* Chip resource */ 733 734 #define PRIO_QUEUES 4 735 736 #define KS_PRIO_IN_REG 4 737 738 #define MIB_COUNTER_NUM 0x20 739 740 /* Common names used by other drivers */ 741 742 #define P_BCAST_STORM_CTRL REG_PORT_CTRL_0 743 #define P_PRIO_CTRL REG_PORT_CTRL_0 744 #define P_TAG_CTRL REG_PORT_CTRL_0 745 #define P_MIRROR_CTRL REG_PORT_CTRL_1 746 #define P_802_1P_CTRL REG_PORT_CTRL_2 747 #define P_PASS_ALL_CTRL REG_PORT_CTRL_12 748 #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12 749 #define P_DROP_TAG_CTRL REG_PORT_CTRL_13 750 #define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT 751 752 #define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12 753 #define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID 754 755 #define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0 756 #define S_LINK_AGING_CTRL REG_SW_CTRL_0 757 #define S_HUGE_PACKET_CTRL REG_SW_CTRL_1 758 #define S_MIRROR_CTRL REG_SW_CTRL_3 759 #define S_REPLACE_VID_CTRL REG_SW_CTRL_4 760 #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10 761 #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12 762 #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0 763 #define S_IPV6_MLD_CTRL REG_SW_CTRL_21 764 765 #define IND_ACC_TABLE(table) ((table) << 8) 766 767 /* */ 768 #define REG_IND_EEE_GLOB2_LO 0x34 769 #define REG_IND_EEE_GLOB2_HI 0x35 770 771 /** 772 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF 773 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF 774 * MIB_PACKET_DROPPED 00-00000000-0000FFFF 775 * MIB_COUNTER_VALID 00-00000020-00000000 776 * MIB_COUNTER_OVERFLOW 00-00000040-00000000 777 */ 778 779 #define MIB_COUNTER_VALUE 0x3FFFFFFF 780 781 #define KSZ8795_MIB_TOTAL_RX_0 0x100 782 #define KSZ8795_MIB_TOTAL_TX_0 0x101 783 #define KSZ8795_MIB_TOTAL_RX_1 0x104 784 #define KSZ8795_MIB_TOTAL_TX_1 0x105 785 786 #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100 787 #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105 788 789 #define MIB_PACKET_DROPPED 0x0000FFFF 790 791 #define MIB_TOTAL_BYTES_H 0x0000000F 792 793 #define TAIL_TAG_OVERRIDE BIT(6) 794 #define TAIL_TAG_LOOKUP BIT(7) 795 796 #define FID_ENTRIES 128 797 #define KSZ8_DYN_MAC_ENTRIES 1024 798 799 #endif 800