xref: /linux/drivers/net/can/sun4i_can.c (revision 9410645520e9b820069761f3450ef6661418e279)
1 /*
2  * sun4i_can.c - CAN bus controller driver for Allwinner SUN4I&SUN7I based SoCs
3  *
4  * Copyright (C) 2013 Peter Chen
5  * Copyright (C) 2015 Gerhard Bertelsmann
6  * All rights reserved.
7  *
8  * Parts of this software are based on (derived from) the SJA1000 code by:
9  *   Copyright (C) 2014 Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
10  *   Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
11  *   Copyright (C) 2002-2007 Volkswagen Group Electronic Research
12  *   Copyright (C) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
13  *   38106 Braunschweig, GERMANY
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions
17  * are met:
18  * 1. Redistributions of source code must retain the above copyright
19  *    notice, this list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright
21  *    notice, this list of conditions and the following disclaimer in the
22  *    documentation and/or other materials provided with the distribution.
23  * 3. Neither the name of Volkswagen nor the names of its contributors
24  *    may be used to endorse or promote products derived from this software
25  *    without specific prior written permission.
26  *
27  * Alternatively, provided that this notice is retained in full, this
28  * software may be distributed under the terms of the GNU General
29  * Public License ("GPL") version 2, in which case the provisions of the
30  * GPL apply INSTEAD OF those given above.
31  *
32  * The provided data structures and external interfaces from this code
33  * are not restricted to be used by modules with a GPL compatible license.
34  *
35  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46  * DAMAGE.
47  *
48  */
49 
50 #include <linux/netdevice.h>
51 #include <linux/can.h>
52 #include <linux/can/dev.h>
53 #include <linux/can/error.h>
54 #include <linux/clk.h>
55 #include <linux/delay.h>
56 #include <linux/ethtool.h>
57 #include <linux/interrupt.h>
58 #include <linux/init.h>
59 #include <linux/io.h>
60 #include <linux/module.h>
61 #include <linux/of.h>
62 #include <linux/platform_device.h>
63 #include <linux/reset.h>
64 
65 #define DRV_NAME "sun4i_can"
66 
67 /* Registers address (physical base address 0x01C2BC00) */
68 #define SUN4I_REG_MSEL_ADDR	0x0000	/* CAN Mode Select */
69 #define SUN4I_REG_CMD_ADDR	0x0004	/* CAN Command */
70 #define SUN4I_REG_STA_ADDR	0x0008	/* CAN Status */
71 #define SUN4I_REG_INT_ADDR	0x000c	/* CAN Interrupt Flag */
72 #define SUN4I_REG_INTEN_ADDR	0x0010	/* CAN Interrupt Enable */
73 #define SUN4I_REG_BTIME_ADDR	0x0014	/* CAN Bus Timing 0 */
74 #define SUN4I_REG_TEWL_ADDR	0x0018	/* CAN Tx Error Warning Limit */
75 #define SUN4I_REG_ERRC_ADDR	0x001c	/* CAN Error Counter */
76 #define SUN4I_REG_RMCNT_ADDR	0x0020	/* CAN Receive Message Counter */
77 #define SUN4I_REG_RBUFSA_ADDR	0x0024	/* CAN Receive Buffer Start Address */
78 #define SUN4I_REG_BUF0_ADDR	0x0040	/* CAN Tx/Rx Buffer 0 */
79 #define SUN4I_REG_BUF1_ADDR	0x0044	/* CAN Tx/Rx Buffer 1 */
80 #define SUN4I_REG_BUF2_ADDR	0x0048	/* CAN Tx/Rx Buffer 2 */
81 #define SUN4I_REG_BUF3_ADDR	0x004c	/* CAN Tx/Rx Buffer 3 */
82 #define SUN4I_REG_BUF4_ADDR	0x0050	/* CAN Tx/Rx Buffer 4 */
83 #define SUN4I_REG_BUF5_ADDR	0x0054	/* CAN Tx/Rx Buffer 5 */
84 #define SUN4I_REG_BUF6_ADDR	0x0058	/* CAN Tx/Rx Buffer 6 */
85 #define SUN4I_REG_BUF7_ADDR	0x005c	/* CAN Tx/Rx Buffer 7 */
86 #define SUN4I_REG_BUF8_ADDR	0x0060	/* CAN Tx/Rx Buffer 8 */
87 #define SUN4I_REG_BUF9_ADDR	0x0064	/* CAN Tx/Rx Buffer 9 */
88 #define SUN4I_REG_BUF10_ADDR	0x0068	/* CAN Tx/Rx Buffer 10 */
89 #define SUN4I_REG_BUF11_ADDR	0x006c	/* CAN Tx/Rx Buffer 11 */
90 #define SUN4I_REG_BUF12_ADDR	0x0070	/* CAN Tx/Rx Buffer 12 */
91 #define SUN4I_REG_ACPC_ADDR	0x0040	/* CAN Acceptance Code 0 */
92 #define SUN4I_REG_ACPM_ADDR	0x0044	/* CAN Acceptance Mask 0 */
93 #define SUN4I_REG_ACPC_ADDR_D1	0x0028	/* CAN Acceptance Code 0 on the D1 */
94 #define SUN4I_REG_ACPM_ADDR_D1	0x002C	/* CAN Acceptance Mask 0 on the D1 */
95 #define SUN4I_REG_RBUF_RBACK_START_ADDR	0x0180	/* CAN transmit buffer start */
96 #define SUN4I_REG_RBUF_RBACK_END_ADDR	0x01b0	/* CAN transmit buffer end */
97 
98 /* Controller Register Description */
99 
100 /* mode select register (r/w)
101  * offset:0x0000 default:0x0000_0001
102  */
103 #define SUN4I_MSEL_SLEEP_MODE		(0x01 << 4) /* write in reset mode */
104 #define SUN4I_MSEL_WAKE_UP		(0x00 << 4)
105 #define SUN4I_MSEL_SINGLE_FILTER	(0x01 << 3) /* write in reset mode */
106 #define SUN4I_MSEL_DUAL_FILTERS		(0x00 << 3)
107 #define SUN4I_MSEL_LOOPBACK_MODE	BIT(2)
108 #define SUN4I_MSEL_LISTEN_ONLY_MODE	BIT(1)
109 #define SUN4I_MSEL_RESET_MODE		BIT(0)
110 
111 /* command register (w)
112  * offset:0x0004 default:0x0000_0000
113  */
114 #define SUN4I_CMD_BUS_OFF_REQ	BIT(5)
115 #define SUN4I_CMD_SELF_RCV_REQ	BIT(4)
116 #define SUN4I_CMD_CLEAR_OR_FLAG	BIT(3)
117 #define SUN4I_CMD_RELEASE_RBUF	BIT(2)
118 #define SUN4I_CMD_ABORT_REQ	BIT(1)
119 #define SUN4I_CMD_TRANS_REQ	BIT(0)
120 
121 /* status register (r)
122  * offset:0x0008 default:0x0000_003c
123  */
124 #define SUN4I_STA_BIT_ERR	(0x00 << 22)
125 #define SUN4I_STA_FORM_ERR	(0x01 << 22)
126 #define SUN4I_STA_STUFF_ERR	(0x02 << 22)
127 #define SUN4I_STA_OTHER_ERR	(0x03 << 22)
128 #define SUN4I_STA_MASK_ERR	(0x03 << 22)
129 #define SUN4I_STA_ERR_DIR	BIT(21)
130 #define SUN4I_STA_ERR_SEG_CODE	(0x1f << 16)
131 #define SUN4I_STA_START		(0x03 << 16)
132 #define SUN4I_STA_ID28_21	(0x02 << 16)
133 #define SUN4I_STA_ID20_18	(0x06 << 16)
134 #define SUN4I_STA_SRTR		(0x04 << 16)
135 #define SUN4I_STA_IDE		(0x05 << 16)
136 #define SUN4I_STA_ID17_13	(0x07 << 16)
137 #define SUN4I_STA_ID12_5	(0x0f << 16)
138 #define SUN4I_STA_ID4_0		(0x0e << 16)
139 #define SUN4I_STA_RTR		(0x0c << 16)
140 #define SUN4I_STA_RB1		(0x0d << 16)
141 #define SUN4I_STA_RB0		(0x09 << 16)
142 #define SUN4I_STA_DLEN		(0x0b << 16)
143 #define SUN4I_STA_DATA_FIELD	(0x0a << 16)
144 #define SUN4I_STA_CRC_SEQUENCE	(0x08 << 16)
145 #define SUN4I_STA_CRC_DELIMITER	(0x18 << 16)
146 #define SUN4I_STA_ACK		(0x19 << 16)
147 #define SUN4I_STA_ACK_DELIMITER	(0x1b << 16)
148 #define SUN4I_STA_END		(0x1a << 16)
149 #define SUN4I_STA_INTERMISSION	(0x12 << 16)
150 #define SUN4I_STA_ACTIVE_ERROR	(0x11 << 16)
151 #define SUN4I_STA_PASSIVE_ERROR	(0x16 << 16)
152 #define SUN4I_STA_TOLERATE_DOMINANT_BITS	(0x13 << 16)
153 #define SUN4I_STA_ERROR_DELIMITER	(0x17 << 16)
154 #define SUN4I_STA_OVERLOAD	(0x1c << 16)
155 #define SUN4I_STA_BUS_OFF	BIT(7)
156 #define SUN4I_STA_ERR_STA	BIT(6)
157 #define SUN4I_STA_TRANS_BUSY	BIT(5)
158 #define SUN4I_STA_RCV_BUSY	BIT(4)
159 #define SUN4I_STA_TRANS_OVER	BIT(3)
160 #define SUN4I_STA_TBUF_RDY	BIT(2)
161 #define SUN4I_STA_DATA_ORUN	BIT(1)
162 #define SUN4I_STA_RBUF_RDY	BIT(0)
163 
164 /* interrupt register (r)
165  * offset:0x000c default:0x0000_0000
166  */
167 #define SUN4I_INT_BUS_ERR	BIT(7)
168 #define SUN4I_INT_ARB_LOST	BIT(6)
169 #define SUN4I_INT_ERR_PASSIVE	BIT(5)
170 #define SUN4I_INT_WAKEUP	BIT(4)
171 #define SUN4I_INT_DATA_OR	BIT(3)
172 #define SUN4I_INT_ERR_WRN	BIT(2)
173 #define SUN4I_INT_TBUF_VLD	BIT(1)
174 #define SUN4I_INT_RBUF_VLD	BIT(0)
175 
176 /* interrupt enable register (r/w)
177  * offset:0x0010 default:0x0000_0000
178  */
179 #define SUN4I_INTEN_BERR	BIT(7)
180 #define SUN4I_INTEN_ARB_LOST	BIT(6)
181 #define SUN4I_INTEN_ERR_PASSIVE	BIT(5)
182 #define SUN4I_INTEN_WAKEUP	BIT(4)
183 #define SUN4I_INTEN_OR		BIT(3)
184 #define SUN4I_INTEN_ERR_WRN	BIT(2)
185 #define SUN4I_INTEN_TX		BIT(1)
186 #define SUN4I_INTEN_RX		BIT(0)
187 
188 /* error code */
189 #define SUN4I_ERR_INRCV		(0x1 << 5)
190 #define SUN4I_ERR_INTRANS	(0x0 << 5)
191 
192 /* filter mode */
193 #define SUN4I_FILTER_CLOSE	0
194 #define SUN4I_SINGLE_FLTER_MODE	1
195 #define SUN4I_DUAL_FILTER_MODE	2
196 
197 /* message buffer flags */
198 #define SUN4I_MSG_EFF_FLAG	BIT(7)
199 #define SUN4I_MSG_RTR_FLAG	BIT(6)
200 
201 /* max. number of interrupts handled in ISR */
202 #define SUN4I_CAN_MAX_IRQ	20
203 #define SUN4I_MODE_MAX_RETRIES	100
204 
205 /**
206  * struct sun4ican_quirks - Differences between SoC variants.
207  *
208  * @has_reset: SoC needs reset deasserted.
209  * @acp_offset: Offset of ACPC and ACPM registers
210  */
211 struct sun4ican_quirks {
212 	bool has_reset;
213 	int acp_offset;
214 };
215 
216 struct sun4ican_priv {
217 	struct can_priv can;
218 	void __iomem *base;
219 	struct clk *clk;
220 	struct reset_control *reset;
221 	spinlock_t cmdreg_lock;	/* lock for concurrent cmd register writes */
222 	int acp_offset;
223 };
224 
225 static const struct can_bittiming_const sun4ican_bittiming_const = {
226 	.name = DRV_NAME,
227 	.tseg1_min = 1,
228 	.tseg1_max = 16,
229 	.tseg2_min = 1,
230 	.tseg2_max = 8,
231 	.sjw_max = 4,
232 	.brp_min = 1,
233 	.brp_max = 64,
234 	.brp_inc = 1,
235 };
236 
sun4i_can_write_cmdreg(struct sun4ican_priv * priv,u8 val)237 static void sun4i_can_write_cmdreg(struct sun4ican_priv *priv, u8 val)
238 {
239 	unsigned long flags;
240 
241 	spin_lock_irqsave(&priv->cmdreg_lock, flags);
242 	writel(val, priv->base + SUN4I_REG_CMD_ADDR);
243 	spin_unlock_irqrestore(&priv->cmdreg_lock, flags);
244 }
245 
set_normal_mode(struct net_device * dev)246 static int set_normal_mode(struct net_device *dev)
247 {
248 	struct sun4ican_priv *priv = netdev_priv(dev);
249 	int retry = SUN4I_MODE_MAX_RETRIES;
250 	u32 mod_reg_val = 0;
251 
252 	do {
253 		mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
254 		mod_reg_val &= ~SUN4I_MSEL_RESET_MODE;
255 		writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
256 	} while (retry-- && (mod_reg_val & SUN4I_MSEL_RESET_MODE));
257 
258 	if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) {
259 		netdev_err(dev,
260 			   "setting controller into normal mode failed!\n");
261 		return -ETIMEDOUT;
262 	}
263 
264 	return 0;
265 }
266 
set_reset_mode(struct net_device * dev)267 static int set_reset_mode(struct net_device *dev)
268 {
269 	struct sun4ican_priv *priv = netdev_priv(dev);
270 	int retry = SUN4I_MODE_MAX_RETRIES;
271 	u32 mod_reg_val = 0;
272 
273 	do {
274 		mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
275 		mod_reg_val |= SUN4I_MSEL_RESET_MODE;
276 		writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
277 	} while (retry-- && !(mod_reg_val & SUN4I_MSEL_RESET_MODE));
278 
279 	if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) &
280 	      SUN4I_MSEL_RESET_MODE)) {
281 		netdev_err(dev, "setting controller into reset mode failed!\n");
282 		return -ETIMEDOUT;
283 	}
284 
285 	return 0;
286 }
287 
288 /* bittiming is called in reset_mode only */
sun4ican_set_bittiming(struct net_device * dev)289 static int sun4ican_set_bittiming(struct net_device *dev)
290 {
291 	struct sun4ican_priv *priv = netdev_priv(dev);
292 	struct can_bittiming *bt = &priv->can.bittiming;
293 	u32 cfg;
294 
295 	cfg = ((bt->brp - 1) & 0x3FF) |
296 	     (((bt->sjw - 1) & 0x3) << 14) |
297 	     (((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) << 16) |
298 	     (((bt->phase_seg2 - 1) & 0x7) << 20);
299 	if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
300 		cfg |= 0x800000;
301 
302 	netdev_dbg(dev, "setting BITTIMING=0x%08x\n", cfg);
303 	writel(cfg, priv->base + SUN4I_REG_BTIME_ADDR);
304 
305 	return 0;
306 }
307 
sun4ican_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)308 static int sun4ican_get_berr_counter(const struct net_device *dev,
309 				     struct can_berr_counter *bec)
310 {
311 	struct sun4ican_priv *priv = netdev_priv(dev);
312 	u32 errors;
313 	int err;
314 
315 	err = clk_prepare_enable(priv->clk);
316 	if (err) {
317 		netdev_err(dev, "could not enable clock\n");
318 		return err;
319 	}
320 
321 	errors = readl(priv->base + SUN4I_REG_ERRC_ADDR);
322 
323 	bec->txerr = errors & 0xFF;
324 	bec->rxerr = (errors >> 16) & 0xFF;
325 
326 	clk_disable_unprepare(priv->clk);
327 
328 	return 0;
329 }
330 
sun4i_can_start(struct net_device * dev)331 static int sun4i_can_start(struct net_device *dev)
332 {
333 	struct sun4ican_priv *priv = netdev_priv(dev);
334 	int err;
335 	u32 mod_reg_val;
336 
337 	/* we need to enter the reset mode */
338 	err = set_reset_mode(dev);
339 	if (err) {
340 		netdev_err(dev, "could not enter reset mode\n");
341 		return err;
342 	}
343 
344 	/* set filters - we accept all */
345 	writel(0x00000000, priv->base + SUN4I_REG_ACPC_ADDR + priv->acp_offset);
346 	writel(0xFFFFFFFF, priv->base + SUN4I_REG_ACPM_ADDR + priv->acp_offset);
347 
348 	/* clear error counters and error code capture */
349 	writel(0, priv->base + SUN4I_REG_ERRC_ADDR);
350 
351 	/* enable interrupts */
352 	if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
353 		writel(0xFF, priv->base + SUN4I_REG_INTEN_ADDR);
354 	else
355 		writel(0xFF & ~SUN4I_INTEN_BERR,
356 		       priv->base + SUN4I_REG_INTEN_ADDR);
357 
358 	/* enter the selected mode */
359 	mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR);
360 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
361 		mod_reg_val |= SUN4I_MSEL_LOOPBACK_MODE;
362 	else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
363 		mod_reg_val |= SUN4I_MSEL_LISTEN_ONLY_MODE;
364 	writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR);
365 
366 	err = sun4ican_set_bittiming(dev);
367 	if (err)
368 		return err;
369 
370 	/* we are ready to enter the normal mode */
371 	err = set_normal_mode(dev);
372 	if (err) {
373 		netdev_err(dev, "could not enter normal mode\n");
374 		return err;
375 	}
376 
377 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
378 
379 	return 0;
380 }
381 
sun4i_can_stop(struct net_device * dev)382 static int sun4i_can_stop(struct net_device *dev)
383 {
384 	struct sun4ican_priv *priv = netdev_priv(dev);
385 	int err;
386 
387 	priv->can.state = CAN_STATE_STOPPED;
388 	/* we need to enter reset mode */
389 	err = set_reset_mode(dev);
390 	if (err) {
391 		netdev_err(dev, "could not enter reset mode\n");
392 		return err;
393 	}
394 
395 	/* disable all interrupts */
396 	writel(0, priv->base + SUN4I_REG_INTEN_ADDR);
397 
398 	return 0;
399 }
400 
sun4ican_set_mode(struct net_device * dev,enum can_mode mode)401 static int sun4ican_set_mode(struct net_device *dev, enum can_mode mode)
402 {
403 	int err;
404 
405 	switch (mode) {
406 	case CAN_MODE_START:
407 		err = sun4i_can_start(dev);
408 		if (err) {
409 			netdev_err(dev, "starting CAN controller failed!\n");
410 			return err;
411 		}
412 		if (netif_queue_stopped(dev))
413 			netif_wake_queue(dev);
414 		break;
415 
416 	default:
417 		return -EOPNOTSUPP;
418 	}
419 	return 0;
420 }
421 
422 /* transmit a CAN message
423  * message layout in the sk_buff should be like this:
424  * xx xx xx xx         ff         ll 00 11 22 33 44 55 66 77
425  * [ can_id ] [flags] [len] [can data (up to 8 bytes]
426  */
sun4ican_start_xmit(struct sk_buff * skb,struct net_device * dev)427 static netdev_tx_t sun4ican_start_xmit(struct sk_buff *skb, struct net_device *dev)
428 {
429 	struct sun4ican_priv *priv = netdev_priv(dev);
430 	struct can_frame *cf = (struct can_frame *)skb->data;
431 	u8 dlc;
432 	u32 dreg, msg_flag_n;
433 	canid_t id;
434 	int i;
435 
436 	if (can_dev_dropped_skb(dev, skb))
437 		return NETDEV_TX_OK;
438 
439 	netif_stop_queue(dev);
440 
441 	id = cf->can_id;
442 	dlc = cf->len;
443 	msg_flag_n = dlc;
444 
445 	if (id & CAN_RTR_FLAG)
446 		msg_flag_n |= SUN4I_MSG_RTR_FLAG;
447 
448 	if (id & CAN_EFF_FLAG) {
449 		msg_flag_n |= SUN4I_MSG_EFF_FLAG;
450 		dreg = SUN4I_REG_BUF5_ADDR;
451 		writel((id >> 21) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
452 		writel((id >> 13) & 0xFF, priv->base + SUN4I_REG_BUF2_ADDR);
453 		writel((id >> 5)  & 0xFF, priv->base + SUN4I_REG_BUF3_ADDR);
454 		writel((id << 3)  & 0xF8, priv->base + SUN4I_REG_BUF4_ADDR);
455 	} else {
456 		dreg = SUN4I_REG_BUF3_ADDR;
457 		writel((id >> 3) & 0xFF, priv->base + SUN4I_REG_BUF1_ADDR);
458 		writel((id << 5) & 0xE0, priv->base + SUN4I_REG_BUF2_ADDR);
459 	}
460 
461 	for (i = 0; i < dlc; i++)
462 		writel(cf->data[i], priv->base + (dreg + i * 4));
463 
464 	writel(msg_flag_n, priv->base + SUN4I_REG_BUF0_ADDR);
465 
466 	can_put_echo_skb(skb, dev, 0, 0);
467 
468 	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
469 		sun4i_can_write_cmdreg(priv, SUN4I_CMD_SELF_RCV_REQ);
470 	else
471 		sun4i_can_write_cmdreg(priv, SUN4I_CMD_TRANS_REQ);
472 
473 	return NETDEV_TX_OK;
474 }
475 
sun4i_can_rx(struct net_device * dev)476 static void sun4i_can_rx(struct net_device *dev)
477 {
478 	struct sun4ican_priv *priv = netdev_priv(dev);
479 	struct net_device_stats *stats = &dev->stats;
480 	struct can_frame *cf;
481 	struct sk_buff *skb;
482 	u8 fi;
483 	u32 dreg;
484 	canid_t id;
485 	int i;
486 
487 	/* create zero'ed CAN frame buffer */
488 	skb = alloc_can_skb(dev, &cf);
489 	if (!skb)
490 		return;
491 
492 	fi = readl(priv->base + SUN4I_REG_BUF0_ADDR);
493 	cf->len = can_cc_dlc2len(fi & 0x0F);
494 	if (fi & SUN4I_MSG_EFF_FLAG) {
495 		dreg = SUN4I_REG_BUF5_ADDR;
496 		id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 21) |
497 		     (readl(priv->base + SUN4I_REG_BUF2_ADDR) << 13) |
498 		     (readl(priv->base + SUN4I_REG_BUF3_ADDR) << 5)  |
499 		    ((readl(priv->base + SUN4I_REG_BUF4_ADDR) >> 3)  & 0x1f);
500 		id |= CAN_EFF_FLAG;
501 	} else {
502 		dreg = SUN4I_REG_BUF3_ADDR;
503 		id = (readl(priv->base + SUN4I_REG_BUF1_ADDR) << 3) |
504 		    ((readl(priv->base + SUN4I_REG_BUF2_ADDR) >> 5) & 0x7);
505 	}
506 
507 	/* remote frame ? */
508 	if (fi & SUN4I_MSG_RTR_FLAG) {
509 		id |= CAN_RTR_FLAG;
510 	} else {
511 		for (i = 0; i < cf->len; i++)
512 			cf->data[i] = readl(priv->base + dreg + i * 4);
513 
514 		stats->rx_bytes += cf->len;
515 	}
516 	stats->rx_packets++;
517 
518 	cf->can_id = id;
519 
520 	sun4i_can_write_cmdreg(priv, SUN4I_CMD_RELEASE_RBUF);
521 
522 	netif_rx(skb);
523 }
524 
sun4i_can_err(struct net_device * dev,u8 isrc,u8 status)525 static int sun4i_can_err(struct net_device *dev, u8 isrc, u8 status)
526 {
527 	struct sun4ican_priv *priv = netdev_priv(dev);
528 	struct net_device_stats *stats = &dev->stats;
529 	struct can_frame *cf;
530 	struct sk_buff *skb;
531 	enum can_state state = priv->can.state;
532 	enum can_state rx_state, tx_state;
533 	unsigned int rxerr, txerr, errc;
534 	u32 ecc, alc;
535 
536 	/* we don't skip if alloc fails because we want the stats anyhow */
537 	skb = alloc_can_err_skb(dev, &cf);
538 
539 	errc = readl(priv->base + SUN4I_REG_ERRC_ADDR);
540 	rxerr = (errc >> 16) & 0xFF;
541 	txerr = errc & 0xFF;
542 
543 	if (isrc & SUN4I_INT_DATA_OR) {
544 		/* data overrun interrupt */
545 		netdev_dbg(dev, "data overrun interrupt\n");
546 		if (likely(skb)) {
547 			cf->can_id |= CAN_ERR_CRTL;
548 			cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
549 		}
550 		stats->rx_over_errors++;
551 		stats->rx_errors++;
552 
553 		/* reset the CAN IP by entering reset mode
554 		 * ignoring timeout error
555 		 */
556 		set_reset_mode(dev);
557 		set_normal_mode(dev);
558 
559 		/* clear bit */
560 		sun4i_can_write_cmdreg(priv, SUN4I_CMD_CLEAR_OR_FLAG);
561 	}
562 	if (isrc & SUN4I_INT_ERR_WRN) {
563 		/* error warning interrupt */
564 		netdev_dbg(dev, "error warning interrupt\n");
565 
566 		if (status & SUN4I_STA_BUS_OFF)
567 			state = CAN_STATE_BUS_OFF;
568 		else if (status & SUN4I_STA_ERR_STA)
569 			state = CAN_STATE_ERROR_WARNING;
570 		else
571 			state = CAN_STATE_ERROR_ACTIVE;
572 	}
573 	if (skb && state != CAN_STATE_BUS_OFF) {
574 		cf->can_id |= CAN_ERR_CNT;
575 		cf->data[6] = txerr;
576 		cf->data[7] = rxerr;
577 	}
578 	if (isrc & SUN4I_INT_BUS_ERR) {
579 		/* bus error interrupt */
580 		netdev_dbg(dev, "bus error interrupt\n");
581 		priv->can.can_stats.bus_error++;
582 		stats->rx_errors++;
583 
584 		if (likely(skb)) {
585 			ecc = readl(priv->base + SUN4I_REG_STA_ADDR);
586 
587 			cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
588 
589 			switch (ecc & SUN4I_STA_MASK_ERR) {
590 			case SUN4I_STA_BIT_ERR:
591 				cf->data[2] |= CAN_ERR_PROT_BIT;
592 				break;
593 			case SUN4I_STA_FORM_ERR:
594 				cf->data[2] |= CAN_ERR_PROT_FORM;
595 				break;
596 			case SUN4I_STA_STUFF_ERR:
597 				cf->data[2] |= CAN_ERR_PROT_STUFF;
598 				break;
599 			default:
600 				cf->data[3] = (ecc & SUN4I_STA_ERR_SEG_CODE)
601 					       >> 16;
602 				break;
603 			}
604 			/* error occurred during transmission? */
605 			if ((ecc & SUN4I_STA_ERR_DIR) == 0)
606 				cf->data[2] |= CAN_ERR_PROT_TX;
607 		}
608 	}
609 	if (isrc & SUN4I_INT_ERR_PASSIVE) {
610 		/* error passive interrupt */
611 		netdev_dbg(dev, "error passive interrupt\n");
612 		if (state == CAN_STATE_ERROR_PASSIVE)
613 			state = CAN_STATE_ERROR_WARNING;
614 		else
615 			state = CAN_STATE_ERROR_PASSIVE;
616 	}
617 	if (isrc & SUN4I_INT_ARB_LOST) {
618 		/* arbitration lost interrupt */
619 		netdev_dbg(dev, "arbitration lost interrupt\n");
620 		alc = readl(priv->base + SUN4I_REG_STA_ADDR);
621 		priv->can.can_stats.arbitration_lost++;
622 		if (likely(skb)) {
623 			cf->can_id |= CAN_ERR_LOSTARB;
624 			cf->data[0] = (alc >> 8) & 0x1f;
625 		}
626 	}
627 
628 	if (state != priv->can.state) {
629 		tx_state = txerr >= rxerr ? state : 0;
630 		rx_state = txerr <= rxerr ? state : 0;
631 
632 		if (likely(skb))
633 			can_change_state(dev, cf, tx_state, rx_state);
634 		else
635 			priv->can.state = state;
636 		if (state == CAN_STATE_BUS_OFF)
637 			can_bus_off(dev);
638 	}
639 
640 	if (likely(skb))
641 		netif_rx(skb);
642 	else
643 		return -ENOMEM;
644 
645 	return 0;
646 }
647 
sun4i_can_interrupt(int irq,void * dev_id)648 static irqreturn_t sun4i_can_interrupt(int irq, void *dev_id)
649 {
650 	struct net_device *dev = (struct net_device *)dev_id;
651 	struct sun4ican_priv *priv = netdev_priv(dev);
652 	struct net_device_stats *stats = &dev->stats;
653 	u8 isrc, status;
654 	int n = 0;
655 
656 	while ((isrc = readl(priv->base + SUN4I_REG_INT_ADDR)) &&
657 	       (n < SUN4I_CAN_MAX_IRQ)) {
658 		n++;
659 		status = readl(priv->base + SUN4I_REG_STA_ADDR);
660 
661 		if (isrc & SUN4I_INT_WAKEUP)
662 			netdev_warn(dev, "wakeup interrupt\n");
663 
664 		if (isrc & SUN4I_INT_TBUF_VLD) {
665 			/* transmission complete interrupt */
666 			stats->tx_bytes += can_get_echo_skb(dev, 0, NULL);
667 			stats->tx_packets++;
668 			netif_wake_queue(dev);
669 		}
670 		if ((isrc & SUN4I_INT_RBUF_VLD) &&
671 		    !(isrc & SUN4I_INT_DATA_OR)) {
672 			/* receive interrupt - don't read if overrun occurred */
673 			while (status & SUN4I_STA_RBUF_RDY) {
674 				/* RX buffer is not empty */
675 				sun4i_can_rx(dev);
676 				status = readl(priv->base + SUN4I_REG_STA_ADDR);
677 			}
678 		}
679 		if (isrc &
680 		    (SUN4I_INT_DATA_OR | SUN4I_INT_ERR_WRN | SUN4I_INT_BUS_ERR |
681 		     SUN4I_INT_ERR_PASSIVE | SUN4I_INT_ARB_LOST)) {
682 			/* error interrupt */
683 			if (sun4i_can_err(dev, isrc, status))
684 				netdev_err(dev, "can't allocate buffer - clearing pending interrupts\n");
685 		}
686 		/* clear interrupts */
687 		writel(isrc, priv->base + SUN4I_REG_INT_ADDR);
688 		readl(priv->base + SUN4I_REG_INT_ADDR);
689 	}
690 	if (n >= SUN4I_CAN_MAX_IRQ)
691 		netdev_dbg(dev, "%d messages handled in ISR", n);
692 
693 	return (n) ? IRQ_HANDLED : IRQ_NONE;
694 }
695 
sun4ican_open(struct net_device * dev)696 static int sun4ican_open(struct net_device *dev)
697 {
698 	struct sun4ican_priv *priv = netdev_priv(dev);
699 	int err;
700 
701 	/* common open */
702 	err = open_candev(dev);
703 	if (err)
704 		return err;
705 
706 	/* register interrupt handler */
707 	err = request_irq(dev->irq, sun4i_can_interrupt, 0, dev->name, dev);
708 	if (err) {
709 		netdev_err(dev, "request_irq err: %d\n", err);
710 		goto exit_irq;
711 	}
712 
713 	/* software reset deassert */
714 	err = reset_control_deassert(priv->reset);
715 	if (err) {
716 		netdev_err(dev, "could not deassert CAN reset\n");
717 		goto exit_soft_reset;
718 	}
719 
720 	/* turn on clocking for CAN peripheral block */
721 	err = clk_prepare_enable(priv->clk);
722 	if (err) {
723 		netdev_err(dev, "could not enable CAN peripheral clock\n");
724 		goto exit_clock;
725 	}
726 
727 	err = sun4i_can_start(dev);
728 	if (err) {
729 		netdev_err(dev, "could not start CAN peripheral\n");
730 		goto exit_can_start;
731 	}
732 
733 	netif_start_queue(dev);
734 
735 	return 0;
736 
737 exit_can_start:
738 	clk_disable_unprepare(priv->clk);
739 exit_clock:
740 	reset_control_assert(priv->reset);
741 exit_soft_reset:
742 	free_irq(dev->irq, dev);
743 exit_irq:
744 	close_candev(dev);
745 	return err;
746 }
747 
sun4ican_close(struct net_device * dev)748 static int sun4ican_close(struct net_device *dev)
749 {
750 	struct sun4ican_priv *priv = netdev_priv(dev);
751 
752 	netif_stop_queue(dev);
753 	sun4i_can_stop(dev);
754 	clk_disable_unprepare(priv->clk);
755 	reset_control_assert(priv->reset);
756 
757 	free_irq(dev->irq, dev);
758 	close_candev(dev);
759 
760 	return 0;
761 }
762 
763 static const struct net_device_ops sun4ican_netdev_ops = {
764 	.ndo_open = sun4ican_open,
765 	.ndo_stop = sun4ican_close,
766 	.ndo_start_xmit = sun4ican_start_xmit,
767 };
768 
769 static const struct ethtool_ops sun4ican_ethtool_ops = {
770 	.get_ts_info = ethtool_op_get_ts_info,
771 };
772 
773 static const struct sun4ican_quirks sun4ican_quirks_a10 = {
774 	.has_reset = false,
775 	.acp_offset = 0,
776 };
777 
778 static const struct sun4ican_quirks sun4ican_quirks_r40 = {
779 	.has_reset = true,
780 	.acp_offset = 0,
781 };
782 
783 static const struct sun4ican_quirks sun4ican_quirks_d1 = {
784 	.has_reset = true,
785 	.acp_offset = (SUN4I_REG_ACPC_ADDR_D1 - SUN4I_REG_ACPC_ADDR),
786 };
787 
788 static const struct of_device_id sun4ican_of_match[] = {
789 	{
790 		.compatible = "allwinner,sun4i-a10-can",
791 		.data = &sun4ican_quirks_a10
792 	}, {
793 		.compatible = "allwinner,sun7i-a20-can",
794 		.data = &sun4ican_quirks_a10
795 	}, {
796 		.compatible = "allwinner,sun8i-r40-can",
797 		.data = &sun4ican_quirks_r40
798 	}, {
799 		.compatible = "allwinner,sun20i-d1-can",
800 		.data = &sun4ican_quirks_d1
801 	}, {
802 		/* sentinel */
803 	},
804 };
805 
806 MODULE_DEVICE_TABLE(of, sun4ican_of_match);
807 
sun4ican_remove(struct platform_device * pdev)808 static void sun4ican_remove(struct platform_device *pdev)
809 {
810 	struct net_device *dev = platform_get_drvdata(pdev);
811 
812 	unregister_netdev(dev);
813 	free_candev(dev);
814 }
815 
sun4ican_probe(struct platform_device * pdev)816 static int sun4ican_probe(struct platform_device *pdev)
817 {
818 	struct device_node *np = pdev->dev.of_node;
819 	struct clk *clk;
820 	struct reset_control *reset = NULL;
821 	void __iomem *addr;
822 	int err, irq;
823 	struct net_device *dev;
824 	struct sun4ican_priv *priv;
825 	const struct sun4ican_quirks *quirks;
826 
827 	quirks = of_device_get_match_data(&pdev->dev);
828 	if (!quirks) {
829 		dev_err(&pdev->dev, "failed to determine the quirks to use\n");
830 		err = -ENODEV;
831 		goto exit;
832 	}
833 
834 	if (quirks->has_reset) {
835 		reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
836 		if (IS_ERR(reset)) {
837 			dev_err(&pdev->dev, "unable to request reset\n");
838 			err = PTR_ERR(reset);
839 			goto exit;
840 		}
841 	}
842 
843 	clk = of_clk_get(np, 0);
844 	if (IS_ERR(clk)) {
845 		dev_err(&pdev->dev, "unable to request clock\n");
846 		err = -ENODEV;
847 		goto exit;
848 	}
849 
850 	irq = platform_get_irq(pdev, 0);
851 	if (irq < 0) {
852 		err = -ENODEV;
853 		goto exit;
854 	}
855 
856 	addr = devm_platform_ioremap_resource(pdev, 0);
857 	if (IS_ERR(addr)) {
858 		err = PTR_ERR(addr);
859 		goto exit;
860 	}
861 
862 	dev = alloc_candev(sizeof(struct sun4ican_priv), 1);
863 	if (!dev) {
864 		dev_err(&pdev->dev,
865 			"could not allocate memory for CAN device\n");
866 		err = -ENOMEM;
867 		goto exit;
868 	}
869 
870 	dev->netdev_ops = &sun4ican_netdev_ops;
871 	dev->ethtool_ops = &sun4ican_ethtool_ops;
872 	dev->irq = irq;
873 	dev->flags |= IFF_ECHO;
874 
875 	priv = netdev_priv(dev);
876 	priv->can.clock.freq = clk_get_rate(clk);
877 	priv->can.bittiming_const = &sun4ican_bittiming_const;
878 	priv->can.do_set_mode = sun4ican_set_mode;
879 	priv->can.do_get_berr_counter = sun4ican_get_berr_counter;
880 	priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
881 				       CAN_CTRLMODE_LISTENONLY |
882 				       CAN_CTRLMODE_LOOPBACK |
883 				       CAN_CTRLMODE_3_SAMPLES;
884 	priv->base = addr;
885 	priv->clk = clk;
886 	priv->reset = reset;
887 	priv->acp_offset = quirks->acp_offset;
888 	spin_lock_init(&priv->cmdreg_lock);
889 
890 	platform_set_drvdata(pdev, dev);
891 	SET_NETDEV_DEV(dev, &pdev->dev);
892 
893 	err = register_candev(dev);
894 	if (err) {
895 		dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
896 			DRV_NAME, err);
897 		goto exit_free;
898 	}
899 
900 	dev_info(&pdev->dev, "device registered (base=%p, irq=%d)\n",
901 		 priv->base, dev->irq);
902 
903 	return 0;
904 
905 exit_free:
906 	free_candev(dev);
907 exit:
908 	return err;
909 }
910 
911 static struct platform_driver sun4i_can_driver = {
912 	.driver = {
913 		.name = DRV_NAME,
914 		.of_match_table = sun4ican_of_match,
915 	},
916 	.probe = sun4ican_probe,
917 	.remove = sun4ican_remove,
918 };
919 
920 module_platform_driver(sun4i_can_driver);
921 
922 MODULE_AUTHOR("Peter Chen <xingkongcp@gmail.com>");
923 MODULE_AUTHOR("Gerhard Bertelsmann <info@gerhard-bertelsmann.de>");
924 MODULE_LICENSE("Dual BSD/GPL");
925 MODULE_DESCRIPTION("CAN driver for Allwinner SoCs (A10/A20/D1)");
926