xref: /linux/drivers/staging/media/atomisp/pci/system_global.h (revision 6fd600d742744dc7ef7fc65ca26daa2b1163158a)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 // SPDX-License-Identifier: GPL-2.0-or-later
3 /*
4  *    (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
5  */
6 
7 #ifndef __SYSTEM_GLOBAL_H_INCLUDED__
8 #define __SYSTEM_GLOBAL_H_INCLUDED__
9 
10 /*
11  * Create a list of HAS and IS properties that defines the system
12  * Those are common for both ISP2400 and ISP2401
13  *
14  * The configuration assumes the following
15  * - The system is hetereogeneous; Multiple cells and devices classes
16  * - The cell and device instances are homogeneous, each device type
17  *   belongs to the same class
18  * - Device instances supporting a subset of the class capabilities are
19  *   allowed
20  *
21  * We could manage different device classes through the enumerated
22  * lists (C) or the use of classes (C++), but that is presently not
23  * fully supported
24  *
25  * N.B. the 3 input formatters are of 2 different classess
26  */
27 
28 #define DMA_DDR_TO_VAMEM_WORKAROUND
29 #define DMA_DDR_TO_HMEM_WORKAROUND
30 
31 /*
32  * The longest allowed (uninteruptible) bus transfer, does not
33  * take stalling into account
34  */
35 #define HIVE_ISP_MAX_BURST_LENGTH	1024
36 
37 /*
38  * Maximum allowed burst length in words for the ISP DMA
39  * This value is set to 2 to prevent the ISP DMA from blocking
40  * the bus for too long; as the input system can only buffer
41  * 2 lines on Moorefield and Cherrytrail, the input system buffers
42  * may overflow if blocked for too long (BZ 2726).
43  */
44 #define ISP2400_DMA_MAX_BURST_LENGTH	128
45 #define ISP2401_DMA_MAX_BURST_LENGTH	2
46 
47 #include <hive_isp_css_defs.h>
48 #include <type_support.h>
49 
50 /* This interface is deprecated */
51 #include "hive_types.h"
52 
53 /*
54  * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
55  */
56 #define HRT_VADDRESS_WIDTH	32
57 
58 #define SIZEOF_HRT_REG		(HRT_DATA_WIDTH >> 3)
59 #define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
60 
61 /* The main bus connecting all devices */
62 #define HRT_BUS_WIDTH		HIVE_ISP_CTRL_DATA_WIDTH
63 #define HRT_BUS_BYTES		HIVE_ISP_CTRL_DATA_BYTES
64 
65 typedef u32			hrt_bus_align_t;
66 
67 /*
68  * Enumerate the devices, device access through the API is by ID,
69  * through the DLI by address. The enumerator terminators are used
70  * to size the wiring arrays and as an exception value.
71  */
72 typedef enum {
73 	DDR0_ID = 0,
74 	N_DDR_ID
75 } ddr_ID_t;
76 
77 typedef enum {
78 	ISP0_ID = 0,
79 	N_ISP_ID
80 } isp_ID_t;
81 
82 typedef enum {
83 	SP0_ID = 0,
84 	N_SP_ID
85 } sp_ID_t;
86 
87 typedef enum {
88 	MMU0_ID = 0,
89 	MMU1_ID,
90 	N_MMU_ID
91 } mmu_ID_t;
92 
93 typedef enum {
94 	DMA0_ID = 0,
95 	N_DMA_ID
96 } dma_ID_t;
97 
98 typedef enum {
99 	GDC0_ID = 0,
100 	GDC1_ID,
101 	N_GDC_ID
102 } gdc_ID_t;
103 
104 /* this extra define is needed because we want to use it also
105    in the preprocessor, and that doesn't work with enums.
106  */
107 #define N_GDC_ID_CPP 2
108 
109 typedef enum {
110 	VAMEM0_ID = 0,
111 	VAMEM1_ID,
112 	VAMEM2_ID,
113 	N_VAMEM_ID
114 } vamem_ID_t;
115 
116 typedef enum {
117 	BAMEM0_ID = 0,
118 	N_BAMEM_ID
119 } bamem_ID_t;
120 
121 typedef enum {
122 	HMEM0_ID = 0,
123 	N_HMEM_ID
124 } hmem_ID_t;
125 
126 typedef enum {
127 	IRQ0_ID = 0,	/* GP IRQ block */
128 	IRQ1_ID,	/* Input formatter */
129 	IRQ2_ID,	/* input system */
130 	IRQ3_ID,	/* input selector */
131 	N_IRQ_ID
132 } irq_ID_t;
133 
134 typedef enum {
135 	FIFO_MONITOR0_ID = 0,
136 	N_FIFO_MONITOR_ID
137 } fifo_monitor_ID_t;
138 
139 typedef enum {
140 	GP_DEVICE0_ID = 0,
141 	N_GP_DEVICE_ID
142 } gp_device_ID_t;
143 
144 typedef enum {
145 	GP_TIMER0_ID = 0,
146 	GP_TIMER1_ID,
147 	GP_TIMER2_ID,
148 	GP_TIMER3_ID,
149 	GP_TIMER4_ID,
150 	GP_TIMER5_ID,
151 	GP_TIMER6_ID,
152 	GP_TIMER7_ID,
153 	N_GP_TIMER_ID
154 } gp_timer_ID_t;
155 
156 typedef enum {
157 	GPIO0_ID = 0,
158 	N_GPIO_ID
159 } gpio_ID_t;
160 
161 typedef enum {
162 	TIMED_CTRL0_ID = 0,
163 	N_TIMED_CTRL_ID
164 } timed_ctrl_ID_t;
165 
166 typedef enum {
167 	INPUT_FORMATTER0_ID = 0,
168 	INPUT_FORMATTER1_ID,
169 	INPUT_FORMATTER2_ID,
170 	INPUT_FORMATTER3_ID,
171 	N_INPUT_FORMATTER_ID
172 } input_formatter_ID_t;
173 
174 /* The IF RST is outside the IF */
175 #define INPUT_FORMATTER0_SRST_OFFSET	0x0824
176 #define INPUT_FORMATTER1_SRST_OFFSET	0x0624
177 #define INPUT_FORMATTER2_SRST_OFFSET	0x0424
178 #define INPUT_FORMATTER3_SRST_OFFSET	0x0224
179 
180 #define INPUT_FORMATTER0_SRST_MASK		0x0001
181 #define INPUT_FORMATTER1_SRST_MASK		0x0002
182 #define INPUT_FORMATTER2_SRST_MASK		0x0004
183 #define INPUT_FORMATTER3_SRST_MASK		0x0008
184 
185 typedef enum {
186 	INPUT_SYSTEM0_ID = 0,
187 	N_INPUT_SYSTEM_ID
188 } input_system_ID_t;
189 
190 typedef enum {
191 	RX0_ID = 0,
192 	N_RX_ID
193 } rx_ID_t;
194 
195 enum mipi_port_id {
196 	MIPI_PORT0_ID = 0,
197 	MIPI_PORT1_ID,
198 	MIPI_PORT2_ID,
199 	N_MIPI_PORT_ID
200 };
201 
202 #define	N_RX_CHANNEL_ID		4
203 
204 typedef enum {
205 	CAPTURE_UNIT0_ID = 0,
206 	CAPTURE_UNIT1_ID,
207 	CAPTURE_UNIT2_ID,
208 	ACQUISITION_UNIT0_ID,
209 	DMA_UNIT0_ID,
210 	CTRL_UNIT0_ID,
211 	GPREGS_UNIT0_ID,
212 	FIFO_UNIT0_ID,
213 	IRQ_UNIT0_ID,
214 	N_SUB_SYSTEM_ID
215 } sub_system_ID_t;
216 
217 #define	N_CAPTURE_UNIT_ID		3
218 #define	N_ACQUISITION_UNIT_ID		1
219 #define	N_CTRL_UNIT_ID			1
220 
221 
222 enum ia_css_isp_memories {
223 	IA_CSS_ISP_PMEM0 = 0,
224 	IA_CSS_ISP_DMEM0,
225 	IA_CSS_ISP_VMEM0,
226 	IA_CSS_ISP_VAMEM0,
227 	IA_CSS_ISP_VAMEM1,
228 	IA_CSS_ISP_VAMEM2,
229 	IA_CSS_ISP_HMEM0,
230 	IA_CSS_SP_DMEM0,
231 	IA_CSS_DDR,
232 	N_IA_CSS_MEMORIES
233 };
234 
235 #define IA_CSS_NUM_MEMORIES 9
236 /* For driver compatibility */
237 #define N_IA_CSS_ISP_MEMORIES   IA_CSS_NUM_MEMORIES
238 #define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
239 
240 /*
241  * ISP2401 specific enums
242  */
243 
244 typedef enum {
245 	ISYS_IRQ0_ID = 0,	/* port a */
246 	ISYS_IRQ1_ID,	/* port b */
247 	ISYS_IRQ2_ID,	/* port c */
248 	N_ISYS_IRQ_ID
249 } isys_irq_ID_t;
250 
251 
252 /*
253  * Input-buffer Controller.
254  */
255 typedef enum {
256 	IBUF_CTRL0_ID = 0,	/* map to ISYS2401_IBUF_CNTRL_A */
257 	IBUF_CTRL1_ID,		/* map to ISYS2401_IBUF_CNTRL_B */
258 	IBUF_CTRL2_ID,		/* map ISYS2401_IBUF_CNTRL_C */
259 	N_IBUF_CTRL_ID
260 } ibuf_ctrl_ID_t;
261 /* end of Input-buffer Controller */
262 
263 /*
264  * Stream2MMIO.
265  */
266 typedef enum {
267 	STREAM2MMIO0_ID = 0,	/* map to ISYS2401_S2M_A */
268 	STREAM2MMIO1_ID,	/* map to ISYS2401_S2M_B */
269 	STREAM2MMIO2_ID,	/* map to ISYS2401_S2M_C */
270 	N_STREAM2MMIO_ID
271 } stream2mmio_ID_t;
272 
273 typedef enum {
274 	/*
275 	 * Stream2MMIO 0 has 8 SIDs that are indexed by
276 	 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
277 	 *
278 	 * Stream2MMIO 1 has 4 SIDs that are indexed by
279 	 * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
280 	 *
281 	 * Stream2MMIO 2 has 4 SIDs that are indexed by
282 	 * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
283 	 */
284 	STREAM2MMIO_SID0_ID = 0,
285 	STREAM2MMIO_SID1_ID,
286 	STREAM2MMIO_SID2_ID,
287 	STREAM2MMIO_SID3_ID,
288 	STREAM2MMIO_SID4_ID,
289 	STREAM2MMIO_SID5_ID,
290 	STREAM2MMIO_SID6_ID,
291 	STREAM2MMIO_SID7_ID,
292 	N_STREAM2MMIO_SID_ID
293 } stream2mmio_sid_ID_t;
294 /* end of Stream2MMIO */
295 
296 /**
297  * Input System 2401: CSI-MIPI recevier.
298  */
299 typedef enum {
300 	CSI_RX_BACKEND0_ID = 0,	/* map to ISYS2401_MIPI_BE_A */
301 	CSI_RX_BACKEND1_ID,		/* map to ISYS2401_MIPI_BE_B */
302 	CSI_RX_BACKEND2_ID,		/* map to ISYS2401_MIPI_BE_C */
303 	N_CSI_RX_BACKEND_ID
304 } csi_rx_backend_ID_t;
305 
306 typedef enum {
307 	CSI_RX_FRONTEND0_ID = 0,	/* map to ISYS2401_CSI_RX_A */
308 	CSI_RX_FRONTEND1_ID,		/* map to ISYS2401_CSI_RX_B */
309 	CSI_RX_FRONTEND2_ID,		/* map to ISYS2401_CSI_RX_C */
310 #define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
311 } csi_rx_frontend_ID_t;
312 
313 typedef enum {
314 	CSI_RX_DLANE0_ID = 0,		/* map to DLANE0 in CSI RX */
315 	CSI_RX_DLANE1_ID,		/* map to DLANE1 in CSI RX */
316 	CSI_RX_DLANE2_ID,		/* map to DLANE2 in CSI RX */
317 	CSI_RX_DLANE3_ID,		/* map to DLANE3 in CSI RX */
318 	N_CSI_RX_DLANE_ID
319 } csi_rx_fe_dlane_ID_t;
320 /* end of CSI-MIPI receiver */
321 
322 typedef enum {
323 	ISYS2401_DMA0_ID = 0,
324 	N_ISYS2401_DMA_ID
325 } isys2401_dma_ID_t;
326 
327 /**
328  * Pixel-generator. ("system_global.h")
329  */
330 typedef enum {
331 	PIXELGEN0_ID = 0,
332 	PIXELGEN1_ID,
333 	PIXELGEN2_ID,
334 	N_PIXELGEN_ID
335 } pixelgen_ID_t;
336 /* end of pixel-generator. ("system_global.h") */
337 
338 typedef enum {
339 	INPUT_SYSTEM_CSI_PORT0_ID = 0,
340 	INPUT_SYSTEM_CSI_PORT1_ID,
341 	INPUT_SYSTEM_CSI_PORT2_ID,
342 
343 	INPUT_SYSTEM_PIXELGEN_PORT0_ID,
344 	INPUT_SYSTEM_PIXELGEN_PORT1_ID,
345 	INPUT_SYSTEM_PIXELGEN_PORT2_ID,
346 
347 	N_INPUT_SYSTEM_INPUT_PORT_ID
348 } input_system_input_port_ID_t;
349 
350 #define N_INPUT_SYSTEM_CSI_PORT	3
351 
352 typedef enum {
353 	ISYS2401_DMA_CHANNEL_0 = 0,
354 	ISYS2401_DMA_CHANNEL_1,
355 	ISYS2401_DMA_CHANNEL_2,
356 	ISYS2401_DMA_CHANNEL_3,
357 	ISYS2401_DMA_CHANNEL_4,
358 	ISYS2401_DMA_CHANNEL_5,
359 	ISYS2401_DMA_CHANNEL_6,
360 	ISYS2401_DMA_CHANNEL_7,
361 	ISYS2401_DMA_CHANNEL_8,
362 	ISYS2401_DMA_CHANNEL_9,
363 	ISYS2401_DMA_CHANNEL_10,
364 	ISYS2401_DMA_CHANNEL_11,
365 	N_ISYS2401_DMA_CHANNEL
366 } isys2401_dma_channel;
367 
368 #endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */
369