1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8953_MASK \ 25 (BIT(DPU_SSPP_QOS) |\ 26 BIT(DPU_SSPP_SCALER_QSEED2) |\ 27 BIT(DPU_SSPP_CSC)) 28 29 #define VIG_MSM8996_MASK \ 30 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ 31 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_QSEED2) |\ 32 BIT(DPU_SSPP_CSC)) 33 34 #define VIG_MSM8998_MASK \ 35 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 36 37 #define VIG_SDM845_MASK \ 38 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 39 40 #define VIG_SDM845_MASK_SDMA \ 41 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 42 43 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 44 45 #define DMA_MSM8953_MASK \ 46 (BIT(DPU_SSPP_QOS)) 47 48 #define DMA_MSM8996_MASK \ 49 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_CDP)) 50 51 #define DMA_MSM8998_MASK \ 52 (BIT(DPU_SSPP_QOS) |\ 53 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 54 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 55 56 #define VIG_SC7280_MASK \ 57 (VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 58 59 #define VIG_SC7280_MASK_SDMA \ 60 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 61 62 #define DMA_SDM845_MASK \ 63 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 64 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 65 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 66 67 #define DMA_CURSOR_SDM845_MASK \ 68 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 69 70 #define DMA_SDM845_MASK_SDMA \ 71 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 72 73 #define DMA_CURSOR_SDM845_MASK_SDMA \ 74 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 75 76 #define DMA_CURSOR_MSM8996_MASK \ 77 (DMA_MSM8996_MASK | BIT(DPU_SSPP_CURSOR)) 78 79 #define DMA_CURSOR_MSM8998_MASK \ 80 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 81 82 #define RGB_MSM8953_MASK \ 83 (BIT(DPU_SSPP_QOS)) 84 85 #define RGB_MSM8996_MASK \ 86 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ 87 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_RGB)) 88 89 #define MIXER_MSM8998_MASK \ 90 (BIT(DPU_MIXER_SOURCESPLIT)) 91 92 #define MIXER_SDM845_MASK \ 93 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 94 95 #define MIXER_QCM2290_MASK \ 96 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 97 98 #define PINGPONG_MSM8996_MASK \ 99 (BIT(DPU_PINGPONG_DSC)) 100 101 #define PINGPONG_MSM8996_TE2_MASK \ 102 (PINGPONG_MSM8996_MASK | BIT(DPU_PINGPONG_TE2)) 103 104 #define PINGPONG_SDM845_MASK \ 105 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 106 107 #define PINGPONG_SDM845_TE2_MASK \ 108 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 109 110 #define PINGPONG_SM8150_MASK \ 111 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 112 113 #define CTL_SC7280_MASK \ 114 (BIT(DPU_CTL_ACTIVE_CFG) | \ 115 BIT(DPU_CTL_FETCH_ACTIVE) | \ 116 BIT(DPU_CTL_VM_CFG) | \ 117 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 118 119 #define CTL_SM8550_MASK \ 120 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 121 122 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 123 124 #define INTF_SC7180_MASK \ 125 (BIT(DPU_INTF_INPUT_CTRL) | \ 126 BIT(DPU_INTF_STATUS_SUPPORTED) | \ 127 BIT(DPU_DATA_HCTL_EN)) 128 129 #define INTF_SC7280_MASK (INTF_SC7180_MASK) 130 131 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ 132 BIT(DPU_WB_UBWC) | \ 133 BIT(DPU_WB_YUV_CONFIG) | \ 134 BIT(DPU_WB_PIPE_ALPHA) | \ 135 BIT(DPU_WB_XY_ROI_OFFSET) | \ 136 BIT(DPU_WB_QOS) | \ 137 BIT(DPU_WB_QOS_8LVL) | \ 138 BIT(DPU_WB_CDP)) 139 140 #define WB_SM8250_MASK (WB_SDM845_MASK | \ 141 BIT(DPU_WB_INPUT_CTRL)) 142 143 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 144 #define DEFAULT_DPU_LINE_WIDTH 2048 145 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 146 147 #define MAX_HORZ_DECIMATION 4 148 #define MAX_VERT_DECIMATION 4 149 150 #define STRCAT(X, Y) (X Y) 151 152 static const uint32_t plane_formats[] = { 153 DRM_FORMAT_ARGB8888, 154 DRM_FORMAT_ABGR8888, 155 DRM_FORMAT_RGBA8888, 156 DRM_FORMAT_BGRA8888, 157 DRM_FORMAT_XRGB8888, 158 DRM_FORMAT_RGBX8888, 159 DRM_FORMAT_BGRX8888, 160 DRM_FORMAT_XBGR8888, 161 DRM_FORMAT_ARGB2101010, 162 DRM_FORMAT_XRGB2101010, 163 DRM_FORMAT_RGB888, 164 DRM_FORMAT_BGR888, 165 DRM_FORMAT_RGB565, 166 DRM_FORMAT_BGR565, 167 DRM_FORMAT_ARGB1555, 168 DRM_FORMAT_ABGR1555, 169 DRM_FORMAT_RGBA5551, 170 DRM_FORMAT_BGRA5551, 171 DRM_FORMAT_XRGB1555, 172 DRM_FORMAT_XBGR1555, 173 DRM_FORMAT_RGBX5551, 174 DRM_FORMAT_BGRX5551, 175 DRM_FORMAT_ARGB4444, 176 DRM_FORMAT_ABGR4444, 177 DRM_FORMAT_RGBA4444, 178 DRM_FORMAT_BGRA4444, 179 DRM_FORMAT_XRGB4444, 180 DRM_FORMAT_XBGR4444, 181 DRM_FORMAT_RGBX4444, 182 DRM_FORMAT_BGRX4444, 183 }; 184 185 static const uint32_t plane_formats_yuv[] = { 186 DRM_FORMAT_ARGB8888, 187 DRM_FORMAT_ABGR8888, 188 DRM_FORMAT_RGBA8888, 189 DRM_FORMAT_BGRX8888, 190 DRM_FORMAT_BGRA8888, 191 DRM_FORMAT_ARGB2101010, 192 DRM_FORMAT_XRGB2101010, 193 DRM_FORMAT_XRGB8888, 194 DRM_FORMAT_XBGR8888, 195 DRM_FORMAT_RGBX8888, 196 DRM_FORMAT_RGB888, 197 DRM_FORMAT_BGR888, 198 DRM_FORMAT_RGB565, 199 DRM_FORMAT_BGR565, 200 DRM_FORMAT_ARGB1555, 201 DRM_FORMAT_ABGR1555, 202 DRM_FORMAT_RGBA5551, 203 DRM_FORMAT_BGRA5551, 204 DRM_FORMAT_XRGB1555, 205 DRM_FORMAT_XBGR1555, 206 DRM_FORMAT_RGBX5551, 207 DRM_FORMAT_BGRX5551, 208 DRM_FORMAT_ARGB4444, 209 DRM_FORMAT_ABGR4444, 210 DRM_FORMAT_RGBA4444, 211 DRM_FORMAT_BGRA4444, 212 DRM_FORMAT_XRGB4444, 213 DRM_FORMAT_XBGR4444, 214 DRM_FORMAT_RGBX4444, 215 DRM_FORMAT_BGRX4444, 216 217 DRM_FORMAT_P010, 218 DRM_FORMAT_NV12, 219 DRM_FORMAT_NV21, 220 DRM_FORMAT_NV16, 221 DRM_FORMAT_NV61, 222 DRM_FORMAT_VYUY, 223 DRM_FORMAT_UYVY, 224 DRM_FORMAT_YUYV, 225 DRM_FORMAT_YVYU, 226 DRM_FORMAT_YUV420, 227 DRM_FORMAT_YVU420, 228 }; 229 230 static const u32 rotation_v2_formats[] = { 231 DRM_FORMAT_NV12, 232 /* TODO add formats after validation */ 233 }; 234 235 static const u32 wb2_formats_rgb[] = { 236 DRM_FORMAT_RGB565, 237 DRM_FORMAT_BGR565, 238 DRM_FORMAT_RGB888, 239 DRM_FORMAT_ARGB8888, 240 DRM_FORMAT_RGBA8888, 241 DRM_FORMAT_ABGR8888, 242 DRM_FORMAT_XRGB8888, 243 DRM_FORMAT_RGBX8888, 244 DRM_FORMAT_XBGR8888, 245 DRM_FORMAT_ARGB1555, 246 DRM_FORMAT_RGBA5551, 247 DRM_FORMAT_XRGB1555, 248 DRM_FORMAT_RGBX5551, 249 DRM_FORMAT_ARGB4444, 250 DRM_FORMAT_RGBA4444, 251 DRM_FORMAT_RGBX4444, 252 DRM_FORMAT_XRGB4444, 253 DRM_FORMAT_BGR888, 254 DRM_FORMAT_BGRA8888, 255 DRM_FORMAT_BGRX8888, 256 DRM_FORMAT_ABGR1555, 257 DRM_FORMAT_BGRA5551, 258 DRM_FORMAT_XBGR1555, 259 DRM_FORMAT_BGRX5551, 260 DRM_FORMAT_ABGR4444, 261 DRM_FORMAT_BGRA4444, 262 DRM_FORMAT_BGRX4444, 263 DRM_FORMAT_XBGR4444, 264 }; 265 266 static const u32 wb2_formats_rgb_yuv[] = { 267 DRM_FORMAT_RGB565, 268 DRM_FORMAT_BGR565, 269 DRM_FORMAT_RGB888, 270 DRM_FORMAT_ARGB8888, 271 DRM_FORMAT_RGBA8888, 272 DRM_FORMAT_ABGR8888, 273 DRM_FORMAT_XRGB8888, 274 DRM_FORMAT_RGBX8888, 275 DRM_FORMAT_XBGR8888, 276 DRM_FORMAT_ARGB1555, 277 DRM_FORMAT_RGBA5551, 278 DRM_FORMAT_XRGB1555, 279 DRM_FORMAT_RGBX5551, 280 DRM_FORMAT_ARGB4444, 281 DRM_FORMAT_RGBA4444, 282 DRM_FORMAT_RGBX4444, 283 DRM_FORMAT_XRGB4444, 284 DRM_FORMAT_BGR888, 285 DRM_FORMAT_BGRA8888, 286 DRM_FORMAT_BGRX8888, 287 DRM_FORMAT_ABGR1555, 288 DRM_FORMAT_BGRA5551, 289 DRM_FORMAT_XBGR1555, 290 DRM_FORMAT_BGRX5551, 291 DRM_FORMAT_ABGR4444, 292 DRM_FORMAT_BGRA4444, 293 DRM_FORMAT_BGRX4444, 294 DRM_FORMAT_XBGR4444, 295 DRM_FORMAT_NV12, 296 }; 297 298 /************************************************************* 299 * SSPP sub blocks config 300 *************************************************************/ 301 302 #define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min)) 303 304 /* SSPP common configuration */ 305 #define _VIG_SBLK(scaler_ver) \ 306 { \ 307 .scaler_blk = {.name = "scaler", \ 308 .version = scaler_ver, \ 309 .base = 0xa00, .len = 0xa0,}, \ 310 .csc_blk = {.name = "csc", \ 311 .base = 0x1a00, .len = 0x100,}, \ 312 .format_list = plane_formats_yuv, \ 313 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 314 .rotation_cfg = NULL, \ 315 } 316 317 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ 318 { \ 319 .scaler_blk = {.name = "scaler", \ 320 .version = scaler_ver, \ 321 .base = 0xa00, .len = 0xa0,}, \ 322 .csc_blk = {.name = "csc", \ 323 .base = 0x1a00, .len = 0x100,}, \ 324 .format_list = plane_formats_yuv, \ 325 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 326 .rotation_cfg = rot_cfg, \ 327 } 328 329 #define _VIG_SBLK_NOSCALE() \ 330 { \ 331 .format_list = plane_formats, \ 332 .num_formats = ARRAY_SIZE(plane_formats), \ 333 } 334 335 /* qseed2 is not supported, so disabled scaling */ 336 #define _VIG_SBLK_QSEED2() \ 337 { \ 338 .scaler_blk = {.name = "scaler", \ 339 /* no version for qseed2 */ \ 340 .base = 0x200, .len = 0xa0,}, \ 341 .csc_blk = {.name = "csc", \ 342 .base = 0x320, .len = 0x100,}, \ 343 .format_list = plane_formats_yuv, \ 344 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 345 .rotation_cfg = NULL, \ 346 } 347 348 #define _RGB_SBLK() \ 349 { \ 350 .scaler_blk = {.name = "scaler", \ 351 .base = 0x200, .len = 0x28,}, \ 352 .format_list = plane_formats, \ 353 .num_formats = ARRAY_SIZE(plane_formats), \ 354 } 355 356 #define _DMA_SBLK() \ 357 { \ 358 .format_list = plane_formats, \ 359 .num_formats = ARRAY_SIZE(plane_formats), \ 360 } 361 362 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 363 .rot_maxheight = 1088, 364 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 365 .rot_format_list = rotation_v2_formats, 366 }; 367 368 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed2 = 369 _VIG_SBLK_QSEED2(); 370 371 static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale = 372 _VIG_SBLK_NOSCALE(); 373 374 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 = 375 _VIG_SBLK(SSPP_SCALER_VER(1, 2)); 376 377 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 = 378 _VIG_SBLK(SSPP_SCALER_VER(1, 3)); 379 380 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 = 381 _VIG_SBLK(SSPP_SCALER_VER(1, 4)); 382 383 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 = 384 _VIG_SBLK(SSPP_SCALER_VER(2, 4)); 385 386 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 = 387 _VIG_SBLK(SSPP_SCALER_VER(3, 0)); 388 389 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 = 390 _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0), 391 &dpu_rot_sc7280_cfg_v2); 392 393 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 = 394 _VIG_SBLK(SSPP_SCALER_VER(3, 1)); 395 396 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 = 397 _VIG_SBLK(SSPP_SCALER_VER(3, 2)); 398 399 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 = 400 _VIG_SBLK(SSPP_SCALER_VER(3, 3)); 401 402 static const struct dpu_sspp_sub_blks dpu_rgb_sblk = _RGB_SBLK(); 403 404 static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK(); 405 406 /************************************************************* 407 * MIXER sub blocks config 408 *************************************************************/ 409 410 /* MSM8998 */ 411 412 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 413 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 414 .maxblendstages = 7, /* excluding base layer */ 415 .blendstage_base = { /* offsets relative to mixer base */ 416 0x20, 0x50, 0x80, 0xb0, 0x230, 417 0x260, 0x290 418 }, 419 }; 420 421 /* SDM845 */ 422 423 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 424 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 425 .maxblendstages = 11, /* excluding base layer */ 426 .blendstage_base = { /* offsets relative to mixer base */ 427 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 428 0xb0, 0xc8, 0xe0, 0xf8, 0x110 429 }, 430 }; 431 432 /* SC7180 */ 433 434 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 435 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 436 .maxblendstages = 7, /* excluding base layer */ 437 .blendstage_base = { /* offsets relative to mixer base */ 438 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 439 }, 440 }; 441 442 /* QCM2290 */ 443 444 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 445 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 446 .maxblendstages = 4, /* excluding base layer */ 447 .blendstage_base = { /* offsets relative to mixer base */ 448 0x20, 0x38, 0x50, 0x68 449 }, 450 }; 451 452 /************************************************************* 453 * DSPP sub blocks config 454 *************************************************************/ 455 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 456 .pcc = {.name = "pcc", .base = 0x1700, 457 .len = 0x90, .version = 0x10007}, 458 }; 459 460 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 461 .pcc = {.name = "pcc", .base = 0x1700, 462 .len = 0x90, .version = 0x40000}, 463 }; 464 465 /************************************************************* 466 * PINGPONG sub blocks config 467 *************************************************************/ 468 static const struct dpu_pingpong_sub_blks msm8996_pp_sblk_te = { 469 .te2 = {.name = "te2", .base = 0x2000, .len = 0x0, 470 .version = 0x1}, 471 }; 472 473 static const struct dpu_pingpong_sub_blks msm8996_pp_sblk = { 474 /* No dither block */ 475 }; 476 477 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 478 .te2 = {.name = "te2", .base = 0x2000, .len = 0x0, 479 .version = 0x1}, 480 .dither = {.name = "dither", .base = 0x30e0, 481 .len = 0x20, .version = 0x10000}, 482 }; 483 484 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 485 .dither = {.name = "dither", .base = 0x30e0, 486 .len = 0x20, .version = 0x10000}, 487 }; 488 489 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 490 .dither = {.name = "dither", .base = 0xe0, 491 .len = 0x20, .version = 0x20000}, 492 }; 493 494 /************************************************************* 495 * DSC sub blocks config 496 *************************************************************/ 497 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 498 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 499 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 500 }; 501 502 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 503 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 504 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 505 }; 506 507 /************************************************************* 508 * CDM block config 509 *************************************************************/ 510 static const struct dpu_cdm_cfg sc7280_cdm = { 511 .name = "cdm_0", 512 .id = CDM_0, 513 .len = 0x228, 514 .base = 0x79200, 515 }; 516 517 /************************************************************* 518 * VBIF sub blocks config 519 *************************************************************/ 520 /* VBIF QOS remap */ 521 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 522 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 523 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 524 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 525 static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 5, 6}; 526 527 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 528 { 529 .pps = 1920 * 1080 * 30, 530 .ot_limit = 2, 531 }, 532 { 533 .pps = 1920 * 1080 * 60, 534 .ot_limit = 4, 535 }, 536 { 537 .pps = 3840 * 2160 * 30, 538 .ot_limit = 16, 539 }, 540 }; 541 542 static const struct dpu_vbif_cfg msm8996_vbif[] = { 543 { 544 .name = "vbif_rt", .id = VBIF_RT, 545 .base = 0, .len = 0x1040, 546 .default_ot_rd_limit = 32, 547 .default_ot_wr_limit = 16, 548 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 549 .xin_halt_timeout = 0x4000, 550 .qos_rp_remap_size = 0x20, 551 .dynamic_ot_rd_tbl = { 552 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 553 .cfg = msm8998_ot_rdwr_cfg, 554 }, 555 .dynamic_ot_wr_tbl = { 556 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 557 .cfg = msm8998_ot_rdwr_cfg, 558 }, 559 .qos_rt_tbl = { 560 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 561 .priority_lvl = msm8998_rt_pri_lvl, 562 }, 563 .qos_nrt_tbl = { 564 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 565 .priority_lvl = msm8998_nrt_pri_lvl, 566 }, 567 }, 568 }; 569 570 static const struct dpu_vbif_cfg msm8998_vbif[] = { 571 { 572 .name = "vbif_rt", .id = VBIF_RT, 573 .base = 0, .len = 0x1040, 574 .default_ot_rd_limit = 32, 575 .default_ot_wr_limit = 32, 576 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 577 .xin_halt_timeout = 0x4000, 578 .qos_rp_remap_size = 0x20, 579 .dynamic_ot_rd_tbl = { 580 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 581 .cfg = msm8998_ot_rdwr_cfg, 582 }, 583 .dynamic_ot_wr_tbl = { 584 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 585 .cfg = msm8998_ot_rdwr_cfg, 586 }, 587 .qos_rt_tbl = { 588 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 589 .priority_lvl = msm8998_rt_pri_lvl, 590 }, 591 .qos_nrt_tbl = { 592 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 593 .priority_lvl = msm8998_nrt_pri_lvl, 594 }, 595 .memtype_count = 14, 596 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 597 }, 598 }; 599 600 static const struct dpu_vbif_cfg sdm845_vbif[] = { 601 { 602 .name = "vbif_rt", .id = VBIF_RT, 603 .base = 0, .len = 0x1040, 604 .features = BIT(DPU_VBIF_QOS_REMAP), 605 .xin_halt_timeout = 0x4000, 606 .qos_rp_remap_size = 0x40, 607 .qos_rt_tbl = { 608 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 609 .priority_lvl = sdm845_rt_pri_lvl, 610 }, 611 .qos_nrt_tbl = { 612 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 613 .priority_lvl = sdm845_nrt_pri_lvl, 614 }, 615 .memtype_count = 14, 616 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 617 }, 618 }; 619 620 static const struct dpu_vbif_cfg sm8550_vbif[] = { 621 { 622 .name = "vbif_rt", .id = VBIF_RT, 623 .base = 0, .len = 0x1040, 624 .features = BIT(DPU_VBIF_QOS_REMAP), 625 .xin_halt_timeout = 0x4000, 626 .qos_rp_remap_size = 0x40, 627 .qos_rt_tbl = { 628 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 629 .priority_lvl = sdm845_rt_pri_lvl, 630 }, 631 .qos_nrt_tbl = { 632 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 633 .priority_lvl = sdm845_nrt_pri_lvl, 634 }, 635 .memtype_count = 16, 636 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 637 }, 638 }; 639 640 static const struct dpu_vbif_cfg sm8650_vbif[] = { 641 { 642 .name = "vbif_rt", .id = VBIF_RT, 643 .base = 0, .len = 0x1074, 644 .features = BIT(DPU_VBIF_QOS_REMAP), 645 .xin_halt_timeout = 0x4000, 646 .qos_rp_remap_size = 0x40, 647 .qos_rt_tbl = { 648 .npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl), 649 .priority_lvl = sm8650_rt_pri_lvl, 650 }, 651 .qos_nrt_tbl = { 652 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 653 .priority_lvl = sdm845_nrt_pri_lvl, 654 }, 655 .memtype_count = 16, 656 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 657 }, 658 }; 659 660 /************************************************************* 661 * PERF data config 662 *************************************************************/ 663 664 /* SSPP QOS LUTs */ 665 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 666 {.fl = 4, .lut = 0x1b}, 667 {.fl = 5, .lut = 0x5b}, 668 {.fl = 6, .lut = 0x15b}, 669 {.fl = 7, .lut = 0x55b}, 670 {.fl = 8, .lut = 0x155b}, 671 {.fl = 9, .lut = 0x555b}, 672 {.fl = 10, .lut = 0x1555b}, 673 {.fl = 11, .lut = 0x5555b}, 674 {.fl = 12, .lut = 0x15555b}, 675 {.fl = 0, .lut = 0x55555b} 676 }; 677 678 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 679 {.fl = 4, .lut = 0x357}, 680 {.fl = 5, .lut = 0x3357}, 681 {.fl = 6, .lut = 0x23357}, 682 {.fl = 7, .lut = 0x223357}, 683 {.fl = 8, .lut = 0x2223357}, 684 {.fl = 9, .lut = 0x22223357}, 685 {.fl = 10, .lut = 0x222223357}, 686 {.fl = 11, .lut = 0x2222223357}, 687 {.fl = 12, .lut = 0x22222223357}, 688 {.fl = 13, .lut = 0x222222223357}, 689 {.fl = 14, .lut = 0x1222222223357}, 690 {.fl = 0, .lut = 0x11222222223357} 691 }; 692 693 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 694 {.fl = 10, .lut = 0x1aaff}, 695 {.fl = 11, .lut = 0x5aaff}, 696 {.fl = 12, .lut = 0x15aaff}, 697 {.fl = 0, .lut = 0x55aaff}, 698 }; 699 700 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 701 {.fl = 0, .lut = 0x0011222222335777}, 702 }; 703 704 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 705 {.fl = 0, .lut = 0x0011223445566777 }, 706 }; 707 708 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 709 {.fl = 0, .lut = 0x0011222222223357 }, 710 }; 711 712 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 713 {.fl = 4, .lut = 0x0000000000000357 }, 714 }; 715 716 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 717 {.fl = 0, .lut = 0x0011222222335777}, 718 }; 719 720 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 721 {.fl = 10, .lut = 0x344556677}, 722 {.fl = 11, .lut = 0x3344556677}, 723 {.fl = 12, .lut = 0x23344556677}, 724 {.fl = 13, .lut = 0x223344556677}, 725 {.fl = 14, .lut = 0x1223344556677}, 726 {.fl = 0, .lut = 0x112233344556677}, 727 }; 728 729 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 730 {.fl = 0, .lut = 0x0011223344556677}, 731 }; 732 733 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 734 {.fl = 10, .lut = 0x0000000344556677}, 735 }; 736 737 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 738 {.fl = 0, .lut = 0x0}, 739 }; 740 741 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 742 {.fl = 0, .lut = 0x0}, 743 }; 744 745 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 746 {.fl = 0, .lut = 0x0}, 747 }; 748 749 /************************************************************* 750 * Hardware catalog 751 *************************************************************/ 752 753 #include "catalog/dpu_1_7_msm8996.h" 754 #include "catalog/dpu_1_14_msm8937.h" 755 #include "catalog/dpu_1_15_msm8917.h" 756 #include "catalog/dpu_1_16_msm8953.h" 757 758 #include "catalog/dpu_3_0_msm8998.h" 759 #include "catalog/dpu_3_2_sdm660.h" 760 #include "catalog/dpu_3_3_sdm630.h" 761 762 #include "catalog/dpu_4_0_sdm845.h" 763 #include "catalog/dpu_4_1_sdm670.h" 764 765 #include "catalog/dpu_5_0_sm8150.h" 766 #include "catalog/dpu_5_1_sc8180x.h" 767 #include "catalog/dpu_5_2_sm7150.h" 768 #include "catalog/dpu_5_4_sm6125.h" 769 770 #include "catalog/dpu_6_0_sm8250.h" 771 #include "catalog/dpu_6_2_sc7180.h" 772 #include "catalog/dpu_6_3_sm6115.h" 773 #include "catalog/dpu_6_4_sm6350.h" 774 #include "catalog/dpu_6_5_qcm2290.h" 775 #include "catalog/dpu_6_9_sm6375.h" 776 777 #include "catalog/dpu_7_0_sm8350.h" 778 #include "catalog/dpu_7_2_sc7280.h" 779 780 #include "catalog/dpu_8_0_sc8280xp.h" 781 #include "catalog/dpu_8_1_sm8450.h" 782 #include "catalog/dpu_8_4_sa8775p.h" 783 784 #include "catalog/dpu_9_0_sm8550.h" 785 786 #include "catalog/dpu_9_2_x1e80100.h" 787 788 #include "catalog/dpu_10_0_sm8650.h" 789