1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <linux/printk.h>
7 #include <linux/soc/qcom/ubwc.h>
8
9 #include "dpu_hw_sspp.h"
10
11 /* >= v13 DPU */
12 /* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */
13 /* Name Offset */
14 #define SSPP_CMN_CLK_CTRL 0x0
15 #define SSPP_CMN_CLK_STATUS 0x4
16 #define SSPP_CMN_MULTI_REC_OP_MODE 0x10
17 #define SSPP_CMN_ADDR_CONFIG 0x14
18 #define SSPP_CMN_CAC_CTRL 0x20
19 #define SSPP_CMN_SYS_CACHE_MODE 0x24
20 #define SSPP_CMN_QOS_CTRL 0x28
21
22 #define SSPP_CMN_FILL_LEVEL_SCALE 0x3c
23 #define SSPP_CMN_FILL_LEVELS 0x40
24 #define SSPP_CMN_STATUS 0x44
25 #define SSPP_CMN_FETCH_DMA_RD_OTS 0x48
26 #define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c
27 #define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50
28 #define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54
29 #define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58
30 #define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c
31 #define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60
32 #define SSPP_CMN_UNPACK_LINE_COUNT 0x64
33 #define SSPP_CMN_TPG_CONTROL 0x68
34 #define SSPP_CMN_TPG_CONFIG 0x6c
35 #define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70
36 #define SSPP_CMN_TPG_RECTANGLE 0x74
37 #define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78
38 #define SSPP_CMN_TPG_RGB_MAPPING 0x7c
39 #define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80
40
41 /*RECRegisterset*/
42 /*Name Offset*/
43 #define SSPP_REC_SRC_FORMAT 0x0
44 #define SSPP_REC_SRC_UNPACK_PATTERN 0x4
45 #define SSPP_REC_SRC_OP_MODE 0x8
46 #define SSPP_REC_SRC_CONSTANT_COLOR 0xc
47 #define SSPP_REC_SRC_IMG_SIZE 0x10
48 #define SSPP_REC_SRC_SIZE 0x14
49 #define SSPP_REC_SRC_XY 0x18
50 #define SSPP_REC_OUT_SIZE 0x1c
51 #define SSPP_REC_OUT_XY 0x20
52 #define SSPP_REC_SW_PIX_EXT_LR 0x24
53 #define SSPP_REC_SW_PIX_EXT_TB 0x28
54 #define SSPP_REC_SRC_SIZE_ODX 0x30
55 #define SSPP_REC_SRC_XY_ODX 0x34
56 #define SSPP_REC_OUT_SIZE_ODX 0x38
57 #define SSPP_REC_OUT_XY_ODX 0x3c
58 #define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40
59 #define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44
60 #define SSPP_REC_PRE_DOWN_SCALE 0x48
61 #define SSPP_REC_SRC0_ADDR 0x4c
62 #define SSPP_REC_SRC1_ADDR 0x50
63 #define SSPP_REC_SRC2_ADDR 0x54
64 #define SSPP_REC_SRC3_ADDR 0x58
65 #define SSPP_REC_SRC_YSTRIDE0 0x5c
66 #define SSPP_REC_SRC_YSTRIDE1 0x60
67 #define SSPP_REC_CURRENT_SRC0_ADDR 0x64
68 #define SSPP_REC_CURRENT_SRC1_ADDR 0x68
69 #define SSPP_REC_CURRENT_SRC2_ADDR 0x6c
70 #define SSPP_REC_CURRENT_SRC3_ADDR 0x70
71 #define SSPP_REC_SRC_ADDR_SW_STATUS 0x74
72 #define SSPP_REC_CDP_CNTL 0x78
73 #define SSPP_REC_TRAFFIC_SHAPER 0x7c
74 #define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80
75 #define SSPP_REC_PD_MEM_ALLOC 0x84
76 #define SSPP_REC_QOS_CLAMP 0x88
77 #define SSPP_REC_UIDLE_CTRL_VALUE 0x8c
78 #define SSPP_REC_UBWC_STATIC_CTRL 0x90
79 #define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94
80 #define SSPP_REC_UBWC_STATS_ROI 0x98
81 #define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c
82 #define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0
83 #define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4
84 #define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8
85 #define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac
86 #define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0
87 #define SSPP_REC_EXCL_REC_CTRL 0xb4
88 #define SSPP_REC_EXCL_REC_SIZE 0xb8
89 #define SSPP_REC_EXCL_REC_XY 0xbc
90 #define SSPP_REC_LINE_INSERTION_CTRL 0xc0
91 #define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4
92 #define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8
93 #define SSPP_REC_META_ERROR_STATUS 0xcc
94 #define SSPP_REC_UBWC_ERROR_STATUS 0xd0
95 #define SSPP_REC_FLUSH_CTRL 0xd4
96 #define SSPP_REC_INTR_EN 0xd8
97 #define SSPP_REC_INTR_STATUS 0xdc
98 #define SSPP_REC_INTR_CLEAR 0xe0
99 #define SSPP_REC_HSYNC_STATUS 0xe4
100 #define SSPP_REC_FP16_CONFIG 0x150
101 #define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154
102 #define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158
103 #define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c
104 #define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160
105 #define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164
106 #define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168
107 #define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c
108 #define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170
109 #define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174
110 #define SSPP_REC_FP16_CSC_POST_CLAMP 0x178
111
dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_index rect_index,struct dpu_hw_sspp * ctx)112 static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_index rect_index,
113 struct dpu_hw_sspp *ctx)
114 {
115 return (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) ?
116 ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base;
117 }
118
dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe * pipe)119 static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe)
120 {
121 struct dpu_hw_sspp *ctx = pipe->sspp;
122
123 if (!ctx)
124 return;
125
126 dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE);
127 }
128
dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe * pipe,const struct msm_format * fmt,u32 flags)129 static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe,
130 const struct msm_format *fmt, u32 flags)
131 {
132 struct dpu_hw_sspp *ctx = pipe->sspp;
133 u32 op_mode_off, unpack_pat_off, format_off;
134 u32 ubwc_ctrl_off, ubwc_err_off;
135 u32 offset;
136
137 if (!ctx || !fmt)
138 return;
139
140 offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
141
142 op_mode_off = offset + SSPP_REC_SRC_OP_MODE;
143 unpack_pat_off = offset + SSPP_REC_SRC_UNPACK_PATTERN;
144 format_off = offset + SSPP_REC_SRC_FORMAT;
145 ubwc_ctrl_off = offset + SSPP_REC_UBWC_STATIC_CTRL;
146 ubwc_err_off = offset + SSPP_REC_UBWC_ERROR_STATUS;
147
148 dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
149 unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off);
150 }
151
dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp * ctx,struct dpu_hw_pixel_ext * pe_ext)152 static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx,
153 struct dpu_hw_pixel_ext *pe_ext)
154 {
155 struct dpu_hw_blk_reg_map *c;
156 u8 color;
157 u32 lr_pe[4], tb_pe[4];
158 const u32 bytemask = 0xff;
159 u32 offset;
160
161 if (!ctx || !pe_ext)
162 return;
163
164 offset = ctx->cap->sblk->sspp_rec0_blk.base;
165
166 c = &ctx->hw;
167 /* program SW pixel extension override for all pipes*/
168 for (color = 0; color < DPU_MAX_PLANES; color++) {
169 /* color 2 has the same set of registers as color 1 */
170 if (color == 2)
171 continue;
172
173 lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24) |
174 ((pe_ext->right_rpt[color] & bytemask) << 16) |
175 ((pe_ext->left_ftch[color] & bytemask) << 8) |
176 (pe_ext->left_rpt[color] & bytemask);
177
178 tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24) |
179 ((pe_ext->btm_rpt[color] & bytemask) << 16) |
180 ((pe_ext->top_ftch[color] & bytemask) << 8) |
181 (pe_ext->top_rpt[color] & bytemask);
182 }
183
184 /* color 0 */
185 DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]);
186 DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]);
187
188 /* color 1 and color 2 */
189 DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]);
190 DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]);
191 }
192
dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * cfg)193 static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe,
194 struct dpu_sw_pipe_cfg *cfg)
195 {
196 struct dpu_hw_sspp *ctx = pipe->sspp;
197 u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
198 u32 offset;
199
200 if (!ctx || !cfg)
201 return;
202
203 offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
204
205 src_size_off = offset + SSPP_REC_SRC_SIZE;
206 src_xy_off = offset + SSPP_REC_SRC_XY;
207 out_size_off = offset + SSPP_REC_OUT_SIZE;
208 out_xy_off = offset + SSPP_REC_OUT_XY;
209
210 dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
211 src_xy_off, out_size_off, out_xy_off);
212 }
213
dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe * pipe,struct dpu_hw_fmt_layout * layout)214 static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe,
215 struct dpu_hw_fmt_layout *layout)
216 {
217 struct dpu_hw_sspp *ctx = pipe->sspp;
218 int i;
219 u32 offset, ystride0, ystride1;
220
221 if (!ctx)
222 return;
223
224 offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
225
226 for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++)
227 DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4,
228 layout->plane_addr[i]);
229
230 ystride0 = (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16);
231 ystride1 = (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16);
232
233 DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0);
234 DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1);
235 }
236
dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe * pipe,u32 color)237 static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 color)
238 {
239 struct dpu_hw_sspp *ctx = pipe->sspp;
240 u32 const_clr_off;
241 u32 offset;
242
243 if (!ctx)
244 return;
245
246 offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
247 const_clr_off = offset + SSPP_REC_SRC_CONSTANT_COLOR;
248
249 dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
250 }
251
dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp * ctx,struct dpu_hw_qos_cfg * cfg)252 static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx,
253 struct dpu_hw_qos_cfg *cfg)
254 {
255 if (!ctx || !cfg)
256 return;
257
258 dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg);
259 }
260
dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp * ctx,bool danger_safe_en)261 static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx,
262 bool danger_safe_en)
263 {
264 if (!ctx)
265 return;
266
267 dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL);
268 }
269
dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe * pipe,const struct msm_format * fmt,bool enable)270 static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe,
271 const struct msm_format *fmt,
272 bool enable)
273 {
274 struct dpu_hw_sspp *ctx = pipe->sspp;
275 u32 offset = 0;
276
277 if (!ctx)
278 return;
279
280 offset = dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx);
281 dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable);
282 }
283
dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp * ctx,bool enable)284 static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, bool enable)
285 {
286 static const struct dpu_clk_ctrl_reg sspp_clk_ctrl = {
287 .reg_off = SSPP_CMN_CLK_CTRL,
288 .bit_off = 0
289 };
290
291 return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable);
292 }
293
dpu_hw_sspp_init_v13(struct dpu_hw_sspp * c,unsigned long features,const struct dpu_mdss_version * mdss_rev)294 void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c,
295 unsigned long features, const struct dpu_mdss_version *mdss_rev)
296 {
297 c->ops.setup_format = dpu_hw_sspp_setup_format_v13;
298 c->ops.setup_rects = dpu_hw_sspp_setup_rects_v13;
299 c->ops.setup_sourceaddress = dpu_hw_sspp_setup_sourceaddress_v13;
300 c->ops.setup_solidfill = dpu_hw_sspp_setup_solidfill_v13;
301 c->ops.setup_pe = dpu_hw_sspp_setup_pe_config_v13;
302
303 if (test_bit(DPU_SSPP_QOS, &features)) {
304 c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut_v13;
305 c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl_v13;
306 }
307
308 if (test_bit(DPU_SSPP_CSC, &features) ||
309 test_bit(DPU_SSPP_CSC_10BIT, &features))
310 c->ops.setup_csc = dpu_hw_sspp_setup_csc;
311
312 if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) ||
313 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features))
314 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect_v13;
315
316 if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
317 c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
318
319 if (test_bit(DPU_SSPP_CDP, &features))
320 c->ops.setup_cdp = dpu_hw_sspp_setup_cdp_v13;
321
322 c->ops.setup_clk_force_ctrl = dpu_hw_sspp_setup_clk_force_ctrl_v13;
323 }
324