1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef SMU14_DRIVER_IF_V14_0_H 25 #define SMU14_DRIVER_IF_V14_0_H 26 27 //Increment this version if SkuTable_t or BoardTable_t change 28 #define PPTABLE_VERSION 0x18 29 30 #define NUM_GFXCLK_DPM_LEVELS 16 31 #define NUM_SOCCLK_DPM_LEVELS 8 32 #define NUM_MP0CLK_DPM_LEVELS 2 33 #define NUM_DCLK_DPM_LEVELS 8 34 #define NUM_VCLK_DPM_LEVELS 8 35 #define NUM_DISPCLK_DPM_LEVELS 8 36 #define NUM_DPPCLK_DPM_LEVELS 8 37 #define NUM_DPREFCLK_DPM_LEVELS 8 38 #define NUM_DCFCLK_DPM_LEVELS 8 39 #define NUM_DTBCLK_DPM_LEVELS 8 40 #define NUM_UCLK_DPM_LEVELS 6 41 #define NUM_LINK_LEVELS 3 42 #define NUM_FCLK_DPM_LEVELS 8 43 #define NUM_OD_FAN_MAX_POINTS 6 44 45 // Feature Control Defines 46 #define FEATURE_FW_DATA_READ_BIT 0 47 #define FEATURE_DPM_GFXCLK_BIT 1 48 #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT 2 49 #define FEATURE_DPM_UCLK_BIT 3 50 #define FEATURE_DPM_FCLK_BIT 4 51 #define FEATURE_DPM_SOCCLK_BIT 5 52 #define FEATURE_DPM_LINK_BIT 6 53 #define FEATURE_DPM_DCN_BIT 7 54 #define FEATURE_VMEMP_SCALING_BIT 8 55 #define FEATURE_VDDIO_MEM_SCALING_BIT 9 56 #define FEATURE_DS_GFXCLK_BIT 10 57 #define FEATURE_DS_SOCCLK_BIT 11 58 #define FEATURE_DS_FCLK_BIT 12 59 #define FEATURE_DS_LCLK_BIT 13 60 #define FEATURE_DS_DCFCLK_BIT 14 61 #define FEATURE_DS_UCLK_BIT 15 62 #define FEATURE_GFX_ULV_BIT 16 63 #define FEATURE_FW_DSTATE_BIT 17 64 #define FEATURE_GFXOFF_BIT 18 65 #define FEATURE_BACO_BIT 19 66 #define FEATURE_MM_DPM_BIT 20 67 #define FEATURE_SOC_MPCLK_DS_BIT 21 68 #define FEATURE_BACO_MPCLK_DS_BIT 22 69 #define FEATURE_THROTTLERS_BIT 23 70 #define FEATURE_SMARTSHIFT_BIT 24 71 #define FEATURE_GTHR_BIT 25 72 #define FEATURE_ACDC_BIT 26 73 #define FEATURE_VR0HOT_BIT 27 74 #define FEATURE_FW_CTF_BIT 28 75 #define FEATURE_FAN_CONTROL_BIT 29 76 #define FEATURE_GFX_DCS_BIT 30 77 #define FEATURE_GFX_READ_MARGIN_BIT 31 78 #define FEATURE_LED_DISPLAY_BIT 32 79 #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT 33 80 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 34 81 #define FEATURE_OPTIMIZED_VMIN_BIT 35 82 #define FEATURE_GFX_IMU_BIT 36 83 #define FEATURE_BOOT_TIME_CAL_BIT 37 84 #define FEATURE_GFX_PCC_DFLL_BIT 38 85 #define FEATURE_SOC_CG_BIT 39 86 #define FEATURE_DF_CSTATE_BIT 40 87 #define FEATURE_GFX_EDC_BIT 41 88 #define FEATURE_BOOT_POWER_OPT_BIT 42 89 #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT 43 90 #define FEATURE_DS_VCN_BIT 44 91 #define FEATURE_BACO_CG_BIT 45 92 #define FEATURE_MEM_TEMP_READ_BIT 46 93 #define FEATURE_ATHUB_MMHUB_PG_BIT 47 94 #define FEATURE_SOC_PCC_BIT 48 95 #define FEATURE_EDC_PWRBRK_BIT 49 96 #define FEATURE_SOC_EDC_XVMIN_BIT 50 97 #define FEATURE_GFX_PSM_DIDT_BIT 51 98 #define FEATURE_APT_ALL_ENABLE_BIT 52 99 #define FEATURE_APT_SQ_THROTTLE_BIT 53 100 #define FEATURE_APT_PF_DCS_BIT 54 101 #define FEATURE_GFX_EDC_XVMIN_BIT 55 102 #define FEATURE_GFX_DIDT_XVMIN_BIT 56 103 #define FEATURE_FAN_ABNORMAL_BIT 57 104 #define FEATURE_CLOCK_STRETCH_COMPENSATOR 58 105 #define FEATURE_SPARE_59_BIT 59 106 #define FEATURE_SPARE_60_BIT 60 107 #define FEATURE_SPARE_61_BIT 61 108 #define FEATURE_SPARE_62_BIT 62 109 #define FEATURE_SPARE_63_BIT 63 110 #define NUM_FEATURES 64 111 112 #define ALLOWED_FEATURE_CTRL_DEFAULT 0xFFFFFFFFFFFFFFFFULL 113 #define ALLOWED_FEATURE_CTRL_SCPM (1 << FEATURE_DPM_GFXCLK_BIT) | \ 114 (1 << FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT) | \ 115 (1 << FEATURE_DPM_UCLK_BIT) | \ 116 (1 << FEATURE_DPM_FCLK_BIT) | \ 117 (1 << FEATURE_DPM_SOCCLK_BIT) | \ 118 (1 << FEATURE_DPM_LINK_BIT) | \ 119 (1 << FEATURE_DPM_DCN_BIT) | \ 120 (1 << FEATURE_DS_GFXCLK_BIT) | \ 121 (1 << FEATURE_DS_SOCCLK_BIT) | \ 122 (1 << FEATURE_DS_FCLK_BIT) | \ 123 (1 << FEATURE_DS_LCLK_BIT) | \ 124 (1 << FEATURE_DS_DCFCLK_BIT) | \ 125 (1 << FEATURE_DS_UCLK_BIT) | \ 126 (1ULL << FEATURE_DS_VCN_BIT) 127 128 129 //For use with feature control messages 130 typedef enum { 131 FEATURE_PWR_ALL, 132 FEATURE_PWR_S5, 133 FEATURE_PWR_BACO, 134 FEATURE_PWR_SOC, 135 FEATURE_PWR_GFX, 136 FEATURE_PWR_DOMAIN_COUNT, 137 } FEATURE_PWR_DOMAIN_e; 138 139 //For use with feature control + BTC save restore 140 typedef enum { 141 FEATURE_BTC_NOP, 142 FEATURE_BTC_SAVE, 143 FEATURE_BTC_RESTORE, 144 FEATURE_BTC_COUNT, 145 } FEATURE_BTC_e; 146 147 // Debug Overrides Bitmask 148 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 149 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 150 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 151 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 152 #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x00000010 153 #define DEBUG_OVERRIDE_DISABLE_VCN_PG 0x00000020 154 #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX 0x00000040 155 #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS 0x00000080 156 #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK 0x00000100 157 #define DEBUG_OVERRIDE_DISABLE_DFLL 0x00000200 158 #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE 0x00000400 159 #define DEBUG_OVERRIDE_DFLL_MASTER_MODE 0x00000800 160 #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE 0x00001000 161 #define DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE 0x00002000 162 #define DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY 0x00004000 163 #define DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING 0x00008000 164 165 // VR Mapping Bit Defines 166 #define VR_MAPPING_VR_SELECT_MASK 0x01 167 #define VR_MAPPING_VR_SELECT_SHIFT 0x00 168 169 #define VR_MAPPING_PLANE_SELECT_MASK 0x02 170 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01 171 172 // PSI Bit Defines 173 #define PSI_SEL_VR0_PLANE0_PSI0 0x01 174 #define PSI_SEL_VR0_PLANE0_PSI1 0x02 175 #define PSI_SEL_VR0_PLANE1_PSI0 0x04 176 #define PSI_SEL_VR0_PLANE1_PSI1 0x08 177 #define PSI_SEL_VR1_PLANE0_PSI0 0x10 178 #define PSI_SEL_VR1_PLANE0_PSI1 0x20 179 #define PSI_SEL_VR1_PLANE1_PSI0 0x40 180 #define PSI_SEL_VR1_PLANE1_PSI1 0x80 181 182 typedef enum { 183 SVI_PSI_0, // Full phase count (default) 184 SVI_PSI_1, // Phase count 1st level 185 SVI_PSI_2, // Phase count 2nd level 186 SVI_PSI_3, // Single phase operation + active diode emulation 187 SVI_PSI_4, // Single phase operation + passive diode emulation *optional* 188 SVI_PSI_5, // Reserved 189 SVI_PSI_6, // Power down to 0V (voltage regulation disabled) 190 SVI_PSI_7, // Automated phase shedding and diode emulation 191 } SVI_PSI_e; 192 193 // Throttler Control/Status Bits 194 #define THROTTLER_TEMP_EDGE_BIT 0 195 #define THROTTLER_TEMP_HOTSPOT_BIT 1 196 #define THROTTLER_TEMP_HOTSPOT_GFX_BIT 2 197 #define THROTTLER_TEMP_HOTSPOT_SOC_BIT 3 198 #define THROTTLER_TEMP_MEM_BIT 4 199 #define THROTTLER_TEMP_VR_GFX_BIT 5 200 #define THROTTLER_TEMP_VR_SOC_BIT 6 201 #define THROTTLER_TEMP_VR_MEM0_BIT 7 202 #define THROTTLER_TEMP_VR_MEM1_BIT 8 203 #define THROTTLER_TEMP_LIQUID0_BIT 9 204 #define THROTTLER_TEMP_LIQUID1_BIT 10 205 #define THROTTLER_TEMP_PLX_BIT 11 206 #define THROTTLER_TDC_GFX_BIT 12 207 #define THROTTLER_TDC_SOC_BIT 13 208 #define THROTTLER_PPT0_BIT 14 209 #define THROTTLER_PPT1_BIT 15 210 #define THROTTLER_PPT2_BIT 16 211 #define THROTTLER_PPT3_BIT 17 212 #define THROTTLER_FIT_BIT 18 213 #define THROTTLER_GFX_APCC_PLUS_BIT 19 214 #define THROTTLER_GFX_DVO_BIT 20 215 #define THROTTLER_COUNT 21 216 217 // FW DState Features Control Bits 218 #define FW_DSTATE_SOC_ULV_BIT 0 219 #define FW_DSTATE_G6_HSR_BIT 1 220 #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT 2 221 #define FW_DSTATE_SMN_DS_BIT 3 222 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 4 223 #define FW_DSTATE_SOC_LIV_MIN_BIT 5 224 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 6 225 #define FW_DSTATE_MEM_PLL_PWRDN_BIT 7 226 #define FW_DSTATE_MALL_ALLOC_BIT 8 227 #define FW_DSTATE_MEM_PSI_BIT 9 228 #define FW_DSTATE_HSR_NON_STROBE_BIT 10 229 #define FW_DSTATE_MP0_ENTER_WFI_BIT 11 230 #define FW_DSTATE_MALL_FLUSH_BIT 12 231 #define FW_DSTATE_SOC_PSI_BIT 13 232 #define FW_DSTATE_MMHUB_INTERLOCK_BIT 14 233 #define FW_DSTATE_D0i3_2_QUIET_FW_BIT 15 234 #define FW_DSTATE_CLDO_PRG_BIT 16 235 #define FW_DSTATE_DF_PLL_PWRDN_BIT 17 236 237 //LED Display Mask & Control Bits 238 #define LED_DISPLAY_GFX_DPM_BIT 0 239 #define LED_DISPLAY_PCIE_BIT 1 240 #define LED_DISPLAY_ERROR_BIT 2 241 242 243 #define MEM_TEMP_READ_OUT_OF_BAND_BIT 0 244 #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT 1 245 #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT 2 246 247 typedef enum { 248 SMARTSHIFT_VERSION_1, 249 SMARTSHIFT_VERSION_2, 250 SMARTSHIFT_VERSION_3, 251 } SMARTSHIFT_VERSION_e; 252 253 typedef enum { 254 FOPT_CALC_AC_CALC_DC, 255 FOPT_PPTABLE_AC_CALC_DC, 256 FOPT_CALC_AC_PPTABLE_DC, 257 FOPT_PPTABLE_AC_PPTABLE_DC, 258 } FOPT_CALC_e; 259 260 typedef enum { 261 DRAM_BIT_WIDTH_DISABLED = 0, 262 DRAM_BIT_WIDTH_X_8 = 8, 263 DRAM_BIT_WIDTH_X_16 = 16, 264 DRAM_BIT_WIDTH_X_32 = 32, 265 DRAM_BIT_WIDTH_X_64 = 64, 266 DRAM_BIT_WIDTH_X_128 = 128, 267 DRAM_BIT_WIDTH_COUNT, 268 } DRAM_BIT_WIDTH_TYPE_e; 269 270 //I2C Interface 271 #define NUM_I2C_CONTROLLERS 8 272 273 #define I2C_CONTROLLER_ENABLED 1 274 #define I2C_CONTROLLER_DISABLED 0 275 276 #define MAX_SW_I2C_COMMANDS 24 277 278 typedef enum { 279 I2C_CONTROLLER_PORT_0 = 0, //CKSVII2C0 280 I2C_CONTROLLER_PORT_1 = 1, //CKSVII2C1 281 I2C_CONTROLLER_PORT_COUNT, 282 } I2cControllerPort_e; 283 284 typedef enum { 285 I2C_CONTROLLER_NAME_VR_GFX = 0, 286 I2C_CONTROLLER_NAME_VR_SOC, 287 I2C_CONTROLLER_NAME_VR_VMEMP, 288 I2C_CONTROLLER_NAME_VR_VDDIO, 289 I2C_CONTROLLER_NAME_LIQUID0, 290 I2C_CONTROLLER_NAME_LIQUID1, 291 I2C_CONTROLLER_NAME_PLX, 292 I2C_CONTROLLER_NAME_FAN_INTAKE, 293 I2C_CONTROLLER_NAME_COUNT, 294 } I2cControllerName_e; 295 296 typedef enum { 297 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 298 I2C_CONTROLLER_THROTTLER_VR_GFX, 299 I2C_CONTROLLER_THROTTLER_VR_SOC, 300 I2C_CONTROLLER_THROTTLER_VR_VMEMP, 301 I2C_CONTROLLER_THROTTLER_VR_VDDIO, 302 I2C_CONTROLLER_THROTTLER_LIQUID0, 303 I2C_CONTROLLER_THROTTLER_LIQUID1, 304 I2C_CONTROLLER_THROTTLER_PLX, 305 I2C_CONTROLLER_THROTTLER_FAN_INTAKE, 306 I2C_CONTROLLER_THROTTLER_INA3221, 307 I2C_CONTROLLER_THROTTLER_COUNT, 308 } I2cControllerThrottler_e; 309 310 typedef enum { 311 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5, 312 I2C_CONTROLLER_PROTOCOL_VR_IR35217, 313 I2C_CONTROLLER_PROTOCOL_TMP_MAX31875, 314 I2C_CONTROLLER_PROTOCOL_INA3221, 315 I2C_CONTROLLER_PROTOCOL_TMP_MAX6604, 316 I2C_CONTROLLER_PROTOCOL_COUNT, 317 } I2cControllerProtocol_e; 318 319 typedef struct { 320 uint8_t Enabled; 321 uint8_t Speed; 322 uint8_t SlaveAddress; 323 uint8_t ControllerPort; 324 uint8_t ControllerName; 325 uint8_t ThermalThrotter; 326 uint8_t I2cProtocol; 327 uint8_t PaddingConfig; 328 } I2cControllerConfig_t; 329 330 typedef enum { 331 I2C_PORT_SVD_SCL = 0, 332 I2C_PORT_GPIO, 333 } I2cPort_e; 334 335 typedef enum { 336 I2C_SPEED_FAST_50K = 0, //50 Kbits/s 337 I2C_SPEED_FAST_100K, //100 Kbits/s 338 I2C_SPEED_FAST_400K, //400 Kbits/s 339 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) 340 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) 341 I2C_SPEED_HIGH_2M, //2.3 Mbits/s 342 I2C_SPEED_COUNT, 343 } I2cSpeed_e; 344 345 typedef enum { 346 I2C_CMD_READ = 0, 347 I2C_CMD_WRITE, 348 I2C_CMD_COUNT, 349 } I2cCmdType_e; 350 351 #define CMDCONFIG_STOP_BIT 0 352 #define CMDCONFIG_RESTART_BIT 1 353 #define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write 354 355 #define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT) 356 #define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT) 357 #define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT) 358 359 typedef struct { 360 uint8_t ReadWriteData; //Return data for read. Data to send for write 361 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write 362 } SwI2cCmd_t; //SW I2C Command Table 363 364 typedef struct { 365 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1) 366 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select 367 uint8_t SlaveAddress; //Slave address of device 368 uint8_t NumCmds; //Number of commands 369 370 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; 371 } SwI2cRequest_t; // SW I2C Request Table 372 373 typedef struct { 374 SwI2cRequest_t SwI2cRequest; 375 376 uint32_t Spare[8]; 377 uint32_t MmHubPadding[8]; // SMU internal use 378 } SwI2cRequestExternal_t; 379 380 typedef struct { 381 uint64_t mca_umc_status; 382 uint64_t mca_umc_addr; 383 384 uint16_t ce_count_lo_chip; 385 uint16_t ce_count_hi_chip; 386 387 uint32_t eccPadding; 388 } EccInfo_t; 389 390 typedef struct { 391 EccInfo_t EccInfo[24]; 392 } EccInfoTable_t; 393 394 //D3HOT sequences 395 typedef enum { 396 BACO_SEQUENCE, 397 MSR_SEQUENCE, 398 BAMACO_SEQUENCE, 399 ULPS_SEQUENCE, 400 D3HOT_SEQUENCE_COUNT, 401 } D3HOTSequence_e; 402 403 //This is aligned with RSMU PGFSM Register Mapping 404 typedef enum { 405 PG_DYNAMIC_MODE = 0, 406 PG_STATIC_MODE, 407 } PowerGatingMode_e; 408 409 //This is aligned with RSMU PGFSM Register Mapping 410 typedef enum { 411 PG_POWER_DOWN = 0, 412 PG_POWER_UP, 413 } PowerGatingSettings_e; 414 415 typedef struct { 416 uint32_t a; // store in IEEE float format in this variable 417 uint32_t b; // store in IEEE float format in this variable 418 uint32_t c; // store in IEEE float format in this variable 419 } QuadraticInt_t; 420 421 typedef struct { 422 uint32_t m; // store in IEEE float format in this variable 423 uint32_t b; // store in IEEE float format in this variable 424 } LinearInt_t; 425 426 typedef struct { 427 uint32_t a; // store in IEEE float format in this variable 428 uint32_t b; // store in IEEE float format in this variable 429 uint32_t c; // store in IEEE float format in this variable 430 } DroopInt_t; 431 432 typedef enum { 433 DCS_ARCH_DISABLED, 434 DCS_ARCH_FADCS, 435 DCS_ARCH_ASYNC, 436 } DCS_ARCH_e; 437 438 //Only Clks that have DPM descriptors are listed here 439 typedef enum { 440 PPCLK_GFXCLK = 0, 441 PPCLK_SOCCLK, 442 PPCLK_UCLK, 443 PPCLK_FCLK, 444 PPCLK_DCLK_0, 445 PPCLK_VCLK_0, 446 PPCLK_DISPCLK, 447 PPCLK_DPPCLK, 448 PPCLK_DPREFCLK, 449 PPCLK_DCFCLK, 450 PPCLK_DTBCLK, 451 PPCLK_COUNT, 452 } PPCLK_e; 453 454 typedef enum { 455 VOLTAGE_MODE_PPTABLE = 0, 456 VOLTAGE_MODE_FUSES, 457 VOLTAGE_MODE_COUNT, 458 } VOLTAGE_MODE_e; 459 460 typedef enum { 461 AVFS_VOLTAGE_GFX = 0, 462 AVFS_VOLTAGE_SOC, 463 AVFS_VOLTAGE_COUNT, 464 } AVFS_VOLTAGE_TYPE_e; 465 466 typedef enum { 467 AVFS_TEMP_COLD = 0, 468 AVFS_TEMP_HOT, 469 AVFS_TEMP_COUNT, 470 } AVFS_TEMP_e; 471 472 typedef enum { 473 AVFS_D_G, 474 AVFS_D_COUNT, 475 } AVFS_D_e; 476 477 478 typedef enum { 479 UCLK_DIV_BY_1 = 0, 480 UCLK_DIV_BY_2, 481 UCLK_DIV_BY_4, 482 UCLK_DIV_BY_8, 483 } UCLK_DIV_e; 484 485 typedef enum { 486 GPIO_INT_POLARITY_ACTIVE_LOW = 0, 487 GPIO_INT_POLARITY_ACTIVE_HIGH, 488 } GpioIntPolarity_e; 489 490 typedef enum { 491 PWR_CONFIG_TDP = 0, 492 PWR_CONFIG_TGP, 493 PWR_CONFIG_TCP_ESTIMATED, 494 PWR_CONFIG_TCP_MEASURED, 495 PWR_CONFIG_TBP_DESKTOP, 496 PWR_CONFIG_TBP_MOBILE, 497 } PwrConfig_e; 498 499 typedef struct { 500 uint8_t Padding; 501 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM 502 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used 503 uint8_t CalculateFopt; // Indication whether FW should calculate Fopt or use values below. Reference FOPT_CALC_e 504 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) 505 uint32_t Padding3[3]; 506 uint16_t Padding4; 507 uint16_t FoptimalDc; //Foptimal frequency in DC power mode. 508 uint16_t FoptimalAc; //Foptimal frequency in AC power mode. 509 uint16_t Padding2; 510 } DpmDescriptor_t; 511 512 typedef enum { 513 PPT_THROTTLER_PPT0, 514 PPT_THROTTLER_PPT1, 515 PPT_THROTTLER_PPT2, 516 PPT_THROTTLER_PPT3, 517 PPT_THROTTLER_COUNT 518 } PPT_THROTTLER_e; 519 520 typedef enum { 521 TEMP_EDGE, 522 TEMP_HOTSPOT, 523 TEMP_HOTSPOT_GFX, 524 TEMP_HOTSPOT_SOC, 525 TEMP_MEM, 526 TEMP_VR_GFX, 527 TEMP_VR_SOC, 528 TEMP_VR_MEM0, 529 TEMP_VR_MEM1, 530 TEMP_LIQUID0, 531 TEMP_LIQUID1, 532 TEMP_PLX, 533 TEMP_COUNT, 534 } TEMP_e; 535 536 typedef enum { 537 TDC_THROTTLER_GFX, 538 TDC_THROTTLER_SOC, 539 TDC_THROTTLER_COUNT 540 } TDC_THROTTLER_e; 541 542 typedef enum { 543 SVI_PLANE_VDD_GFX, 544 SVI_PLANE_VDD_SOC, 545 SVI_PLANE_VDDCI_MEM, 546 SVI_PLANE_VDDIO_MEM, 547 SVI_PLANE_COUNT, 548 } SVI_PLANE_e; 549 550 typedef enum { 551 PMFW_VOLT_PLANE_GFX, 552 PMFW_VOLT_PLANE_SOC, 553 PMFW_VOLT_PLANE_COUNT 554 } PMFW_VOLT_PLANE_e; 555 556 typedef enum { 557 CUSTOMER_VARIANT_ROW, 558 CUSTOMER_VARIANT_FALCON, 559 CUSTOMER_VARIANT_COUNT, 560 } CUSTOMER_VARIANT_e; 561 562 typedef enum { 563 POWER_SOURCE_AC, 564 POWER_SOURCE_DC, 565 POWER_SOURCE_COUNT, 566 } POWER_SOURCE_e; 567 568 typedef enum { 569 MEM_VENDOR_PLACEHOLDER0, // 0 570 MEM_VENDOR_SAMSUNG, // 1 571 MEM_VENDOR_INFINEON, // 2 572 MEM_VENDOR_ELPIDA, // 3 573 MEM_VENDOR_ETRON, // 4 574 MEM_VENDOR_NANYA, // 5 575 MEM_VENDOR_HYNIX, // 6 576 MEM_VENDOR_MOSEL, // 7 577 MEM_VENDOR_WINBOND, // 8 578 MEM_VENDOR_ESMT, // 9 579 MEM_VENDOR_PLACEHOLDER1, // 10 580 MEM_VENDOR_PLACEHOLDER2, // 11 581 MEM_VENDOR_PLACEHOLDER3, // 12 582 MEM_VENDOR_PLACEHOLDER4, // 13 583 MEM_VENDOR_PLACEHOLDER5, // 14 584 MEM_VENDOR_MICRON, // 15 585 MEM_VENDOR_COUNT, 586 } MEM_VENDOR_e; 587 588 typedef enum { 589 PP_GRTAVFS_HW_CPO_CTL_ZONE0, 590 PP_GRTAVFS_HW_CPO_CTL_ZONE1, 591 PP_GRTAVFS_HW_CPO_CTL_ZONE2, 592 PP_GRTAVFS_HW_CPO_CTL_ZONE3, 593 PP_GRTAVFS_HW_CPO_CTL_ZONE4, 594 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE0, 595 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE0, 596 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE1, 597 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE1, 598 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE2, 599 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE2, 600 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE3, 601 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE3, 602 PP_GRTAVFS_HW_CPO_EN_0_31_ZONE4, 603 PP_GRTAVFS_HW_CPO_EN_32_63_ZONE4, 604 PP_GRTAVFS_HW_ZONE0_VF, 605 PP_GRTAVFS_HW_ZONE1_VF1, 606 PP_GRTAVFS_HW_ZONE2_VF2, 607 PP_GRTAVFS_HW_ZONE3_VF3, 608 PP_GRTAVFS_HW_VOLTAGE_GB, 609 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE0, 610 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE1, 611 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE2, 612 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE3, 613 PP_GRTAVFS_HW_CPOSCALINGCTRL_ZONE4, 614 PP_GRTAVFS_HW_RESERVED_0, 615 PP_GRTAVFS_HW_RESERVED_1, 616 PP_GRTAVFS_HW_RESERVED_2, 617 PP_GRTAVFS_HW_RESERVED_3, 618 PP_GRTAVFS_HW_RESERVED_4, 619 PP_GRTAVFS_HW_RESERVED_5, 620 PP_GRTAVFS_HW_RESERVED_6, 621 PP_GRTAVFS_HW_FUSE_COUNT, 622 } PP_GRTAVFS_HW_FUSE_e; 623 624 typedef enum { 625 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_HOT_T0, 626 PP_GRTAVFS_FW_COMMON_PPVMIN_Z1_COLD_T0, 627 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_HOT_T0, 628 PP_GRTAVFS_FW_COMMON_PPVMIN_Z2_COLD_T0, 629 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_HOT_T0, 630 PP_GRTAVFS_FW_COMMON_PPVMIN_Z3_COLD_T0, 631 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_HOT_T0, 632 PP_GRTAVFS_FW_COMMON_PPVMIN_Z4_COLD_T0, 633 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z0, 634 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z1, 635 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z2, 636 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z3, 637 PP_GRTAVFS_FW_COMMON_SRAM_RM_Z4, 638 PP_GRTAVFS_FW_COMMON_FUSE_COUNT, 639 } PP_GRTAVFS_FW_COMMON_FUSE_e; 640 641 typedef enum { 642 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_NEG_1, 643 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_0, 644 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_1, 645 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_2, 646 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_3, 647 PP_GRTAVFS_FW_SEP_FUSE_GB1_PWL_VOLTAGE_4, 648 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_NEG_1, 649 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_0, 650 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_1, 651 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_2, 652 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_3, 653 PP_GRTAVFS_FW_SEP_FUSE_GB2_PWL_VOLTAGE_4, 654 PP_GRTAVFS_FW_SEP_FUSE_VF_NEG_1_FREQUENCY, 655 PP_GRTAVFS_FW_SEP_FUSE_VF4_FREQUENCY, 656 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_0, 657 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_1, 658 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_2, 659 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_3, 660 PP_GRTAVFS_FW_SEP_FUSE_FREQUENCY_TO_COUNT_SCALER_4, 661 PP_GRTAVFS_FW_SEP_FUSE_COUNT, 662 } PP_GRTAVFS_FW_SEP_FUSE_e; 663 664 #define PP_NUM_RTAVFS_PWL_ZONES 5 665 666 667 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 668 // Slope Q1.7, Offset Q1.2 669 typedef struct { 670 int8_t Offset; // in Amps 671 uint8_t Padding; 672 uint16_t MaxCurrent; // in Amps 673 } SviTelemetryScale_t; 674 675 #define PP_NUM_OD_VF_CURVE_POINTS PP_NUM_RTAVFS_PWL_ZONES + 1 676 677 #define PP_OD_FEATURE_GFX_VF_CURVE_BIT 0 678 #define PP_OD_FEATURE_GFX_VMAX_BIT 1 679 #define PP_OD_FEATURE_SOC_VMAX_BIT 2 680 #define PP_OD_FEATURE_PPT_BIT 3 681 #define PP_OD_FEATURE_FAN_CURVE_BIT 4 682 #define PP_OD_FEATURE_FAN_LEGACY_BIT 5 683 #define PP_OD_FEATURE_FULL_CTRL_BIT 6 684 #define PP_OD_FEATURE_TDC_BIT 7 685 #define PP_OD_FEATURE_GFXCLK_BIT 8 686 #define PP_OD_FEATURE_UCLK_BIT 9 687 #define PP_OD_FEATURE_FCLK_BIT 10 688 #define PP_OD_FEATURE_ZERO_FAN_BIT 11 689 #define PP_OD_FEATURE_TEMPERATURE_BIT 12 690 #define PP_OD_FEATURE_EDC_BIT 13 691 #define PP_OD_FEATURE_COUNT 14 692 693 typedef enum { 694 PP_OD_POWER_FEATURE_ALWAYS_ENABLED, 695 PP_OD_POWER_FEATURE_DISABLED_WHILE_GAMING, 696 PP_OD_POWER_FEATURE_ALWAYS_DISABLED, 697 } PP_OD_POWER_FEATURE_e; 698 699 typedef enum { 700 FAN_MODE_AUTO = 0, 701 FAN_MODE_MANUAL_LINEAR, 702 } FanMode_e; 703 704 typedef enum { 705 OD_NO_ERROR, 706 OD_REQUEST_ADVANCED_NOT_SUPPORTED, 707 OD_UNSUPPORTED_FEATURE, 708 OD_INVALID_FEATURE_COMBO_ERROR, 709 OD_GFXCLK_VF_CURVE_OFFSET_ERROR, 710 OD_VDD_GFX_VMAX_ERROR, 711 OD_VDD_SOC_VMAX_ERROR, 712 OD_PPT_ERROR, 713 OD_FAN_MIN_PWM_ERROR, 714 OD_FAN_ACOUSTIC_TARGET_ERROR, 715 OD_FAN_ACOUSTIC_LIMIT_ERROR, 716 OD_FAN_TARGET_TEMP_ERROR, 717 OD_FAN_ZERO_RPM_STOP_TEMP_ERROR, 718 OD_FAN_CURVE_PWM_ERROR, 719 OD_FAN_CURVE_TEMP_ERROR, 720 OD_FULL_CTRL_GFXCLK_ERROR, 721 OD_FULL_CTRL_UCLK_ERROR, 722 OD_FULL_CTRL_FCLK_ERROR, 723 OD_FULL_CTRL_VDD_GFX_ERROR, 724 OD_FULL_CTRL_VDD_SOC_ERROR, 725 OD_TDC_ERROR, 726 OD_GFXCLK_ERROR, 727 OD_UCLK_ERROR, 728 OD_FCLK_ERROR, 729 OD_OP_TEMP_ERROR, 730 OD_OP_GFX_EDC_ERROR, 731 OD_OP_GFX_PCC_ERROR, 732 OD_POWER_FEATURE_CTRL_ERROR, 733 } OD_FAIL_e; 734 735 typedef struct { 736 uint32_t FeatureCtrlMask; 737 738 //Voltage control 739 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 740 741 uint16_t VddGfxVmax; // in mV 742 uint16_t VddSocVmax; 743 744 uint8_t IdlePwrSavingFeaturesCtrl; 745 uint8_t RuntimePwrSavingFeaturesCtrl; 746 uint16_t Padding; 747 748 //Frequency changes 749 int16_t GfxclkFmin; // MHz 750 int16_t GfxclkFmax; // MHz 751 uint16_t UclkFmin; // MHz 752 uint16_t UclkFmax; // MHz 753 uint16_t FclkFmin; 754 uint16_t FclkFmax; 755 756 //PPT 757 int16_t Ppt; // % 758 int16_t Tdc; 759 760 //Fan control 761 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 762 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 763 uint16_t FanMinimumPwm; 764 uint16_t AcousticTargetRpmThreshold; 765 uint16_t AcousticLimitRpmThreshold; 766 uint16_t FanTargetTemperature; // Degree Celcius 767 uint8_t FanZeroRpmEnable; 768 uint8_t FanZeroRpmStopTemp; 769 uint8_t FanMode; 770 uint8_t MaxOpTemp; 771 772 uint8_t AdvancedOdModeEnabled; 773 uint8_t Padding1[3]; 774 775 uint16_t GfxVoltageFullCtrlMode; 776 uint16_t SocVoltageFullCtrlMode; 777 uint16_t GfxclkFullCtrlMode; 778 uint16_t UclkFullCtrlMode; 779 uint16_t FclkFullCtrlMode; 780 uint16_t Padding2; 781 782 int16_t GfxEdc; 783 int16_t GfxPccLimitControl; 784 785 uint32_t Spare[10]; 786 uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround 787 } OverDriveTable_t; 788 789 typedef struct { 790 OverDriveTable_t OverDriveTable; 791 792 } OverDriveTableExternal_t; 793 794 typedef struct { 795 uint32_t FeatureCtrlMask; 796 797 //Gfx Vf Curve 798 int16_t VoltageOffsetPerZoneBoundary[PP_NUM_OD_VF_CURVE_POINTS]; 799 //gfx Vmax 800 uint16_t VddGfxVmax; // in mV 801 //soc Vmax 802 uint16_t VddSocVmax; 803 804 //gfxclk 805 int16_t GfxclkFmin; // MHz 806 int16_t GfxclkFmax; // MHz 807 //uclk 808 uint16_t UclkFmin; // MHz 809 uint16_t UclkFmax; // MHz 810 //fclk 811 uint16_t FclkFmin; 812 uint16_t FclkFmax; 813 814 //PPT 815 int16_t Ppt; // % 816 //TDC 817 int16_t Tdc; 818 819 //Fan Curve 820 uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; 821 uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; 822 //Fan Legacy 823 uint16_t FanMinimumPwm; 824 uint16_t AcousticTargetRpmThreshold; 825 uint16_t AcousticLimitRpmThreshold; 826 uint16_t FanTargetTemperature; // Degree Celcius 827 //zero fan 828 uint8_t FanZeroRpmEnable; 829 //temperature 830 uint8_t MaxOpTemp; 831 uint8_t Padding[2]; 832 833 //Full Ctrl 834 uint16_t GfxVoltageFullCtrlMode; 835 uint16_t SocVoltageFullCtrlMode; 836 uint16_t GfxclkFullCtrlMode; 837 uint16_t UclkFullCtrlMode; 838 uint16_t FclkFullCtrlMode; 839 //EDC 840 int16_t GfxEdc; 841 int16_t GfxPccLimitControl; 842 int16_t Padding1; 843 844 uint32_t Spare[5]; 845 } OverDriveLimits_t; 846 847 typedef enum { 848 BOARD_GPIO_SMUIO_0, 849 BOARD_GPIO_SMUIO_1, 850 BOARD_GPIO_SMUIO_2, 851 BOARD_GPIO_SMUIO_3, 852 BOARD_GPIO_SMUIO_4, 853 BOARD_GPIO_SMUIO_5, 854 BOARD_GPIO_SMUIO_6, 855 BOARD_GPIO_SMUIO_7, 856 BOARD_GPIO_SMUIO_8, 857 BOARD_GPIO_SMUIO_9, 858 BOARD_GPIO_SMUIO_10, 859 BOARD_GPIO_SMUIO_11, 860 BOARD_GPIO_SMUIO_12, 861 BOARD_GPIO_SMUIO_13, 862 BOARD_GPIO_SMUIO_14, 863 BOARD_GPIO_SMUIO_15, 864 BOARD_GPIO_SMUIO_16, 865 BOARD_GPIO_SMUIO_17, 866 BOARD_GPIO_SMUIO_18, 867 BOARD_GPIO_SMUIO_19, 868 BOARD_GPIO_SMUIO_20, 869 BOARD_GPIO_SMUIO_21, 870 BOARD_GPIO_SMUIO_22, 871 BOARD_GPIO_SMUIO_23, 872 BOARD_GPIO_SMUIO_24, 873 BOARD_GPIO_SMUIO_25, 874 BOARD_GPIO_SMUIO_26, 875 BOARD_GPIO_SMUIO_27, 876 BOARD_GPIO_SMUIO_28, 877 BOARD_GPIO_SMUIO_29, 878 BOARD_GPIO_SMUIO_30, 879 BOARD_GPIO_SMUIO_31, 880 MAX_BOARD_GPIO_SMUIO_NUM, 881 BOARD_GPIO_DC_GEN_A, 882 BOARD_GPIO_DC_GEN_B, 883 BOARD_GPIO_DC_GEN_C, 884 BOARD_GPIO_DC_GEN_D, 885 BOARD_GPIO_DC_GEN_E, 886 BOARD_GPIO_DC_GEN_F, 887 BOARD_GPIO_DC_GEN_G, 888 BOARD_GPIO_DC_GENLK_CLK, 889 BOARD_GPIO_DC_GENLK_VSYNC, 890 BOARD_GPIO_DC_SWAPLOCK_A, 891 BOARD_GPIO_DC_SWAPLOCK_B, 892 MAX_BOARD_DC_GPIO_NUM, 893 BOARD_GPIO_LV_EN, 894 } BOARD_GPIO_TYPE_e; 895 896 #define INVALID_BOARD_GPIO 0xFF 897 898 899 typedef struct { 900 //PLL 0 901 uint16_t InitImuClk; 902 uint16_t InitSocclk; 903 uint16_t InitMpioclk; 904 uint16_t InitSmnclk; 905 //PLL 1 906 uint16_t InitDispClk; 907 uint16_t InitDppClk; 908 uint16_t InitDprefclk; 909 uint16_t InitDcfclk; 910 uint16_t InitDtbclk; 911 uint16_t InitDbguSocClk; 912 //PLL 2 913 uint16_t InitGfxclk_bypass; 914 uint16_t InitMp1clk; 915 uint16_t InitLclk; 916 uint16_t InitDbguBacoClk; 917 uint16_t InitBaco400clk; 918 uint16_t InitBaco1200clk_bypass; 919 uint16_t InitBaco700clk_bypass; 920 uint16_t InitBaco500clk; 921 // PLL 3 922 uint16_t InitDclk0; 923 uint16_t InitVclk0; 924 // PLL 4 925 uint16_t InitFclk; 926 uint16_t Padding1; 927 // PLL 5 928 //UCLK clocks, assumed all UCLK instances will be the same. 929 uint8_t InitUclkLevel; // =0,1,2,3,4,5 frequency from FreqTableUclk 930 931 uint8_t Padding[3]; 932 933 uint32_t InitVcoFreqPll0; //smu_socclk_t 934 uint32_t InitVcoFreqPll1; //smu_displayclk_t 935 uint32_t InitVcoFreqPll2; //smu_nbioclk_t 936 uint32_t InitVcoFreqPll3; //smu_vcnclk_t 937 uint32_t InitVcoFreqPll4; //smu_fclk_t 938 uint32_t InitVcoFreqPll5; //smu_uclk_01_t 939 uint32_t InitVcoFreqPll6; //smu_uclk_23_t 940 uint32_t InitVcoFreqPll7; //smu_uclk_45_t 941 uint32_t InitVcoFreqPll8; //smu_uclk_67_t 942 943 //encoding will be SVI3 944 uint16_t InitGfx; // In mV(Q2) , should be 0? 945 uint16_t InitSoc; // In mV(Q2) 946 uint16_t InitVddIoMem; // In mV(Q2) MemVdd 947 uint16_t InitVddCiMem; // In mV(Q2) VMemP 948 949 //uint16_t Padding2; 950 951 uint32_t Spare[8]; 952 } BootValues_t; 953 954 typedef struct { 955 uint16_t Power[PPT_THROTTLER_COUNT][POWER_SOURCE_COUNT]; // Watts 956 uint16_t Tdc[TDC_THROTTLER_COUNT]; // Amps 957 958 uint16_t Temperature[TEMP_COUNT]; // Celsius 959 960 uint8_t PwmLimitMin; 961 uint8_t PwmLimitMax; 962 uint8_t FanTargetTemperature; 963 uint8_t Spare1[1]; 964 965 uint16_t AcousticTargetRpmThresholdMin; 966 uint16_t AcousticTargetRpmThresholdMax; 967 968 uint16_t AcousticLimitRpmThresholdMin; 969 uint16_t AcousticLimitRpmThresholdMax; 970 971 uint16_t PccLimitMin; 972 uint16_t PccLimitMax; 973 974 uint16_t FanStopTempMin; 975 uint16_t FanStopTempMax; 976 uint16_t FanStartTempMin; 977 uint16_t FanStartTempMax; 978 979 uint16_t PowerMinPpt0[POWER_SOURCE_COUNT]; 980 uint32_t Spare[11]; 981 } MsgLimits_t; 982 983 typedef struct { 984 uint16_t BaseClockAc; 985 uint16_t GameClockAc; 986 uint16_t BoostClockAc; 987 uint16_t BaseClockDc; 988 uint16_t GameClockDc; 989 uint16_t BoostClockDc; 990 991 uint32_t Reserved[4]; 992 } DriverReportedClocks_t; 993 994 typedef struct { 995 uint8_t DcBtcEnabled; 996 uint8_t Padding[3]; 997 998 uint16_t DcTol; // mV Q2 999 uint16_t DcBtcGb; // mV Q2 1000 1001 uint16_t DcBtcMin; // mV Q2 1002 uint16_t DcBtcMax; // mV Q2 1003 1004 LinearInt_t DcBtcGbScalar; 1005 } AvfsDcBtcParams_t; 1006 1007 typedef struct { 1008 uint16_t AvfsTemp[AVFS_TEMP_COUNT]; //in degrees C 1009 uint16_t VftFMin; // in MHz 1010 uint16_t VInversion; // in mV Q2 1011 QuadraticInt_t qVft[AVFS_TEMP_COUNT]; 1012 QuadraticInt_t qAvfsGb; 1013 QuadraticInt_t qAvfsGb2; 1014 } AvfsFuseOverride_t; 1015 1016 //all settings maintained by PFE team 1017 typedef struct { 1018 uint8_t Version; 1019 uint8_t Spare8[3]; 1020 // SECTION: Feature Control 1021 uint32_t FeaturesToRun[NUM_FEATURES / 32]; // Features that PMFW will attempt to enable. Use FEATURE_*_BIT as mapping 1022 // SECTION: FW DSTATE Settings 1023 uint32_t FwDStateMask; // See FW_DSTATE_*_BIT for mapping 1024 // SECTION: Advanced Options 1025 uint32_t DebugOverrides; 1026 1027 uint32_t Spare[2]; 1028 } PFE_Settings_t; 1029 1030 typedef struct { 1031 // SECTION: Version 1032 uint32_t Version; // should be unique to each SKU(i.e if any value changes in below structure then this value must be different) 1033 1034 // SECTION: Miscellaneous Configuration 1035 uint8_t TotalPowerConfig; // Determines how PMFW calculates the power. Use defines from PwrConfig_e 1036 uint8_t CustomerVariant; //To specify if this PPTable is intended for a particular customer. Use defines from CUSTOMER_VARIANT_e 1037 uint8_t MemoryTemperatureTypeMask; // Bit mapping indicating which methods of memory temperature reading are enabled. Use defines from MEM_TEMP_*BIT 1038 uint8_t SmartShiftVersion; // Determine what SmartShift feature version is supported Use defines from SMARTSHIFT_VERSION_e 1039 1040 // SECTION: Infrastructure Limits 1041 uint8_t SocketPowerLimitSpare[10]; 1042 1043 //if set to 1, SocketPowerLimitAc and SocketPowerLimitDc will be interpreted as legacy programs(i.e absolute power). If 0, all except index 0 will be scalars 1044 //relative index 0 1045 uint8_t EnableLegacyPptLimit; 1046 uint8_t UseInputTelemetry; //applicable to SVI3 only and only to be set if VRs support 1047 1048 uint8_t SmartShiftMinReportedPptinDcs; //minimum possible active power consumption for this SKU. Used for SmartShift power reporting 1049 1050 uint8_t PaddingPpt[7]; 1051 1052 uint16_t HwCtfTempLimit; // In degrees Celsius. Temperature above which HW will trigger CTF. Consumed by VBIOS only 1053 1054 uint16_t PaddingInfra; 1055 1056 // Per year normalized Vmax state failure rates (sum of the two domains divided by life time in years) 1057 uint32_t FitControllerFailureRateLimit; //in IEEE float 1058 //Expected GFX Duty Cycle at Vmax. 1059 uint32_t FitControllerGfxDutyCycle; // in IEEE float 1060 //Expected SOC Duty Cycle at Vmax. 1061 uint32_t FitControllerSocDutyCycle; // in IEEE float 1062 1063 //This offset will be deducted from the controller output to before it goes through the SOC Vset limiter block. 1064 uint32_t FitControllerSocOffset; //in IEEE float 1065 1066 uint32_t GfxApccPlusResidencyLimit; // Percentage value. Used by APCC+ controller to control PCC residency to some value 1067 1068 // SECTION: Throttler settings 1069 uint32_t ThrottlerControlMask; // See THROTTLER_*_BIT for mapping 1070 1071 1072 // SECTION: Voltage Control Parameters 1073 uint16_t UlvVoltageOffset[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2). ULV offset used in either GFX_ULV or SOC_ULV(part of FW_DSTATE) 1074 1075 uint8_t Padding[2]; 1076 uint16_t DeepUlvVoltageOffsetSoc; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC as part of FW_DSTATE 1077 1078 // Voltage Limits 1079 uint16_t DefaultMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage without FIT controller enabled 1080 uint16_t BoostMaxVoltage[PMFW_VOLT_PLANE_COUNT]; // In mV(Q2) Maximum voltage with FIT controller enabled 1081 1082 //Vmin Optimizations 1083 int16_t VminTempHystersis[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature hysteresis for switching between low/high temperature values for Vmin 1084 int16_t VminTempThreshold[PMFW_VOLT_PLANE_COUNT]; // Celsius Temperature threshold for switching between low/high temperature values for Vmin 1085 uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at hot. 1086 uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vset to be used at cold. 1087 uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at hot. 1088 uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be used at cold. 1089 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin 1090 uint16_t Spare_Vmin_Plat_Offset_Hot[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Hot 1091 uint16_t Spare_Vmin_Plat_Offset_Cold[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Platform offset apply to T0 Cold 1092 1093 //This is a fixed/minimum VMIN aging degradation offset which is applied at T0. This reflects the minimum amount of aging already accounted for. 1094 uint16_t VcBtcFixedVminAgingOffset[PMFW_VOLT_PLANE_COUNT]; 1095 //Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across parts. 1096 uint16_t VcBtcVmin2PsmDegrationGb[PMFW_VOLT_PLANE_COUNT]; 1097 //Scalar coefficient of the PSM aging degradation function 1098 uint32_t VcBtcPsmA[PMFW_VOLT_PLANE_COUNT]; // A_PSM 1099 //Exponential coefficient of the PSM aging degradation function 1100 uint32_t VcBtcPsmB[PMFW_VOLT_PLANE_COUNT]; // B_PSM 1101 //Scalar coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1102 uint32_t VcBtcVminA[PMFW_VOLT_PLANE_COUNT]; // A_VMIN 1103 //Exponential coefficient of the VMIN aging degradation function. Specified as worst case between hot and cold. 1104 uint32_t VcBtcVminB[PMFW_VOLT_PLANE_COUNT]; // B_VMIN 1105 1106 uint8_t PerPartVminEnabled[PMFW_VOLT_PLANE_COUNT]; 1107 uint8_t VcBtcEnabled[PMFW_VOLT_PLANE_COUNT]; 1108 1109 uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1110 uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; // Time constant of LPF in ms 1111 1112 QuadraticInt_t Gfx_Vmin_droop; 1113 QuadraticInt_t Soc_Vmin_droop; 1114 uint32_t SpareVmin[6]; 1115 1116 //SECTION: DPM Configuration 1 1117 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT]; 1118 1119 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1120 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1121 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1122 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1123 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1124 uint16_t FreqTableShadowUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1125 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1126 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1127 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1128 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1129 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1130 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1131 1132 uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1133 1134 uint16_t GfxclkAibFmax; 1135 uint16_t GfxclkFreqCap; 1136 1137 //GFX Idle Power Settings 1138 uint16_t GfxclkFgfxoffEntry; // Entry in RLC stage (PLL), in Mhz 1139 uint16_t GfxclkFgfxoffExitImu; // Exit/Entry in IMU stage (BYPASS), in Mhz 1140 uint16_t GfxclkFgfxoffExitRlc; // Exit in RLC stage (PLL), in Mhz 1141 uint16_t GfxclkThrottleClock; //Used primarily in DCS 1142 uint8_t EnableGfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages 1143 uint8_t GfxIdlePadding; 1144 1145 uint8_t SmsRepairWRCKClkDivEn; 1146 uint8_t SmsRepairWRCKClkDivVal; 1147 uint8_t GfxOffEntryEarlyMGCGEn; 1148 uint8_t GfxOffEntryForceCGCGEn; 1149 uint8_t GfxOffEntryForceCGCGDelayEn; 1150 uint8_t GfxOffEntryForceCGCGDelayVal; // in microseconds 1151 1152 uint16_t GfxclkFreqGfxUlv; // in MHz 1153 uint8_t GfxIdlePadding2[2]; 1154 uint32_t GfxOffEntryHysteresis; //For RLC to count after it enters CGCG, and before triggers GFXOFF entry 1155 uint32_t GfxoffSpare[15]; 1156 1157 // DFLL 1158 uint16_t DfllMstrOscConfigA; //Used for voltage sensitivity slope tuning: 0 = (en_leaker << 9) | (en_vint1_reduce << 8) | (gain_code << 6) | (bias_code << 3) | (vint1_code << 1) | en_bias 1159 uint16_t DfllSlvOscConfigA; //Used for voltage sensitivity slope tuning: 0 = (en_leaker << 9) | (en_vint1_reduce << 8) | (gain_code << 6) | (bias_code << 3) | (vint1_code << 1) | en_bias 1160 uint32_t DfllBtcMasterScalerM; 1161 int32_t DfllBtcMasterScalerB; 1162 uint32_t DfllBtcSlaveScalerM; 1163 int32_t DfllBtcSlaveScalerB; 1164 1165 uint32_t DfllPccAsWaitCtrl; //GDFLL_AS_WAIT_CTRL_PCC register value to be passed to RLC msg 1166 uint32_t DfllPccAsStepCtrl; //GDFLL_AS_STEP_CTRL_PCC register value to be passed to RLC msg 1167 uint32_t GfxDfllSpare[9]; 1168 1169 // DVO 1170 uint32_t DvoPsmDownThresholdVoltage; //Voltage float 1171 uint32_t DvoPsmUpThresholdVoltage; //Voltage float 1172 uint32_t DvoFmaxLowScaler; //Unitless float 1173 1174 // GFX DCS 1175 uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase 1176 uint16_t PaddingDcs; 1177 1178 uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase 1179 uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. 1180 1181 uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. 1182 1183 uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. 1184 uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. 1185 1186 uint32_t DcsPfGfxFopt; //Default to GFX FMIN 1187 uint32_t DcsPfUclkFopt; //Default to UCLK FMIN 1188 1189 uint8_t FoptEnabled; 1190 uint8_t DcsSpare2[3]; 1191 uint32_t DcsFoptM; //Tuning paramters to shift Fopt calculation, IEEE754 float 1192 uint32_t DcsFoptB; //Tuning paramters to shift Fopt calculation, IEEE754 float 1193 uint32_t DcsSpare[9]; 1194 1195 // UCLK section 1196 uint8_t UseStrobeModeOptimizations; //Set to indicate that FW should use strobe mode optimizations 1197 uint8_t PaddingMem[3]; 1198 1199 uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 6 Primary SW DPM states (6 + 6 Shadow) 1200 uint8_t UclkDpmShadowPstates [NUM_UCLK_DPM_LEVELS]; // 6 Shadow SW DPM states (6 + 6 Shadow) 1201 uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1202 uint8_t FreqTableShadowUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 1203 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1204 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) 1205 uint16_t DalDcModeMaxUclkFreq; 1206 uint8_t PaddingsMem[2]; 1207 //FCLK Section 1208 uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value 1209 uint16_t PaddingFclk; 1210 1211 // Link DPM Settings 1212 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 4:PciE-gen5 1213 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 1214 uint16_t LclkFreq[NUM_LINK_LEVELS]; 1215 1216 // SECTION: VDD_GFX AVFS 1217 uint8_t OverrideGfxAvfsFuses; 1218 uint8_t GfxAvfsPadding[3]; 1219 1220 uint32_t SocHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //new added for Soc domain 1221 uint32_t GfxL2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding 1222 //uint32_t GfxSeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1223 uint32_t spare_HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; 1224 1225 uint32_t SocCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1226 uint32_t GfxCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; 1227 1228 uint32_t SocFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1229 uint32_t GfxL2FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1230 //uint32_t GfxSeFwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1231 uint32_t spare_FwRtAvfsFuses[PP_GRTAVFS_FW_SEP_FUSE_COUNT]; 1232 1233 uint32_t Soc_Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1234 uint32_t Soc_Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1235 uint32_t Soc_Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1236 uint32_t Soc_Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1237 1238 uint32_t Gfx_Droop_PWL_F[PP_NUM_RTAVFS_PWL_ZONES]; 1239 uint32_t Gfx_Droop_PWL_a[PP_NUM_RTAVFS_PWL_ZONES]; 1240 uint32_t Gfx_Droop_PWL_b[PP_NUM_RTAVFS_PWL_ZONES]; 1241 uint32_t Gfx_Droop_PWL_c[PP_NUM_RTAVFS_PWL_ZONES]; 1242 1243 uint32_t Gfx_Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1244 uint32_t Soc_Static_PWL_Offset[PP_NUM_RTAVFS_PWL_ZONES]; 1245 1246 uint32_t dGbV_dT_vmin; 1247 uint32_t dGbV_dT_vmax; 1248 1249 //Unused: PMFW-9370 1250 uint32_t V2F_vmin_range_low; 1251 uint32_t V2F_vmin_range_high; 1252 uint32_t V2F_vmax_range_low; 1253 uint32_t V2F_vmax_range_high; 1254 1255 AvfsDcBtcParams_t DcBtcGfxParams; 1256 QuadraticInt_t SSCurve_GFX; 1257 uint32_t GfxAvfsSpare[29]; 1258 1259 //SECTION: VDD_SOC AVFS 1260 uint8_t OverrideSocAvfsFuses; 1261 uint8_t MinSocAvfsRevision; 1262 uint8_t SocAvfsPadding[2]; 1263 1264 AvfsFuseOverride_t SocAvfsFuseOverride[AVFS_D_COUNT]; 1265 1266 DroopInt_t dBtcGbSoc[AVFS_D_COUNT]; // GHz->V BtcGb 1267 1268 LinearInt_t qAgingGb[AVFS_D_COUNT]; // GHz->V 1269 1270 QuadraticInt_t qStaticVoltageOffset[AVFS_D_COUNT]; // GHz->V 1271 1272 AvfsDcBtcParams_t DcBtcSocParams[AVFS_D_COUNT]; 1273 1274 QuadraticInt_t SSCurve_SOC; 1275 uint32_t SocAvfsSpare[29]; 1276 1277 //SECTION: Boot clock and voltage values 1278 BootValues_t BootValues; 1279 1280 //SECTION: Driver Reported Clocks 1281 DriverReportedClocks_t DriverReportedClocks; 1282 1283 //SECTION: Message Limits 1284 MsgLimits_t MsgLimits; 1285 1286 //SECTION: OverDrive Limits 1287 OverDriveLimits_t OverDriveLimitsBasicMin; 1288 OverDriveLimits_t OverDriveLimitsBasicMax; 1289 OverDriveLimits_t OverDriveLimitsAdvancedMin; 1290 OverDriveLimits_t OverDriveLimitsAdvancedMax; 1291 1292 // Section: Total Board Power idle vs active coefficients 1293 uint8_t TotalBoardPowerSupport; 1294 uint8_t TotalBoardPowerPadding[1]; 1295 uint16_t TotalBoardPowerRoc; 1296 1297 //PMFW-11158 1298 QuadraticInt_t qFeffCoeffGameClock[POWER_SOURCE_COUNT]; 1299 QuadraticInt_t qFeffCoeffBaseClock[POWER_SOURCE_COUNT]; 1300 QuadraticInt_t qFeffCoeffBoostClock[POWER_SOURCE_COUNT]; 1301 1302 // APT GFX to UCLK mapping 1303 int32_t AptUclkGfxclkLookup[POWER_SOURCE_COUNT][6]; 1304 uint32_t AptUclkGfxclkLookupHyst[POWER_SOURCE_COUNT][6]; 1305 uint32_t AptPadding; 1306 1307 // Xvmin didt 1308 QuadraticInt_t GfxXvminDidtDroopThresh; 1309 uint32_t GfxXvminDidtResetDDWait; 1310 uint32_t GfxXvminDidtClkStopWait; 1311 uint32_t GfxXvminDidtFcsStepCtrl; 1312 uint32_t GfxXvminDidtFcsWaitCtrl; 1313 1314 // PSM based didt controller 1315 uint32_t PsmModeEnabled; //0: all disabled 1: static mode only 2: dynamic mode only 3:static + dynamic mode 1316 uint32_t P2v_a; // floating point in U32 format 1317 uint32_t P2v_b; 1318 uint32_t P2v_c; 1319 uint32_t T2p_a; 1320 uint32_t T2p_b; 1321 uint32_t T2p_c; 1322 uint32_t P2vTemp; 1323 QuadraticInt_t PsmDidtStaticSettings; 1324 QuadraticInt_t PsmDidtDynamicSettings; 1325 uint8_t PsmDidtAvgDiv; 1326 uint8_t PsmDidtForceStall; 1327 uint16_t PsmDidtReleaseTimer; 1328 uint32_t PsmDidtStallPattern; //Will be written to both pattern 1 and didt_static_level_prog 1329 // CAC EDC 1330 uint32_t Leakage_C0; // in IEEE float 1331 uint32_t Leakage_C1; // in IEEE float 1332 uint32_t Leakage_C2; // in IEEE float 1333 uint32_t Leakage_C3; // in IEEE float 1334 uint32_t Leakage_C4; // in IEEE float 1335 uint32_t Leakage_C5; // in IEEE float 1336 uint32_t GFX_CLK_SCALAR; // in IEEE float 1337 uint32_t GFX_CLK_INTERCEPT; // in IEEE float 1338 uint32_t GFX_CAC_M; // in IEEE float 1339 uint32_t GFX_CAC_B; // in IEEE float 1340 uint32_t VDD_GFX_CurrentLimitGuardband; // in IEEE float 1341 uint32_t DynToTotalCacScalar; // in IEEE 1342 // GFX EDC XVMIN 1343 uint32_t XVmin_Gfx_EdcThreshScalar; 1344 uint32_t XVmin_Gfx_EdcEnableFreq; 1345 uint32_t XVmin_Gfx_EdcPccAsStepCtrl; 1346 uint32_t XVmin_Gfx_EdcPccAsWaitCtrl; 1347 uint16_t XVmin_Gfx_EdcThreshold; 1348 uint16_t XVmin_Gfx_EdcFiltHysWaitCtrl; 1349 // SOC EDC XVMIN 1350 uint32_t XVmin_Soc_EdcThreshScalar; 1351 uint32_t XVmin_Soc_EdcEnableFreq; 1352 uint32_t XVmin_Soc_EdcThreshold; // LPF: number of cycles Xvmin_trig_filt will react. 1353 uint16_t XVmin_Soc_EdcStepUpTime; // 10 bit, refclk count to step up throttle when PCC remains asserted. 1354 uint16_t XVmin_Soc_EdcStepDownTime;// 10 bit, refclk count to step down throttle when PCC remains asserted. 1355 uint8_t XVmin_Soc_EdcInitPccStep; // 3 bit, First Pcc Step number that will applied when PCC asserts. 1356 uint8_t PaddingSocEdc[3]; 1357 1358 // Fuse Override for SOC and GFX XVMIN 1359 uint8_t GfxXvminFuseOverride; 1360 uint8_t SocXvminFuseOverride; 1361 uint8_t PaddingXvminFuseOverride[2]; 1362 uint8_t GfxXvminFddTempLow; // bit 7: sign, bit 0-6: ABS value 1363 uint8_t GfxXvminFddTempHigh; // bit 7: sign, bit 0-6: ABS value 1364 uint8_t SocXvminFddTempLow; // bit 7: sign, bit 0-6: ABS value 1365 uint8_t SocXvminFddTempHigh; // bit 7: sign, bit 0-6: ABS value 1366 1367 1368 uint16_t GfxXvminFddVolt0; // low voltage, in VID 1369 uint16_t GfxXvminFddVolt1; // mid voltage, in VID 1370 uint16_t GfxXvminFddVolt2; // high voltage, in VID 1371 uint16_t SocXvminFddVolt0; // low voltage, in VID 1372 uint16_t SocXvminFddVolt1; // mid voltage, in VID 1373 uint16_t SocXvminFddVolt2; // high voltage, in VID 1374 uint16_t GfxXvminDsFddDsm[6]; // XVMIN DS, same organization with fuse 1375 uint16_t GfxXvminEdcFddDsm[6];// XVMIN GFX EDC, same organization with fuse 1376 uint16_t SocXvminEdcFddDsm[6];// XVMIN SOC EDC, same organization with fuse 1377 1378 // SECTION: Sku Reserved 1379 uint32_t Spare; 1380 1381 // Padding for MMHUB - do not modify this 1382 uint32_t MmHubPadding[8]; 1383 } SkuTable_t; 1384 1385 typedef struct { 1386 uint8_t SlewRateConditions; 1387 uint8_t LoadLineAdjust; 1388 uint8_t VoutOffset; 1389 uint8_t VidMax; 1390 uint8_t VidMin; 1391 uint8_t TenBitTelEn; 1392 uint8_t SixteenBitTelEn; 1393 uint8_t OcpThresh; 1394 uint8_t OcpWarnThresh; 1395 uint8_t OcpSettings; 1396 uint8_t VrhotThresh; 1397 uint8_t OtpThresh; 1398 uint8_t UvpOvpDeltaRef; 1399 uint8_t PhaseShed; 1400 uint8_t Padding[10]; 1401 uint32_t SettingOverrideMask; 1402 } Svi3RegulatorSettings_t; 1403 1404 typedef struct { 1405 // SECTION: Version 1406 uint32_t Version; //should be unique to each board type 1407 1408 // SECTION: I2C Control 1409 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; 1410 1411 //SECTION SVI3 Board Parameters 1412 uint8_t SlaveAddrMapping[SVI_PLANE_COUNT]; 1413 uint8_t VrPsiSupport[SVI_PLANE_COUNT]; 1414 1415 uint32_t Svi3SvcSpeed; 1416 uint8_t EnablePsi6[SVI_PLANE_COUNT]; // only applicable in SVI3 1417 1418 // SECTION: Voltage Regulator Settings 1419 Svi3RegulatorSettings_t Svi3RegSettings[SVI_PLANE_COUNT]; 1420 1421 // SECTION: GPIO Settings 1422 uint8_t LedOffGpio; 1423 uint8_t FanOffGpio; 1424 uint8_t GfxVrPowerStageOffGpio; 1425 1426 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1427 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1428 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1429 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1430 1431 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1432 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1433 1434 // LED Display Settings 1435 uint8_t LedPin0; // GPIO number for LedPin[0] 1436 uint8_t LedPin1; // GPIO number for LedPin[1] 1437 uint8_t LedPin2; // GPIO number for LedPin[2] 1438 uint8_t LedEnableMask; 1439 1440 uint8_t LedPcie; // GPIO number for PCIE results 1441 uint8_t LedError; // GPIO number for Error Cases 1442 uint8_t PaddingLed; 1443 1444 // SECTION: Clock Spread Spectrum 1445 1446 // UCLK Spread Spectrum 1447 uint8_t UclkTrainingModeSpreadPercent; // Q4.4 1448 uint8_t UclkSpreadPadding; 1449 uint16_t UclkSpreadFreq; // kHz 1450 1451 // UCLK Spread Spectrum 1452 uint8_t UclkSpreadPercent[MEM_VENDOR_COUNT]; 1453 1454 // DFLL Spread Spectrum 1455 uint8_t GfxclkSpreadEnable; 1456 1457 // FCLK Spread Spectrum 1458 uint8_t FclkSpreadPercent; // Q4.4 1459 uint16_t FclkSpreadFreq; // kHz 1460 1461 // Section: Memory Config 1462 uint8_t DramWidth; // Width of interface to the channel for each DRAM module. See DRAM_BIT_WIDTH_TYPE_e 1463 uint8_t PaddingMem1[7]; 1464 1465 // SECTION: UMC feature flags 1466 uint8_t HsrEnabled; 1467 uint8_t VddqOffEnabled; 1468 uint8_t PaddingUmcFlags[2]; 1469 1470 uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued 1471 uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS 1472 1473 uint8_t FuseWritePowerMuxPresent; 1474 uint8_t FuseWritePadding[3]; 1475 1476 // SECTION: EDC Params 1477 uint32_t LoadlineGfx; 1478 uint32_t LoadlineSoc; 1479 uint32_t GfxEdcLimit; 1480 uint32_t SocEdcLimit; 1481 1482 uint32_t RestBoardPower; //power consumed by board that is not captured by the SVI3 input telemetry 1483 uint32_t ConnectorsImpedance; // impedance of the input ATX power connectors 1484 1485 uint8_t EpcsSens0; //GPIO number for External Power Connector Support Sense0 1486 uint8_t EpcsSens1; //GPIO Number for External Power Connector Support Sense1 1487 uint8_t PaddingEpcs[2]; 1488 1489 // SECTION: Board Reserved 1490 uint32_t BoardSpare[52]; 1491 1492 // SECTION: Structure Padding 1493 1494 // Padding for MMHUB - do not modify this 1495 uint32_t MmHubPadding[8]; 1496 } BoardTable_t; 1497 1498 typedef struct { 1499 // SECTION: Infrastructure Limits 1500 uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in AC mode. Multiple limits supported 1501 1502 uint16_t VrTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with VR regulator maximum temperature 1503 1504 int16_t TotalIdleBoardPowerM; 1505 int16_t TotalIdleBoardPowerB; 1506 int16_t TotalBoardPowerM; 1507 int16_t TotalBoardPowerB; 1508 1509 uint16_t TemperatureLimit[TEMP_COUNT]; // In degrees Celsius. Temperature limit associated with each input 1510 1511 // SECTION: Fan Control 1512 uint16_t FanStopTemp[TEMP_COUNT]; //Celsius 1513 uint16_t FanStartTemp[TEMP_COUNT]; //Celsius 1514 1515 uint16_t FanGain[TEMP_COUNT]; 1516 1517 uint16_t FanPwmMin; 1518 uint16_t AcousticTargetRpmThreshold; 1519 uint16_t AcousticLimitRpmThreshold; 1520 uint16_t FanMaximumRpm; 1521 uint16_t MGpuAcousticLimitRpmThreshold; 1522 uint16_t FanTargetGfxclk; 1523 uint32_t TempInputSelectMask; 1524 uint8_t FanZeroRpmEnable; 1525 uint8_t FanTachEdgePerRev; 1526 uint16_t FanPadding; 1527 uint16_t FanTargetTemperature[TEMP_COUNT]; 1528 1529 // The following are AFC override parameters. Leave at 0 to use FW defaults. 1530 int16_t FuzzyFan_ErrorSetDelta; 1531 int16_t FuzzyFan_ErrorRateSetDelta; 1532 int16_t FuzzyFan_PwmSetDelta; 1533 uint16_t FuzzyFan_Reserved; 1534 1535 uint16_t FwCtfLimit[TEMP_COUNT]; 1536 1537 uint16_t IntakeTempEnableRPM; 1538 int16_t IntakeTempOffsetTemp; 1539 uint16_t IntakeTempReleaseTemp; 1540 uint16_t IntakeTempHighIntakeAcousticLimit; 1541 1542 uint16_t IntakeTempAcouticLimitReleaseRate; 1543 int16_t FanAbnormalTempLimitOffset; // FanStalledTempLimitOffset 1544 uint16_t FanStalledTriggerRpm; // 1545 uint16_t FanAbnormalTriggerRpmCoeff; // FanAbnormalTriggerRpm 1546 1547 uint16_t FanSpare[1]; 1548 uint8_t FanIntakeSensorSupport; 1549 uint8_t FanIntakePadding; 1550 uint32_t FanAmbientPerfBoostThreshold; 1551 uint32_t FanSpare2[12]; 1552 1553 uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix 1554 uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron 1555 uint16_t TemperatureFwCtfLimit_Hynix; 1556 uint16_t TemperatureFwCtfLimit_Micron; 1557 1558 // SECTION: Board Reserved 1559 uint16_t PlatformTdcLimit[TDC_THROTTLER_COUNT]; // In Amperes. Current limit associated with platform maximum temperature per VR current rail 1560 uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; // In Watts. Power limit that PMFW attempts to control to in DC mode. Multiple limits supported 1561 uint16_t SocketPowerLimitSmartShift2; // In Watts. Power limit used SmartShift 1562 uint16_t CustomSkuSpare16b; 1563 uint32_t CustomSkuSpare32b[10]; 1564 1565 // SECTION: Structure Padding 1566 1567 // Padding for MMHUB - do not modify this 1568 uint32_t MmHubPadding[8]; 1569 } CustomSkuTable_t; 1570 1571 typedef struct { 1572 PFE_Settings_t PFE_Settings; 1573 SkuTable_t SkuTable; 1574 CustomSkuTable_t CustomSkuTable; 1575 BoardTable_t BoardTable; 1576 } PPTable_t; 1577 1578 typedef struct { 1579 // Time constant parameters for clock averages in ms 1580 uint16_t GfxclkAverageLpfTau; 1581 uint16_t FclkAverageLpfTau; 1582 uint16_t UclkAverageLpfTau; 1583 uint16_t GfxActivityLpfTau; 1584 uint16_t UclkActivityLpfTau; 1585 uint16_t UclkMaxActivityLpfTau; 1586 uint16_t SocketPowerLpfTau; 1587 uint16_t VcnClkAverageLpfTau; 1588 uint16_t VcnUsageAverageLpfTau; 1589 uint16_t PcieActivityLpTau; 1590 } DriverSmuConfig_t; 1591 1592 typedef struct { 1593 DriverSmuConfig_t DriverSmuConfig; 1594 1595 uint32_t Spare[8]; 1596 // Padding - ignore 1597 uint32_t MmHubPadding[8]; // SMU internal use 1598 } DriverSmuConfigExternal_t; 1599 1600 1601 typedef struct { 1602 1603 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz 1604 uint16_t FreqTableVclk [NUM_VCLK_DPM_LEVELS ]; // In MHz 1605 uint16_t FreqTableDclk [NUM_DCLK_DPM_LEVELS ]; // In MHz 1606 uint16_t FreqTableSocclk [NUM_SOCCLK_DPM_LEVELS ]; // In MHz 1607 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz 1608 uint16_t FreqTableDispclk [NUM_DISPCLK_DPM_LEVELS ]; // In MHz 1609 uint16_t FreqTableDppClk [NUM_DPPCLK_DPM_LEVELS ]; // In MHz 1610 uint16_t FreqTableDprefclk [NUM_DPREFCLK_DPM_LEVELS]; // In MHz 1611 uint16_t FreqTableDcfclk [NUM_DCFCLK_DPM_LEVELS ]; // In MHz 1612 uint16_t FreqTableDtbclk [NUM_DTBCLK_DPM_LEVELS ]; // In MHz 1613 uint16_t FreqTableFclk [NUM_FCLK_DPM_LEVELS ]; // In MHz 1614 1615 uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz 1616 1617 uint16_t Padding; 1618 1619 uint32_t Spare[32]; 1620 1621 // Padding - ignore 1622 uint32_t MmHubPadding[8]; // SMU internal use 1623 1624 } DriverInfoTable_t; 1625 1626 typedef struct { 1627 uint32_t CurrClock[PPCLK_COUNT]; 1628 1629 uint16_t AverageGfxclkFrequencyTarget; 1630 uint16_t AverageGfxclkFrequencyPreDs; 1631 uint16_t AverageGfxclkFrequencyPostDs; 1632 uint16_t AverageFclkFrequencyPreDs; 1633 uint16_t AverageFclkFrequencyPostDs; 1634 uint16_t AverageMemclkFrequencyPreDs ; // this is scaled to actual memory clock 1635 uint16_t AverageMemclkFrequencyPostDs ; // this is scaled to actual memory clock 1636 uint16_t AverageVclk0Frequency ; 1637 uint16_t AverageDclk0Frequency ; 1638 uint16_t AverageVclk1Frequency ; 1639 uint16_t AverageDclk1Frequency ; 1640 uint16_t PCIeBusy ; 1641 uint16_t dGPU_W_MAX ; 1642 uint16_t padding ; 1643 1644 uint16_t MovingAverageGfxclkFrequencyTarget; 1645 uint16_t MovingAverageGfxclkFrequencyPreDs; 1646 uint16_t MovingAverageGfxclkFrequencyPostDs; 1647 uint16_t MovingAverageFclkFrequencyPreDs; 1648 uint16_t MovingAverageFclkFrequencyPostDs; 1649 uint16_t MovingAverageMemclkFrequencyPreDs; 1650 uint16_t MovingAverageMemclkFrequencyPostDs; 1651 uint16_t MovingAverageVclk0Frequency; 1652 uint16_t MovingAverageDclk0Frequency; 1653 uint16_t MovingAverageGfxActivity; 1654 uint16_t MovingAverageUclkActivity; 1655 uint16_t MovingAverageVcn0ActivityPercentage; 1656 uint16_t MovingAveragePCIeBusy; 1657 uint16_t MovingAverageUclkActivity_MAX; 1658 uint16_t MovingAverageSocketPower; 1659 uint16_t MovingAveragePadding; 1660 1661 uint32_t MetricsCounter ; 1662 1663 uint16_t AvgVoltage[SVI_PLANE_COUNT]; 1664 uint16_t AvgCurrent[SVI_PLANE_COUNT]; 1665 1666 uint16_t AverageGfxActivity ; 1667 uint16_t AverageUclkActivity ; 1668 uint16_t Vcn0ActivityPercentage ; 1669 uint16_t Vcn1ActivityPercentage ; 1670 1671 uint32_t EnergyAccumulator; 1672 uint16_t AverageSocketPower; 1673 uint16_t MovingAverageTotalBoardPower; 1674 1675 uint16_t AvgTemperature[TEMP_COUNT]; 1676 uint16_t AvgTemperatureFanIntake; 1677 1678 uint8_t PcieRate ; 1679 uint8_t PcieWidth ; 1680 1681 uint8_t AvgFanPwm; 1682 uint8_t Padding[1]; 1683 uint16_t AvgFanRpm; 1684 1685 1686 uint8_t ThrottlingPercentage[THROTTLER_COUNT]; 1687 uint8_t padding1[3]; 1688 1689 //metrics for D3hot entry/exit and driver ARM msgs 1690 uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; 1691 uint32_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT]; 1692 uint32_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT]; 1693 1694 uint16_t ApuSTAPMSmartShiftLimit; 1695 uint16_t ApuSTAPMLimit; 1696 uint16_t MovingAvgApuSocketPower; 1697 1698 uint16_t AverageUclkActivity_MAX; 1699 1700 uint32_t PublicSerialNumberLower; 1701 uint32_t PublicSerialNumberUpper; 1702 1703 } SmuMetrics_t; 1704 1705 typedef struct { 1706 SmuMetrics_t SmuMetrics; 1707 uint32_t Spare[30]; 1708 1709 // Padding - ignore 1710 uint32_t MmHubPadding[8]; // SMU internal use 1711 } SmuMetricsExternal_t; 1712 1713 typedef struct { 1714 uint8_t WmSetting; 1715 uint8_t Flags; 1716 uint8_t Padding[2]; 1717 1718 } WatermarkRowGeneric_t; 1719 1720 #define NUM_WM_RANGES 4 1721 1722 typedef enum { 1723 WATERMARKS_CLOCK_RANGE = 0, 1724 WATERMARKS_DUMMY_PSTATE, 1725 WATERMARKS_MALL, 1726 WATERMARKS_COUNT, 1727 } WATERMARKS_FLAGS_e; 1728 1729 typedef struct { 1730 // Watermarks 1731 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; 1732 } Watermarks_t; 1733 1734 typedef struct { 1735 Watermarks_t Watermarks; 1736 uint32_t Spare[16]; 1737 1738 uint32_t MmHubPadding[8]; // SMU internal use 1739 } WatermarksExternal_t; 1740 1741 typedef struct { 1742 uint16_t avgPsmCount[76]; 1743 uint16_t minPsmCount[76]; 1744 uint16_t maxPsmCount[76]; 1745 float avgPsmVoltage[76]; 1746 float minPsmVoltage[76]; 1747 float maxPsmVoltage[76]; 1748 } AvfsDebugTable_t; 1749 1750 typedef struct { 1751 AvfsDebugTable_t AvfsDebugTable; 1752 1753 uint32_t MmHubPadding[8]; // SMU internal use 1754 } AvfsDebugTableExternal_t; 1755 1756 1757 typedef struct { 1758 uint8_t Gfx_ActiveHystLimit; 1759 uint8_t Gfx_IdleHystLimit; 1760 uint8_t Gfx_FPS; 1761 uint8_t Gfx_MinActiveFreqType; 1762 uint8_t Gfx_BoosterFreqType; 1763 uint8_t PaddingGfx; 1764 uint16_t Gfx_MinActiveFreq; // MHz 1765 uint16_t Gfx_BoosterFreq; // MHz 1766 uint16_t Gfx_PD_Data_time_constant; // Time constant of PD controller in ms 1767 uint32_t Gfx_PD_Data_limit_a; // Q16 1768 uint32_t Gfx_PD_Data_limit_b; // Q16 1769 uint32_t Gfx_PD_Data_limit_c; // Q16 1770 uint32_t Gfx_PD_Data_error_coeff; // Q16 1771 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 1772 1773 uint8_t Fclk_ActiveHystLimit; 1774 uint8_t Fclk_IdleHystLimit; 1775 uint8_t Fclk_FPS; 1776 uint8_t Fclk_MinActiveFreqType; 1777 uint8_t Fclk_BoosterFreqType; 1778 uint8_t PaddingFclk; 1779 uint16_t Fclk_MinActiveFreq; // MHz 1780 uint16_t Fclk_BoosterFreq; // MHz 1781 uint16_t Fclk_PD_Data_time_constant; // Time constant of PD controller in ms 1782 uint32_t Fclk_PD_Data_limit_a; // Q16 1783 uint32_t Fclk_PD_Data_limit_b; // Q16 1784 uint32_t Fclk_PD_Data_limit_c; // Q16 1785 uint32_t Fclk_PD_Data_error_coeff; // Q16 1786 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 1787 1788 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16 1789 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS]; 1790 uint16_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS]; 1791 uint16_t Mem_Fps; 1792 1793 } DpmActivityMonitorCoeffInt_t; 1794 1795 1796 typedef struct { 1797 DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; 1798 uint32_t MmHubPadding[8]; // SMU internal use 1799 } DpmActivityMonitorCoeffIntExternal_t; 1800 1801 1802 1803 // Workload bits 1804 #define WORKLOAD_PPLIB_DEFAULT_BIT 0 1805 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 1806 #define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 1807 #define WORKLOAD_PPLIB_VIDEO_BIT 3 1808 #define WORKLOAD_PPLIB_VR_BIT 4 1809 #define WORKLOAD_PPLIB_COMPUTE_BIT 5 1810 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 1811 #define WORKLOAD_PPLIB_WINDOW_3D_BIT 7 1812 #define WORKLOAD_PPLIB_DIRECT_ML_BIT 8 1813 #define WORKLOAD_PPLIB_CGVDI_BIT 9 1814 #define WORKLOAD_PPLIB_COUNT 10 1815 1816 1817 // These defines are used with the following messages: 1818 // SMC_MSG_TransferTableDram2Smu 1819 // SMC_MSG_TransferTableSmu2Dram 1820 1821 // Table transfer status 1822 #define TABLE_TRANSFER_OK 0x0 1823 #define TABLE_TRANSFER_FAILED 0xFF 1824 #define TABLE_TRANSFER_PENDING 0xAB 1825 1826 // Table types 1827 #define TABLE_PPTABLE 0 1828 #define TABLE_COMBO_PPTABLE 1 1829 #define TABLE_WATERMARKS 2 1830 #define TABLE_AVFS_PSM_DEBUG 3 1831 #define TABLE_PMSTATUSLOG 4 1832 #define TABLE_SMU_METRICS 5 1833 #define TABLE_DRIVER_SMU_CONFIG 6 1834 #define TABLE_ACTIVITY_MONITOR_COEFF 7 1835 #define TABLE_OVERDRIVE 8 1836 #define TABLE_I2C_COMMANDS 9 1837 #define TABLE_DRIVER_INFO 10 1838 #define TABLE_ECCINFO 11 1839 #define TABLE_CUSTOM_SKUTABLE 12 1840 #define TABLE_COUNT 13 1841 1842 //IH Interupt ID 1843 #define IH_INTERRUPT_ID_TO_DRIVER 0xFE 1844 #define IH_INTERRUPT_CONTEXT_ID_BACO 0x2 1845 #define IH_INTERRUPT_CONTEXT_ID_AC 0x3 1846 #define IH_INTERRUPT_CONTEXT_ID_DC 0x4 1847 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 1848 #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 1849 #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 1850 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 1851 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 1852 1853 #endif 1854