xref: /linux/include/dt-bindings/clock/rk3568-cru.h (revision 619b92b9c8fe5369503ae948ad4e0a9c195c2c4a)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4  * Author: Elaine Zhang <zhangqing@rock-chips.com>
5  */
6 
7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
9 
10 /* pmucru-clocks indices */
11 
12 /* pmucru plls */
13 #define PLL_PPLL		1
14 #define PLL_HPLL		2
15 
16 /* pmucru clocks */
17 #define XIN_OSC0_DIV		4
18 #define CLK_RTC_32K		5
19 #define CLK_PMU			6
20 #define CLK_I2C0		7
21 #define CLK_RTC32K_FRAC		8
22 #define CLK_UART0_DIV		9
23 #define CLK_UART0_FRAC		10
24 #define SCLK_UART0		11
25 #define DBCLK_GPIO0		12
26 #define CLK_PWM0		13
27 #define CLK_CAPTURE_PWM0_NDFT	14
28 #define CLK_PMUPVTM		15
29 #define CLK_CORE_PMUPVTM	16
30 #define CLK_REF24M		17
31 #define XIN_OSC0_USBPHY0_G	18
32 #define CLK_USBPHY0_REF		19
33 #define XIN_OSC0_USBPHY1_G	20
34 #define CLK_USBPHY1_REF		21
35 #define XIN_OSC0_MIPIDSIPHY0_G	22
36 #define CLK_MIPIDSIPHY0_REF	23
37 #define XIN_OSC0_MIPIDSIPHY1_G	24
38 #define CLK_MIPIDSIPHY1_REF	25
39 #define CLK_WIFI_DIV		26
40 #define CLK_WIFI_OSC0		27
41 #define CLK_WIFI		28
42 #define CLK_PCIEPHY0_DIV	29
43 #define CLK_PCIEPHY0_OSC0	30
44 #define CLK_PCIEPHY0_REF	31
45 #define CLK_PCIEPHY1_DIV	32
46 #define CLK_PCIEPHY1_OSC0	33
47 #define CLK_PCIEPHY1_REF	34
48 #define CLK_PCIEPHY2_DIV	35
49 #define CLK_PCIEPHY2_OSC0	36
50 #define CLK_PCIEPHY2_REF	37
51 #define CLK_PCIE30PHY_REF_M	38
52 #define CLK_PCIE30PHY_REF_N	39
53 #define CLK_HDMI_REF		40
54 #define XIN_OSC0_EDPPHY_G	41
55 #define PCLK_PDPMU		42
56 #define PCLK_PMU		43
57 #define PCLK_UART0		44
58 #define PCLK_I2C0		45
59 #define PCLK_GPIO0		46
60 #define PCLK_PMUPVTM		47
61 #define PCLK_PWM0		48
62 #define CLK_PDPMU		49
63 #define SCLK_32K_IOE		50
64 
65 #define CLKPMU_NR_CLKS		(SCLK_32K_IOE + 1)
66 
67 /* cru-clocks indices */
68 
69 /* cru plls */
70 #define PLL_APLL		1
71 #define PLL_DPLL		2
72 #define PLL_CPLL		3
73 #define PLL_GPLL		4
74 #define PLL_VPLL		5
75 #define PLL_NPLL		6
76 
77 /* cru clocks */
78 #define CPLL_333M		9
79 #define ARMCLK			10
80 #define USB480M			11
81 #define USB480M_PHY		12
82 #define ACLK_CORE_NIU2BUS	18
83 #define CLK_CORE_PVTM		19
84 #define CLK_CORE_PVTM_CORE	20
85 #define CLK_CORE_PVTPLL		21
86 #define CLK_GPU_SRC		22
87 #define CLK_GPU_PRE_NDFT	23
88 #define CLK_GPU_PRE_MUX		24
89 #define ACLK_GPU_PRE		25
90 #define PCLK_GPU_PRE		26
91 #define CLK_GPU			27
92 #define CLK_GPU_NP5		28
93 #define PCLK_GPU_PVTM		29
94 #define CLK_GPU_PVTM		30
95 #define CLK_GPU_PVTM_CORE	31
96 #define CLK_GPU_PVTPLL		32
97 #define CLK_NPU_SRC		33
98 #define CLK_NPU_PRE_NDFT	34
99 #define CLK_NPU			35
100 #define CLK_NPU_NP5		36
101 #define HCLK_NPU_PRE		37
102 #define PCLK_NPU_PRE		38
103 #define ACLK_NPU_PRE		39
104 #define ACLK_NPU		40
105 #define HCLK_NPU		41
106 #define PCLK_NPU_PVTM		42
107 #define CLK_NPU_PVTM		43
108 #define CLK_NPU_PVTM_CORE	44
109 #define CLK_NPU_PVTPLL		45
110 #define CLK_DDRPHY1X_SRC	46
111 #define CLK_DDRPHY1X_HWFFC_SRC	47
112 #define CLK_DDR1X		48
113 #define CLK_MSCH		49
114 #define CLK24_DDRMON		50
115 #define ACLK_GIC_AUDIO		51
116 #define HCLK_GIC_AUDIO		52
117 #define HCLK_SDMMC_BUFFER	53
118 #define DCLK_SDMMC_BUFFER	54
119 #define ACLK_GIC600		55
120 #define ACLK_SPINLOCK		56
121 #define HCLK_I2S0_8CH		57
122 #define HCLK_I2S1_8CH		58
123 #define HCLK_I2S2_2CH		59
124 #define HCLK_I2S3_2CH		60
125 #define CLK_I2S0_8CH_TX_SRC	61
126 #define CLK_I2S0_8CH_TX_FRAC	62
127 #define MCLK_I2S0_8CH_TX	63
128 #define I2S0_MCLKOUT_TX		64
129 #define CLK_I2S0_8CH_RX_SRC	65
130 #define CLK_I2S0_8CH_RX_FRAC	66
131 #define MCLK_I2S0_8CH_RX	67
132 #define I2S0_MCLKOUT_RX		68
133 #define CLK_I2S1_8CH_TX_SRC	69
134 #define CLK_I2S1_8CH_TX_FRAC	70
135 #define MCLK_I2S1_8CH_TX	71
136 #define I2S1_MCLKOUT_TX		72
137 #define CLK_I2S1_8CH_RX_SRC	73
138 #define CLK_I2S1_8CH_RX_FRAC	74
139 #define MCLK_I2S1_8CH_RX	75
140 #define I2S1_MCLKOUT_RX		76
141 #define CLK_I2S2_2CH_SRC	77
142 #define CLK_I2S2_2CH_FRAC	78
143 #define MCLK_I2S2_2CH		79
144 #define I2S2_MCLKOUT		80
145 #define CLK_I2S3_2CH_TX_SRC	81
146 #define CLK_I2S3_2CH_TX_FRAC	82
147 #define MCLK_I2S3_2CH_TX	83
148 #define I2S3_MCLKOUT_TX		84
149 #define CLK_I2S3_2CH_RX_SRC	85
150 #define CLK_I2S3_2CH_RX_FRAC	86
151 #define MCLK_I2S3_2CH_RX	87
152 #define I2S3_MCLKOUT_RX		88
153 #define HCLK_PDM		89
154 #define MCLK_PDM		90
155 #define HCLK_VAD		91
156 #define HCLK_SPDIF_8CH		92
157 #define MCLK_SPDIF_8CH_SRC	93
158 #define MCLK_SPDIF_8CH_FRAC	94
159 #define MCLK_SPDIF_8CH		95
160 #define HCLK_AUDPWM		96
161 #define SCLK_AUDPWM_SRC		97
162 #define SCLK_AUDPWM_FRAC	98
163 #define SCLK_AUDPWM		99
164 #define HCLK_ACDCDIG		100
165 #define CLK_ACDCDIG_I2C		101
166 #define CLK_ACDCDIG_DAC		102
167 #define CLK_ACDCDIG_ADC		103
168 #define ACLK_SECURE_FLASH	104
169 #define HCLK_SECURE_FLASH	105
170 #define ACLK_CRYPTO_NS		106
171 #define HCLK_CRYPTO_NS		107
172 #define CLK_CRYPTO_NS_CORE	108
173 #define CLK_CRYPTO_NS_PKA	109
174 #define CLK_CRYPTO_NS_RNG	110
175 #define HCLK_TRNG_NS		111
176 #define CLK_TRNG_NS		112
177 #define PCLK_OTPC_NS		113
178 #define CLK_OTPC_NS_SBPI	114
179 #define CLK_OTPC_NS_USR		115
180 #define HCLK_NANDC		116
181 #define NCLK_NANDC		117
182 #define HCLK_SFC		118
183 #define HCLK_SFC_XIP		119
184 #define SCLK_SFC		120
185 #define ACLK_EMMC		121
186 #define HCLK_EMMC		122
187 #define BCLK_EMMC		123
188 #define CCLK_EMMC		124
189 #define TCLK_EMMC		125
190 #define ACLK_PIPE		126
191 #define PCLK_PIPE		127
192 #define PCLK_PIPE_GRF		128
193 #define ACLK_PCIE20_MST		129
194 #define ACLK_PCIE20_SLV		130
195 #define ACLK_PCIE20_DBI		131
196 #define PCLK_PCIE20		132
197 #define CLK_PCIE20_AUX_NDFT	133
198 #define CLK_PCIE20_AUX_DFT	134
199 #define CLK_PCIE20_PIPE_DFT	135
200 #define ACLK_PCIE30X1_MST	136
201 #define ACLK_PCIE30X1_SLV	137
202 #define ACLK_PCIE30X1_DBI	138
203 #define PCLK_PCIE30X1		139
204 #define CLK_PCIE30X1_AUX_NDFT	140
205 #define CLK_PCIE30X1_AUX_DFT	141
206 #define CLK_PCIE30X1_PIPE_DFT	142
207 #define ACLK_PCIE30X2_MST	143
208 #define ACLK_PCIE30X2_SLV	144
209 #define ACLK_PCIE30X2_DBI	145
210 #define PCLK_PCIE30X2		146
211 #define CLK_PCIE30X2_AUX_NDFT	147
212 #define CLK_PCIE30X2_AUX_DFT	148
213 #define CLK_PCIE30X2_PIPE_DFT	149
214 #define ACLK_SATA0		150
215 #define CLK_SATA0_PMALIVE	151
216 #define CLK_SATA0_RXOOB		152
217 #define CLK_SATA0_PIPE_NDFT	153
218 #define CLK_SATA0_PIPE_DFT	154
219 #define ACLK_SATA1		155
220 #define CLK_SATA1_PMALIVE	156
221 #define CLK_SATA1_RXOOB		157
222 #define CLK_SATA1_PIPE_NDFT	158
223 #define CLK_SATA1_PIPE_DFT	159
224 #define ACLK_SATA2		160
225 #define CLK_SATA2_PMALIVE	161
226 #define CLK_SATA2_RXOOB		162
227 #define CLK_SATA2_PIPE_NDFT	163
228 #define CLK_SATA2_PIPE_DFT	164
229 #define ACLK_USB3OTG0		165
230 #define CLK_USB3OTG0_REF	166
231 #define CLK_USB3OTG0_SUSPEND	167
232 #define ACLK_USB3OTG1		168
233 #define CLK_USB3OTG1_REF	169
234 #define CLK_USB3OTG1_SUSPEND	170
235 #define CLK_XPCS_EEE		171
236 #define PCLK_XPCS		172
237 #define ACLK_PHP		173
238 #define HCLK_PHP		174
239 #define PCLK_PHP		175
240 #define HCLK_SDMMC0		176
241 #define CLK_SDMMC0		177
242 #define HCLK_SDMMC1		178
243 #define CLK_SDMMC1		179
244 #define ACLK_GMAC0		180
245 #define PCLK_GMAC0		181
246 #define CLK_MAC0_2TOP		182
247 #define CLK_MAC0_OUT		183
248 #define CLK_MAC0_REFOUT		184
249 #define CLK_GMAC0_PTP_REF	185
250 #define ACLK_USB		186
251 #define HCLK_USB		187
252 #define PCLK_USB		188
253 #define HCLK_USB2HOST0		189
254 #define HCLK_USB2HOST0_ARB	190
255 #define HCLK_USB2HOST1		191
256 #define HCLK_USB2HOST1_ARB	192
257 #define HCLK_SDMMC2		193
258 #define CLK_SDMMC2		194
259 #define ACLK_GMAC1		195
260 #define PCLK_GMAC1		196
261 #define CLK_MAC1_2TOP		197
262 #define CLK_MAC1_OUT		198
263 #define CLK_MAC1_REFOUT		199
264 #define CLK_GMAC1_PTP_REF	200
265 #define ACLK_PERIMID		201
266 #define HCLK_PERIMID		202
267 #define ACLK_VI			203
268 #define HCLK_VI			204
269 #define PCLK_VI			205
270 #define ACLK_VICAP		206
271 #define HCLK_VICAP		207
272 #define DCLK_VICAP		208
273 #define ICLK_VICAP_G		209
274 #define ACLK_ISP		210
275 #define HCLK_ISP		211
276 #define CLK_ISP			212
277 #define PCLK_CSI2HOST1		213
278 #define CLK_CIF_OUT		214
279 #define CLK_CAM0_OUT		215
280 #define CLK_CAM1_OUT		216
281 #define ACLK_VO			217
282 #define HCLK_VO			218
283 #define PCLK_VO			219
284 #define ACLK_VOP_PRE		220
285 #define ACLK_VOP		221
286 #define HCLK_VOP		222
287 #define DCLK_VOP0		223
288 #define DCLK_VOP1		224
289 #define DCLK_VOP2		225
290 #define CLK_VOP_PWM		226
291 #define ACLK_HDCP		227
292 #define HCLK_HDCP		228
293 #define PCLK_HDCP		229
294 #define PCLK_HDMI_HOST		230
295 #define CLK_HDMI_SFR		231
296 #define PCLK_DSITX_0		232
297 #define PCLK_DSITX_1		233
298 #define PCLK_EDP_CTRL		234
299 #define CLK_EDP_200M		235
300 #define ACLK_VPU_PRE		236
301 #define HCLK_VPU_PRE		237
302 #define ACLK_VPU		238
303 #define HCLK_VPU		239
304 #define ACLK_RGA_PRE		240
305 #define HCLK_RGA_PRE		241
306 #define PCLK_RGA_PRE		242
307 #define ACLK_RGA		243
308 #define HCLK_RGA		244
309 #define CLK_RGA_CORE		245
310 #define ACLK_IEP		246
311 #define HCLK_IEP		247
312 #define CLK_IEP_CORE		248
313 #define HCLK_EBC		249
314 #define DCLK_EBC		250
315 #define ACLK_JDEC		251
316 #define HCLK_JDEC		252
317 #define ACLK_JENC		253
318 #define HCLK_JENC		254
319 #define PCLK_EINK		255
320 #define HCLK_EINK		256
321 #define ACLK_RKVENC_PRE		257
322 #define HCLK_RKVENC_PRE		258
323 #define ACLK_RKVENC		259
324 #define HCLK_RKVENC		260
325 #define CLK_RKVENC_CORE		261
326 #define ACLK_RKVDEC_PRE		262
327 #define HCLK_RKVDEC_PRE		263
328 #define ACLK_RKVDEC		264
329 #define HCLK_RKVDEC		265
330 #define CLK_RKVDEC_CA		266
331 #define CLK_RKVDEC_CORE		267
332 #define CLK_RKVDEC_HEVC_CA	268
333 #define ACLK_BUS		269
334 #define PCLK_BUS		270
335 #define PCLK_TSADC		271
336 #define CLK_TSADC_TSEN		272
337 #define CLK_TSADC		273
338 #define PCLK_SARADC		274
339 #define CLK_SARADC		275
340 #define PCLK_SCR		276
341 #define PCLK_WDT_NS		277
342 #define TCLK_WDT_NS		278
343 #define ACLK_DMAC0		279
344 #define ACLK_DMAC1		280
345 #define ACLK_MCU		281
346 #define PCLK_INTMUX		282
347 #define PCLK_MAILBOX		283
348 #define PCLK_UART1		284
349 #define CLK_UART1_SRC		285
350 #define CLK_UART1_FRAC		286
351 #define SCLK_UART1		287
352 #define PCLK_UART2		288
353 #define CLK_UART2_SRC		289
354 #define CLK_UART2_FRAC		290
355 #define SCLK_UART2		291
356 #define PCLK_UART3		292
357 #define CLK_UART3_SRC		293
358 #define CLK_UART3_FRAC		294
359 #define SCLK_UART3		295
360 #define PCLK_UART4		296
361 #define CLK_UART4_SRC		297
362 #define CLK_UART4_FRAC		298
363 #define SCLK_UART4		299
364 #define PCLK_UART5		300
365 #define CLK_UART5_SRC		301
366 #define CLK_UART5_FRAC		302
367 #define SCLK_UART5		303
368 #define PCLK_UART6		304
369 #define CLK_UART6_SRC		305
370 #define CLK_UART6_FRAC		306
371 #define SCLK_UART6		307
372 #define PCLK_UART7		308
373 #define CLK_UART7_SRC		309
374 #define CLK_UART7_FRAC		310
375 #define SCLK_UART7		311
376 #define PCLK_UART8		312
377 #define CLK_UART8_SRC		313
378 #define CLK_UART8_FRAC		314
379 #define SCLK_UART8		315
380 #define PCLK_UART9		316
381 #define CLK_UART9_SRC		317
382 #define CLK_UART9_FRAC		318
383 #define SCLK_UART9		319
384 #define PCLK_CAN0		320
385 #define CLK_CAN0		321
386 #define PCLK_CAN1		322
387 #define CLK_CAN1		323
388 #define PCLK_CAN2		324
389 #define CLK_CAN2		325
390 #define CLK_I2C			326
391 #define PCLK_I2C1		327
392 #define CLK_I2C1		328
393 #define PCLK_I2C2		329
394 #define CLK_I2C2		330
395 #define PCLK_I2C3		331
396 #define CLK_I2C3		332
397 #define PCLK_I2C4		333
398 #define CLK_I2C4		334
399 #define PCLK_I2C5		335
400 #define CLK_I2C5		336
401 #define PCLK_SPI0		337
402 #define CLK_SPI0		338
403 #define PCLK_SPI1		339
404 #define CLK_SPI1		340
405 #define PCLK_SPI2		341
406 #define CLK_SPI2		342
407 #define PCLK_SPI3		343
408 #define CLK_SPI3		344
409 #define PCLK_PWM1		345
410 #define CLK_PWM1		346
411 #define CLK_PWM1_CAPTURE	347
412 #define PCLK_PWM2		348
413 #define CLK_PWM2		349
414 #define CLK_PWM2_CAPTURE	350
415 #define PCLK_PWM3		351
416 #define CLK_PWM3		352
417 #define CLK_PWM3_CAPTURE	353
418 #define DBCLK_GPIO		354
419 #define PCLK_GPIO1		355
420 #define DBCLK_GPIO1		356
421 #define PCLK_GPIO2		357
422 #define DBCLK_GPIO2		358
423 #define PCLK_GPIO3		359
424 #define DBCLK_GPIO3		360
425 #define PCLK_GPIO4		361
426 #define DBCLK_GPIO4		362
427 #define OCC_SCAN_CLK_GPIO	363
428 #define PCLK_TIMER		364
429 #define CLK_TIMER0		365
430 #define CLK_TIMER1		366
431 #define CLK_TIMER2		367
432 #define CLK_TIMER3		368
433 #define CLK_TIMER4		369
434 #define CLK_TIMER5		370
435 #define ACLK_TOP_HIGH		371
436 #define ACLK_TOP_LOW		372
437 #define HCLK_TOP		373
438 #define PCLK_TOP		374
439 #define PCLK_PCIE30PHY		375
440 #define CLK_OPTC_ARB		376
441 #define PCLK_MIPICSIPHY		377
442 #define PCLK_MIPIDSIPHY0	378
443 #define PCLK_MIPIDSIPHY1	379
444 #define PCLK_PIPEPHY0		380
445 #define PCLK_PIPEPHY1		381
446 #define PCLK_PIPEPHY2		382
447 #define PCLK_CPU_BOOST		383
448 #define CLK_CPU_BOOST		384
449 #define PCLK_OTPPHY		385
450 #define SCLK_GMAC0		386
451 #define SCLK_GMAC0_RGMII_SPEED	387
452 #define SCLK_GMAC0_RMII_SPEED	388
453 #define SCLK_GMAC0_RX_TX	389
454 #define SCLK_GMAC1		390
455 #define SCLK_GMAC1_RGMII_SPEED	391
456 #define SCLK_GMAC1_RMII_SPEED	392
457 #define SCLK_GMAC1_RX_TX	393
458 #define SCLK_SDMMC0_DRV		394
459 #define SCLK_SDMMC0_SAMPLE	395
460 #define SCLK_SDMMC1_DRV		396
461 #define SCLK_SDMMC1_SAMPLE	397
462 #define SCLK_SDMMC2_DRV		398
463 #define SCLK_SDMMC2_SAMPLE	399
464 #define SCLK_EMMC_DRV		400
465 #define SCLK_EMMC_SAMPLE	401
466 #define PCLK_EDPPHY_GRF		402
467 #define CLK_HDMI_CEC            403
468 #define CLK_I2S0_8CH_TX		404
469 #define CLK_I2S0_8CH_RX		405
470 #define CLK_I2S1_8CH_TX		406
471 #define CLK_I2S1_8CH_RX		407
472 #define CLK_I2S2_2CH		408
473 #define CLK_I2S3_2CH_TX		409
474 #define CLK_I2S3_2CH_RX		410
475 #define CPLL_500M		411
476 #define CPLL_250M		412
477 #define CPLL_125M		413
478 #define CPLL_62P5M		414
479 #define CPLL_50M		415
480 #define CPLL_25M		416
481 #define CPLL_100M		417
482 #define SCLK_DDRCLK		418
483 
484 #define PCLK_CORE_PVTM		450
485 
486 #define CLK_NR_CLKS		(PCLK_CORE_PVTM + 1)
487 
488 /* pmu soft-reset indices */
489 /* pmucru_softrst_con0 */
490 #define SRST_P_PDPMU_NIU	0
491 #define SRST_P_PMUCRU		1
492 #define SRST_P_PMUGRF		2
493 #define SRST_P_I2C0		3
494 #define SRST_I2C0		4
495 #define SRST_P_UART0		5
496 #define SRST_S_UART0		6
497 #define SRST_P_PWM0		7
498 #define SRST_PWM0		8
499 #define SRST_P_GPIO0		9
500 #define SRST_GPIO0		10
501 #define SRST_P_PMUPVTM		11
502 #define SRST_PMUPVTM		12
503 
504 /* soft-reset indices */
505 
506 /* cru_softrst_con0 */
507 #define SRST_NCORERESET0	0
508 #define SRST_NCORERESET1	1
509 #define SRST_NCORERESET2	2
510 #define SRST_NCORERESET3	3
511 #define SRST_NCPUPORESET0	4
512 #define SRST_NCPUPORESET1	5
513 #define SRST_NCPUPORESET2	6
514 #define SRST_NCPUPORESET3	7
515 #define SRST_NSRESET		8
516 #define SRST_NSPORESET		9
517 #define SRST_NATRESET		10
518 #define SRST_NGICRESET		11
519 #define SRST_NPRESET		12
520 #define SRST_NPERIPHRESET	13
521 
522 /* cru_softrst_con1 */
523 #define SRST_A_CORE_NIU2DDR	16
524 #define SRST_A_CORE_NIU2BUS	17
525 #define SRST_P_DBG_NIU		18
526 #define SRST_P_DBG		19
527 #define SRST_P_DBG_DAPLITE	20
528 #define SRST_DAP		21
529 #define SRST_A_ADB400_CORE2GIC	22
530 #define SRST_A_ADB400_GIC2CORE	23
531 #define SRST_P_CORE_GRF		24
532 #define SRST_P_CORE_PVTM	25
533 #define SRST_CORE_PVTM		26
534 #define SRST_CORE_PVTPLL	27
535 
536 /* cru_softrst_con2 */
537 #define SRST_GPU		32
538 #define SRST_A_GPU_NIU		33
539 #define SRST_P_GPU_NIU		34
540 #define SRST_P_GPU_PVTM		35
541 #define SRST_GPU_PVTM		36
542 #define SRST_GPU_PVTPLL		37
543 #define SRST_A_NPU_NIU		40
544 #define SRST_H_NPU_NIU		41
545 #define SRST_P_NPU_NIU		42
546 #define SRST_A_NPU		43
547 #define SRST_H_NPU		44
548 #define SRST_P_NPU_PVTM		45
549 #define SRST_NPU_PVTM		46
550 #define SRST_NPU_PVTPLL		47
551 
552 /* cru_softrst_con3 */
553 #define SRST_A_MSCH		51
554 #define SRST_HWFFC_CTRL		52
555 #define SRST_DDR_ALWAYSON	53
556 #define SRST_A_DDRSPLIT		54
557 #define SRST_DDRDFI_CTL		55
558 #define SRST_A_DMA2DDR		57
559 
560 /* cru_softrst_con4 */
561 #define SRST_A_PERIMID_NIU	64
562 #define SRST_H_PERIMID_NIU	65
563 #define SRST_A_GIC_AUDIO_NIU	66
564 #define SRST_H_GIC_AUDIO_NIU	67
565 #define SRST_A_GIC600		68
566 #define SRST_A_GIC600_DEBUG	69
567 #define SRST_A_GICADB_CORE2GIC	70
568 #define SRST_A_GICADB_GIC2CORE	71
569 #define SRST_A_SPINLOCK		72
570 #define SRST_H_SDMMC_BUFFER	73
571 #define SRST_D_SDMMC_BUFFER	74
572 #define SRST_H_I2S0_8CH		75
573 #define SRST_H_I2S1_8CH		76
574 #define SRST_H_I2S2_2CH		77
575 #define SRST_H_I2S3_2CH		78
576 
577 /* cru_softrst_con5 */
578 #define SRST_M_I2S0_8CH_TX	80
579 #define SRST_M_I2S0_8CH_RX	81
580 #define SRST_M_I2S1_8CH_TX	82
581 #define SRST_M_I2S1_8CH_RX	83
582 #define SRST_M_I2S2_2CH		84
583 #define SRST_M_I2S3_2CH_TX	85
584 #define SRST_M_I2S3_2CH_RX	86
585 #define SRST_H_PDM		87
586 #define SRST_M_PDM		88
587 #define SRST_H_VAD		89
588 #define SRST_H_SPDIF_8CH	90
589 #define SRST_M_SPDIF_8CH	91
590 #define SRST_H_AUDPWM		92
591 #define SRST_S_AUDPWM		93
592 #define SRST_H_ACDCDIG		94
593 #define SRST_ACDCDIG		95
594 
595 /* cru_softrst_con6 */
596 #define SRST_A_SECURE_FLASH_NIU	96
597 #define SRST_H_SECURE_FLASH_NIU	97
598 #define SRST_A_CRYPTO_NS	103
599 #define SRST_H_CRYPTO_NS	104
600 #define SRST_CRYPTO_NS_CORE	105
601 #define SRST_CRYPTO_NS_PKA	106
602 #define SRST_CRYPTO_NS_RNG	107
603 #define SRST_H_TRNG_NS		108
604 #define SRST_TRNG_NS		109
605 
606 /* cru_softrst_con7 */
607 #define SRST_H_NANDC		112
608 #define SRST_N_NANDC		113
609 #define SRST_H_SFC		114
610 #define SRST_H_SFC_XIP		115
611 #define SRST_S_SFC		116
612 #define SRST_A_EMMC		117
613 #define SRST_H_EMMC		118
614 #define SRST_B_EMMC		119
615 #define SRST_C_EMMC		120
616 #define SRST_T_EMMC		121
617 
618 /* cru_softrst_con8 */
619 #define SRST_A_PIPE_NIU		128
620 #define SRST_P_PIPE_NIU		130
621 #define SRST_P_PIPE_GRF		133
622 #define SRST_A_SATA0		134
623 #define SRST_SATA0_PIPE		135
624 #define SRST_SATA0_PMALIVE	136
625 #define SRST_SATA0_RXOOB	137
626 #define SRST_A_SATA1		138
627 #define SRST_SATA1_PIPE		139
628 #define SRST_SATA1_PMALIVE	140
629 #define SRST_SATA1_RXOOB	141
630 
631 /* cru_softrst_con9 */
632 #define SRST_A_SATA2		144
633 #define SRST_SATA2_PIPE		145
634 #define SRST_SATA2_PMALIVE	146
635 #define SRST_SATA2_RXOOB	147
636 #define SRST_USB3OTG0		148
637 #define SRST_USB3OTG1		149
638 #define SRST_XPCS		150
639 #define SRST_XPCS_TX_DIV10	151
640 #define SRST_XPCS_RX_DIV10	152
641 #define SRST_XPCS_XGXS_RX	153
642 
643 /* cru_softrst_con10 */
644 #define SRST_P_PCIE20		160
645 #define SRST_PCIE20_POWERUP	161
646 #define SRST_MSTR_ARESET_PCIE20	162
647 #define SRST_SLV_ARESET_PCIE20	163
648 #define SRST_DBI_ARESET_PCIE20	164
649 #define SRST_BRESET_PCIE20	165
650 #define SRST_PERST_PCIE20	166
651 #define SRST_CORE_RST_PCIE20	167
652 #define SRST_NSTICKY_RST_PCIE20	168
653 #define SRST_STICKY_RST_PCIE20	169
654 #define SRST_PWR_RST_PCIE20	170
655 
656 /* cru_softrst_con11 */
657 #define SRST_P_PCIE30X1		176
658 #define SRST_PCIE30X1_POWERUP	177
659 #define SRST_M_ARESET_PCIE30X1	178
660 #define SRST_S_ARESET_PCIE30X1	179
661 #define SRST_D_ARESET_PCIE30X1	180
662 #define SRST_BRESET_PCIE30X1	181
663 #define SRST_PERST_PCIE30X1	182
664 #define SRST_CORE_RST_PCIE30X1	183
665 #define SRST_NSTC_RST_PCIE30X1	184
666 #define SRST_STC_RST_PCIE30X1	185
667 #define SRST_PWR_RST_PCIE30X1	186
668 
669 /* cru_softrst_con12 */
670 #define SRST_P_PCIE30X2		192
671 #define SRST_PCIE30X2_POWERUP	193
672 #define SRST_M_ARESET_PCIE30X2	194
673 #define SRST_S_ARESET_PCIE30X2	195
674 #define SRST_D_ARESET_PCIE30X2	196
675 #define SRST_BRESET_PCIE30X2	197
676 #define SRST_PERST_PCIE30X2	198
677 #define SRST_CORE_RST_PCIE30X2	199
678 #define SRST_NSTC_RST_PCIE30X2	200
679 #define SRST_STC_RST_PCIE30X2	201
680 #define SRST_PWR_RST_PCIE30X2	202
681 
682 /* cru_softrst_con13 */
683 #define SRST_A_PHP_NIU		208
684 #define SRST_H_PHP_NIU		209
685 #define SRST_P_PHP_NIU		210
686 #define SRST_H_SDMMC0		211
687 #define SRST_SDMMC0		212
688 #define SRST_H_SDMMC1		213
689 #define SRST_SDMMC1		214
690 #define SRST_A_GMAC0		215
691 #define SRST_GMAC0_TIMESTAMP	216
692 
693 /* cru_softrst_con14 */
694 #define SRST_A_USB_NIU		224
695 #define SRST_H_USB_NIU		225
696 #define SRST_P_USB_NIU		226
697 #define SRST_P_USB_GRF		227
698 #define SRST_H_USB2HOST0	228
699 #define SRST_H_USB2HOST0_ARB	229
700 #define SRST_USB2HOST0_UTMI	230
701 #define SRST_H_USB2HOST1	231
702 #define SRST_H_USB2HOST1_ARB	232
703 #define SRST_USB2HOST1_UTMI	233
704 #define SRST_H_SDMMC2		234
705 #define SRST_SDMMC2		235
706 #define SRST_A_GMAC1		236
707 #define SRST_GMAC1_TIMESTAMP	237
708 
709 /* cru_softrst_con15 */
710 #define SRST_A_VI_NIU		240
711 #define SRST_H_VI_NIU		241
712 #define SRST_P_VI_NIU		242
713 #define SRST_A_VICAP		247
714 #define SRST_H_VICAP		248
715 #define SRST_D_VICAP		249
716 #define SRST_I_VICAP		250
717 #define SRST_P_VICAP		251
718 #define SRST_H_ISP		252
719 #define SRST_ISP		253
720 #define SRST_P_CSI2HOST1	255
721 
722 /* cru_softrst_con16 */
723 #define SRST_A_VO_NIU		256
724 #define SRST_H_VO_NIU		257
725 #define SRST_P_VO_NIU		258
726 #define SRST_A_VOP_NIU		259
727 #define SRST_A_VOP		260
728 #define SRST_H_VOP		261
729 #define SRST_VOP0		262
730 #define SRST_VOP1		263
731 #define SRST_VOP2		264
732 #define SRST_VOP_PWM		265
733 #define SRST_A_HDCP		266
734 #define SRST_H_HDCP		267
735 #define SRST_P_HDCP		268
736 #define SRST_P_HDMI_HOST	270
737 #define SRST_HDMI_HOST		271
738 
739 /* cru_softrst_con17 */
740 #define SRST_P_DSITX_0		272
741 #define SRST_P_DSITX_1		273
742 #define SRST_P_EDP_CTRL		274
743 #define SRST_EDP_24M		275
744 #define SRST_A_VPU_NIU		280
745 #define SRST_H_VPU_NIU		281
746 #define SRST_A_VPU		282
747 #define SRST_H_VPU		283
748 #define SRST_H_EINK		286
749 #define SRST_P_EINK		287
750 
751 /* cru_softrst_con18 */
752 #define SRST_A_RGA_NIU		288
753 #define SRST_H_RGA_NIU		289
754 #define SRST_P_RGA_NIU		290
755 #define SRST_A_RGA		292
756 #define SRST_H_RGA		293
757 #define SRST_RGA_CORE		294
758 #define SRST_A_IEP		295
759 #define SRST_H_IEP		296
760 #define SRST_IEP_CORE		297
761 #define SRST_H_EBC		298
762 #define SRST_D_EBC		299
763 #define SRST_A_JDEC		300
764 #define SRST_H_JDEC		301
765 #define SRST_A_JENC		302
766 #define SRST_H_JENC		303
767 
768 /* cru_softrst_con19 */
769 #define SRST_A_VENC_NIU		304
770 #define SRST_H_VENC_NIU		305
771 #define SRST_A_RKVENC		307
772 #define SRST_H_RKVENC		308
773 #define SRST_RKVENC_CORE	309
774 
775 /* cru_softrst_con20 */
776 #define SRST_A_RKVDEC_NIU	320
777 #define SRST_H_RKVDEC_NIU	321
778 #define SRST_A_RKVDEC		322
779 #define SRST_H_RKVDEC		323
780 #define SRST_RKVDEC_CA		324
781 #define SRST_RKVDEC_CORE	325
782 #define SRST_RKVDEC_HEVC_CA	326
783 
784 /* cru_softrst_con21 */
785 #define SRST_A_BUS_NIU		336
786 #define SRST_P_BUS_NIU		338
787 #define SRST_P_CAN0		340
788 #define SRST_CAN0		341
789 #define SRST_P_CAN1		342
790 #define SRST_CAN1		343
791 #define SRST_P_CAN2		344
792 #define SRST_CAN2		345
793 #define SRST_P_GPIO1		346
794 #define SRST_GPIO1		347
795 #define SRST_P_GPIO2		348
796 #define SRST_GPIO2		349
797 #define SRST_P_GPIO3		350
798 #define SRST_GPIO3		351
799 
800 /* cru_softrst_con22 */
801 #define SRST_P_GPIO4		352
802 #define SRST_GPIO4		353
803 #define SRST_P_I2C1		354
804 #define SRST_I2C1		355
805 #define SRST_P_I2C2		356
806 #define SRST_I2C2		357
807 #define SRST_P_I2C3		358
808 #define SRST_I2C3		359
809 #define SRST_P_I2C4		360
810 #define SRST_I2C4		361
811 #define SRST_P_I2C5		362
812 #define SRST_I2C5		363
813 #define SRST_P_OTPC_NS		364
814 #define SRST_OTPC_NS_SBPI	365
815 #define SRST_OTPC_NS_USR	366
816 
817 /* cru_softrst_con23 */
818 #define SRST_P_PWM1		368
819 #define SRST_PWM1		369
820 #define SRST_P_PWM2		370
821 #define SRST_PWM2		371
822 #define SRST_P_PWM3		372
823 #define SRST_PWM3		373
824 #define SRST_P_SPI0		374
825 #define SRST_SPI0		375
826 #define SRST_P_SPI1		376
827 #define SRST_SPI1		377
828 #define SRST_P_SPI2		378
829 #define SRST_SPI2		379
830 #define SRST_P_SPI3		380
831 #define SRST_SPI3		381
832 
833 /* cru_softrst_con24 */
834 #define SRST_P_SARADC		384
835 #define SRST_P_TSADC		385
836 #define SRST_TSADC		386
837 #define SRST_P_TIMER		387
838 #define SRST_TIMER0		388
839 #define SRST_TIMER1		389
840 #define SRST_TIMER2		390
841 #define SRST_TIMER3		391
842 #define SRST_TIMER4		392
843 #define SRST_TIMER5		393
844 #define SRST_P_UART1		394
845 #define SRST_S_UART1		395
846 
847 /* cru_softrst_con25 */
848 #define SRST_P_UART2		400
849 #define SRST_S_UART2		401
850 #define SRST_P_UART3		402
851 #define SRST_S_UART3		403
852 #define SRST_P_UART4		404
853 #define SRST_S_UART4		405
854 #define SRST_P_UART5		406
855 #define SRST_S_UART5		407
856 #define SRST_P_UART6		408
857 #define SRST_S_UART6		409
858 #define SRST_P_UART7		410
859 #define SRST_S_UART7		411
860 #define SRST_P_UART8		412
861 #define SRST_S_UART8		413
862 #define SRST_P_UART9		414
863 #define SRST_S_UART9		415
864 
865 /* cru_softrst_con26 */
866 #define SRST_P_GRF 416
867 #define SRST_P_GRF_VCCIO12	417
868 #define SRST_P_GRF_VCCIO34	418
869 #define SRST_P_GRF_VCCIO567	419
870 #define SRST_P_SCR		420
871 #define SRST_P_WDT_NS		421
872 #define SRST_T_WDT_NS		422
873 #define SRST_P_DFT2APB		423
874 #define SRST_A_MCU		426
875 #define SRST_P_INTMUX		427
876 #define SRST_P_MAILBOX		428
877 
878 /* cru_softrst_con27 */
879 #define SRST_A_TOP_HIGH_NIU	432
880 #define SRST_A_TOP_LOW_NIU	433
881 #define SRST_H_TOP_NIU		434
882 #define SRST_P_TOP_NIU		435
883 #define SRST_P_TOP_CRU		438
884 #define SRST_P_DDRPHY		439
885 #define SRST_DDRPHY		440
886 #define SRST_P_MIPICSIPHY	442
887 #define SRST_P_MIPIDSIPHY0	443
888 #define SRST_P_MIPIDSIPHY1	444
889 #define SRST_P_PCIE30PHY	445
890 #define SRST_PCIE30PHY		446
891 #define SRST_P_PCIE30PHY_GRF	447
892 
893 /* cru_softrst_con28 */
894 #define SRST_P_APB2ASB_LEFT	448
895 #define SRST_P_APB2ASB_BOTTOM	449
896 #define SRST_P_ASB2APB_LEFT	450
897 #define SRST_P_ASB2APB_BOTTOM	451
898 #define SRST_P_PIPEPHY0		452
899 #define SRST_PIPEPHY0		453
900 #define SRST_P_PIPEPHY1		454
901 #define SRST_PIPEPHY1		455
902 #define SRST_P_PIPEPHY2		456
903 #define SRST_PIPEPHY2		457
904 #define SRST_P_USB2PHY0_GRF	458
905 #define SRST_P_USB2PHY1_GRF	459
906 #define SRST_P_CPU_BOOST	460
907 #define SRST_CPU_BOOST		461
908 #define SRST_P_OTPPHY		462
909 #define SRST_OTPPHY		463
910 
911 /* cru_softrst_con29 */
912 #define SRST_USB2PHY0_POR	464
913 #define SRST_USB2PHY0_USB3OTG0	465
914 #define SRST_USB2PHY0_USB3OTG1	466
915 #define SRST_USB2PHY1_POR	467
916 #define SRST_USB2PHY1_USB2HOST0	468
917 #define SRST_USB2PHY1_USB2HOST1	469
918 #define SRST_P_EDPPHY_GRF	470
919 #define SRST_TSADCPHY		471
920 #define SRST_GMAC0_DELAYLINE	472
921 #define SRST_GMAC1_DELAYLINE	473
922 #define SRST_OTPC_ARB		474
923 #define SRST_P_PIPEPHY0_GRF	475
924 #define SRST_P_PIPEPHY1_GRF	476
925 #define SRST_P_PIPEPHY2_GRF	477
926 
927 #endif
928