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Searched refs:SOCCLK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h367 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
840 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1169 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1732 double SOCCLK; member
H A Ddml2_core_dcn4.c547 …ode_support_result.global.socclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.SOCCLK * 1000); in core_dcn4_mode_support()
H A Ddml2_core_dcn4_calcs.c6764 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6773 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6774 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7928 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_ms_prefetch_check()
7990 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()
8011 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_support()
10448 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml_core_mode_programming()
10505 DML_ASSERT(s->SOCCLK > 0); in dml_core_mode_programming()
10520 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); in dml_core_mode_programming()
11744 CalculateWatermarks_params->SOCCLK = s->SOCCLK; in dml_core_mode_programming()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h810 double SOCCLK,
H A Ddisplay_mode_vba_32.c1197 v->SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3735 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
H A Ddcn32_fpu.c1629 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn32_calculate_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()
H A Ddisplay_mode_vba.h437 double SOCCLK; member
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core_structs.h833 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1346 dml_float_t SOCCLK; member
H A Ddisplay_mode_core.c2873 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2882 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2883 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6682 CalculateWatermarks_params->SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_prefetch_check()
8264 mode_lib->ms.SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_core_mode_support()
8358 dml_print("DML::%s: Using SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_programming()
9455 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_mode_programming()
10101 mode_lib->ms.SOCCLK = (dml_float_t)state->socclk_mhz; in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Daldebaran_ppt.c160 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
H A Dsmu_v13_0_7_ppt.c168 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
H A Dsmu_v13_0_0_ppt.c177 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
H A Dsmu_v13_0_6_ppt.c186 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_2_ppt.c150 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1155 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()