| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 810 double SOCCLK,
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| H A D | display_mode_vba_util_32.c | 4265 double SOCCLK, in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() argument
4363 + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4376 + mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4378 + mmSOCParameters.WritebackLatency + v->WritebackChunkSize * 1024 / 32 / SOCCLK; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
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| H A D | display_mode_vba_32.c | 1197 v->SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3735 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_vba.h | 437 double SOCCLK; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core_structs.h | 833 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1346 dml_float_t SOCCLK; member
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| H A D | display_mode_core.c | 2862 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2871 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2872 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6665 CalculateWatermarks_params->SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_prefetch_check()
8247 mode_lib->ms.SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_core_mode_support()
8341 dml_print("DML::%s: Using SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_programming()
9438 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_mode_programming()
10084 mode_lib->ms.SOCCLK = (dml_float_t)state->socclk_mhz; in fetch_socbb_params()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 114 FEA_MAP_REVERSE(SOCCLK),
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| H A D | smu_v13_0_4_ppt.c | 118 FEA_MAP_REVERSE(SOCCLK),
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| H A D | yellow_carp_ppt.c | 114 FEA_MAP_REVERSE(SOCCLK),
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| H A D | aldebaran_ppt.c | 160 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_7_ppt.c | 168 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_0_ppt.c | 177 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_6_ppt.c | 186 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 272 double SOCCLK,
2614 v->SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4944 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel]; in dml30_ModeSupportAndSystemConfigurationFull()
4957 double SOCCLK, in CalculateWatermarksAndDRAMSpeedChangeSupport() argument
5013 …v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in CalculateWatermarksAndDRAMSpeedChangeSupport()
5019 …FinalDRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; in CalculateWatermarksAndDRAMSpeedChangeSupport()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu15/ |
| H A D | smu_v15_0_0_ppt.c | 132 FEA_MAP_REVERSE(SOCCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 109 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 156 FEA_MAP_REVERSE(SOCCLK),
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| H A D | smu_v14_0_2_ppt.c | 148 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | arcturus_ppt.c | 165 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | vangogh_ppt.c | 190 FEA_MAP_REVERSE(SOCCLK),
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| H A D | navi10_ppt.c | 154 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | sienna_cichlid_ppt.c | 169 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 6743 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6752 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6753 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7908 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_ms_prefetch_check()
7970 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()
7991 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_support()
10426 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml_core_mode_programming()
10483 DML_ASSERT(s->SOCCLK > 0); in dml_core_mode_programming()
10498 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); in dml_core_mode_programming()
11723 CalculateWatermarks_params->SOCCLK = s->SOCCLK; in dml_core_mode_programming()
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