1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/cpuid/api.h>
20 #include <asm/debugreg.h>
21 #include <asm/hardirq.h>
22 #include <asm/intel-family.h>
23 #include <asm/intel_pt.h>
24 #include <asm/apic.h>
25 #include <asm/cpu_device_id.h>
26 #include <asm/msr.h>
27
28 #include "../perf_event.h"
29
30 /*
31 * Intel PerfMon, used on Core and later.
32 */
33 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
34 {
35 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
36 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
37 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
38 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
39 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
40 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
41 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
42 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
43 };
44
45 static struct event_constraint intel_core_event_constraints[] __read_mostly =
46 {
47 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
48 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
49 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
50 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
51 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
52 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
53 EVENT_CONSTRAINT_END
54 };
55
56 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
57 {
58 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
59 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
60 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
61 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
62 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
63 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
64 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
65 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
66 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
67 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
68 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
69 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
70 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
71 EVENT_CONSTRAINT_END
72 };
73
74 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
75 {
76 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
77 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
78 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
79 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
80 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
81 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
82 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
83 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
84 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
85 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
86 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
87 EVENT_CONSTRAINT_END
88 };
89
90 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
91 {
92 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
93 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
94 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
95 EVENT_EXTRA_END
96 };
97
98 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
99 {
100 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
101 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
102 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
103 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
104 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
105 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
106 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
107 EVENT_CONSTRAINT_END
108 };
109
110 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
111 {
112 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
113 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
114 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
119 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
120 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
121 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
122 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
123 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
124
125 /*
126 * When HT is off these events can only run on the bottom 4 counters
127 * When HT is on, they are impacted by the HT bug and require EXCL access
128 */
129 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
130 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
132 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
133
134 EVENT_CONSTRAINT_END
135 };
136
137 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
138 {
139 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
140 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
141 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
142 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
144 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
145 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
147 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
151 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
152
153 /*
154 * When HT is off these events can only run on the bottom 4 counters
155 * When HT is on, they are impacted by the HT bug and require EXCL access
156 */
157 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
158 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
160 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
161
162 EVENT_CONSTRAINT_END
163 };
164
165 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
166 {
167 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
168 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
169 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
170 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
171 EVENT_EXTRA_END
172 };
173
174 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
175 {
176 EVENT_CONSTRAINT_END
177 };
178
179 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
180 {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 EVENT_CONSTRAINT_END
185 };
186
187 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
188 {
189 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
190 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
191 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
192 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
193 FIXED_EVENT_CONSTRAINT(0x0500, 4),
194 FIXED_EVENT_CONSTRAINT(0x0600, 5),
195 FIXED_EVENT_CONSTRAINT(0x0700, 6),
196 FIXED_EVENT_CONSTRAINT(0x0800, 7),
197 FIXED_EVENT_CONSTRAINT(0x0900, 8),
198 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
199 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
200 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
201 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
202 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
203 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
204 FIXED_EVENT_CONSTRAINT(0x1000, 15),
205 EVENT_CONSTRAINT_END
206 };
207
208 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
209 {
210 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
211 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
212 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
213 EVENT_CONSTRAINT_END
214 };
215
216 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
217 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
218 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
219 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
220 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
221 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
222 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
223 EVENT_CONSTRAINT_END
224 };
225
226 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
227 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
228 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
229 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
230 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
231 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
232 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
233 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
234 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
235 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
236 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
237 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
238 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
239 EVENT_CONSTRAINT_END
240 };
241
242 static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
243 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
244 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
245 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
246 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
247 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
248 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
249 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
250 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
251 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
252 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
253 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
254 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
255 INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
256 INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
257 INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
258 INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
259 INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
260 INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
261 INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
262 INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1),
263 EVENT_CONSTRAINT_END
264 };
265
266 static struct event_constraint intel_skl_event_constraints[] = {
267 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
268 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
269 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
270 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
271
272 /*
273 * when HT is off, these can only run on the bottom 4 counters
274 */
275 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
276 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
277 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
278 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
279 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
280
281 EVENT_CONSTRAINT_END
282 };
283
284 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
285 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
286 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
287 EVENT_EXTRA_END
288 };
289
290 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
291 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
292 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
293 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
294 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
295 EVENT_EXTRA_END
296 };
297
298 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
299 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
300 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
301 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
302 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
303 EVENT_EXTRA_END
304 };
305
306 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
307 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
308 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
309 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
310 /*
311 * Note the low 8 bits eventsel code is not a continuous field, containing
312 * some #GPing bits. These are masked out.
313 */
314 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
315 EVENT_EXTRA_END
316 };
317
318 static struct event_constraint intel_icl_event_constraints[] = {
319 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
320 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
321 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
322 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
323 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
324 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
325 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
326 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
327 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
328 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
329 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
330 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
331 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
332 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
333 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
334 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
335 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
336 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
337 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
338 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
339 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
340 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
341 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
342 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
343 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
344 EVENT_CONSTRAINT_END
345 };
346
347 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
348 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
349 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
350 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
351 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
352 EVENT_EXTRA_END
353 };
354
355 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
356 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
357 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
358 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
359 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
360 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
361 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
362 EVENT_EXTRA_END
363 };
364
365 static struct event_constraint intel_glc_event_constraints[] = {
366 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
367 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
368 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
369 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
370 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
371 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
372 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
373 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
374 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
375 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
376 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
377 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
378 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
379 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
380 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
381
382 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
383 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
384 /*
385 * Generally event codes < 0x90 are restricted to counters 0-3.
386 * The 0x2E and 0x3C are exception, which has no restriction.
387 */
388 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
389
390 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
391 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
392 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
393 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
394 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
395 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
396 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
397 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
398 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
399 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
400 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
401 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
402 /*
403 * Generally event codes >= 0x90 are likely to have no restrictions.
404 * The exception are defined as above.
405 */
406 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
407
408 EVENT_CONSTRAINT_END
409 };
410
411 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
412 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
413 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
414 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
415 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
416 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
417 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
418 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
419 EVENT_EXTRA_END
420 };
421
422 static struct event_constraint intel_lnc_event_constraints[] = {
423 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
424 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
425 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
426 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
427 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
428 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
429 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
430 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
431 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
432 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
433 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
434 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
435 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
436 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
437 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
438
439 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
440
441 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
442 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
443
444 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
445 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
446
447 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
448 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
449 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
450 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
451 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8),
452 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
453 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
454 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
455
456 INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff),
457 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
458
459 EVENT_CONSTRAINT_END
460 };
461
462 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
463 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
464 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
465 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
466 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
467 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
468 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
469 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
470 EVENT_EXTRA_END
471 };
472
473 static struct event_constraint intel_pnc_event_constraints[] = {
474 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
475 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
476 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
477 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
478 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
479 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
480 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
481 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
482 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
483 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
484 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
485 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
486 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
487 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
488 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
489
490 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
491 INTEL_EVENT_CONSTRAINT(0x79, 0xf),
492
493 INTEL_UEVENT_CONSTRAINT(0x0275, 0xf),
494 INTEL_UEVENT_CONSTRAINT(0x0176, 0xf),
495 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
496 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
497 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc),
498 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
499
500 INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
501 INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
502 INTEL_EVENT_CONSTRAINT(0xd4, 0xf),
503 INTEL_EVENT_CONSTRAINT(0xd6, 0xf),
504 INTEL_EVENT_CONSTRAINT(0xdf, 0xf),
505 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
506
507 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
508 INTEL_UEVENT_CONSTRAINT(0x01b2, 0xf),
509 INTEL_UEVENT_CONSTRAINT(0x02b2, 0xf),
510 INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
511 INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
512 INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
513 INTEL_UEVENT_CONSTRAINT(0x0148, 0xf),
514
515 EVENT_CONSTRAINT_END
516 };
517
518 static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
519 /* must define OMR_X first, see intel_alt_er() */
520 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
521 INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
522 INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
523 INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
524 INTEL_UEVENT_EXTRA_REG(0x014f, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
525 INTEL_UEVENT_EXTRA_REG(0x024f, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
526 INTEL_UEVENT_EXTRA_REG(0x044f, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
527 INTEL_UEVENT_EXTRA_REG(0x084f, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
528 INTEL_UEVENT_EXTRA_REG(0x01d6, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
529 INTEL_UEVENT_EXTRA_REG(0x02d6, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
530 INTEL_UEVENT_EXTRA_REG(0x04d6, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
531 INTEL_UEVENT_EXTRA_REG(0x08d6, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
532 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
533 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
534 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
535 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
536 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
537 EVENT_EXTRA_END
538 };
539
540 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
541 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
542 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
543
544 static struct attribute *nhm_mem_events_attrs[] = {
545 EVENT_PTR(mem_ld_nhm),
546 NULL,
547 };
548
549 /*
550 * topdown events for Intel Core CPUs.
551 *
552 * The events are all in slots, which is a free slot in a 4 wide
553 * pipeline. Some events are already reported in slots, for cycle
554 * events we multiply by the pipeline width (4).
555 *
556 * With Hyper Threading on, topdown metrics are either summed or averaged
557 * between the threads of a core: (count_t0 + count_t1).
558 *
559 * For the average case the metric is always scaled to pipeline width,
560 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
561 */
562
563 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
564 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
565 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
566 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
567 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
568 "event=0xe,umask=0x1"); /* uops_issued.any */
569 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
570 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
571 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
572 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
573 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
574 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
575 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
576 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
577 "4", "2");
578
579 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
580 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
581 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
582 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
583 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
584 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
585 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
586 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
587 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
588
589 static struct attribute *snb_events_attrs[] = {
590 EVENT_PTR(td_slots_issued),
591 EVENT_PTR(td_slots_retired),
592 EVENT_PTR(td_fetch_bubbles),
593 EVENT_PTR(td_total_slots),
594 EVENT_PTR(td_total_slots_scale),
595 EVENT_PTR(td_recovery_bubbles),
596 EVENT_PTR(td_recovery_bubbles_scale),
597 NULL,
598 };
599
600 static struct attribute *snb_mem_events_attrs[] = {
601 EVENT_PTR(mem_ld_snb),
602 EVENT_PTR(mem_st_snb),
603 NULL,
604 };
605
606 static struct event_constraint intel_hsw_event_constraints[] = {
607 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
608 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
609 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
610 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
611 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
612 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
613 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
614 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
615 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
616 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
617 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
618 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
619
620 /*
621 * When HT is off these events can only run on the bottom 4 counters
622 * When HT is on, they are impacted by the HT bug and require EXCL access
623 */
624 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
625 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
626 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
627 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
628
629 EVENT_CONSTRAINT_END
630 };
631
632 static struct event_constraint intel_bdw_event_constraints[] = {
633 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
634 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
635 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
636 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
637 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
638 /*
639 * when HT is off, these can only run on the bottom 4 counters
640 */
641 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
642 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
643 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
644 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
645 EVENT_CONSTRAINT_END
646 };
647
intel_pmu_event_map(int hw_event)648 static u64 intel_pmu_event_map(int hw_event)
649 {
650 return intel_perfmon_event_map[hw_event];
651 }
652
653 static __initconst const u64 glc_hw_cache_event_ids
654 [PERF_COUNT_HW_CACHE_MAX]
655 [PERF_COUNT_HW_CACHE_OP_MAX]
656 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
657 {
658 [ C(L1D ) ] = {
659 [ C(OP_READ) ] = {
660 [ C(RESULT_ACCESS) ] = 0x81d0,
661 [ C(RESULT_MISS) ] = 0xe124,
662 },
663 [ C(OP_WRITE) ] = {
664 [ C(RESULT_ACCESS) ] = 0x82d0,
665 },
666 },
667 [ C(L1I ) ] = {
668 [ C(OP_READ) ] = {
669 [ C(RESULT_MISS) ] = 0xe424,
670 },
671 [ C(OP_WRITE) ] = {
672 [ C(RESULT_ACCESS) ] = -1,
673 [ C(RESULT_MISS) ] = -1,
674 },
675 },
676 [ C(LL ) ] = {
677 [ C(OP_READ) ] = {
678 [ C(RESULT_ACCESS) ] = 0x12a,
679 [ C(RESULT_MISS) ] = 0x12a,
680 },
681 [ C(OP_WRITE) ] = {
682 [ C(RESULT_ACCESS) ] = 0x12a,
683 [ C(RESULT_MISS) ] = 0x12a,
684 },
685 },
686 [ C(DTLB) ] = {
687 [ C(OP_READ) ] = {
688 [ C(RESULT_ACCESS) ] = 0x81d0,
689 [ C(RESULT_MISS) ] = 0xe12,
690 },
691 [ C(OP_WRITE) ] = {
692 [ C(RESULT_ACCESS) ] = 0x82d0,
693 [ C(RESULT_MISS) ] = 0xe13,
694 },
695 },
696 [ C(ITLB) ] = {
697 [ C(OP_READ) ] = {
698 [ C(RESULT_ACCESS) ] = -1,
699 [ C(RESULT_MISS) ] = 0xe11,
700 },
701 [ C(OP_WRITE) ] = {
702 [ C(RESULT_ACCESS) ] = -1,
703 [ C(RESULT_MISS) ] = -1,
704 },
705 [ C(OP_PREFETCH) ] = {
706 [ C(RESULT_ACCESS) ] = -1,
707 [ C(RESULT_MISS) ] = -1,
708 },
709 },
710 [ C(BPU ) ] = {
711 [ C(OP_READ) ] = {
712 [ C(RESULT_ACCESS) ] = 0x4c4,
713 [ C(RESULT_MISS) ] = 0x4c5,
714 },
715 [ C(OP_WRITE) ] = {
716 [ C(RESULT_ACCESS) ] = -1,
717 [ C(RESULT_MISS) ] = -1,
718 },
719 [ C(OP_PREFETCH) ] = {
720 [ C(RESULT_ACCESS) ] = -1,
721 [ C(RESULT_MISS) ] = -1,
722 },
723 },
724 [ C(NODE) ] = {
725 [ C(OP_READ) ] = {
726 [ C(RESULT_ACCESS) ] = 0x12a,
727 [ C(RESULT_MISS) ] = 0x12a,
728 },
729 },
730 };
731
732 /* ADL P-core (Golden cove) specific event code. */
733 static __initconst const u64 adl_glc_hw_cache_event_ids
734 [PERF_COUNT_HW_CACHE_MAX]
735 [PERF_COUNT_HW_CACHE_OP_MAX]
736 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
737 {
738 [ C(L1D ) ] = {
739 [ C(OP_READ) ] = {
740 [ C(RESULT_ACCESS) ] = 0x81d0,
741 [ C(RESULT_MISS) ] = 0xe124,
742 },
743 [ C(OP_WRITE) ] = {
744 [ C(RESULT_ACCESS) ] = 0x82d0,
745 },
746 },
747 [ C(L1I ) ] = {
748 [ C(OP_READ) ] = {
749 [ C(RESULT_MISS) ] = 0xe424,
750 },
751 [ C(OP_WRITE) ] = {
752 [ C(RESULT_ACCESS) ] = -1,
753 [ C(RESULT_MISS) ] = -1,
754 },
755 },
756 [ C(LL ) ] = {
757 [ C(OP_READ) ] = {
758 [ C(RESULT_ACCESS) ] = 0x12a,
759 [ C(RESULT_MISS) ] = 0x12a,
760 },
761 [ C(OP_WRITE) ] = {
762 [ C(RESULT_ACCESS) ] = 0x12a,
763 [ C(RESULT_MISS) ] = 0x12a,
764 },
765 },
766 [ C(DTLB) ] = {
767 [ C(OP_READ) ] = {
768 [ C(RESULT_ACCESS) ] = 0x81d0,
769 [ C(RESULT_MISS) ] = 0xe12,
770 },
771 [ C(OP_WRITE) ] = {
772 [ C(RESULT_ACCESS) ] = 0x82d0,
773 [ C(RESULT_MISS) ] = 0xe13,
774 },
775 },
776 [ C(ITLB) ] = {
777 [ C(OP_READ) ] = {
778 [ C(RESULT_ACCESS) ] = -1,
779 [ C(RESULT_MISS) ] = 0xe11,
780 },
781 [ C(OP_WRITE) ] = {
782 [ C(RESULT_ACCESS) ] = -1,
783 [ C(RESULT_MISS) ] = -1,
784 },
785 [ C(OP_PREFETCH) ] = {
786 [ C(RESULT_ACCESS) ] = -1,
787 [ C(RESULT_MISS) ] = -1,
788 },
789 },
790 [ C(BPU ) ] = {
791 [ C(OP_READ) ] = {
792 [ C(RESULT_ACCESS) ] = 0x4c4,
793 [ C(RESULT_MISS) ] = 0x4c5,
794 },
795 [ C(OP_WRITE) ] = {
796 [ C(RESULT_ACCESS) ] = -1,
797 [ C(RESULT_MISS) ] = -1,
798 },
799 [ C(OP_PREFETCH) ] = {
800 [ C(RESULT_ACCESS) ] = -1,
801 [ C(RESULT_MISS) ] = -1,
802 },
803 },
804 };
805
806 static __initconst const u64 glc_hw_cache_extra_regs
807 [PERF_COUNT_HW_CACHE_MAX]
808 [PERF_COUNT_HW_CACHE_OP_MAX]
809 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
810 {
811 [ C(LL ) ] = {
812 [ C(OP_READ) ] = {
813 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
814 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
815 },
816 [ C(OP_WRITE) ] = {
817 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
818 [ C(RESULT_MISS) ] = 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */
819 },
820 },
821 [ C(NODE) ] = {
822 [ C(OP_READ) ] = {
823 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
824 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
825 },
826 },
827 };
828
829 /* ADL P-core (Golden cove) specific extra regs value. */
830 static __initconst const u64 adl_glc_hw_cache_extra_regs
831 [PERF_COUNT_HW_CACHE_MAX]
832 [PERF_COUNT_HW_CACHE_OP_MAX]
833 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
834 {
835 [ C(LL ) ] = {
836 [ C(OP_READ) ] = {
837 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
838 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
839 },
840 [ C(OP_WRITE) ] = {
841 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
842 [ C(RESULT_MISS) ] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
843 },
844 },
845 };
846
847 static __initconst const u64 lnc_hw_cache_extra_regs
848 [PERF_COUNT_HW_CACHE_MAX]
849 [PERF_COUNT_HW_CACHE_OP_MAX]
850 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
851 {
852 [ C(LL ) ] = {
853 [ C(OP_READ) ] = {
854 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
855 [ C(RESULT_MISS) ] = 0x9E7FA000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
856 },
857 [ C(OP_WRITE) ] = {
858 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
859 [ C(RESULT_MISS) ] = 0x9E7FA000002, /* OCR.DEMAND_RFO.L3_MISS */
860 },
861 },
862 };
863
864 /* ARL specific lioncove hw_cache_extra_regs[] variant. */
865 static __initconst const u64 arl_lnc_hw_cache_extra_regs
866 [PERF_COUNT_HW_CACHE_MAX]
867 [PERF_COUNT_HW_CACHE_OP_MAX]
868 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
869 {
870 [ C(LL ) ] = {
871 [ C(OP_READ) ] = {
872 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
873 [ C(RESULT_MISS) ] = 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
874 },
875 [ C(OP_WRITE) ] = {
876 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
877 [ C(RESULT_MISS) ] = 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */
878 },
879 },
880 };
881
882 static __initconst const u64 pnc_hw_cache_event_ids
883 [PERF_COUNT_HW_CACHE_MAX]
884 [PERF_COUNT_HW_CACHE_OP_MAX]
885 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
886 {
887 [ C(L1D ) ] = {
888 [ C(OP_READ) ] = {
889 [ C(RESULT_ACCESS) ] = 0x81d0,
890 [ C(RESULT_MISS) ] = 0xe124,
891 },
892 [ C(OP_WRITE) ] = {
893 [ C(RESULT_ACCESS) ] = 0x82d0,
894 },
895 },
896 [ C(L1I ) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_MISS) ] = 0xe424,
899 },
900 [ C(OP_WRITE) ] = {
901 [ C(RESULT_ACCESS) ] = -1,
902 [ C(RESULT_MISS) ] = -1,
903 },
904 },
905 [ C(LL ) ] = {
906 [ C(OP_READ) ] = {
907 [ C(RESULT_ACCESS) ] = 0x12a,
908 [ C(RESULT_MISS) ] = 0x12a,
909 },
910 [ C(OP_WRITE) ] = {
911 [ C(RESULT_ACCESS) ] = 0x12a,
912 [ C(RESULT_MISS) ] = 0x12a,
913 },
914 },
915 [ C(DTLB) ] = {
916 [ C(OP_READ) ] = {
917 [ C(RESULT_ACCESS) ] = 0x81d0,
918 [ C(RESULT_MISS) ] = 0xe12,
919 },
920 [ C(OP_WRITE) ] = {
921 [ C(RESULT_ACCESS) ] = 0x82d0,
922 [ C(RESULT_MISS) ] = 0xe13,
923 },
924 },
925 [ C(ITLB) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = -1,
928 [ C(RESULT_MISS) ] = 0xe11,
929 },
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = -1,
932 [ C(RESULT_MISS) ] = -1,
933 },
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = -1,
936 [ C(RESULT_MISS) ] = -1,
937 },
938 },
939 [ C(BPU ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x4c4,
942 [ C(RESULT_MISS) ] = 0x4c5,
943 },
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
947 },
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = -1,
950 [ C(RESULT_MISS) ] = -1,
951 },
952 },
953 [ C(NODE) ] = {
954 [ C(OP_READ) ] = {
955 [ C(RESULT_ACCESS) ] = -1,
956 [ C(RESULT_MISS) ] = -1,
957 },
958 },
959 };
960
961 static __initconst const u64 pnc_hw_cache_extra_regs
962 [PERF_COUNT_HW_CACHE_MAX]
963 [PERF_COUNT_HW_CACHE_OP_MAX]
964 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
965 {
966 [ C(LL ) ] = {
967 [ C(OP_READ) ] = {
968 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
969 [ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
970 },
971 [ C(OP_WRITE) ] = {
972 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
973 [ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */
974 },
975 },
976 };
977
978 static __initconst const u64 cyc_hw_cache_extra_regs
979 [PERF_COUNT_HW_CACHE_MAX]
980 [PERF_COUNT_HW_CACHE_OP_MAX]
981 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
982 {
983 [ C(LL ) ] = {
984 [ C(OP_READ) ] = {
985 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
986 [ C(RESULT_MISS) ] = 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
987 },
988 [ C(OP_WRITE) ] = {
989 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
990 [ C(RESULT_MISS) ] = 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */
991 },
992 },
993 };
994
995 /*
996 * Notes on the events:
997 * - data reads do not include code reads (comparable to earlier tables)
998 * - data counts include speculative execution (except L1 write, dtlb, bpu)
999 * - remote node access includes remote memory, remote cache, remote mmio.
1000 * - prefetches are not included in the counts.
1001 * - icache miss does not include decoded icache
1002 */
1003
1004 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
1005 #define SKL_DEMAND_RFO BIT_ULL(1)
1006 #define SKL_ANY_RESPONSE BIT_ULL(16)
1007 #define SKL_SUPPLIER_NONE BIT_ULL(17)
1008 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
1009 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
1010 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
1011 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
1012 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
1013 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
1014 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
1015 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
1016 #define SKL_SPL_HIT BIT_ULL(30)
1017 #define SKL_SNOOP_NONE BIT_ULL(31)
1018 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
1019 #define SKL_SNOOP_MISS BIT_ULL(33)
1020 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
1021 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1022 #define SKL_SNOOP_HITM BIT_ULL(36)
1023 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
1024 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
1025 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
1026 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
1027 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
1028 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
1029 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
1030 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
1031 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
1032 SKL_SNOOP_HITM|SKL_SPL_HIT)
1033 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
1034 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
1035 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
1036 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
1037 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
1038
1039 static __initconst const u64 skl_hw_cache_event_ids
1040 [PERF_COUNT_HW_CACHE_MAX]
1041 [PERF_COUNT_HW_CACHE_OP_MAX]
1042 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1043 {
1044 [ C(L1D ) ] = {
1045 [ C(OP_READ) ] = {
1046 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
1047 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1048 },
1049 [ C(OP_WRITE) ] = {
1050 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
1051 [ C(RESULT_MISS) ] = 0x0,
1052 },
1053 [ C(OP_PREFETCH) ] = {
1054 [ C(RESULT_ACCESS) ] = 0x0,
1055 [ C(RESULT_MISS) ] = 0x0,
1056 },
1057 },
1058 [ C(L1I ) ] = {
1059 [ C(OP_READ) ] = {
1060 [ C(RESULT_ACCESS) ] = 0x0,
1061 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
1062 },
1063 [ C(OP_WRITE) ] = {
1064 [ C(RESULT_ACCESS) ] = -1,
1065 [ C(RESULT_MISS) ] = -1,
1066 },
1067 [ C(OP_PREFETCH) ] = {
1068 [ C(RESULT_ACCESS) ] = 0x0,
1069 [ C(RESULT_MISS) ] = 0x0,
1070 },
1071 },
1072 [ C(LL ) ] = {
1073 [ C(OP_READ) ] = {
1074 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1075 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1076 },
1077 [ C(OP_WRITE) ] = {
1078 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1079 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1080 },
1081 [ C(OP_PREFETCH) ] = {
1082 [ C(RESULT_ACCESS) ] = 0x0,
1083 [ C(RESULT_MISS) ] = 0x0,
1084 },
1085 },
1086 [ C(DTLB) ] = {
1087 [ C(OP_READ) ] = {
1088 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
1089 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1090 },
1091 [ C(OP_WRITE) ] = {
1092 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
1093 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1094 },
1095 [ C(OP_PREFETCH) ] = {
1096 [ C(RESULT_ACCESS) ] = 0x0,
1097 [ C(RESULT_MISS) ] = 0x0,
1098 },
1099 },
1100 [ C(ITLB) ] = {
1101 [ C(OP_READ) ] = {
1102 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
1103 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
1104 },
1105 [ C(OP_WRITE) ] = {
1106 [ C(RESULT_ACCESS) ] = -1,
1107 [ C(RESULT_MISS) ] = -1,
1108 },
1109 [ C(OP_PREFETCH) ] = {
1110 [ C(RESULT_ACCESS) ] = -1,
1111 [ C(RESULT_MISS) ] = -1,
1112 },
1113 },
1114 [ C(BPU ) ] = {
1115 [ C(OP_READ) ] = {
1116 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1117 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1118 },
1119 [ C(OP_WRITE) ] = {
1120 [ C(RESULT_ACCESS) ] = -1,
1121 [ C(RESULT_MISS) ] = -1,
1122 },
1123 [ C(OP_PREFETCH) ] = {
1124 [ C(RESULT_ACCESS) ] = -1,
1125 [ C(RESULT_MISS) ] = -1,
1126 },
1127 },
1128 [ C(NODE) ] = {
1129 [ C(OP_READ) ] = {
1130 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1131 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1132 },
1133 [ C(OP_WRITE) ] = {
1134 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1135 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1136 },
1137 [ C(OP_PREFETCH) ] = {
1138 [ C(RESULT_ACCESS) ] = 0x0,
1139 [ C(RESULT_MISS) ] = 0x0,
1140 },
1141 },
1142 };
1143
1144 static __initconst const u64 skl_hw_cache_extra_regs
1145 [PERF_COUNT_HW_CACHE_MAX]
1146 [PERF_COUNT_HW_CACHE_OP_MAX]
1147 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1148 {
1149 [ C(LL ) ] = {
1150 [ C(OP_READ) ] = {
1151 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
1152 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
1153 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
1154 SKL_L3_MISS|SKL_ANY_SNOOP|
1155 SKL_SUPPLIER_NONE,
1156 },
1157 [ C(OP_WRITE) ] = {
1158 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
1159 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
1160 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
1161 SKL_L3_MISS|SKL_ANY_SNOOP|
1162 SKL_SUPPLIER_NONE,
1163 },
1164 [ C(OP_PREFETCH) ] = {
1165 [ C(RESULT_ACCESS) ] = 0x0,
1166 [ C(RESULT_MISS) ] = 0x0,
1167 },
1168 },
1169 [ C(NODE) ] = {
1170 [ C(OP_READ) ] = {
1171 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
1172 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
1173 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
1174 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
1175 },
1176 [ C(OP_WRITE) ] = {
1177 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
1178 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
1179 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
1180 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
1181 },
1182 [ C(OP_PREFETCH) ] = {
1183 [ C(RESULT_ACCESS) ] = 0x0,
1184 [ C(RESULT_MISS) ] = 0x0,
1185 },
1186 },
1187 };
1188
1189 static __initconst const u64 snc_hw_cache_extra_regs
1190 [PERF_COUNT_HW_CACHE_MAX]
1191 [PERF_COUNT_HW_CACHE_OP_MAX]
1192 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1193 {
1194 [ C(LL ) ] = {
1195 [ C(OP_READ) ] = {
1196 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
1197 [ C(RESULT_MISS) ] = 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
1198 },
1199 [ C(OP_WRITE) ] = {
1200 [ C(RESULT_ACCESS) ] = 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
1201 [ C(RESULT_MISS) ] = 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */
1202 },
1203 [ C(OP_PREFETCH) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x0,
1205 [ C(RESULT_MISS) ] = 0x0,
1206 },
1207 },
1208 [ C(NODE) ] = {
1209 [ C(OP_READ) ] = {
1210 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
1211 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
1212 },
1213 [ C(OP_WRITE) ] = {
1214 [ C(RESULT_ACCESS) ] = 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */
1215 [ C(RESULT_MISS) ] = 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */
1216 },
1217 [ C(OP_PREFETCH) ] = {
1218 [ C(RESULT_ACCESS) ] = 0x0,
1219 [ C(RESULT_MISS) ] = 0x0,
1220 },
1221 },
1222 };
1223
1224 #define SNB_DMND_DATA_RD (1ULL << 0)
1225 #define SNB_DMND_RFO (1ULL << 1)
1226 #define SNB_DMND_IFETCH (1ULL << 2)
1227 #define SNB_DMND_WB (1ULL << 3)
1228 #define SNB_PF_DATA_RD (1ULL << 4)
1229 #define SNB_PF_RFO (1ULL << 5)
1230 #define SNB_PF_IFETCH (1ULL << 6)
1231 #define SNB_LLC_DATA_RD (1ULL << 7)
1232 #define SNB_LLC_RFO (1ULL << 8)
1233 #define SNB_LLC_IFETCH (1ULL << 9)
1234 #define SNB_BUS_LOCKS (1ULL << 10)
1235 #define SNB_STRM_ST (1ULL << 11)
1236 #define SNB_OTHER (1ULL << 15)
1237 #define SNB_RESP_ANY (1ULL << 16)
1238 #define SNB_NO_SUPP (1ULL << 17)
1239 #define SNB_LLC_HITM (1ULL << 18)
1240 #define SNB_LLC_HITE (1ULL << 19)
1241 #define SNB_LLC_HITS (1ULL << 20)
1242 #define SNB_LLC_HITF (1ULL << 21)
1243 #define SNB_LOCAL (1ULL << 22)
1244 #define SNB_REMOTE (0xffULL << 23)
1245 #define SNB_SNP_NONE (1ULL << 31)
1246 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
1247 #define SNB_SNP_MISS (1ULL << 33)
1248 #define SNB_NO_FWD (1ULL << 34)
1249 #define SNB_SNP_FWD (1ULL << 35)
1250 #define SNB_HITM (1ULL << 36)
1251 #define SNB_NON_DRAM (1ULL << 37)
1252
1253 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
1254 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
1255 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1256
1257 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
1258 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
1259 SNB_HITM)
1260
1261 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
1262 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
1263
1264 #define SNB_L3_ACCESS SNB_RESP_ANY
1265 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
1266
1267 static __initconst const u64 snb_hw_cache_extra_regs
1268 [PERF_COUNT_HW_CACHE_MAX]
1269 [PERF_COUNT_HW_CACHE_OP_MAX]
1270 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1271 {
1272 [ C(LL ) ] = {
1273 [ C(OP_READ) ] = {
1274 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
1275 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
1276 },
1277 [ C(OP_WRITE) ] = {
1278 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
1279 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
1280 },
1281 [ C(OP_PREFETCH) ] = {
1282 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
1283 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
1284 },
1285 },
1286 [ C(NODE) ] = {
1287 [ C(OP_READ) ] = {
1288 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
1289 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
1290 },
1291 [ C(OP_WRITE) ] = {
1292 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
1293 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
1294 },
1295 [ C(OP_PREFETCH) ] = {
1296 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
1297 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
1298 },
1299 },
1300 };
1301
1302 static __initconst const u64 snb_hw_cache_event_ids
1303 [PERF_COUNT_HW_CACHE_MAX]
1304 [PERF_COUNT_HW_CACHE_OP_MAX]
1305 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1306 {
1307 [ C(L1D) ] = {
1308 [ C(OP_READ) ] = {
1309 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
1310 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
1311 },
1312 [ C(OP_WRITE) ] = {
1313 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
1314 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
1315 },
1316 [ C(OP_PREFETCH) ] = {
1317 [ C(RESULT_ACCESS) ] = 0x0,
1318 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
1319 },
1320 },
1321 [ C(L1I ) ] = {
1322 [ C(OP_READ) ] = {
1323 [ C(RESULT_ACCESS) ] = 0x0,
1324 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
1325 },
1326 [ C(OP_WRITE) ] = {
1327 [ C(RESULT_ACCESS) ] = -1,
1328 [ C(RESULT_MISS) ] = -1,
1329 },
1330 [ C(OP_PREFETCH) ] = {
1331 [ C(RESULT_ACCESS) ] = 0x0,
1332 [ C(RESULT_MISS) ] = 0x0,
1333 },
1334 },
1335 [ C(LL ) ] = {
1336 [ C(OP_READ) ] = {
1337 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1338 [ C(RESULT_ACCESS) ] = 0x01b7,
1339 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1340 [ C(RESULT_MISS) ] = 0x01b7,
1341 },
1342 [ C(OP_WRITE) ] = {
1343 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1344 [ C(RESULT_ACCESS) ] = 0x01b7,
1345 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1346 [ C(RESULT_MISS) ] = 0x01b7,
1347 },
1348 [ C(OP_PREFETCH) ] = {
1349 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1350 [ C(RESULT_ACCESS) ] = 0x01b7,
1351 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1352 [ C(RESULT_MISS) ] = 0x01b7,
1353 },
1354 },
1355 [ C(DTLB) ] = {
1356 [ C(OP_READ) ] = {
1357 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
1358 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
1359 },
1360 [ C(OP_WRITE) ] = {
1361 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
1362 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1363 },
1364 [ C(OP_PREFETCH) ] = {
1365 [ C(RESULT_ACCESS) ] = 0x0,
1366 [ C(RESULT_MISS) ] = 0x0,
1367 },
1368 },
1369 [ C(ITLB) ] = {
1370 [ C(OP_READ) ] = {
1371 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
1372 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
1373 },
1374 [ C(OP_WRITE) ] = {
1375 [ C(RESULT_ACCESS) ] = -1,
1376 [ C(RESULT_MISS) ] = -1,
1377 },
1378 [ C(OP_PREFETCH) ] = {
1379 [ C(RESULT_ACCESS) ] = -1,
1380 [ C(RESULT_MISS) ] = -1,
1381 },
1382 },
1383 [ C(BPU ) ] = {
1384 [ C(OP_READ) ] = {
1385 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1386 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1387 },
1388 [ C(OP_WRITE) ] = {
1389 [ C(RESULT_ACCESS) ] = -1,
1390 [ C(RESULT_MISS) ] = -1,
1391 },
1392 [ C(OP_PREFETCH) ] = {
1393 [ C(RESULT_ACCESS) ] = -1,
1394 [ C(RESULT_MISS) ] = -1,
1395 },
1396 },
1397 [ C(NODE) ] = {
1398 [ C(OP_READ) ] = {
1399 [ C(RESULT_ACCESS) ] = 0x01b7,
1400 [ C(RESULT_MISS) ] = 0x01b7,
1401 },
1402 [ C(OP_WRITE) ] = {
1403 [ C(RESULT_ACCESS) ] = 0x01b7,
1404 [ C(RESULT_MISS) ] = 0x01b7,
1405 },
1406 [ C(OP_PREFETCH) ] = {
1407 [ C(RESULT_ACCESS) ] = 0x01b7,
1408 [ C(RESULT_MISS) ] = 0x01b7,
1409 },
1410 },
1411
1412 };
1413
1414 /*
1415 * Notes on the events:
1416 * - data reads do not include code reads (comparable to earlier tables)
1417 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1418 * - remote node access includes remote memory, remote cache, remote mmio.
1419 * - prefetches are not included in the counts because they are not
1420 * reliably counted.
1421 */
1422
1423 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1424 #define HSW_DEMAND_RFO BIT_ULL(1)
1425 #define HSW_ANY_RESPONSE BIT_ULL(16)
1426 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1427 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1428 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1429 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1430 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1431 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1432 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1433 HSW_L3_MISS_REMOTE_HOP2P)
1434 #define HSW_SNOOP_NONE BIT_ULL(31)
1435 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1436 #define HSW_SNOOP_MISS BIT_ULL(33)
1437 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1438 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1439 #define HSW_SNOOP_HITM BIT_ULL(36)
1440 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1441 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1442 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1443 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1444 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1445 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1446 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1447 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1448 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1449 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1450 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1451
1452 #define BDW_L3_MISS_LOCAL BIT(26)
1453 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1454 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1455 HSW_L3_MISS_REMOTE_HOP2P)
1456
1457
1458 static __initconst const u64 hsw_hw_cache_event_ids
1459 [PERF_COUNT_HW_CACHE_MAX]
1460 [PERF_COUNT_HW_CACHE_OP_MAX]
1461 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1462 {
1463 [ C(L1D ) ] = {
1464 [ C(OP_READ) ] = {
1465 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1466 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1467 },
1468 [ C(OP_WRITE) ] = {
1469 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1470 [ C(RESULT_MISS) ] = 0x0,
1471 },
1472 [ C(OP_PREFETCH) ] = {
1473 [ C(RESULT_ACCESS) ] = 0x0,
1474 [ C(RESULT_MISS) ] = 0x0,
1475 },
1476 },
1477 [ C(L1I ) ] = {
1478 [ C(OP_READ) ] = {
1479 [ C(RESULT_ACCESS) ] = 0x0,
1480 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1481 },
1482 [ C(OP_WRITE) ] = {
1483 [ C(RESULT_ACCESS) ] = -1,
1484 [ C(RESULT_MISS) ] = -1,
1485 },
1486 [ C(OP_PREFETCH) ] = {
1487 [ C(RESULT_ACCESS) ] = 0x0,
1488 [ C(RESULT_MISS) ] = 0x0,
1489 },
1490 },
1491 [ C(LL ) ] = {
1492 [ C(OP_READ) ] = {
1493 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1494 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1495 },
1496 [ C(OP_WRITE) ] = {
1497 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1498 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1499 },
1500 [ C(OP_PREFETCH) ] = {
1501 [ C(RESULT_ACCESS) ] = 0x0,
1502 [ C(RESULT_MISS) ] = 0x0,
1503 },
1504 },
1505 [ C(DTLB) ] = {
1506 [ C(OP_READ) ] = {
1507 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1508 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1509 },
1510 [ C(OP_WRITE) ] = {
1511 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1512 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1513 },
1514 [ C(OP_PREFETCH) ] = {
1515 [ C(RESULT_ACCESS) ] = 0x0,
1516 [ C(RESULT_MISS) ] = 0x0,
1517 },
1518 },
1519 [ C(ITLB) ] = {
1520 [ C(OP_READ) ] = {
1521 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1522 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1523 },
1524 [ C(OP_WRITE) ] = {
1525 [ C(RESULT_ACCESS) ] = -1,
1526 [ C(RESULT_MISS) ] = -1,
1527 },
1528 [ C(OP_PREFETCH) ] = {
1529 [ C(RESULT_ACCESS) ] = -1,
1530 [ C(RESULT_MISS) ] = -1,
1531 },
1532 },
1533 [ C(BPU ) ] = {
1534 [ C(OP_READ) ] = {
1535 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1536 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1537 },
1538 [ C(OP_WRITE) ] = {
1539 [ C(RESULT_ACCESS) ] = -1,
1540 [ C(RESULT_MISS) ] = -1,
1541 },
1542 [ C(OP_PREFETCH) ] = {
1543 [ C(RESULT_ACCESS) ] = -1,
1544 [ C(RESULT_MISS) ] = -1,
1545 },
1546 },
1547 [ C(NODE) ] = {
1548 [ C(OP_READ) ] = {
1549 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1550 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1551 },
1552 [ C(OP_WRITE) ] = {
1553 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1554 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1555 },
1556 [ C(OP_PREFETCH) ] = {
1557 [ C(RESULT_ACCESS) ] = 0x0,
1558 [ C(RESULT_MISS) ] = 0x0,
1559 },
1560 },
1561 };
1562
1563 static __initconst const u64 hsw_hw_cache_extra_regs
1564 [PERF_COUNT_HW_CACHE_MAX]
1565 [PERF_COUNT_HW_CACHE_OP_MAX]
1566 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1567 {
1568 [ C(LL ) ] = {
1569 [ C(OP_READ) ] = {
1570 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1571 HSW_LLC_ACCESS,
1572 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1573 HSW_L3_MISS|HSW_ANY_SNOOP,
1574 },
1575 [ C(OP_WRITE) ] = {
1576 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1577 HSW_LLC_ACCESS,
1578 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1579 HSW_L3_MISS|HSW_ANY_SNOOP,
1580 },
1581 [ C(OP_PREFETCH) ] = {
1582 [ C(RESULT_ACCESS) ] = 0x0,
1583 [ C(RESULT_MISS) ] = 0x0,
1584 },
1585 },
1586 [ C(NODE) ] = {
1587 [ C(OP_READ) ] = {
1588 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1589 HSW_L3_MISS_LOCAL_DRAM|
1590 HSW_SNOOP_DRAM,
1591 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1592 HSW_L3_MISS_REMOTE|
1593 HSW_SNOOP_DRAM,
1594 },
1595 [ C(OP_WRITE) ] = {
1596 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1597 HSW_L3_MISS_LOCAL_DRAM|
1598 HSW_SNOOP_DRAM,
1599 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1600 HSW_L3_MISS_REMOTE|
1601 HSW_SNOOP_DRAM,
1602 },
1603 [ C(OP_PREFETCH) ] = {
1604 [ C(RESULT_ACCESS) ] = 0x0,
1605 [ C(RESULT_MISS) ] = 0x0,
1606 },
1607 },
1608 };
1609
1610 static __initconst const u64 westmere_hw_cache_event_ids
1611 [PERF_COUNT_HW_CACHE_MAX]
1612 [PERF_COUNT_HW_CACHE_OP_MAX]
1613 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1614 {
1615 [ C(L1D) ] = {
1616 [ C(OP_READ) ] = {
1617 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1618 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1619 },
1620 [ C(OP_WRITE) ] = {
1621 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1622 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1623 },
1624 [ C(OP_PREFETCH) ] = {
1625 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1626 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1627 },
1628 },
1629 [ C(L1I ) ] = {
1630 [ C(OP_READ) ] = {
1631 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1632 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1633 },
1634 [ C(OP_WRITE) ] = {
1635 [ C(RESULT_ACCESS) ] = -1,
1636 [ C(RESULT_MISS) ] = -1,
1637 },
1638 [ C(OP_PREFETCH) ] = {
1639 [ C(RESULT_ACCESS) ] = 0x0,
1640 [ C(RESULT_MISS) ] = 0x0,
1641 },
1642 },
1643 [ C(LL ) ] = {
1644 [ C(OP_READ) ] = {
1645 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1646 [ C(RESULT_ACCESS) ] = 0x01b7,
1647 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1648 [ C(RESULT_MISS) ] = 0x01b7,
1649 },
1650 /*
1651 * Use RFO, not WRITEBACK, because a write miss would typically occur
1652 * on RFO.
1653 */
1654 [ C(OP_WRITE) ] = {
1655 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1656 [ C(RESULT_ACCESS) ] = 0x01b7,
1657 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1658 [ C(RESULT_MISS) ] = 0x01b7,
1659 },
1660 [ C(OP_PREFETCH) ] = {
1661 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1662 [ C(RESULT_ACCESS) ] = 0x01b7,
1663 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1664 [ C(RESULT_MISS) ] = 0x01b7,
1665 },
1666 },
1667 [ C(DTLB) ] = {
1668 [ C(OP_READ) ] = {
1669 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1670 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1671 },
1672 [ C(OP_WRITE) ] = {
1673 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1674 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1675 },
1676 [ C(OP_PREFETCH) ] = {
1677 [ C(RESULT_ACCESS) ] = 0x0,
1678 [ C(RESULT_MISS) ] = 0x0,
1679 },
1680 },
1681 [ C(ITLB) ] = {
1682 [ C(OP_READ) ] = {
1683 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1684 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1685 },
1686 [ C(OP_WRITE) ] = {
1687 [ C(RESULT_ACCESS) ] = -1,
1688 [ C(RESULT_MISS) ] = -1,
1689 },
1690 [ C(OP_PREFETCH) ] = {
1691 [ C(RESULT_ACCESS) ] = -1,
1692 [ C(RESULT_MISS) ] = -1,
1693 },
1694 },
1695 [ C(BPU ) ] = {
1696 [ C(OP_READ) ] = {
1697 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1698 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1699 },
1700 [ C(OP_WRITE) ] = {
1701 [ C(RESULT_ACCESS) ] = -1,
1702 [ C(RESULT_MISS) ] = -1,
1703 },
1704 [ C(OP_PREFETCH) ] = {
1705 [ C(RESULT_ACCESS) ] = -1,
1706 [ C(RESULT_MISS) ] = -1,
1707 },
1708 },
1709 [ C(NODE) ] = {
1710 [ C(OP_READ) ] = {
1711 [ C(RESULT_ACCESS) ] = 0x01b7,
1712 [ C(RESULT_MISS) ] = 0x01b7,
1713 },
1714 [ C(OP_WRITE) ] = {
1715 [ C(RESULT_ACCESS) ] = 0x01b7,
1716 [ C(RESULT_MISS) ] = 0x01b7,
1717 },
1718 [ C(OP_PREFETCH) ] = {
1719 [ C(RESULT_ACCESS) ] = 0x01b7,
1720 [ C(RESULT_MISS) ] = 0x01b7,
1721 },
1722 },
1723 };
1724
1725 /*
1726 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1727 * See IA32 SDM Vol 3B 30.6.1.3
1728 */
1729
1730 #define NHM_DMND_DATA_RD (1 << 0)
1731 #define NHM_DMND_RFO (1 << 1)
1732 #define NHM_DMND_IFETCH (1 << 2)
1733 #define NHM_DMND_WB (1 << 3)
1734 #define NHM_PF_DATA_RD (1 << 4)
1735 #define NHM_PF_DATA_RFO (1 << 5)
1736 #define NHM_PF_IFETCH (1 << 6)
1737 #define NHM_OFFCORE_OTHER (1 << 7)
1738 #define NHM_UNCORE_HIT (1 << 8)
1739 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1740 #define NHM_OTHER_CORE_HITM (1 << 10)
1741 /* reserved */
1742 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1743 #define NHM_REMOTE_DRAM (1 << 13)
1744 #define NHM_LOCAL_DRAM (1 << 14)
1745 #define NHM_NON_DRAM (1 << 15)
1746
1747 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1748 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1749
1750 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1751 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1752 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1753
1754 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1755 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1756 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1757
1758 static __initconst const u64 nehalem_hw_cache_extra_regs
1759 [PERF_COUNT_HW_CACHE_MAX]
1760 [PERF_COUNT_HW_CACHE_OP_MAX]
1761 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1762 {
1763 [ C(LL ) ] = {
1764 [ C(OP_READ) ] = {
1765 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1766 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1767 },
1768 [ C(OP_WRITE) ] = {
1769 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1770 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1771 },
1772 [ C(OP_PREFETCH) ] = {
1773 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1774 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1775 },
1776 },
1777 [ C(NODE) ] = {
1778 [ C(OP_READ) ] = {
1779 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1780 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1781 },
1782 [ C(OP_WRITE) ] = {
1783 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1784 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1785 },
1786 [ C(OP_PREFETCH) ] = {
1787 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1788 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1789 },
1790 },
1791 };
1792
1793 static __initconst const u64 nehalem_hw_cache_event_ids
1794 [PERF_COUNT_HW_CACHE_MAX]
1795 [PERF_COUNT_HW_CACHE_OP_MAX]
1796 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1797 {
1798 [ C(L1D) ] = {
1799 [ C(OP_READ) ] = {
1800 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1801 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1802 },
1803 [ C(OP_WRITE) ] = {
1804 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1805 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1806 },
1807 [ C(OP_PREFETCH) ] = {
1808 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1809 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1810 },
1811 },
1812 [ C(L1I ) ] = {
1813 [ C(OP_READ) ] = {
1814 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1815 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1816 },
1817 [ C(OP_WRITE) ] = {
1818 [ C(RESULT_ACCESS) ] = -1,
1819 [ C(RESULT_MISS) ] = -1,
1820 },
1821 [ C(OP_PREFETCH) ] = {
1822 [ C(RESULT_ACCESS) ] = 0x0,
1823 [ C(RESULT_MISS) ] = 0x0,
1824 },
1825 },
1826 [ C(LL ) ] = {
1827 [ C(OP_READ) ] = {
1828 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1829 [ C(RESULT_ACCESS) ] = 0x01b7,
1830 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1831 [ C(RESULT_MISS) ] = 0x01b7,
1832 },
1833 /*
1834 * Use RFO, not WRITEBACK, because a write miss would typically occur
1835 * on RFO.
1836 */
1837 [ C(OP_WRITE) ] = {
1838 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1839 [ C(RESULT_ACCESS) ] = 0x01b7,
1840 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1841 [ C(RESULT_MISS) ] = 0x01b7,
1842 },
1843 [ C(OP_PREFETCH) ] = {
1844 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1845 [ C(RESULT_ACCESS) ] = 0x01b7,
1846 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1847 [ C(RESULT_MISS) ] = 0x01b7,
1848 },
1849 },
1850 [ C(DTLB) ] = {
1851 [ C(OP_READ) ] = {
1852 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1853 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1854 },
1855 [ C(OP_WRITE) ] = {
1856 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1857 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1858 },
1859 [ C(OP_PREFETCH) ] = {
1860 [ C(RESULT_ACCESS) ] = 0x0,
1861 [ C(RESULT_MISS) ] = 0x0,
1862 },
1863 },
1864 [ C(ITLB) ] = {
1865 [ C(OP_READ) ] = {
1866 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1867 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1868 },
1869 [ C(OP_WRITE) ] = {
1870 [ C(RESULT_ACCESS) ] = -1,
1871 [ C(RESULT_MISS) ] = -1,
1872 },
1873 [ C(OP_PREFETCH) ] = {
1874 [ C(RESULT_ACCESS) ] = -1,
1875 [ C(RESULT_MISS) ] = -1,
1876 },
1877 },
1878 [ C(BPU ) ] = {
1879 [ C(OP_READ) ] = {
1880 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1881 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1882 },
1883 [ C(OP_WRITE) ] = {
1884 [ C(RESULT_ACCESS) ] = -1,
1885 [ C(RESULT_MISS) ] = -1,
1886 },
1887 [ C(OP_PREFETCH) ] = {
1888 [ C(RESULT_ACCESS) ] = -1,
1889 [ C(RESULT_MISS) ] = -1,
1890 },
1891 },
1892 [ C(NODE) ] = {
1893 [ C(OP_READ) ] = {
1894 [ C(RESULT_ACCESS) ] = 0x01b7,
1895 [ C(RESULT_MISS) ] = 0x01b7,
1896 },
1897 [ C(OP_WRITE) ] = {
1898 [ C(RESULT_ACCESS) ] = 0x01b7,
1899 [ C(RESULT_MISS) ] = 0x01b7,
1900 },
1901 [ C(OP_PREFETCH) ] = {
1902 [ C(RESULT_ACCESS) ] = 0x01b7,
1903 [ C(RESULT_MISS) ] = 0x01b7,
1904 },
1905 },
1906 };
1907
1908 static __initconst const u64 core2_hw_cache_event_ids
1909 [PERF_COUNT_HW_CACHE_MAX]
1910 [PERF_COUNT_HW_CACHE_OP_MAX]
1911 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1912 {
1913 [ C(L1D) ] = {
1914 [ C(OP_READ) ] = {
1915 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1916 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1917 },
1918 [ C(OP_WRITE) ] = {
1919 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1920 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1921 },
1922 [ C(OP_PREFETCH) ] = {
1923 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1924 [ C(RESULT_MISS) ] = 0,
1925 },
1926 },
1927 [ C(L1I ) ] = {
1928 [ C(OP_READ) ] = {
1929 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1930 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1931 },
1932 [ C(OP_WRITE) ] = {
1933 [ C(RESULT_ACCESS) ] = -1,
1934 [ C(RESULT_MISS) ] = -1,
1935 },
1936 [ C(OP_PREFETCH) ] = {
1937 [ C(RESULT_ACCESS) ] = 0,
1938 [ C(RESULT_MISS) ] = 0,
1939 },
1940 },
1941 [ C(LL ) ] = {
1942 [ C(OP_READ) ] = {
1943 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1944 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1945 },
1946 [ C(OP_WRITE) ] = {
1947 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1948 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1949 },
1950 [ C(OP_PREFETCH) ] = {
1951 [ C(RESULT_ACCESS) ] = 0,
1952 [ C(RESULT_MISS) ] = 0,
1953 },
1954 },
1955 [ C(DTLB) ] = {
1956 [ C(OP_READ) ] = {
1957 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1958 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1959 },
1960 [ C(OP_WRITE) ] = {
1961 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1962 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1963 },
1964 [ C(OP_PREFETCH) ] = {
1965 [ C(RESULT_ACCESS) ] = 0,
1966 [ C(RESULT_MISS) ] = 0,
1967 },
1968 },
1969 [ C(ITLB) ] = {
1970 [ C(OP_READ) ] = {
1971 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1972 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1973 },
1974 [ C(OP_WRITE) ] = {
1975 [ C(RESULT_ACCESS) ] = -1,
1976 [ C(RESULT_MISS) ] = -1,
1977 },
1978 [ C(OP_PREFETCH) ] = {
1979 [ C(RESULT_ACCESS) ] = -1,
1980 [ C(RESULT_MISS) ] = -1,
1981 },
1982 },
1983 [ C(BPU ) ] = {
1984 [ C(OP_READ) ] = {
1985 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1986 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1987 },
1988 [ C(OP_WRITE) ] = {
1989 [ C(RESULT_ACCESS) ] = -1,
1990 [ C(RESULT_MISS) ] = -1,
1991 },
1992 [ C(OP_PREFETCH) ] = {
1993 [ C(RESULT_ACCESS) ] = -1,
1994 [ C(RESULT_MISS) ] = -1,
1995 },
1996 },
1997 };
1998
1999 static __initconst const u64 atom_hw_cache_event_ids
2000 [PERF_COUNT_HW_CACHE_MAX]
2001 [PERF_COUNT_HW_CACHE_OP_MAX]
2002 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2003 {
2004 [ C(L1D) ] = {
2005 [ C(OP_READ) ] = {
2006 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
2007 [ C(RESULT_MISS) ] = 0,
2008 },
2009 [ C(OP_WRITE) ] = {
2010 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
2011 [ C(RESULT_MISS) ] = 0,
2012 },
2013 [ C(OP_PREFETCH) ] = {
2014 [ C(RESULT_ACCESS) ] = 0x0,
2015 [ C(RESULT_MISS) ] = 0,
2016 },
2017 },
2018 [ C(L1I ) ] = {
2019 [ C(OP_READ) ] = {
2020 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
2021 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
2022 },
2023 [ C(OP_WRITE) ] = {
2024 [ C(RESULT_ACCESS) ] = -1,
2025 [ C(RESULT_MISS) ] = -1,
2026 },
2027 [ C(OP_PREFETCH) ] = {
2028 [ C(RESULT_ACCESS) ] = 0,
2029 [ C(RESULT_MISS) ] = 0,
2030 },
2031 },
2032 [ C(LL ) ] = {
2033 [ C(OP_READ) ] = {
2034 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
2035 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
2036 },
2037 [ C(OP_WRITE) ] = {
2038 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
2039 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
2040 },
2041 [ C(OP_PREFETCH) ] = {
2042 [ C(RESULT_ACCESS) ] = 0,
2043 [ C(RESULT_MISS) ] = 0,
2044 },
2045 },
2046 [ C(DTLB) ] = {
2047 [ C(OP_READ) ] = {
2048 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
2049 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
2050 },
2051 [ C(OP_WRITE) ] = {
2052 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
2053 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
2054 },
2055 [ C(OP_PREFETCH) ] = {
2056 [ C(RESULT_ACCESS) ] = 0,
2057 [ C(RESULT_MISS) ] = 0,
2058 },
2059 },
2060 [ C(ITLB) ] = {
2061 [ C(OP_READ) ] = {
2062 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
2063 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
2064 },
2065 [ C(OP_WRITE) ] = {
2066 [ C(RESULT_ACCESS) ] = -1,
2067 [ C(RESULT_MISS) ] = -1,
2068 },
2069 [ C(OP_PREFETCH) ] = {
2070 [ C(RESULT_ACCESS) ] = -1,
2071 [ C(RESULT_MISS) ] = -1,
2072 },
2073 },
2074 [ C(BPU ) ] = {
2075 [ C(OP_READ) ] = {
2076 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
2077 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
2078 },
2079 [ C(OP_WRITE) ] = {
2080 [ C(RESULT_ACCESS) ] = -1,
2081 [ C(RESULT_MISS) ] = -1,
2082 },
2083 [ C(OP_PREFETCH) ] = {
2084 [ C(RESULT_ACCESS) ] = -1,
2085 [ C(RESULT_MISS) ] = -1,
2086 },
2087 },
2088 };
2089
2090 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
2091 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
2092 /* no_alloc_cycles.not_delivered */
2093 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
2094 "event=0xca,umask=0x50");
2095 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
2096 /* uops_retired.all */
2097 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
2098 "event=0xc2,umask=0x10");
2099 /* uops_retired.all */
2100 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
2101 "event=0xc2,umask=0x10");
2102
2103 static struct attribute *slm_events_attrs[] = {
2104 EVENT_PTR(td_total_slots_slm),
2105 EVENT_PTR(td_total_slots_scale_slm),
2106 EVENT_PTR(td_fetch_bubbles_slm),
2107 EVENT_PTR(td_fetch_bubbles_scale_slm),
2108 EVENT_PTR(td_slots_issued_slm),
2109 EVENT_PTR(td_slots_retired_slm),
2110 NULL
2111 };
2112
2113 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
2114 {
2115 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2116 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
2117 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
2118 EVENT_EXTRA_END
2119 };
2120
2121 #define SLM_DMND_READ SNB_DMND_DATA_RD
2122 #define SLM_DMND_WRITE SNB_DMND_RFO
2123 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
2124
2125 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
2126 #define SLM_LLC_ACCESS SNB_RESP_ANY
2127 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
2128
2129 static __initconst const u64 slm_hw_cache_extra_regs
2130 [PERF_COUNT_HW_CACHE_MAX]
2131 [PERF_COUNT_HW_CACHE_OP_MAX]
2132 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2133 {
2134 [ C(LL ) ] = {
2135 [ C(OP_READ) ] = {
2136 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
2137 [ C(RESULT_MISS) ] = 0,
2138 },
2139 [ C(OP_WRITE) ] = {
2140 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
2141 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
2142 },
2143 [ C(OP_PREFETCH) ] = {
2144 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
2145 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
2146 },
2147 },
2148 };
2149
2150 static __initconst const u64 slm_hw_cache_event_ids
2151 [PERF_COUNT_HW_CACHE_MAX]
2152 [PERF_COUNT_HW_CACHE_OP_MAX]
2153 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2154 {
2155 [ C(L1D) ] = {
2156 [ C(OP_READ) ] = {
2157 [ C(RESULT_ACCESS) ] = 0,
2158 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
2159 },
2160 [ C(OP_WRITE) ] = {
2161 [ C(RESULT_ACCESS) ] = 0,
2162 [ C(RESULT_MISS) ] = 0,
2163 },
2164 [ C(OP_PREFETCH) ] = {
2165 [ C(RESULT_ACCESS) ] = 0,
2166 [ C(RESULT_MISS) ] = 0,
2167 },
2168 },
2169 [ C(L1I ) ] = {
2170 [ C(OP_READ) ] = {
2171 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
2172 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
2173 },
2174 [ C(OP_WRITE) ] = {
2175 [ C(RESULT_ACCESS) ] = -1,
2176 [ C(RESULT_MISS) ] = -1,
2177 },
2178 [ C(OP_PREFETCH) ] = {
2179 [ C(RESULT_ACCESS) ] = 0,
2180 [ C(RESULT_MISS) ] = 0,
2181 },
2182 },
2183 [ C(LL ) ] = {
2184 [ C(OP_READ) ] = {
2185 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
2186 [ C(RESULT_ACCESS) ] = 0x01b7,
2187 [ C(RESULT_MISS) ] = 0,
2188 },
2189 [ C(OP_WRITE) ] = {
2190 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
2191 [ C(RESULT_ACCESS) ] = 0x01b7,
2192 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
2193 [ C(RESULT_MISS) ] = 0x01b7,
2194 },
2195 [ C(OP_PREFETCH) ] = {
2196 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
2197 [ C(RESULT_ACCESS) ] = 0x01b7,
2198 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
2199 [ C(RESULT_MISS) ] = 0x01b7,
2200 },
2201 },
2202 [ C(DTLB) ] = {
2203 [ C(OP_READ) ] = {
2204 [ C(RESULT_ACCESS) ] = 0,
2205 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
2206 },
2207 [ C(OP_WRITE) ] = {
2208 [ C(RESULT_ACCESS) ] = 0,
2209 [ C(RESULT_MISS) ] = 0,
2210 },
2211 [ C(OP_PREFETCH) ] = {
2212 [ C(RESULT_ACCESS) ] = 0,
2213 [ C(RESULT_MISS) ] = 0,
2214 },
2215 },
2216 [ C(ITLB) ] = {
2217 [ C(OP_READ) ] = {
2218 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
2219 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
2220 },
2221 [ C(OP_WRITE) ] = {
2222 [ C(RESULT_ACCESS) ] = -1,
2223 [ C(RESULT_MISS) ] = -1,
2224 },
2225 [ C(OP_PREFETCH) ] = {
2226 [ C(RESULT_ACCESS) ] = -1,
2227 [ C(RESULT_MISS) ] = -1,
2228 },
2229 },
2230 [ C(BPU ) ] = {
2231 [ C(OP_READ) ] = {
2232 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
2233 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
2234 },
2235 [ C(OP_WRITE) ] = {
2236 [ C(RESULT_ACCESS) ] = -1,
2237 [ C(RESULT_MISS) ] = -1,
2238 },
2239 [ C(OP_PREFETCH) ] = {
2240 [ C(RESULT_ACCESS) ] = -1,
2241 [ C(RESULT_MISS) ] = -1,
2242 },
2243 },
2244 };
2245
2246 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
2247 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
2248 /* UOPS_NOT_DELIVERED.ANY */
2249 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
2250 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
2251 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
2252 /* UOPS_RETIRED.ANY */
2253 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
2254 /* UOPS_ISSUED.ANY */
2255 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
2256
2257 static struct attribute *glm_events_attrs[] = {
2258 EVENT_PTR(td_total_slots_glm),
2259 EVENT_PTR(td_total_slots_scale_glm),
2260 EVENT_PTR(td_fetch_bubbles_glm),
2261 EVENT_PTR(td_recovery_bubbles_glm),
2262 EVENT_PTR(td_slots_issued_glm),
2263 EVENT_PTR(td_slots_retired_glm),
2264 NULL
2265 };
2266
2267 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
2268 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2269 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
2270 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
2271 EVENT_EXTRA_END
2272 };
2273
2274 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
2275 #define GLM_DEMAND_RFO BIT_ULL(1)
2276 #define GLM_ANY_RESPONSE BIT_ULL(16)
2277 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
2278 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
2279 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
2280 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
2281 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
2282 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
2283 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
2284
2285 static __initconst const u64 glm_hw_cache_event_ids
2286 [PERF_COUNT_HW_CACHE_MAX]
2287 [PERF_COUNT_HW_CACHE_OP_MAX]
2288 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2289 [C(L1D)] = {
2290 [C(OP_READ)] = {
2291 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2292 [C(RESULT_MISS)] = 0x0,
2293 },
2294 [C(OP_WRITE)] = {
2295 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2296 [C(RESULT_MISS)] = 0x0,
2297 },
2298 [C(OP_PREFETCH)] = {
2299 [C(RESULT_ACCESS)] = 0x0,
2300 [C(RESULT_MISS)] = 0x0,
2301 },
2302 },
2303 [C(L1I)] = {
2304 [C(OP_READ)] = {
2305 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2306 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2307 },
2308 [C(OP_WRITE)] = {
2309 [C(RESULT_ACCESS)] = -1,
2310 [C(RESULT_MISS)] = -1,
2311 },
2312 [C(OP_PREFETCH)] = {
2313 [C(RESULT_ACCESS)] = 0x0,
2314 [C(RESULT_MISS)] = 0x0,
2315 },
2316 },
2317 [C(LL)] = {
2318 [C(OP_READ)] = {
2319 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2320 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2321 },
2322 [C(OP_WRITE)] = {
2323 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2324 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2325 },
2326 [C(OP_PREFETCH)] = {
2327 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2328 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2329 },
2330 },
2331 [C(DTLB)] = {
2332 [C(OP_READ)] = {
2333 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2334 [C(RESULT_MISS)] = 0x0,
2335 },
2336 [C(OP_WRITE)] = {
2337 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2338 [C(RESULT_MISS)] = 0x0,
2339 },
2340 [C(OP_PREFETCH)] = {
2341 [C(RESULT_ACCESS)] = 0x0,
2342 [C(RESULT_MISS)] = 0x0,
2343 },
2344 },
2345 [C(ITLB)] = {
2346 [C(OP_READ)] = {
2347 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2348 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2349 },
2350 [C(OP_WRITE)] = {
2351 [C(RESULT_ACCESS)] = -1,
2352 [C(RESULT_MISS)] = -1,
2353 },
2354 [C(OP_PREFETCH)] = {
2355 [C(RESULT_ACCESS)] = -1,
2356 [C(RESULT_MISS)] = -1,
2357 },
2358 },
2359 [C(BPU)] = {
2360 [C(OP_READ)] = {
2361 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2362 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2363 },
2364 [C(OP_WRITE)] = {
2365 [C(RESULT_ACCESS)] = -1,
2366 [C(RESULT_MISS)] = -1,
2367 },
2368 [C(OP_PREFETCH)] = {
2369 [C(RESULT_ACCESS)] = -1,
2370 [C(RESULT_MISS)] = -1,
2371 },
2372 },
2373 };
2374
2375 static __initconst const u64 glm_hw_cache_extra_regs
2376 [PERF_COUNT_HW_CACHE_MAX]
2377 [PERF_COUNT_HW_CACHE_OP_MAX]
2378 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2379 [C(LL)] = {
2380 [C(OP_READ)] = {
2381 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2382 GLM_LLC_ACCESS,
2383 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2384 GLM_LLC_MISS,
2385 },
2386 [C(OP_WRITE)] = {
2387 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2388 GLM_LLC_ACCESS,
2389 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2390 GLM_LLC_MISS,
2391 },
2392 [C(OP_PREFETCH)] = {
2393 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2394 GLM_LLC_ACCESS,
2395 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2396 GLM_LLC_MISS,
2397 },
2398 },
2399 };
2400
2401 static __initconst const u64 glp_hw_cache_event_ids
2402 [PERF_COUNT_HW_CACHE_MAX]
2403 [PERF_COUNT_HW_CACHE_OP_MAX]
2404 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2405 [C(L1D)] = {
2406 [C(OP_READ)] = {
2407 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2408 [C(RESULT_MISS)] = 0x0,
2409 },
2410 [C(OP_WRITE)] = {
2411 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2412 [C(RESULT_MISS)] = 0x0,
2413 },
2414 [C(OP_PREFETCH)] = {
2415 [C(RESULT_ACCESS)] = 0x0,
2416 [C(RESULT_MISS)] = 0x0,
2417 },
2418 },
2419 [C(L1I)] = {
2420 [C(OP_READ)] = {
2421 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2422 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2423 },
2424 [C(OP_WRITE)] = {
2425 [C(RESULT_ACCESS)] = -1,
2426 [C(RESULT_MISS)] = -1,
2427 },
2428 [C(OP_PREFETCH)] = {
2429 [C(RESULT_ACCESS)] = 0x0,
2430 [C(RESULT_MISS)] = 0x0,
2431 },
2432 },
2433 [C(LL)] = {
2434 [C(OP_READ)] = {
2435 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2436 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2437 },
2438 [C(OP_WRITE)] = {
2439 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2440 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2441 },
2442 [C(OP_PREFETCH)] = {
2443 [C(RESULT_ACCESS)] = 0x0,
2444 [C(RESULT_MISS)] = 0x0,
2445 },
2446 },
2447 [C(DTLB)] = {
2448 [C(OP_READ)] = {
2449 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2450 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2451 },
2452 [C(OP_WRITE)] = {
2453 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2454 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2455 },
2456 [C(OP_PREFETCH)] = {
2457 [C(RESULT_ACCESS)] = 0x0,
2458 [C(RESULT_MISS)] = 0x0,
2459 },
2460 },
2461 [C(ITLB)] = {
2462 [C(OP_READ)] = {
2463 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2464 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2465 },
2466 [C(OP_WRITE)] = {
2467 [C(RESULT_ACCESS)] = -1,
2468 [C(RESULT_MISS)] = -1,
2469 },
2470 [C(OP_PREFETCH)] = {
2471 [C(RESULT_ACCESS)] = -1,
2472 [C(RESULT_MISS)] = -1,
2473 },
2474 },
2475 [C(BPU)] = {
2476 [C(OP_READ)] = {
2477 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2478 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2479 },
2480 [C(OP_WRITE)] = {
2481 [C(RESULT_ACCESS)] = -1,
2482 [C(RESULT_MISS)] = -1,
2483 },
2484 [C(OP_PREFETCH)] = {
2485 [C(RESULT_ACCESS)] = -1,
2486 [C(RESULT_MISS)] = -1,
2487 },
2488 },
2489 };
2490
2491 static __initconst const u64 glp_hw_cache_extra_regs
2492 [PERF_COUNT_HW_CACHE_MAX]
2493 [PERF_COUNT_HW_CACHE_OP_MAX]
2494 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2495 [C(LL)] = {
2496 [C(OP_READ)] = {
2497 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2498 GLM_LLC_ACCESS,
2499 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2500 GLM_LLC_MISS,
2501 },
2502 [C(OP_WRITE)] = {
2503 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2504 GLM_LLC_ACCESS,
2505 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2506 GLM_LLC_MISS,
2507 },
2508 [C(OP_PREFETCH)] = {
2509 [C(RESULT_ACCESS)] = 0x0,
2510 [C(RESULT_MISS)] = 0x0,
2511 },
2512 },
2513 };
2514
2515 #define TNT_LOCAL_DRAM BIT_ULL(26)
2516 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2517 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2518 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2519 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2520 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2521 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2522
2523 static __initconst const u64 tnt_hw_cache_extra_regs
2524 [PERF_COUNT_HW_CACHE_MAX]
2525 [PERF_COUNT_HW_CACHE_OP_MAX]
2526 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2527 [C(LL)] = {
2528 [C(OP_READ)] = {
2529 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2530 TNT_LLC_ACCESS,
2531 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2532 TNT_LLC_MISS,
2533 },
2534 [C(OP_WRITE)] = {
2535 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2536 TNT_LLC_ACCESS,
2537 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2538 TNT_LLC_MISS,
2539 },
2540 [C(OP_PREFETCH)] = {
2541 [C(RESULT_ACCESS)] = 0x0,
2542 [C(RESULT_MISS)] = 0x0,
2543 },
2544 },
2545 };
2546
2547 static __initconst const u64 grt_hw_cache_extra_regs
2548 [PERF_COUNT_HW_CACHE_MAX]
2549 [PERF_COUNT_HW_CACHE_OP_MAX]
2550 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2551 [C(LL)] = {
2552 [C(OP_READ)] = {
2553 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2554 [C(RESULT_MISS)] = 0x3F84400001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2555 },
2556 [C(OP_WRITE)] = {
2557 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2558 [C(RESULT_MISS)] = 0x3F84400002, /* OCR.DEMAND_RFO.L3_MISS */
2559 },
2560 },
2561 };
2562
2563 static __initconst const u64 cmt_hw_cache_extra_regs
2564 [PERF_COUNT_HW_CACHE_MAX]
2565 [PERF_COUNT_HW_CACHE_OP_MAX]
2566 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2567 [C(LL)] = {
2568 [C(OP_READ)] = {
2569 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2570 [C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2571 },
2572 [C(OP_WRITE)] = {
2573 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2574 [C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
2575 },
2576 },
2577 };
2578
2579 static __initconst const u64 skt_hw_cache_extra_regs
2580 [PERF_COUNT_HW_CACHE_MAX]
2581 [PERF_COUNT_HW_CACHE_OP_MAX]
2582 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2583 [C(LL)] = {
2584 [C(OP_READ)] = {
2585 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2586 [C(RESULT_MISS)] = 0x13FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2587 },
2588 [C(OP_WRITE)] = {
2589 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2590 [C(RESULT_MISS)] = 0x13FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
2591 },
2592 },
2593 };
2594
2595 static __initconst const u64 dkt_hw_cache_extra_regs
2596 [PERF_COUNT_HW_CACHE_MAX]
2597 [PERF_COUNT_HW_CACHE_OP_MAX]
2598 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2599 [C(LL)] = {
2600 [C(OP_READ)] = {
2601 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2602 [C(RESULT_MISS)] = 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2603 },
2604 [C(OP_WRITE)] = {
2605 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2606 [C(RESULT_MISS)] = 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
2607 },
2608 },
2609 };
2610
2611 static __initconst const u64 arw_hw_cache_extra_regs
2612 [PERF_COUNT_HW_CACHE_MAX]
2613 [PERF_COUNT_HW_CACHE_OP_MAX]
2614 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2615 [C(LL)] = {
2616 [C(OP_READ)] = {
2617 [C(RESULT_ACCESS)] = 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
2618 [C(RESULT_MISS)] = 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */
2619 },
2620 [C(OP_WRITE)] = {
2621 [C(RESULT_ACCESS)] = 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPONSE */
2622 [C(RESULT_MISS)] = 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */
2623 },
2624 },
2625 };
2626
2627 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2628 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2629 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2630 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2631
2632 static struct attribute *tnt_events_attrs[] = {
2633 EVENT_PTR(td_fe_bound_tnt),
2634 EVENT_PTR(td_retiring_tnt),
2635 EVENT_PTR(td_bad_spec_tnt),
2636 EVENT_PTR(td_be_bound_tnt),
2637 NULL,
2638 };
2639
2640 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2641 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2642 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2643 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2644 EVENT_EXTRA_END
2645 };
2646
2647 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2648 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2649
2650 static struct attribute *grt_mem_attrs[] = {
2651 EVENT_PTR(mem_ld_grt),
2652 EVENT_PTR(mem_st_grt),
2653 NULL
2654 };
2655
2656 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2657 /*
2658 * Must define OFFCORE_RSP_X first, see intel_fixup_er().
2659 * Bit 63 only valid on OFFCORE_RSP_0 MSR.
2660 */
2661 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x8003f03fffffffffull, RSP_0),
2662 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3f03fffffffffull, RSP_1),
2663 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2664 EVENT_EXTRA_END
2665 };
2666
2667 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2668 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2669
2670 static struct attribute *cmt_events_attrs[] = {
2671 EVENT_PTR(td_fe_bound_tnt),
2672 EVENT_PTR(td_retiring_cmt),
2673 EVENT_PTR(td_bad_spec_cmt),
2674 EVENT_PTR(td_be_bound_tnt),
2675 NULL
2676 };
2677
2678 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2679 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2680 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2681 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2682 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2683 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2684 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2685 EVENT_EXTRA_END
2686 };
2687
2688 static struct extra_reg intel_arw_extra_regs[] __read_mostly = {
2689 /* must define OMR_X first, see intel_alt_er() */
2690 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2691 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2692 INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2693 INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2694 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2695 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2696 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2697 EVENT_EXTRA_END
2698 };
2699
2700 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
2701 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
2702 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
2703
2704 static struct attribute *skt_events_attrs[] = {
2705 EVENT_PTR(td_fe_bound_skt),
2706 EVENT_PTR(td_retiring_skt),
2707 EVENT_PTR(td_bad_spec_cmt),
2708 EVENT_PTR(td_be_bound_skt),
2709 NULL,
2710 };
2711
2712 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2713 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2714 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2715 #define KNL_MCDRAM_FAR BIT_ULL(22)
2716 #define KNL_DDR_LOCAL BIT_ULL(23)
2717 #define KNL_DDR_FAR BIT_ULL(24)
2718 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2719 KNL_DDR_LOCAL | KNL_DDR_FAR)
2720 #define KNL_L2_READ SLM_DMND_READ
2721 #define KNL_L2_WRITE SLM_DMND_WRITE
2722 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2723 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2724 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2725 KNL_DRAM_ANY | SNB_SNP_ANY | \
2726 SNB_NON_DRAM)
2727
2728 static __initconst const u64 knl_hw_cache_extra_regs
2729 [PERF_COUNT_HW_CACHE_MAX]
2730 [PERF_COUNT_HW_CACHE_OP_MAX]
2731 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2732 [C(LL)] = {
2733 [C(OP_READ)] = {
2734 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2735 [C(RESULT_MISS)] = 0,
2736 },
2737 [C(OP_WRITE)] = {
2738 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2739 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2740 },
2741 [C(OP_PREFETCH)] = {
2742 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2743 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2744 },
2745 },
2746 };
2747
2748 /*
2749 * Used from PMIs where the LBRs are already disabled.
2750 *
2751 * This function could be called consecutively. It is required to remain in
2752 * disabled state if called consecutively.
2753 *
2754 * During consecutive calls, the same disable value will be written to related
2755 * registers, so the PMU state remains unchanged.
2756 *
2757 * intel_bts events don't coexist with intel PMU's BTS events because of
2758 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2759 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2760 *
2761 * Avoid PEBS_ENABLE MSR access in PMIs.
2762 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2763 * It doesn't matter if the PEBS is enabled or not.
2764 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2765 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2766 * However, there are some cases which may change PEBS status, e.g. PMI
2767 * throttle. The PEBS_ENABLE should be updated where the status changes.
2768 */
__intel_pmu_disable_all(bool bts)2769 static __always_inline void __intel_pmu_disable_all(bool bts)
2770 {
2771 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2772
2773 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2774
2775 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2776 intel_pmu_disable_bts();
2777 }
2778
intel_pmu_disable_all(void)2779 static __always_inline void intel_pmu_disable_all(void)
2780 {
2781 __intel_pmu_disable_all(true);
2782 static_call_cond(x86_pmu_pebs_disable_all)();
2783 intel_pmu_lbr_disable_all();
2784 }
2785
__intel_pmu_enable_all(int added,bool pmi)2786 static void __intel_pmu_enable_all(int added, bool pmi)
2787 {
2788 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2789 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2790
2791 intel_pmu_lbr_enable_all(pmi);
2792
2793 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2794 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2795 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2796 }
2797
2798 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL,
2799 intel_ctrl & ~cpuc->intel_ctrl_exclude_host_mask);
2800
2801 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2802 struct perf_event *event =
2803 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2804
2805 if (WARN_ON_ONCE(!event))
2806 return;
2807
2808 intel_pmu_enable_bts(event->hw.config);
2809 }
2810 }
2811
intel_pmu_enable_all(int added)2812 static void intel_pmu_enable_all(int added)
2813 {
2814 static_call_cond(x86_pmu_pebs_enable_all)();
2815 __intel_pmu_enable_all(added, false);
2816 }
2817
2818 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2819 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2820 unsigned int cnt, unsigned long flags)
2821 {
2822 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2823
2824 intel_pmu_lbr_read();
2825 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2826
2827 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2828 intel_pmu_enable_all(0);
2829 local_irq_restore(flags);
2830 return cnt;
2831 }
2832
2833 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2834 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2835 {
2836 unsigned long flags;
2837
2838 /* must not have branches... */
2839 local_irq_save(flags);
2840 __intel_pmu_disable_all(false); /* we don't care about BTS */
2841 __intel_pmu_lbr_disable();
2842 /* ... until here */
2843 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2844 }
2845
2846 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2847 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2848 {
2849 unsigned long flags;
2850
2851 /* must not have branches... */
2852 local_irq_save(flags);
2853 __intel_pmu_disable_all(false); /* we don't care about BTS */
2854 __intel_pmu_arch_lbr_disable();
2855 /* ... until here */
2856 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2857 }
2858
2859 /*
2860 * Workaround for:
2861 * Intel Errata AAK100 (model 26)
2862 * Intel Errata AAP53 (model 30)
2863 * Intel Errata BD53 (model 44)
2864 *
2865 * The official story:
2866 * These chips need to be 'reset' when adding counters by programming the
2867 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2868 * in sequence on the same PMC or on different PMCs.
2869 *
2870 * In practice it appears some of these events do in fact count, and
2871 * we need to program all 4 events.
2872 */
intel_pmu_nhm_workaround(void)2873 static void intel_pmu_nhm_workaround(void)
2874 {
2875 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2876 static const unsigned long nhm_magic[4] = {
2877 0x4300B5,
2878 0x4300D2,
2879 0x4300B1,
2880 0x4300B1
2881 };
2882 struct perf_event *event;
2883 int i;
2884
2885 /*
2886 * The Errata requires below steps:
2887 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2888 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2889 * the corresponding PMCx;
2890 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2891 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2892 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2893 */
2894
2895 /*
2896 * The real steps we choose are a little different from above.
2897 * A) To reduce MSR operations, we don't run step 1) as they
2898 * are already cleared before this function is called;
2899 * B) Call x86_perf_event_update to save PMCx before configuring
2900 * PERFEVTSELx with magic number;
2901 * C) With step 5), we do clear only when the PERFEVTSELx is
2902 * not used currently.
2903 * D) Call x86_perf_event_set_period to restore PMCx;
2904 */
2905
2906 /* We always operate 4 pairs of PERF Counters */
2907 for (i = 0; i < 4; i++) {
2908 event = cpuc->events[i];
2909 if (event)
2910 static_call(x86_pmu_update)(event);
2911 }
2912
2913 for (i = 0; i < 4; i++) {
2914 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2915 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2916 }
2917
2918 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2919 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2920
2921 for (i = 0; i < 4; i++) {
2922 event = cpuc->events[i];
2923
2924 if (event) {
2925 static_call(x86_pmu_set_period)(event);
2926 __x86_pmu_enable_event(&event->hw,
2927 ARCH_PERFMON_EVENTSEL_ENABLE);
2928 } else
2929 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2930 }
2931 }
2932
intel_pmu_nhm_enable_all(int added)2933 static void intel_pmu_nhm_enable_all(int added)
2934 {
2935 if (added)
2936 intel_pmu_nhm_workaround();
2937 intel_pmu_enable_all(added);
2938 }
2939
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2940 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2941 {
2942 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2943
2944 if (cpuc->tfa_shadow != val) {
2945 cpuc->tfa_shadow = val;
2946 wrmsrq(MSR_TSX_FORCE_ABORT, val);
2947 }
2948 }
2949
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2950 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2951 {
2952 /*
2953 * We're going to use PMC3, make sure TFA is set before we touch it.
2954 */
2955 if (cntr == 3)
2956 intel_set_tfa(cpuc, true);
2957 }
2958
intel_tfa_pmu_enable_all(int added)2959 static void intel_tfa_pmu_enable_all(int added)
2960 {
2961 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2962
2963 /*
2964 * If we find PMC3 is no longer used when we enable the PMU, we can
2965 * clear TFA.
2966 */
2967 if (!test_bit(3, cpuc->active_mask))
2968 intel_set_tfa(cpuc, false);
2969
2970 intel_pmu_enable_all(added);
2971 }
2972
intel_pmu_get_status(void)2973 static inline u64 intel_pmu_get_status(void)
2974 {
2975 u64 status;
2976
2977 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
2978
2979 return status;
2980 }
2981
intel_pmu_ack_status(u64 ack)2982 static inline void intel_pmu_ack_status(u64 ack)
2983 {
2984 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2985 }
2986
event_is_checkpointed(struct perf_event * event)2987 static inline bool event_is_checkpointed(struct perf_event *event)
2988 {
2989 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2990 }
2991
intel_set_masks(struct perf_event * event,int idx)2992 static inline void intel_set_masks(struct perf_event *event, int idx)
2993 {
2994 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2995
2996 if (event->attr.exclude_host)
2997 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask);
2998 if (event->attr.exclude_guest)
2999 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_guest_mask);
3000 if (event_is_checkpointed(event))
3001 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
3002 }
3003
intel_clear_masks(struct perf_event * event,int idx)3004 static inline void intel_clear_masks(struct perf_event *event, int idx)
3005 {
3006 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3007
3008 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_host_mask);
3009 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_exclude_guest_mask);
3010 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
3011 }
3012
intel_pmu_disable_fixed(struct perf_event * event)3013 static void intel_pmu_disable_fixed(struct perf_event *event)
3014 {
3015 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3016 struct hw_perf_event *hwc = &event->hw;
3017 int idx = hwc->idx;
3018 u64 mask;
3019
3020 if (is_topdown_idx(idx)) {
3021 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3022
3023 /*
3024 * When there are other active TopDown events,
3025 * don't disable the fixed counter 3.
3026 */
3027 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
3028 return;
3029 idx = INTEL_PMC_IDX_FIXED_SLOTS;
3030 }
3031
3032 intel_clear_masks(event, idx);
3033
3034 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
3035 cpuc->fixed_ctrl_val &= ~mask;
3036 }
3037
__intel_pmu_update_event_ext(int idx,u64 ext)3038 static inline void __intel_pmu_update_event_ext(int idx, u64 ext)
3039 {
3040 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3041 u32 msr;
3042
3043 if (idx < INTEL_PMC_IDX_FIXED) {
3044 msr = MSR_IA32_PMC_V6_GP0_CFG_C +
3045 x86_pmu.addr_offset(idx, false);
3046 } else {
3047 msr = MSR_IA32_PMC_V6_FX0_CFG_C +
3048 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
3049 }
3050
3051 cpuc->cfg_c_val[idx] = ext;
3052 wrmsrq(msr, ext);
3053 }
3054
intel_pmu_disable_event_ext(struct perf_event * event)3055 static void intel_pmu_disable_event_ext(struct perf_event *event)
3056 {
3057 /*
3058 * Only clear CFG_C MSR for PEBS counter group events,
3059 * it avoids the HW counter's value to be added into
3060 * other PEBS records incorrectly after PEBS counter
3061 * group events are disabled.
3062 *
3063 * For other events, it's unnecessary to clear CFG_C MSRs
3064 * since CFG_C doesn't take effect if counter is in
3065 * disabled state. That helps to reduce the WRMSR overhead
3066 * in context switches.
3067 */
3068 if (!is_pebs_counter_event_group(event))
3069 return;
3070
3071 __intel_pmu_update_event_ext(event->hw.idx, 0);
3072 }
3073
3074 DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext);
3075
intel_pmu_disable_event(struct perf_event * event)3076 static void intel_pmu_disable_event(struct perf_event *event)
3077 {
3078 struct hw_perf_event *hwc = &event->hw;
3079 int idx = hwc->idx;
3080
3081 switch (idx) {
3082 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3083 intel_clear_masks(event, idx);
3084 static_call_cond(intel_pmu_disable_event_ext)(event);
3085 x86_pmu_disable_event(event);
3086 break;
3087 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3088 static_call_cond(intel_pmu_disable_event_ext)(event);
3089 fallthrough;
3090 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3091 intel_pmu_disable_fixed(event);
3092 break;
3093 case INTEL_PMC_IDX_FIXED_BTS:
3094 intel_pmu_disable_bts();
3095 intel_pmu_drain_bts_buffer();
3096 return;
3097 case INTEL_PMC_IDX_FIXED_VLBR:
3098 intel_clear_masks(event, idx);
3099 break;
3100 default:
3101 intel_clear_masks(event, idx);
3102 pr_warn("Failed to disable the event with invalid index %d\n",
3103 idx);
3104 return;
3105 }
3106
3107 /*
3108 * Needs to be called after x86_pmu_disable_event,
3109 * so we don't trigger the event without PEBS bit set.
3110 */
3111 if (unlikely(event->attr.precise_ip))
3112 static_call(x86_pmu_pebs_disable)(event);
3113 }
3114
intel_pmu_assign_event(struct perf_event * event,int idx)3115 static void intel_pmu_assign_event(struct perf_event *event, int idx)
3116 {
3117 if (is_pebs_pt(event))
3118 perf_report_aux_output_id(event, idx);
3119 }
3120
intel_pmu_needs_branch_stack(struct perf_event * event)3121 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
3122 {
3123 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
3124 }
3125
intel_pmu_del_event(struct perf_event * event)3126 static void intel_pmu_del_event(struct perf_event *event)
3127 {
3128 if (intel_pmu_needs_branch_stack(event))
3129 intel_pmu_lbr_del(event);
3130 if (event->attr.precise_ip)
3131 intel_pmu_pebs_del(event);
3132 if (is_pebs_counter_event_group(event) ||
3133 is_acr_event_group(event))
3134 this_cpu_ptr(&cpu_hw_events)->n_late_setup--;
3135 }
3136
__intel_pmu_quiesce(void)3137 int __intel_pmu_quiesce(void)
3138 {
3139 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3140 int pmu_enabled = cpuc->enabled;
3141
3142 cpuc->enabled = 0;
3143 if (pmu_enabled)
3144 intel_pmu_disable_all();
3145
3146 return pmu_enabled;
3147 }
3148
__intel_pmu_resume(int pmu_enabled)3149 void __intel_pmu_resume(int pmu_enabled)
3150 {
3151 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3152
3153 cpuc->enabled = pmu_enabled;
3154 if (pmu_enabled)
3155 intel_pmu_enable_all(0);
3156 }
3157
icl_set_topdown_event_period(struct perf_event * event)3158 static int icl_set_topdown_event_period(struct perf_event *event)
3159 {
3160 struct hw_perf_event *hwc = &event->hw;
3161 s64 left = local64_read(&hwc->period_left);
3162
3163 /*
3164 * The values in PERF_METRICS MSR are derived from fixed counter 3.
3165 * Software should start both registers, PERF_METRICS and fixed
3166 * counter 3, from zero.
3167 * Clear PERF_METRICS and Fixed counter 3 in initialization.
3168 * After that, both MSRs will be cleared for each read.
3169 * Don't need to clear them again.
3170 */
3171 if (left == x86_pmu.max_period) {
3172 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
3173 wrmsrq(MSR_PERF_METRICS, 0);
3174 hwc->saved_slots = 0;
3175 hwc->saved_metric = 0;
3176 }
3177
3178 if ((hwc->saved_slots) && is_slots_event(event)) {
3179 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
3180 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric);
3181 }
3182
3183 perf_event_update_userpage(event);
3184
3185 return 0;
3186 }
3187
3188 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
3189
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)3190 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
3191 {
3192 u32 val;
3193
3194 /*
3195 * The metric is reported as an 8bit integer fraction
3196 * summing up to 0xff.
3197 * slots-in-metric = (Metric / 0xff) * slots
3198 */
3199 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
3200 return mul_u64_u32_div(slots, val, 0xff);
3201 }
3202
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)3203 static u64 icl_get_topdown_value(struct perf_event *event,
3204 u64 slots, u64 metrics)
3205 {
3206 int idx = event->hw.idx;
3207 u64 delta;
3208
3209 if (is_metric_idx(idx))
3210 delta = icl_get_metrics_event_value(metrics, slots, idx);
3211 else
3212 delta = slots;
3213
3214 return delta;
3215 }
3216
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)3217 static void __icl_update_topdown_event(struct perf_event *event,
3218 u64 slots, u64 metrics,
3219 u64 last_slots, u64 last_metrics)
3220 {
3221 u64 delta, last = 0;
3222
3223 delta = icl_get_topdown_value(event, slots, metrics);
3224 if (last_slots)
3225 last = icl_get_topdown_value(event, last_slots, last_metrics);
3226
3227 /*
3228 * The 8bit integer fraction of metric may be not accurate,
3229 * especially when the changes is very small.
3230 * For example, if only a few bad_spec happens, the fraction
3231 * may be reduced from 1 to 0. If so, the bad_spec event value
3232 * will be 0 which is definitely less than the last value.
3233 * Avoid update event->count for this case.
3234 */
3235 if (delta > last) {
3236 delta -= last;
3237 local64_add(delta, &event->count);
3238 }
3239 }
3240
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)3241 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
3242 u64 metrics, int metric_end)
3243 {
3244 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3245 struct perf_event *other;
3246 int idx;
3247
3248 event->hw.saved_slots = slots;
3249 event->hw.saved_metric = metrics;
3250
3251 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
3252 if (!is_topdown_idx(idx))
3253 continue;
3254 other = cpuc->events[idx];
3255 other->hw.saved_slots = slots;
3256 other->hw.saved_metric = metrics;
3257 }
3258 }
3259
3260 /*
3261 * Update all active Topdown events.
3262 *
3263 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
3264 * modify by a NMI. PMU has to be disabled before calling this function.
3265 */
3266
intel_update_topdown_event(struct perf_event * event,int metric_end,u64 * val)3267 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val)
3268 {
3269 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3270 struct perf_event *other;
3271 u64 slots, metrics;
3272 bool reset = true;
3273 int idx;
3274
3275 if (!val) {
3276 /* read Fixed counter 3 */
3277 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE);
3278 if (!slots)
3279 return 0;
3280
3281 /* read PERF_METRICS */
3282 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS);
3283 } else {
3284 slots = val[0];
3285 metrics = val[1];
3286 /*
3287 * Don't reset the PERF_METRICS and Fixed counter 3
3288 * for each PEBS record read. Utilize the RDPMC metrics
3289 * clear mode.
3290 */
3291 reset = false;
3292 }
3293
3294 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
3295 if (!is_topdown_idx(idx))
3296 continue;
3297 other = cpuc->events[idx];
3298 __icl_update_topdown_event(other, slots, metrics,
3299 event ? event->hw.saved_slots : 0,
3300 event ? event->hw.saved_metric : 0);
3301 }
3302
3303 /*
3304 * Check and update this event, which may have been cleared
3305 * in active_mask e.g. x86_pmu_stop()
3306 */
3307 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
3308 __icl_update_topdown_event(event, slots, metrics,
3309 event->hw.saved_slots,
3310 event->hw.saved_metric);
3311
3312 /*
3313 * In x86_pmu_stop(), the event is cleared in active_mask first,
3314 * then drain the delta, which indicates context switch for
3315 * counting.
3316 * Save metric and slots for context switch.
3317 * Don't need to reset the PERF_METRICS and Fixed counter 3.
3318 * Because the values will be restored in next schedule in.
3319 */
3320 update_saved_topdown_regs(event, slots, metrics, metric_end);
3321 reset = false;
3322 }
3323
3324 if (reset) {
3325 /* The fixed counter 3 has to be written before the PERF_METRICS. */
3326 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
3327 wrmsrq(MSR_PERF_METRICS, 0);
3328 if (event)
3329 update_saved_topdown_regs(event, 0, 0, metric_end);
3330 }
3331
3332 return slots;
3333 }
3334
icl_update_topdown_event(struct perf_event * event,u64 * val)3335 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val)
3336 {
3337 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
3338 x86_pmu.num_topdown_events - 1,
3339 val);
3340 }
3341
3342 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
3343
intel_pmu_read_event(struct perf_event * event)3344 static void intel_pmu_read_event(struct perf_event *event)
3345 {
3346 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) ||
3347 is_pebs_counter_event_group(event)) {
3348 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3349 int pmu_enabled;
3350
3351 /* Only need to call update_topdown_event() once for group read. */
3352 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
3353 return;
3354
3355 pmu_enabled = __intel_pmu_quiesce();
3356 /*
3357 * If the PEBS counters snapshotting is enabled,
3358 * the topdown event is available in PEBS records.
3359 */
3360 if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
3361 static_call(intel_pmu_update_topdown_event)(event, NULL);
3362 else
3363 intel_pmu_drain_pebs_buffer();
3364 __intel_pmu_resume(pmu_enabled);
3365
3366 return;
3367 }
3368
3369 x86_perf_event_update(event);
3370 }
3371
intel_pmu_enable_fixed(struct perf_event * event)3372 static void intel_pmu_enable_fixed(struct perf_event *event)
3373 {
3374 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3375 struct hw_perf_event *hwc = &event->hw;
3376 int idx = hwc->idx;
3377 u64 bits = 0;
3378
3379 if (is_topdown_idx(idx)) {
3380 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3381 /*
3382 * When there are other active TopDown events,
3383 * don't enable the fixed counter 3 again.
3384 */
3385 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
3386 return;
3387
3388 idx = INTEL_PMC_IDX_FIXED_SLOTS;
3389
3390 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
3391 bits |= INTEL_FIXED_3_METRICS_CLEAR;
3392 }
3393
3394 intel_set_masks(event, idx);
3395
3396 /*
3397 * Enable IRQ generation (0x8), if not PEBS or self-reloaded
3398 * ACR event, and enable ring-3 counting (0x2) and ring-0
3399 * counting (0x1) if requested:
3400 */
3401 if (!event->attr.precise_ip && !is_acr_self_reload_event(event))
3402 bits |= INTEL_FIXED_0_ENABLE_PMI;
3403 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
3404 bits |= INTEL_FIXED_0_USER;
3405 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
3406 bits |= INTEL_FIXED_0_KERNEL;
3407 if (hwc->config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE)
3408 bits |= INTEL_FIXED_0_RDPMC_USER_DISABLE;
3409
3410 /*
3411 * ANY bit is supported in v3 and up
3412 */
3413 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
3414 bits |= INTEL_FIXED_0_ANYTHREAD;
3415
3416 idx -= INTEL_PMC_IDX_FIXED;
3417 bits = intel_fixed_bits_by_idx(idx, bits);
3418 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip)
3419 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
3420
3421 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
3422 cpuc->fixed_ctrl_val |= bits;
3423 }
3424
intel_pmu_config_acr(int idx,u64 mask,u32 reload)3425 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
3426 {
3427 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3428 int msr_b, msr_c;
3429 int msr_offset;
3430
3431 if (!mask && !cpuc->acr_cfg_b[idx])
3432 return;
3433
3434 if (idx < INTEL_PMC_IDX_FIXED) {
3435 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
3436 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
3437 msr_offset = x86_pmu.addr_offset(idx, false);
3438 } else {
3439 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
3440 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
3441 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
3442 }
3443
3444 if (cpuc->acr_cfg_b[idx] != mask) {
3445 wrmsrq(msr_b + msr_offset, mask);
3446 cpuc->acr_cfg_b[idx] = mask;
3447 }
3448 /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */
3449 if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) {
3450 wrmsrq(msr_c + msr_offset, reload);
3451 cpuc->cfg_c_val[idx] = reload;
3452 }
3453 }
3454
intel_pmu_enable_acr(struct perf_event * event)3455 static void intel_pmu_enable_acr(struct perf_event *event)
3456 {
3457 struct hw_perf_event *hwc = &event->hw;
3458
3459 if (!is_acr_event_group(event) || !event->attr.config2) {
3460 /*
3461 * The disable doesn't clear the ACR CFG register.
3462 * Check and clear the ACR CFG register.
3463 */
3464 intel_pmu_config_acr(hwc->idx, 0, 0);
3465 return;
3466 }
3467
3468 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period);
3469 }
3470
3471 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
3472
intel_pmu_enable_event_ext(struct perf_event * event)3473 static void intel_pmu_enable_event_ext(struct perf_event *event)
3474 {
3475 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3476 struct hw_perf_event *hwc = &event->hw;
3477 u64 ext = 0;
3478
3479 if (is_acr_event_group(event))
3480 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3481
3482 if (event->attr.precise_ip) {
3483 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
3484 struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);
3485 union arch_pebs_index old, new;
3486
3487 ext |= ARCH_PEBS_EN;
3488 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
3489 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3490
3491 if (pebs_data_cfg && cap.caps) {
3492 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
3493 ext |= ARCH_PEBS_AUX & cap.caps;
3494
3495 if (pebs_data_cfg & PEBS_DATACFG_GP)
3496 ext |= ARCH_PEBS_GPR & cap.caps;
3497
3498 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
3499 ext |= ARCH_PEBS_VECR_XMM & cap.caps;
3500
3501 if (pebs_data_cfg & PEBS_DATACFG_YMMHS)
3502 ext |= ARCH_PEBS_VECR_YMMH & cap.caps;
3503
3504 if (pebs_data_cfg & PEBS_DATACFG_EGPRS)
3505 ext |= ARCH_PEBS_VECR_EGPRS & cap.caps;
3506
3507 if (pebs_data_cfg & PEBS_DATACFG_OPMASKS)
3508 ext |= ARCH_PEBS_VECR_OPMASK & cap.caps;
3509
3510 if (pebs_data_cfg & PEBS_DATACFG_ZMMHS)
3511 ext |= ARCH_PEBS_VECR_ZMMH & cap.caps;
3512
3513 if (pebs_data_cfg & PEBS_DATACFG_H16ZMMS)
3514 ext |= ARCH_PEBS_VECR_H16ZMM & cap.caps;
3515
3516 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
3517 ext |= ARCH_PEBS_LBR & cap.caps;
3518
3519 if (pebs_data_cfg &
3520 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT))
3521 ext |= ARCH_PEBS_CNTR_GP & cap.caps;
3522
3523 if (pebs_data_cfg &
3524 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT))
3525 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps;
3526
3527 if (pebs_data_cfg & PEBS_DATACFG_METRICS)
3528 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps;
3529 }
3530
3531 if (cpuc->n_pebs == cpuc->n_large_pebs)
3532 new.thresh = ARCH_PEBS_THRESH_MULTI;
3533 else
3534 new.thresh = ARCH_PEBS_THRESH_SINGLE;
3535
3536 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
3537 if (new.thresh != old.thresh || !old.en) {
3538 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
3539 /*
3540 * Large PEBS was enabled.
3541 * Drain PEBS buffer before applying the single PEBS.
3542 */
3543 intel_pmu_drain_pebs_buffer();
3544 } else {
3545 new.wr = 0;
3546 new.full = 0;
3547 new.en = 1;
3548 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole);
3549 }
3550 }
3551 }
3552
3553 if (is_pebs_counter_event_group(event))
3554 ext |= ARCH_PEBS_CNTR_ALLOW;
3555
3556 if (cpuc->cfg_c_val[hwc->idx] != ext)
3557 __intel_pmu_update_event_ext(hwc->idx, ext);
3558 }
3559
intel_pmu_update_rdpmc_user_disable(struct perf_event * event)3560 static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event)
3561 {
3562 if (!x86_pmu_has_rdpmc_user_disable(event->pmu))
3563 return;
3564
3565 /*
3566 * Counter scope's user-space rdpmc is disabled by default
3567 * except two cases.
3568 * a. rdpmc = 2 (user space rdpmc enabled unconditionally)
3569 * b. rdpmc = 1 and the event is not a system-wide event.
3570 * The count of non-system-wide events would be cleared when
3571 * context switches, so no count data is leaked.
3572 */
3573 if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE ||
3574 (x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE &&
3575 (event->attach_state & PERF_ATTACH_TASK)))
3576 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
3577 else
3578 event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
3579 }
3580
3581 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext);
3582
intel_pmu_enable_event(struct perf_event * event)3583 static void intel_pmu_enable_event(struct perf_event *event)
3584 {
3585 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
3586 struct hw_perf_event *hwc = &event->hw;
3587 int idx = hwc->idx;
3588
3589 if (unlikely(event->attr.precise_ip))
3590 static_call(x86_pmu_pebs_enable)(event);
3591
3592 switch (idx) {
3593 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3594 if (branch_sample_counters(event))
3595 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
3596 intel_set_masks(event, idx);
3597 static_call_cond(intel_pmu_enable_acr_event)(event);
3598 static_call_cond(intel_pmu_enable_event_ext)(event);
3599 /*
3600 * For self-reloaded ACR event, don't enable PMI since
3601 * HW won't set overflow bit in GLOBAL_STATUS. Otherwise,
3602 * the PMI would be recognized as a suspicious NMI.
3603 */
3604 if (is_acr_self_reload_event(event))
3605 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
3606 else if (!event->attr.precise_ip)
3607 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
3608 __x86_pmu_enable_event(hwc, enable_mask);
3609 break;
3610 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3611 static_call_cond(intel_pmu_enable_acr_event)(event);
3612 static_call_cond(intel_pmu_enable_event_ext)(event);
3613 fallthrough;
3614 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3615 intel_pmu_enable_fixed(event);
3616 break;
3617 case INTEL_PMC_IDX_FIXED_BTS:
3618 if (!__this_cpu_read(cpu_hw_events.enabled))
3619 return;
3620 intel_pmu_enable_bts(hwc->config);
3621 break;
3622 case INTEL_PMC_IDX_FIXED_VLBR:
3623 intel_set_masks(event, idx);
3624 break;
3625 default:
3626 pr_warn("Failed to enable the event with invalid index %d\n",
3627 idx);
3628 }
3629 }
3630
intel_pmu_acr_late_setup(struct cpu_hw_events * cpuc)3631 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc)
3632 {
3633 struct perf_event *event, *leader;
3634 int i, j, k, bit, idx;
3635
3636 /*
3637 * FIXME: ACR mask parsing relies on cpuc->event_list[] (active events only).
3638 * Disabling an ACR event causes bit-shifting errors in the acr_mask of
3639 * remaining group members. As ACR sampling requires all events to be active,
3640 * this limitation is acceptable for now. Revisit if independent event toggling
3641 * is required.
3642 */
3643 for (i = 0; i < cpuc->n_events; i++) {
3644 leader = cpuc->event_list[i];
3645 if (!is_acr_event_group(leader))
3646 continue;
3647
3648 /* Find the last event of the ACR group. */
3649 for (j = i; j < cpuc->n_events; j++) {
3650 event = cpuc->event_list[j];
3651 if (event->group_leader != leader->group_leader)
3652 break;
3653 }
3654
3655 /*
3656 * Translate the user-space ACR mask (attr.config2) into the physical
3657 * counter bitmask (hw.config1) for each ACR event in the group.
3658 * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config().
3659 */
3660 for (k = i; k < j; k++) {
3661 event = cpuc->event_list[k];
3662 event->hw.config1 = 0;
3663 for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {
3664 idx = i + bit;
3665 /* Event index of ACR group must locate in [i, j). */
3666 if (idx >= j || !is_acr_event_group(cpuc->event_list[idx]))
3667 continue;
3668 __set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1);
3669 }
3670 }
3671 i = j - 1;
3672 }
3673 }
3674
intel_pmu_late_setup(void)3675 void intel_pmu_late_setup(void)
3676 {
3677 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3678
3679 if (!cpuc->n_late_setup)
3680 return;
3681
3682 intel_pmu_pebs_late_setup(cpuc);
3683 intel_pmu_acr_late_setup(cpuc);
3684 }
3685
intel_pmu_add_event(struct perf_event * event)3686 static void intel_pmu_add_event(struct perf_event *event)
3687 {
3688 if (event->attr.precise_ip)
3689 intel_pmu_pebs_add(event);
3690 if (intel_pmu_needs_branch_stack(event))
3691 intel_pmu_lbr_add(event);
3692 if (is_pebs_counter_event_group(event) ||
3693 is_acr_event_group(event))
3694 this_cpu_ptr(&cpu_hw_events)->n_late_setup++;
3695 }
3696
3697 /*
3698 * Save and restart an expired event. Called by NMI contexts,
3699 * so it has to be careful about preempting normal event ops:
3700 */
intel_pmu_save_and_restart(struct perf_event * event)3701 int intel_pmu_save_and_restart(struct perf_event *event)
3702 {
3703 static_call(x86_pmu_update)(event);
3704 /*
3705 * For a checkpointed counter always reset back to 0. This
3706 * avoids a situation where the counter overflows, aborts the
3707 * transaction and is then set back to shortly before the
3708 * overflow, and overflows and aborts again.
3709 */
3710 if (unlikely(event_is_checkpointed(event))) {
3711 /* No race with NMIs because the counter should not be armed */
3712 wrmsrq(event->hw.event_base, 0);
3713 local64_set(&event->hw.prev_count, 0);
3714 }
3715 return static_call(x86_pmu_set_period)(event);
3716 }
3717
intel_pmu_set_period(struct perf_event * event)3718 static int intel_pmu_set_period(struct perf_event *event)
3719 {
3720 if (unlikely(is_topdown_count(event)))
3721 return static_call(intel_pmu_set_topdown_event_period)(event);
3722
3723 return x86_perf_event_set_period(event);
3724 }
3725
intel_pmu_update(struct perf_event * event)3726 static u64 intel_pmu_update(struct perf_event *event)
3727 {
3728 if (unlikely(is_topdown_count(event)))
3729 return static_call(intel_pmu_update_topdown_event)(event, NULL);
3730
3731 return x86_perf_event_update(event);
3732 }
3733
intel_pmu_reset(void)3734 static void intel_pmu_reset(void)
3735 {
3736 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
3737 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3738 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
3739 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
3740 unsigned long flags;
3741 int idx;
3742
3743 if (!*(u64 *)cntr_mask)
3744 return;
3745
3746 local_irq_save(flags);
3747
3748 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
3749
3750 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
3751 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull);
3752 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull);
3753 }
3754 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
3755 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
3756 }
3757
3758 if (ds)
3759 ds->bts_index = ds->bts_buffer_base;
3760
3761 /* Ack all overflows and disable fixed counters */
3762 if (x86_pmu.version >= 2) {
3763 intel_pmu_ack_status(intel_pmu_get_status());
3764 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
3765 }
3766
3767 /* Reset LBRs and LBR freezing */
3768 if (x86_pmu.lbr_nr) {
3769 update_debugctlmsr(get_debugctlmsr() &
3770 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
3771 }
3772
3773 local_irq_restore(flags);
3774 }
3775
3776 /*
3777 * We may be running with guest PEBS events created by KVM, and the
3778 * PEBS records are logged into the guest's DS and invisible to host.
3779 *
3780 * In the case of guest PEBS overflow, we only trigger a fake event
3781 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
3782 * The guest will then vm-entry and check the guest DS area to read
3783 * the guest PEBS records.
3784 *
3785 * The contents and other behavior of the guest event do not matter.
3786 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3787 static int x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3788 struct perf_sample_data *data)
3789 {
3790 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3791 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_exclude_guest_mask;
3792 struct perf_event *event = NULL;
3793 int bit;
3794
3795 if (!unlikely(perf_guest_state()))
3796 return 0;
3797
3798 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3799 !guest_pebs_idxs)
3800 return 0;
3801
3802 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3803 event = cpuc->events[bit];
3804 if (!event->attr.precise_ip)
3805 continue;
3806
3807 perf_sample_data_init(data, 0, event->hw.last_period);
3808 perf_event_overflow(event, data, regs);
3809
3810 /*
3811 * Inject one fake event is enough.
3812 * Returning 1 to inform PMI is handled.
3813 */
3814 return 1;
3815 }
3816
3817 return 0;
3818 }
3819
handle_pmi_common(struct pt_regs * regs,u64 status)3820 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3821 {
3822 struct perf_sample_data data;
3823 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3824 int bit;
3825 int handled = 0;
3826
3827 inc_perf_irq_stat();
3828
3829 /*
3830 * Ignore a range of extra bits in status that do not indicate
3831 * overflow by themselves.
3832 */
3833 status &= ~(GLOBAL_STATUS_COND_CHG |
3834 GLOBAL_STATUS_ASIF |
3835 GLOBAL_STATUS_LBRS_FROZEN);
3836 if (!status)
3837 return 0;
3838 /*
3839 * In case multiple PEBS events are sampled at the same time,
3840 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3841 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3842 * having their bits set in the status register. This is a sign
3843 * that there was at least one PEBS record pending at the time
3844 * of the PMU interrupt. PEBS counters must only be processed
3845 * via the drain_pebs() calls and not via the regular sample
3846 * processing loop coming after that the function, otherwise
3847 * phony regular samples may be generated in the sampling buffer
3848 * not marked with the EXACT tag. Another possibility is to have
3849 * one PEBS event and at least one non-PEBS event which overflows
3850 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3851 * not be set, yet the overflow status bit for the PEBS counter will
3852 * be on Skylake.
3853 *
3854 * To avoid this problem, we systematically ignore the PEBS-enabled
3855 * counters from the GLOBAL_STATUS mask and we always process PEBS
3856 * events via drain_pebs().
3857 */
3858 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3859
3860 /*
3861 * PEBS overflow sets bit 62 in the global status register
3862 */
3863 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3864 u64 pebs_enabled = cpuc->pebs_enabled;
3865
3866 handled += x86_pmu_handle_guest_pebs(regs, &data);
3867 handled += static_call(x86_pmu_drain_pebs)(regs, &data);
3868 /* Ensure no "suspicious NMI" warning for empty PEBS buffer. */
3869 if (!handled)
3870 handled++;
3871
3872 /*
3873 * PMI throttle may be triggered, which stops the PEBS event.
3874 * Although cpuc->pebs_enabled is updated accordingly, the
3875 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3876 * cpuc->enabled has been forced to 0 in PMI.
3877 * Update the MSR if pebs_enabled is changed.
3878 */
3879 if (pebs_enabled != cpuc->pebs_enabled)
3880 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3881
3882 /*
3883 * Above PEBS handler (PEBS counters snapshotting) has updated fixed
3884 * counter 3 and perf metrics counts if they are in counter group,
3885 * unnecessary to update again.
3886 */
3887 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3888 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3889 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3890 }
3891
3892 /*
3893 * Arch PEBS sets bit 54 in the global status register
3894 */
3895 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
3896 (unsigned long *)&status)) {
3897 handled += static_call(x86_pmu_drain_pebs)(regs, &data);
3898 /* Ensure no "suspicious NMI" warning for empty PEBS buffer. */
3899 if (!handled)
3900 handled++;
3901
3902 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3903 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3904 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3905 }
3906
3907 /*
3908 * Intel PT
3909 */
3910 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3911 handled++;
3912 if (!perf_guest_handle_intel_pt_intr())
3913 intel_pt_interrupt();
3914 }
3915
3916 /*
3917 * Intel Perf metrics
3918 */
3919 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3920 handled++;
3921 static_call(intel_pmu_update_topdown_event)(NULL, NULL);
3922 }
3923
3924 status &= hybrid(cpuc->pmu, intel_ctrl);
3925
3926 /*
3927 * Checkpointed counters can lead to 'spurious' PMIs because the
3928 * rollback caused by the PMI will have cleared the overflow status
3929 * bit. Therefore always force probe these counters.
3930 */
3931 status |= cpuc->intel_cp_status;
3932
3933 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3934 struct perf_event *event = cpuc->events[bit];
3935 u64 last_period;
3936
3937 handled++;
3938
3939 if (!test_bit(bit, cpuc->active_mask))
3940 continue;
3941 /* Event may have already been cleared: */
3942 if (!event)
3943 continue;
3944
3945 /*
3946 * There may be unprocessed PEBS records in the PEBS buffer,
3947 * which still stores the previous values.
3948 * Process those records first before handling the latest value.
3949 * For example,
3950 * A is a regular counter
3951 * B is a PEBS event which reads A
3952 * C is a PEBS event
3953 *
3954 * The following can happen:
3955 * B-assist A=1
3956 * C A=2
3957 * B-assist A=3
3958 * A-overflow-PMI A=4
3959 * C-assist-PMI (PEBS buffer) A=5
3960 *
3961 * The PEBS buffer has to be drained before handling the A-PMI
3962 */
3963 if (is_pebs_counter_event_group(event))
3964 static_call(x86_pmu_drain_pebs)(regs, &data);
3965
3966 last_period = event->hw.last_period;
3967
3968 if (!intel_pmu_save_and_restart(event))
3969 continue;
3970
3971 perf_sample_data_init(&data, 0, last_period);
3972
3973 if (has_branch_stack(event))
3974 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3975
3976 x86_pmu_clear_perf_regs(regs);
3977 x86_pmu_update_perf_regs(event, &data, regs, false);
3978
3979 perf_event_overflow(event, &data, regs);
3980 }
3981
3982 return handled;
3983 }
3984
3985 /*
3986 * This handler is triggered by the local APIC, so the APIC IRQ handling
3987 * rules apply:
3988 */
intel_pmu_handle_irq(struct pt_regs * regs)3989 static int intel_pmu_handle_irq(struct pt_regs *regs)
3990 {
3991 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3992 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3993 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3994 int loops;
3995 u64 status;
3996 int handled;
3997 int pmu_enabled;
3998
3999 /*
4000 * Save the PMU state.
4001 * It needs to be restored when leaving the handler.
4002 */
4003 pmu_enabled = cpuc->enabled;
4004 /*
4005 * In general, the early ACK is only applied for old platforms.
4006 * For the big core starts from Haswell, the late ACK should be
4007 * applied.
4008 * For the small core after Tremont, we have to do the ACK right
4009 * before re-enabling counters, which is in the middle of the
4010 * NMI handler.
4011 */
4012 if (!late_ack && !mid_ack)
4013 apic_write(APIC_LVTPC, APIC_DM_NMI);
4014 intel_bts_disable_local();
4015 cpuc->enabled = 0;
4016 __intel_pmu_disable_all(true);
4017 handled = intel_pmu_drain_bts_buffer();
4018 handled += intel_bts_interrupt();
4019 status = intel_pmu_get_status();
4020 if (!status)
4021 goto done;
4022
4023 loops = 0;
4024 again:
4025 intel_pmu_lbr_read();
4026 intel_pmu_ack_status(status);
4027 if (++loops > 100) {
4028 static bool warned;
4029
4030 if (!warned) {
4031 WARN(1, "perfevents: irq loop stuck!\n");
4032 perf_event_print_debug();
4033 warned = true;
4034 }
4035 intel_pmu_reset();
4036 goto done;
4037 }
4038
4039 handled += handle_pmi_common(regs, status);
4040
4041 /*
4042 * Repeat if there is more work to be done:
4043 */
4044 status = intel_pmu_get_status();
4045 if (status)
4046 goto again;
4047
4048 done:
4049 if (mid_ack)
4050 apic_write(APIC_LVTPC, APIC_DM_NMI);
4051 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
4052 cpuc->enabled = pmu_enabled;
4053 if (pmu_enabled)
4054 __intel_pmu_enable_all(0, true);
4055 intel_bts_enable_local();
4056
4057 /*
4058 * Only unmask the NMI after the overflow counters
4059 * have been reset. This avoids spurious NMIs on
4060 * Haswell CPUs.
4061 */
4062 if (late_ack)
4063 apic_write(APIC_LVTPC, APIC_DM_NMI);
4064 return handled;
4065 }
4066
4067 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)4068 intel_bts_constraints(struct perf_event *event)
4069 {
4070 if (unlikely(intel_pmu_has_bts(event)))
4071 return &bts_constraint;
4072
4073 return NULL;
4074 }
4075
4076 /*
4077 * Note: matches a fake event, like Fixed2.
4078 */
4079 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)4080 intel_vlbr_constraints(struct perf_event *event)
4081 {
4082 struct event_constraint *c = &vlbr_constraint;
4083
4084 if (unlikely(constraint_match(c, event->hw.config))) {
4085 event->hw.flags |= c->flags;
4086 return c;
4087 }
4088
4089 return NULL;
4090 }
4091
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)4092 static int intel_alt_er(struct cpu_hw_events *cpuc,
4093 int idx, u64 config)
4094 {
4095 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
4096 int alt_idx = idx;
4097
4098 switch (idx) {
4099 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
4100 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
4101 return idx;
4102 if (++alt_idx > EXTRA_REG_RSP_1)
4103 alt_idx = EXTRA_REG_RSP_0;
4104 if (config & ~extra_regs[alt_idx].valid_mask)
4105 return idx;
4106 break;
4107
4108 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
4109 if (!(x86_pmu.flags & PMU_FL_HAS_OMR))
4110 return idx;
4111 if (++alt_idx > EXTRA_REG_OMR_3)
4112 alt_idx = EXTRA_REG_OMR_0;
4113 /*
4114 * Subtracting EXTRA_REG_OMR_0 ensures to get correct
4115 * OMR extra_reg entries which start from 0.
4116 */
4117 if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask)
4118 return idx;
4119 break;
4120
4121 default:
4122 break;
4123 }
4124
4125 return alt_idx;
4126 }
4127
intel_fixup_er(struct perf_event * event,int idx)4128 static void intel_fixup_er(struct perf_event *event, int idx)
4129 {
4130 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
4131 int er_idx;
4132
4133 event->hw.extra_reg.idx = idx;
4134 switch (idx) {
4135 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
4136 er_idx = idx - EXTRA_REG_RSP_0;
4137 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
4138 event->hw.config |= extra_regs[er_idx].event;
4139 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0 + er_idx;
4140 break;
4141
4142 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
4143 er_idx = idx - EXTRA_REG_OMR_0;
4144 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK;
4145 event->hw.config |= 1ULL << (8 + er_idx);
4146 event->hw.extra_reg.reg = MSR_OMR_0 + er_idx;
4147 break;
4148
4149 default:
4150 pr_warn("The extra reg idx %d is not supported.\n", idx);
4151 }
4152 }
4153
4154 /*
4155 * manage allocation of shared extra msr for certain events
4156 *
4157 * sharing can be:
4158 * per-cpu: to be shared between the various events on a single PMU
4159 * per-core: per-cpu + shared by HT threads
4160 */
4161 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)4162 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
4163 struct perf_event *event,
4164 struct hw_perf_event_extra *reg)
4165 {
4166 struct event_constraint *c = &emptyconstraint;
4167 struct er_account *era;
4168 unsigned long flags;
4169 int idx = reg->idx;
4170
4171 /*
4172 * reg->alloc can be set due to existing state, so for fake cpuc we
4173 * need to ignore this, otherwise we might fail to allocate proper fake
4174 * state for this extra reg constraint. Also see the comment below.
4175 */
4176 if (reg->alloc && !cpuc->is_fake)
4177 return NULL; /* call x86_get_event_constraint() */
4178
4179 again:
4180 era = &cpuc->shared_regs->regs[idx];
4181 /*
4182 * we use spin_lock_irqsave() to avoid lockdep issues when
4183 * passing a fake cpuc
4184 */
4185 raw_spin_lock_irqsave(&era->lock, flags);
4186
4187 if (!atomic_read(&era->ref) || era->config == reg->config) {
4188
4189 /*
4190 * If its a fake cpuc -- as per validate_{group,event}() we
4191 * shouldn't touch event state and we can avoid doing so
4192 * since both will only call get_event_constraints() once
4193 * on each event, this avoids the need for reg->alloc.
4194 *
4195 * Not doing the ER fixup will only result in era->reg being
4196 * wrong, but since we won't actually try and program hardware
4197 * this isn't a problem either.
4198 */
4199 if (!cpuc->is_fake) {
4200 if (idx != reg->idx)
4201 intel_fixup_er(event, idx);
4202
4203 /*
4204 * x86_schedule_events() can call get_event_constraints()
4205 * multiple times on events in the case of incremental
4206 * scheduling(). reg->alloc ensures we only do the ER
4207 * allocation once.
4208 */
4209 reg->alloc = 1;
4210 }
4211
4212 /* lock in msr value */
4213 era->config = reg->config;
4214 era->reg = reg->reg;
4215
4216 /* one more user */
4217 atomic_inc(&era->ref);
4218
4219 /*
4220 * need to call x86_get_event_constraint()
4221 * to check if associated event has constraints
4222 */
4223 c = NULL;
4224 } else {
4225 idx = intel_alt_er(cpuc, idx, reg->config);
4226 if (idx != reg->idx) {
4227 raw_spin_unlock_irqrestore(&era->lock, flags);
4228 goto again;
4229 }
4230 }
4231 raw_spin_unlock_irqrestore(&era->lock, flags);
4232
4233 return c;
4234 }
4235
4236 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)4237 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
4238 struct hw_perf_event_extra *reg)
4239 {
4240 struct er_account *era;
4241
4242 /*
4243 * Only put constraint if extra reg was actually allocated. Also takes
4244 * care of event which do not use an extra shared reg.
4245 *
4246 * Also, if this is a fake cpuc we shouldn't touch any event state
4247 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
4248 * either since it'll be thrown out.
4249 */
4250 if (!reg->alloc || cpuc->is_fake)
4251 return;
4252
4253 era = &cpuc->shared_regs->regs[reg->idx];
4254
4255 /* one fewer user */
4256 atomic_dec(&era->ref);
4257
4258 /* allocate again next time */
4259 reg->alloc = 0;
4260 }
4261
4262 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4263 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
4264 struct perf_event *event)
4265 {
4266 struct event_constraint *c = NULL, *d;
4267 struct hw_perf_event_extra *xreg, *breg;
4268
4269 xreg = &event->hw.extra_reg;
4270 if (xreg->idx != EXTRA_REG_NONE) {
4271 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
4272 if (c == &emptyconstraint)
4273 return c;
4274 }
4275 breg = &event->hw.branch_reg;
4276 if (breg->idx != EXTRA_REG_NONE) {
4277 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
4278 if (d == &emptyconstraint) {
4279 __intel_shared_reg_put_constraints(cpuc, xreg);
4280 c = d;
4281 }
4282 }
4283 return c;
4284 }
4285
4286 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4287 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4288 struct perf_event *event)
4289 {
4290 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
4291 struct event_constraint *c;
4292
4293 if (event_constraints) {
4294 for_each_event_constraint(c, event_constraints) {
4295 if (constraint_match(c, event->hw.config)) {
4296 event->hw.flags |= c->flags;
4297 return c;
4298 }
4299 }
4300 }
4301
4302 return &hybrid_var(cpuc->pmu, unconstrained);
4303 }
4304
4305 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4306 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4307 struct perf_event *event)
4308 {
4309 struct event_constraint *c;
4310
4311 c = intel_vlbr_constraints(event);
4312 if (c)
4313 return c;
4314
4315 c = intel_bts_constraints(event);
4316 if (c)
4317 return c;
4318
4319 c = intel_shared_regs_constraints(cpuc, event);
4320 if (c)
4321 return c;
4322
4323 c = intel_pebs_constraints(event);
4324 if (c)
4325 return c;
4326
4327 return x86_get_event_constraints(cpuc, idx, event);
4328 }
4329
4330 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)4331 intel_start_scheduling(struct cpu_hw_events *cpuc)
4332 {
4333 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4334 struct intel_excl_states *xl;
4335 int tid = cpuc->excl_thread_id;
4336
4337 /*
4338 * nothing needed if in group validation mode
4339 */
4340 if (cpuc->is_fake || !is_ht_workaround_enabled())
4341 return;
4342
4343 /*
4344 * no exclusion needed
4345 */
4346 if (WARN_ON_ONCE(!excl_cntrs))
4347 return;
4348
4349 xl = &excl_cntrs->states[tid];
4350
4351 xl->sched_started = true;
4352 /*
4353 * lock shared state until we are done scheduling
4354 * in stop_event_scheduling()
4355 * makes scheduling appear as a transaction
4356 */
4357 raw_spin_lock(&excl_cntrs->lock);
4358 }
4359
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)4360 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
4361 {
4362 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4363 struct event_constraint *c = cpuc->event_constraint[idx];
4364 struct intel_excl_states *xl;
4365 int tid = cpuc->excl_thread_id;
4366
4367 if (cpuc->is_fake || !is_ht_workaround_enabled())
4368 return;
4369
4370 if (WARN_ON_ONCE(!excl_cntrs))
4371 return;
4372
4373 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
4374 return;
4375
4376 xl = &excl_cntrs->states[tid];
4377
4378 lockdep_assert_held(&excl_cntrs->lock);
4379
4380 if (c->flags & PERF_X86_EVENT_EXCL)
4381 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
4382 else
4383 xl->state[cntr] = INTEL_EXCL_SHARED;
4384 }
4385
4386 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)4387 intel_stop_scheduling(struct cpu_hw_events *cpuc)
4388 {
4389 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4390 struct intel_excl_states *xl;
4391 int tid = cpuc->excl_thread_id;
4392
4393 /*
4394 * nothing needed if in group validation mode
4395 */
4396 if (cpuc->is_fake || !is_ht_workaround_enabled())
4397 return;
4398 /*
4399 * no exclusion needed
4400 */
4401 if (WARN_ON_ONCE(!excl_cntrs))
4402 return;
4403
4404 xl = &excl_cntrs->states[tid];
4405
4406 xl->sched_started = false;
4407 /*
4408 * release shared state lock (acquired in intel_start_scheduling())
4409 */
4410 raw_spin_unlock(&excl_cntrs->lock);
4411 }
4412
4413 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)4414 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
4415 {
4416 WARN_ON_ONCE(!cpuc->constraint_list);
4417
4418 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
4419 struct event_constraint *cx;
4420
4421 /*
4422 * grab pre-allocated constraint entry
4423 */
4424 cx = &cpuc->constraint_list[idx];
4425
4426 /*
4427 * initialize dynamic constraint
4428 * with static constraint
4429 */
4430 *cx = *c;
4431
4432 /*
4433 * mark constraint as dynamic
4434 */
4435 cx->flags |= PERF_X86_EVENT_DYNAMIC;
4436 c = cx;
4437 }
4438
4439 return c;
4440 }
4441
4442 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)4443 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
4444 int idx, struct event_constraint *c)
4445 {
4446 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4447 struct intel_excl_states *xlo;
4448 int tid = cpuc->excl_thread_id;
4449 int is_excl, i, w;
4450
4451 /*
4452 * validating a group does not require
4453 * enforcing cross-thread exclusion
4454 */
4455 if (cpuc->is_fake || !is_ht_workaround_enabled())
4456 return c;
4457
4458 /*
4459 * no exclusion needed
4460 */
4461 if (WARN_ON_ONCE(!excl_cntrs))
4462 return c;
4463
4464 /*
4465 * because we modify the constraint, we need
4466 * to make a copy. Static constraints come
4467 * from static const tables.
4468 *
4469 * only needed when constraint has not yet
4470 * been cloned (marked dynamic)
4471 */
4472 c = dyn_constraint(cpuc, c, idx);
4473
4474 /*
4475 * From here on, the constraint is dynamic.
4476 * Either it was just allocated above, or it
4477 * was allocated during a earlier invocation
4478 * of this function
4479 */
4480
4481 /*
4482 * state of sibling HT
4483 */
4484 xlo = &excl_cntrs->states[tid ^ 1];
4485
4486 /*
4487 * event requires exclusive counter access
4488 * across HT threads
4489 */
4490 is_excl = c->flags & PERF_X86_EVENT_EXCL;
4491 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
4492 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
4493 if (!cpuc->n_excl++)
4494 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
4495 }
4496
4497 /*
4498 * Modify static constraint with current dynamic
4499 * state of thread
4500 *
4501 * EXCLUSIVE: sibling counter measuring exclusive event
4502 * SHARED : sibling counter measuring non-exclusive event
4503 * UNUSED : sibling counter unused
4504 */
4505 w = c->weight;
4506 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
4507 /*
4508 * exclusive event in sibling counter
4509 * our corresponding counter cannot be used
4510 * regardless of our event
4511 */
4512 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
4513 __clear_bit(i, c->idxmsk);
4514 w--;
4515 continue;
4516 }
4517 /*
4518 * if measuring an exclusive event, sibling
4519 * measuring non-exclusive, then counter cannot
4520 * be used
4521 */
4522 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
4523 __clear_bit(i, c->idxmsk);
4524 w--;
4525 continue;
4526 }
4527 }
4528
4529 /*
4530 * if we return an empty mask, then switch
4531 * back to static empty constraint to avoid
4532 * the cost of freeing later on
4533 */
4534 if (!w)
4535 c = &emptyconstraint;
4536
4537 c->weight = w;
4538
4539 return c;
4540 }
4541
4542 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4543 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4544 struct perf_event *event)
4545 {
4546 struct event_constraint *c1, *c2;
4547
4548 c1 = cpuc->event_constraint[idx];
4549
4550 /*
4551 * first time only
4552 * - static constraint: no change across incremental scheduling calls
4553 * - dynamic constraint: handled by intel_get_excl_constraints()
4554 */
4555 c2 = __intel_get_event_constraints(cpuc, idx, event);
4556 if (c1) {
4557 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
4558 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
4559 c1->weight = c2->weight;
4560 c2 = c1;
4561 }
4562
4563 if (cpuc->excl_cntrs)
4564 return intel_get_excl_constraints(cpuc, event, idx, c2);
4565
4566 if (event->hw.dyn_constraint != ~0ULL) {
4567 c2 = dyn_constraint(cpuc, c2, idx);
4568 c2->idxmsk64 &= event->hw.dyn_constraint;
4569 c2->weight = hweight64(c2->idxmsk64);
4570 }
4571
4572 return c2;
4573 }
4574
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4575 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
4576 struct perf_event *event)
4577 {
4578 struct hw_perf_event *hwc = &event->hw;
4579 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4580 int tid = cpuc->excl_thread_id;
4581 struct intel_excl_states *xl;
4582
4583 /*
4584 * nothing needed if in group validation mode
4585 */
4586 if (cpuc->is_fake)
4587 return;
4588
4589 if (WARN_ON_ONCE(!excl_cntrs))
4590 return;
4591
4592 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
4593 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
4594 if (!--cpuc->n_excl)
4595 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
4596 }
4597
4598 /*
4599 * If event was actually assigned, then mark the counter state as
4600 * unused now.
4601 */
4602 if (hwc->idx >= 0) {
4603 xl = &excl_cntrs->states[tid];
4604
4605 /*
4606 * put_constraint may be called from x86_schedule_events()
4607 * which already has the lock held so here make locking
4608 * conditional.
4609 */
4610 if (!xl->sched_started)
4611 raw_spin_lock(&excl_cntrs->lock);
4612
4613 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
4614
4615 if (!xl->sched_started)
4616 raw_spin_unlock(&excl_cntrs->lock);
4617 }
4618 }
4619
4620 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4621 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
4622 struct perf_event *event)
4623 {
4624 struct hw_perf_event_extra *reg;
4625
4626 reg = &event->hw.extra_reg;
4627 if (reg->idx != EXTRA_REG_NONE)
4628 __intel_shared_reg_put_constraints(cpuc, reg);
4629
4630 reg = &event->hw.branch_reg;
4631 if (reg->idx != EXTRA_REG_NONE)
4632 __intel_shared_reg_put_constraints(cpuc, reg);
4633 }
4634
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4635 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
4636 struct perf_event *event)
4637 {
4638 intel_put_shared_regs_event_constraints(cpuc, event);
4639
4640 /*
4641 * is PMU has exclusive counter restrictions, then
4642 * all events are subject to and must call the
4643 * put_excl_constraints() routine
4644 */
4645 if (cpuc->excl_cntrs)
4646 intel_put_excl_constraints(cpuc, event);
4647 }
4648
intel_pebs_aliases_core2(struct perf_event * event)4649 static void intel_pebs_aliases_core2(struct perf_event *event)
4650 {
4651 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4652 /*
4653 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4654 * (0x003c) so that we can use it with PEBS.
4655 *
4656 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4657 * PEBS capable. However we can use INST_RETIRED.ANY_P
4658 * (0x00c0), which is a PEBS capable event, to get the same
4659 * count.
4660 *
4661 * INST_RETIRED.ANY_P counts the number of cycles that retires
4662 * CNTMASK instructions. By setting CNTMASK to a value (16)
4663 * larger than the maximum number of instructions that can be
4664 * retired per cycle (4) and then inverting the condition, we
4665 * count all cycles that retire 16 or less instructions, which
4666 * is every cycle.
4667 *
4668 * Thereby we gain a PEBS capable cycle counter.
4669 */
4670 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
4671
4672 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4673 event->hw.config = alt_config;
4674 }
4675 }
4676
intel_pebs_aliases_snb(struct perf_event * event)4677 static void intel_pebs_aliases_snb(struct perf_event *event)
4678 {
4679 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4680 /*
4681 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4682 * (0x003c) so that we can use it with PEBS.
4683 *
4684 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4685 * PEBS capable. However we can use UOPS_RETIRED.ALL
4686 * (0x01c2), which is a PEBS capable event, to get the same
4687 * count.
4688 *
4689 * UOPS_RETIRED.ALL counts the number of cycles that retires
4690 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
4691 * larger than the maximum number of micro-ops that can be
4692 * retired per cycle (4) and then inverting the condition, we
4693 * count all cycles that retire 16 or less micro-ops, which
4694 * is every cycle.
4695 *
4696 * Thereby we gain a PEBS capable cycle counter.
4697 */
4698 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
4699
4700 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4701 event->hw.config = alt_config;
4702 }
4703 }
4704
intel_pebs_aliases_precdist(struct perf_event * event)4705 static void intel_pebs_aliases_precdist(struct perf_event *event)
4706 {
4707 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4708 /*
4709 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4710 * (0x003c) so that we can use it with PEBS.
4711 *
4712 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4713 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
4714 * (0x01c0), which is a PEBS capable event, to get the same
4715 * count.
4716 *
4717 * The PREC_DIST event has special support to minimize sample
4718 * shadowing effects. One drawback is that it can be
4719 * only programmed on counter 1, but that seems like an
4720 * acceptable trade off.
4721 */
4722 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
4723
4724 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4725 event->hw.config = alt_config;
4726 }
4727 }
4728
intel_pebs_aliases_ivb(struct perf_event * event)4729 static void intel_pebs_aliases_ivb(struct perf_event *event)
4730 {
4731 if (event->attr.precise_ip < 3)
4732 return intel_pebs_aliases_snb(event);
4733 return intel_pebs_aliases_precdist(event);
4734 }
4735
intel_pebs_aliases_skl(struct perf_event * event)4736 static void intel_pebs_aliases_skl(struct perf_event *event)
4737 {
4738 if (event->attr.precise_ip < 3)
4739 return intel_pebs_aliases_core2(event);
4740 return intel_pebs_aliases_precdist(event);
4741 }
4742
intel_pmu_large_pebs_flags(struct perf_event * event)4743 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
4744 {
4745 unsigned long flags = x86_pmu.large_pebs_flags;
4746 u64 gprs_mask = event->attr.sample_simd_regs_enabled ?
4747 PEBS_GP_REGS | PERF_X86_EGPRS_MASK |
4748 BIT_ULL(PERF_REG_X86_SSP) :
4749 PEBS_GP_REGS | PERF_REG_EXTENDED_MASK;
4750
4751 if (event->attr.use_clockid)
4752 flags &= ~PERF_SAMPLE_TIME;
4753 if (!event->attr.exclude_kernel)
4754 flags &= ~PERF_SAMPLE_REGS_USER;
4755 if ((event->attr.sample_type & PERF_SAMPLE_REGS_USER) &&
4756 (event->attr.sample_regs_user & ~gprs_mask))
4757 flags &= ~PERF_SAMPLE_REGS_USER;
4758 if ((event->attr.sample_type & PERF_SAMPLE_REGS_INTR) &&
4759 (event->attr.sample_regs_intr & ~gprs_mask))
4760 flags &= ~PERF_SAMPLE_REGS_INTR;
4761 return flags;
4762 }
4763
intel_pmu_bts_config(struct perf_event * event)4764 static int intel_pmu_bts_config(struct perf_event *event)
4765 {
4766 struct perf_event_attr *attr = &event->attr;
4767
4768 if (unlikely(intel_pmu_has_bts(event))) {
4769 /* BTS is not supported by this architecture. */
4770 if (!x86_pmu.bts_active)
4771 return -EOPNOTSUPP;
4772
4773 /* BTS is currently only allowed for user-mode. */
4774 if (!attr->exclude_kernel)
4775 return -EOPNOTSUPP;
4776
4777 /* BTS is not allowed for precise events. */
4778 if (attr->precise_ip)
4779 return -EOPNOTSUPP;
4780
4781 /* disallow bts if conflicting events are present */
4782 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4783 return -EBUSY;
4784
4785 event->destroy = hw_perf_lbr_event_destroy;
4786 }
4787
4788 return 0;
4789 }
4790
core_pmu_hw_config(struct perf_event * event)4791 static int core_pmu_hw_config(struct perf_event *event)
4792 {
4793 int ret = x86_pmu_hw_config(event);
4794
4795 if (ret)
4796 return ret;
4797
4798 return intel_pmu_bts_config(event);
4799 }
4800
4801 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
4802 ((x86_pmu.num_topdown_events - 1) << 8))
4803
is_available_metric_event(struct perf_event * event)4804 static bool is_available_metric_event(struct perf_event *event)
4805 {
4806 return is_metric_event(event) &&
4807 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
4808 }
4809
is_mem_loads_event(struct perf_event * event)4810 static inline bool is_mem_loads_event(struct perf_event *event)
4811 {
4812 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
4813 }
4814
is_mem_loads_aux_event(struct perf_event * event)4815 static inline bool is_mem_loads_aux_event(struct perf_event *event)
4816 {
4817 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
4818 }
4819
require_mem_loads_aux_event(struct perf_event * event)4820 static inline bool require_mem_loads_aux_event(struct perf_event *event)
4821 {
4822 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
4823 return false;
4824
4825 if (is_hybrid())
4826 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
4827
4828 return true;
4829 }
4830
intel_pmu_has_cap(struct perf_event * event,int idx)4831 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
4832 {
4833 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
4834
4835 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
4836 }
4837
intel_pmu_freq_start_period(struct perf_event * event)4838 static u64 intel_pmu_freq_start_period(struct perf_event *event)
4839 {
4840 int type = event->attr.type;
4841 u64 config, factor;
4842 s64 start;
4843
4844 /*
4845 * The 127 is the lowest possible recommended SAV (sample after value)
4846 * for a 4000 freq (default freq), according to the event list JSON file.
4847 * Also, assume the workload is idle 50% time.
4848 */
4849 factor = 64 * 4000;
4850 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
4851 goto end;
4852
4853 /*
4854 * The estimation of the start period in the freq mode is
4855 * based on the below assumption.
4856 *
4857 * For a cycles or an instructions event, 1GHZ of the
4858 * underlying platform, 1 IPC. The workload is idle 50% time.
4859 * The start period = 1,000,000,000 * 1 / freq / 2.
4860 * = 500,000,000 / freq
4861 *
4862 * Usually, the branch-related events occur less than the
4863 * instructions event. According to the Intel event list JSON
4864 * file, the SAV (sample after value) of a branch-related event
4865 * is usually 1/4 of an instruction event.
4866 * The start period of branch-related events = 125,000,000 / freq.
4867 *
4868 * The cache-related events occurs even less. The SAV is usually
4869 * 1/20 of an instruction event.
4870 * The start period of cache-related events = 25,000,000 / freq.
4871 */
4872 config = event->attr.config & PERF_HW_EVENT_MASK;
4873 if (type == PERF_TYPE_HARDWARE) {
4874 switch (config) {
4875 case PERF_COUNT_HW_CPU_CYCLES:
4876 case PERF_COUNT_HW_INSTRUCTIONS:
4877 case PERF_COUNT_HW_BUS_CYCLES:
4878 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
4879 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
4880 case PERF_COUNT_HW_REF_CPU_CYCLES:
4881 factor = 500000000;
4882 break;
4883 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4884 case PERF_COUNT_HW_BRANCH_MISSES:
4885 factor = 125000000;
4886 break;
4887 case PERF_COUNT_HW_CACHE_REFERENCES:
4888 case PERF_COUNT_HW_CACHE_MISSES:
4889 factor = 25000000;
4890 break;
4891 default:
4892 goto end;
4893 }
4894 }
4895
4896 if (type == PERF_TYPE_HW_CACHE)
4897 factor = 25000000;
4898 end:
4899 /*
4900 * Usually, a prime or a number with less factors (close to prime)
4901 * is chosen as an SAV, which makes it less likely that the sampling
4902 * period synchronizes with some periodic event in the workload.
4903 * Minus 1 to make it at least avoiding values near power of twos
4904 * for the default freq.
4905 */
4906 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4907
4908 if (start > x86_pmu.max_period)
4909 start = x86_pmu.max_period;
4910
4911 if (x86_pmu.limit_period)
4912 x86_pmu.limit_period(event, &start);
4913
4914 return start;
4915 }
4916
intel_pmu_has_acr(struct pmu * pmu)4917 static inline bool intel_pmu_has_acr(struct pmu *pmu)
4918 {
4919 return !!hybrid(pmu, acr_cause_mask64);
4920 }
4921
intel_pmu_is_acr_group(struct perf_event * event)4922 static bool intel_pmu_is_acr_group(struct perf_event *event)
4923 {
4924 /* The group leader has the ACR flag set */
4925 if (is_acr_event_group(event))
4926 return true;
4927
4928 /* The acr_mask is set */
4929 if (event->attr.config2)
4930 return true;
4931
4932 return false;
4933 }
4934
intel_pmu_has_pebs_counter_group(struct pmu * pmu)4935 static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu)
4936 {
4937 u64 caps;
4938
4939 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline)
4940 return true;
4941
4942 caps = hybrid(pmu, arch_pebs_cap).caps;
4943 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK))
4944 return true;
4945
4946 return false;
4947 }
4948
intel_pmu_set_acr_cntr_constr(struct perf_event * event,u64 * cause_mask,int * num)4949 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event,
4950 u64 *cause_mask, int *num)
4951 {
4952 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64);
4953 *cause_mask |= event->attr.config2;
4954 *num += 1;
4955 }
4956
intel_pmu_set_acr_caused_constr(struct perf_event * event,int idx,u64 cause_mask)4957 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event,
4958 int idx, u64 cause_mask)
4959 {
4960 if (test_bit(idx, (unsigned long *)&cause_mask))
4961 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64);
4962 }
4963
intel_set_branch_counter_constr(struct perf_event * event,int * num)4964 static inline int intel_set_branch_counter_constr(struct perf_event *event,
4965 int *num)
4966 {
4967 if (branch_sample_call_stack(event))
4968 return -EINVAL;
4969 if (branch_sample_counters(event)) {
4970 (*num)++;
4971 event->hw.dyn_constraint &= x86_pmu.lbr_counters;
4972 }
4973
4974 return 0;
4975 }
4976
intel_pmu_hw_config(struct perf_event * event)4977 static int intel_pmu_hw_config(struct perf_event *event)
4978 {
4979 int ret = x86_pmu_hw_config(event);
4980
4981 if (ret)
4982 return ret;
4983
4984 ret = intel_pmu_bts_config(event);
4985 if (ret)
4986 return ret;
4987
4988 if (event->attr.freq && event->attr.sample_freq) {
4989 event->hw.sample_period = intel_pmu_freq_start_period(event);
4990 event->hw.last_period = event->hw.sample_period;
4991 local64_set(&event->hw.period_left, event->hw.sample_period);
4992 }
4993
4994 if (event->attr.precise_ip) {
4995 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
4996
4997 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4998 return -EINVAL;
4999
5000 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
5001 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
5002 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
5003 !has_aux_action(event)) {
5004 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
5005 event->attach_state |= PERF_ATTACH_SCHED_CB;
5006 }
5007 }
5008 if (x86_pmu.pebs_aliases)
5009 x86_pmu.pebs_aliases(event);
5010
5011 if (x86_pmu.arch_pebs) {
5012 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
5013 ~GLOBAL_CTRL_EN_PERF_METRICS;
5014 u64 pebs_mask = event->attr.precise_ip >= 3 ?
5015 pebs_cap.pdists : pebs_cap.counters;
5016 if (cntr_mask != pebs_mask)
5017 event->hw.dyn_constraint &= pebs_mask;
5018 }
5019 }
5020
5021 if (needs_branch_stack(event)) {
5022 /* Avoid branch stack setup for counting events in SAMPLE READ */
5023 if (is_sampling_event(event) ||
5024 !(event->attr.sample_type & PERF_SAMPLE_READ))
5025 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
5026 }
5027
5028 if (branch_sample_counters(event)) {
5029 struct perf_event *leader, *sibling;
5030 int num = 0;
5031
5032 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
5033 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
5034 return -EINVAL;
5035
5036 /*
5037 * The branch counter logging is not supported in the call stack
5038 * mode yet, since we cannot simply flush the LBR during e.g.,
5039 * multiplexing. Also, there is no obvious usage with the call
5040 * stack mode. Simply forbids it for now.
5041 *
5042 * If any events in the group enable the branch counter logging
5043 * feature, the group is treated as a branch counter logging
5044 * group, which requires the extra space to store the counters.
5045 */
5046 leader = event->group_leader;
5047 if (intel_set_branch_counter_constr(leader, &num))
5048 return -EINVAL;
5049 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
5050
5051 for_each_sibling_event(sibling, leader) {
5052 if (intel_set_branch_counter_constr(sibling, &num))
5053 return -EINVAL;
5054 }
5055
5056 /* event isn't installed as a sibling yet. */
5057 if (event != leader) {
5058 if (intel_set_branch_counter_constr(event, &num))
5059 return -EINVAL;
5060 }
5061
5062 if (num > fls(x86_pmu.lbr_counters))
5063 return -EINVAL;
5064 /*
5065 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
5066 * require any branch stack setup.
5067 * Clear the bit to avoid unnecessary branch stack setup.
5068 */
5069 if (0 == (event->attr.branch_sample_type &
5070 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
5071 PERF_SAMPLE_BRANCH_COUNTERS)))
5072 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
5073
5074 /*
5075 * Force the leader to be a LBR event. So LBRs can be reset
5076 * with the leader event. See intel_pmu_lbr_del() for details.
5077 */
5078 if (!intel_pmu_needs_branch_stack(leader))
5079 return -EINVAL;
5080 }
5081
5082 if (intel_pmu_needs_branch_stack(event)) {
5083 ret = intel_pmu_setup_lbr_filter(event);
5084 if (ret)
5085 return ret;
5086 event->attach_state |= PERF_ATTACH_SCHED_CB;
5087
5088 /*
5089 * BTS is set up earlier in this path, so don't account twice
5090 */
5091 if (!unlikely(intel_pmu_has_bts(event))) {
5092 /* disallow lbr if conflicting events are present */
5093 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
5094 return -EBUSY;
5095
5096 event->destroy = hw_perf_lbr_event_destroy;
5097 }
5098 }
5099
5100 if (event->attr.aux_output) {
5101 if (!event->attr.precise_ip)
5102 return -EINVAL;
5103
5104 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
5105 }
5106
5107 if ((event->attr.sample_type & PERF_SAMPLE_READ) &&
5108 intel_pmu_has_pebs_counter_group(event->pmu) &&
5109 is_sampling_event(event) &&
5110 event->attr.precise_ip)
5111 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR;
5112
5113 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) {
5114 struct perf_event *sibling, *leader = event->group_leader;
5115 struct pmu *pmu = event->pmu;
5116 bool has_sw_event = false;
5117 int num = 0, idx = 0;
5118 u64 cause_mask = 0;
5119
5120 /* Not support perf metrics */
5121 if (is_metric_event(event))
5122 return -EINVAL;
5123
5124 /* Not support freq mode */
5125 if (event->attr.freq)
5126 return -EINVAL;
5127
5128 /* PDist is not supported */
5129 if (event->attr.config2 && event->attr.precise_ip > 2)
5130 return -EINVAL;
5131
5132 /* The reload value cannot exceeds the max period */
5133 if (event->attr.sample_period > x86_pmu.max_period)
5134 return -EINVAL;
5135 /*
5136 * The counter-constraints of each event cannot be finalized
5137 * unless the whole group is scanned. However, it's hard
5138 * to know whether the event is the last one of the group.
5139 * Recalculate the counter-constraints for each event when
5140 * adding a new event.
5141 *
5142 * The group is traversed twice, which may be optimized later.
5143 * In the first round,
5144 * - Find all events which do reload when other events
5145 * overflow and set the corresponding counter-constraints
5146 * - Add all events, which can cause other events reload,
5147 * in the cause_mask
5148 * - Error out if the number of events exceeds the HW limit
5149 * - The ACR events must be contiguous.
5150 * Error out if there are non-X86 events between ACR events.
5151 * This is not a HW limit, but a SW limit.
5152 * With the assumption, the intel_pmu_acr_late_setup() can
5153 * easily convert the event idx to counter idx without
5154 * traversing the whole event list.
5155 */
5156 if (!is_x86_event(leader))
5157 return -EINVAL;
5158
5159 if (leader->attr.config2)
5160 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num);
5161
5162 if (leader->nr_siblings) {
5163 for_each_sibling_event(sibling, leader) {
5164 if (!is_x86_event(sibling)) {
5165 has_sw_event = true;
5166 continue;
5167 }
5168 if (!sibling->attr.config2)
5169 continue;
5170 if (has_sw_event)
5171 return -EINVAL;
5172 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num);
5173 }
5174 }
5175 if (leader != event && event->attr.config2) {
5176 if (has_sw_event)
5177 return -EINVAL;
5178 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num);
5179 }
5180
5181 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||
5182 num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))
5183 return -EINVAL;
5184 /*
5185 * In the second round, apply the counter-constraints for
5186 * the events which can cause other events reload.
5187 */
5188 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask);
5189
5190 if (leader->nr_siblings) {
5191 for_each_sibling_event(sibling, leader) {
5192 if (is_x86_event(sibling))
5193 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask);
5194 }
5195 }
5196
5197 if (leader != event)
5198 intel_pmu_set_acr_caused_constr(event, idx, cause_mask);
5199
5200 leader->hw.flags |= PERF_X86_EVENT_ACR;
5201 }
5202
5203 intel_pmu_update_rdpmc_user_disable(event);
5204
5205 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
5206 (event->attr.type == PERF_TYPE_HW_CACHE))
5207 return 0;
5208
5209 /*
5210 * Config Topdown slots and metric events
5211 *
5212 * The slots event on Fixed Counter 3 can support sampling,
5213 * which will be handled normally in x86_perf_event_update().
5214 *
5215 * Metric events don't support sampling and require being paired
5216 * with a slots event as group leader. When the slots event
5217 * is used in a metrics group, it too cannot support sampling.
5218 */
5219 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
5220 /* The metrics_clear can only be set for the slots event */
5221 if (event->attr.config1 &&
5222 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
5223 return -EINVAL;
5224
5225 if (event->attr.config2)
5226 return -EINVAL;
5227
5228 /*
5229 * The TopDown metrics events and slots event don't
5230 * support any filters.
5231 */
5232 if (event->attr.config & X86_ALL_EVENT_FLAGS)
5233 return -EINVAL;
5234
5235 if (is_available_metric_event(event)) {
5236 struct perf_event *leader = event->group_leader;
5237
5238 /* The metric events don't support sampling. */
5239 if (is_sampling_event(event))
5240 return -EINVAL;
5241
5242 /* The metric events require a slots group leader. */
5243 if (!is_slots_event(leader))
5244 return -EINVAL;
5245
5246 /*
5247 * The leader/SLOTS must not be a sampling event for
5248 * metric use; hardware requires it starts at 0 when used
5249 * in conjunction with MSR_PERF_METRICS.
5250 */
5251 if (is_sampling_event(leader))
5252 return -EINVAL;
5253
5254 event->event_caps |= PERF_EV_CAP_SIBLING;
5255 /*
5256 * Only once we have a METRICs sibling do we
5257 * need TopDown magic.
5258 */
5259 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
5260 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
5261 }
5262 }
5263
5264 /*
5265 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
5266 * doesn't function quite right. As a work-around it needs to always be
5267 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
5268 * The actual count of this second event is irrelevant it just needs
5269 * to be active to make the first event function correctly.
5270 *
5271 * In a group, the auxiliary event must be in front of the load latency
5272 * event. The rule is to simplify the implementation of the check.
5273 * That's because perf cannot have a complete group at the moment.
5274 */
5275 if (require_mem_loads_aux_event(event) &&
5276 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
5277 is_mem_loads_event(event)) {
5278 struct perf_event *leader = event->group_leader;
5279 struct perf_event *sibling = NULL;
5280
5281 /*
5282 * When this memload event is also the first event (no group
5283 * exists yet), then there is no aux event before it.
5284 */
5285 if (leader == event)
5286 return -ENODATA;
5287
5288 if (!is_mem_loads_aux_event(leader)) {
5289 for_each_sibling_event(sibling, leader) {
5290 if (is_mem_loads_aux_event(sibling))
5291 break;
5292 }
5293 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
5294 return -ENODATA;
5295 }
5296 }
5297
5298 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
5299 return 0;
5300
5301 if (x86_pmu.version < 3)
5302 return -EINVAL;
5303
5304 ret = perf_allow_cpu();
5305 if (ret)
5306 return ret;
5307
5308 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
5309
5310 return 0;
5311 }
5312
5313 /*
5314 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
5315 * The host perf context helps to prepare the values of the real hardware for
5316 * a set of msrs that need to be switched atomically in a vmx transaction.
5317 *
5318 * For example, the pseudocode needed to add a new msr should look like:
5319 *
5320 * arr[(*nr)++] = (struct perf_guest_switch_msr){
5321 * .msr = the hardware msr address,
5322 * .host = the value the hardware has when it doesn't run a guest,
5323 * .guest = the value the hardware has when it runs a guest,
5324 * };
5325 *
5326 * These values have nothing to do with the emulated values the guest sees
5327 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
5328 * specifically in the intel_pmu_{get,set}_msr().
5329 */
intel_guest_get_msrs(int * nr,struct x86_guest_pebs * guest_pebs)5330 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr,
5331 struct x86_guest_pebs *guest_pebs)
5332 {
5333 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5334 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
5335 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
5336 u64 pebs_mask = intel_ctrl & cpuc->pebs_enabled & x86_pmu.pebs_capable;
5337 u64 guest_pebs_mask;
5338 int global_ctrl;
5339
5340 /*
5341 * In addition to obeying exclude_guest/exclude_host, remove bits being
5342 * used for PEBS when running a guest, because PEBS writes to virtual
5343 * addresses (not physical addresses). If the guest wants to utilize
5344 * PEBS, and PEBS can be safely enabled in the guest, bits for the guest's
5345 * PEBS-enabled counters will be OR'd back in as appropriate.
5346 */
5347 *nr = 0;
5348 global_ctrl = (*nr)++;
5349 arr[global_ctrl] = (struct perf_guest_switch_msr){
5350 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
5351 .host = intel_ctrl & ~cpuc->intel_ctrl_exclude_host_mask,
5352 .guest = intel_ctrl & ~cpuc->intel_ctrl_exclude_guest_mask & ~pebs_mask,
5353 };
5354
5355 if (!x86_pmu.ds_pebs)
5356 return arr;
5357
5358 /*
5359 * If PMU counter has PEBS enabled it is not enough to
5360 * disable counter on a guest entry since PEBS memory
5361 * write can overshoot guest entry and corrupt guest
5362 * memory. Disabling PEBS solves the problem.
5363 *
5364 * Don't do this if the CPU already enforces it.
5365 */
5366 if (x86_pmu.pebs_no_isolation) {
5367 arr[(*nr)++] = (struct perf_guest_switch_msr){
5368 .msr = MSR_IA32_PEBS_ENABLE,
5369 .host = cpuc->pebs_enabled,
5370 .guest = 0,
5371 };
5372 return arr;
5373 }
5374
5375 /*
5376 * If the CPU doesn't support PEBS in the guest, then there's nothing
5377 * more to do as disabling PMCs via PERF_GLOBAL_CTRL is sufficient on
5378 * CPUs with guest/host isolation.
5379 */
5380 if (!x86_pmu.pebs_ept)
5381 return arr;
5382
5383 /*
5384 * Restrict guest PEBS events to counters that (a) perf supports, (b)
5385 * the guest wants to use for PEBS, (c) are not excluded from counting
5386 * in the guest, and (d) _are_ excluded from counting in the host.
5387 */
5388 guest_pebs_mask = pebs_mask & guest_pebs->enable &
5389 ~cpuc->intel_ctrl_exclude_guest_mask &
5390 cpuc->intel_ctrl_exclude_host_mask;
5391
5392 /*
5393 * FIXME: Allow guest and host usage of PEBS events to co-exist instead
5394 * of disabling guest PEBS entirely if the host is using PEBS.
5395 * What exactly goes wrong if guest and host are using PEBS is
5396 * unknown.
5397 */
5398 if (pebs_mask & ~cpuc->intel_ctrl_exclude_host_mask)
5399 guest_pebs_mask = 0;
5400
5401 /*
5402 * Context switch DS_AREA and PEBS_DATA_CFG if and only if PEBS will be
5403 * active in the guest; if no records will be generated while the guest
5404 * is running, then simply keep the host values resident in hardware.
5405 */
5406 arr[(*nr)++] = (struct perf_guest_switch_msr){
5407 .msr = MSR_IA32_DS_AREA,
5408 .host = (unsigned long)cpuc->ds,
5409 .guest = guest_pebs_mask ? guest_pebs->ds_area : (unsigned long)cpuc->ds,
5410 };
5411
5412 if (x86_pmu.intel_cap.pebs_baseline) {
5413 arr[(*nr)++] = (struct perf_guest_switch_msr){
5414 .msr = MSR_PEBS_DATA_CFG,
5415 .host = cpuc->active_pebs_data_cfg,
5416 .guest = guest_pebs_mask ? guest_pebs->data_cfg :
5417 cpuc->active_pebs_data_cfg,
5418 };
5419 }
5420
5421 /*
5422 * Do NOT mess with PEBS_ENABLED. As above, disabling counters via
5423 * PERF_GLOBAL_CTRL is sufficient, and loading a stale PEBS_ENABLED,
5424 * e.g. on VM-Exit, can put the system in a bad state. Simply enable
5425 * counters in PERF_GLOBAL_CTRL, as perf load PEBS_ENABLED with the
5426 * full value, i.e. perf *also* relies on PERF_GLOBAL_CTRL.
5427 */
5428 arr[global_ctrl].guest |= guest_pebs_mask;
5429 return arr;
5430 }
5431
core_guest_get_msrs(int * nr,struct x86_guest_pebs * guest_pebs)5432 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr,
5433 struct x86_guest_pebs *guest_pebs)
5434 {
5435 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5436 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
5437 int idx;
5438
5439 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
5440 struct perf_event *event = cpuc->events[idx];
5441
5442 arr[idx].msr = x86_pmu_config_addr(idx);
5443 arr[idx].host = arr[idx].guest = 0;
5444
5445 if (!test_bit(idx, cpuc->active_mask))
5446 continue;
5447
5448 arr[idx].host = arr[idx].guest =
5449 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
5450
5451 if (event->attr.exclude_host)
5452 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
5453 else if (event->attr.exclude_guest)
5454 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
5455 }
5456
5457 *nr = x86_pmu_max_num_counters(cpuc->pmu);
5458 return arr;
5459 }
5460
core_pmu_enable_event(struct perf_event * event)5461 static void core_pmu_enable_event(struct perf_event *event)
5462 {
5463 if (!event->attr.exclude_host)
5464 x86_pmu_enable_event(event);
5465 }
5466
core_pmu_enable_all(int added)5467 static void core_pmu_enable_all(int added)
5468 {
5469 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5470 int idx;
5471
5472 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
5473 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
5474
5475 if (!test_bit(idx, cpuc->active_mask) ||
5476 cpuc->events[idx]->attr.exclude_host)
5477 continue;
5478
5479 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
5480 }
5481 }
5482
hsw_hw_config(struct perf_event * event)5483 static int hsw_hw_config(struct perf_event *event)
5484 {
5485 int ret = intel_pmu_hw_config(event);
5486
5487 if (ret)
5488 return ret;
5489 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
5490 return 0;
5491 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
5492
5493 /*
5494 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
5495 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
5496 * this combination.
5497 */
5498 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
5499 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
5500 event->attr.precise_ip > 0))
5501 return -EOPNOTSUPP;
5502
5503 if (event_is_checkpointed(event)) {
5504 /*
5505 * Sampling of checkpointed events can cause situations where
5506 * the CPU constantly aborts because of a overflow, which is
5507 * then checkpointed back and ignored. Forbid checkpointing
5508 * for sampling.
5509 *
5510 * But still allow a long sampling period, so that perf stat
5511 * from KVM works.
5512 */
5513 if (event->attr.sample_period > 0 &&
5514 event->attr.sample_period < 0x7fffffff)
5515 return -EOPNOTSUPP;
5516 }
5517 return 0;
5518 }
5519
5520 static struct event_constraint counter0_constraint =
5521 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
5522
5523 static struct event_constraint counter1_constraint =
5524 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
5525
5526 static struct event_constraint counter0_1_constraint =
5527 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
5528
5529 static struct event_constraint counter2_constraint =
5530 EVENT_CONSTRAINT(0, 0x4, 0);
5531
5532 static struct event_constraint fixed0_constraint =
5533 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
5534
5535 static struct event_constraint fixed0_counter0_constraint =
5536 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
5537
5538 static struct event_constraint fixed0_counter0_1_constraint =
5539 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
5540
5541 static struct event_constraint counters_1_7_constraint =
5542 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
5543
5544 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5545 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5546 struct perf_event *event)
5547 {
5548 struct event_constraint *c;
5549
5550 c = intel_get_event_constraints(cpuc, idx, event);
5551
5552 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
5553 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
5554 if (c->idxmsk64 & (1U << 2))
5555 return &counter2_constraint;
5556 return &emptyconstraint;
5557 }
5558
5559 return c;
5560 }
5561
5562 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5563 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5564 struct perf_event *event)
5565 {
5566 /*
5567 * Fixed counter 0 has less skid.
5568 * Force instruction:ppp in Fixed counter 0
5569 */
5570 if ((event->attr.precise_ip == 3) &&
5571 constraint_match(&fixed0_constraint, event->hw.config))
5572 return &fixed0_constraint;
5573
5574 return hsw_get_event_constraints(cpuc, idx, event);
5575 }
5576
5577 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5578 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5579 struct perf_event *event)
5580 {
5581 struct event_constraint *c;
5582
5583 c = icl_get_event_constraints(cpuc, idx, event);
5584
5585 /*
5586 * The :ppp indicates the Precise Distribution (PDist) facility, which
5587 * is only supported on the GP counter 0. If a :ppp event which is not
5588 * available on the GP counter 0, error out.
5589 * Exception: Instruction PDIR is only available on the fixed counter 0.
5590 */
5591 if ((event->attr.precise_ip == 3) &&
5592 !constraint_match(&fixed0_constraint, event->hw.config)) {
5593 if (c->idxmsk64 & BIT_ULL(0))
5594 return &counter0_constraint;
5595
5596 return &emptyconstraint;
5597 }
5598
5599 return c;
5600 }
5601
5602 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5603 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5604 struct perf_event *event)
5605 {
5606 struct event_constraint *c;
5607
5608 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
5609 if (event->attr.precise_ip == 3)
5610 return &counter0_constraint;
5611
5612 c = intel_get_event_constraints(cpuc, idx, event);
5613
5614 return c;
5615 }
5616
5617 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5618 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5619 struct perf_event *event)
5620 {
5621 struct event_constraint *c;
5622
5623 c = intel_get_event_constraints(cpuc, idx, event);
5624
5625 /*
5626 * :ppp means to do reduced skid PEBS,
5627 * which is available on PMC0 and fixed counter 0.
5628 */
5629 if (event->attr.precise_ip == 3) {
5630 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
5631 if (constraint_match(&fixed0_constraint, event->hw.config))
5632 return &fixed0_counter0_constraint;
5633
5634 return &counter0_constraint;
5635 }
5636
5637 return c;
5638 }
5639
5640 static bool allow_tsx_force_abort = true;
5641
5642 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5643 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5644 struct perf_event *event)
5645 {
5646 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
5647
5648 /*
5649 * Without TFA we must not use PMC3.
5650 */
5651 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
5652 c = dyn_constraint(cpuc, c, idx);
5653 c->idxmsk64 &= ~(1ULL << 3);
5654 c->weight--;
5655 }
5656
5657 return c;
5658 }
5659
5660 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5661 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5662 struct perf_event *event)
5663 {
5664 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5665
5666 if (pmu->pmu_type == hybrid_big)
5667 return glc_get_event_constraints(cpuc, idx, event);
5668 else if (pmu->pmu_type == hybrid_small)
5669 return tnt_get_event_constraints(cpuc, idx, event);
5670
5671 WARN_ON(1);
5672 return &emptyconstraint;
5673 }
5674
5675 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5676 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5677 struct perf_event *event)
5678 {
5679 struct event_constraint *c;
5680
5681 c = intel_get_event_constraints(cpuc, idx, event);
5682
5683 /*
5684 * The :ppp indicates the Precise Distribution (PDist) facility, which
5685 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
5686 * If a :ppp event which is not available on the above eligible counters,
5687 * error out.
5688 */
5689 if (event->attr.precise_ip == 3) {
5690 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
5691 if (constraint_match(&fixed0_constraint, event->hw.config)) {
5692 /* The fixed counter 0 doesn't support LBR event logging. */
5693 if (branch_sample_counters(event))
5694 return &counter0_1_constraint;
5695 else
5696 return &fixed0_counter0_1_constraint;
5697 }
5698
5699 switch (c->idxmsk64 & 0x3ull) {
5700 case 0x1:
5701 return &counter0_constraint;
5702 case 0x2:
5703 return &counter1_constraint;
5704 case 0x3:
5705 return &counter0_1_constraint;
5706 }
5707 return &emptyconstraint;
5708 }
5709
5710 return c;
5711 }
5712
5713 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5714 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5715 struct perf_event *event)
5716 {
5717 struct event_constraint *c;
5718
5719 c = glc_get_event_constraints(cpuc, idx, event);
5720
5721 /* The Retire Latency is not supported by the fixed counter 0. */
5722 if (event->attr.precise_ip &&
5723 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
5724 constraint_match(&fixed0_constraint, event->hw.config)) {
5725 /*
5726 * The Instruction PDIR is only available
5727 * on the fixed counter 0. Error out for this case.
5728 */
5729 if (event->attr.precise_ip == 3)
5730 return &emptyconstraint;
5731 return &counters_1_7_constraint;
5732 }
5733
5734 return c;
5735 }
5736
5737 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5738 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5739 struct perf_event *event)
5740 {
5741 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5742
5743 if (pmu->pmu_type == hybrid_big)
5744 return rwc_get_event_constraints(cpuc, idx, event);
5745 if (pmu->pmu_type == hybrid_small)
5746 return cmt_get_event_constraints(cpuc, idx, event);
5747
5748 WARN_ON(1);
5749 return &emptyconstraint;
5750 }
5751
adl_hw_config(struct perf_event * event)5752 static int adl_hw_config(struct perf_event *event)
5753 {
5754 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5755
5756 if (pmu->pmu_type == hybrid_big)
5757 return hsw_hw_config(event);
5758 else if (pmu->pmu_type == hybrid_small)
5759 return intel_pmu_hw_config(event);
5760
5761 WARN_ON(1);
5762 return -EOPNOTSUPP;
5763 }
5764
adl_get_hybrid_cpu_type(void)5765 static enum intel_cpu_type adl_get_hybrid_cpu_type(void)
5766 {
5767 return INTEL_CPU_TYPE_CORE;
5768 }
5769
erratum_hsw11(struct perf_event * event)5770 static inline bool erratum_hsw11(struct perf_event *event)
5771 {
5772 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
5773 X86_CONFIG(.event=0xc0, .umask=0x01);
5774 }
5775
5776 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5777 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5778 struct perf_event *event)
5779 {
5780 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5781
5782 if (pmu->pmu_type == hybrid_tiny)
5783 return cmt_get_event_constraints(cpuc, idx, event);
5784
5785 return mtl_get_event_constraints(cpuc, idx, event);
5786 }
5787
arl_h_hw_config(struct perf_event * event)5788 static int arl_h_hw_config(struct perf_event *event)
5789 {
5790 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5791
5792 if (pmu->pmu_type == hybrid_tiny)
5793 return intel_pmu_hw_config(event);
5794
5795 return adl_hw_config(event);
5796 }
5797
5798 /*
5799 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
5800 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
5801 *
5802 * The message 'interrupt took too long' can be observed on any counter which
5803 * was armed with a period < 32 and two events expired in the same NMI.
5804 * A minimum period of 32 is enforced for the rest of the events.
5805 */
hsw_limit_period(struct perf_event * event,s64 * left)5806 static void hsw_limit_period(struct perf_event *event, s64 *left)
5807 {
5808 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
5809 }
5810
5811 /*
5812 * Broadwell:
5813 *
5814 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
5815 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
5816 * the two to enforce a minimum period of 128 (the smallest value that has bits
5817 * 0-5 cleared and >= 100).
5818 *
5819 * Because of how the code in x86_perf_event_set_period() works, the truncation
5820 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
5821 * to make up for the 'lost' events due to carrying the 'error' in period_left.
5822 *
5823 * Therefore the effective (average) period matches the requested period,
5824 * despite coarser hardware granularity.
5825 */
bdw_limit_period(struct perf_event * event,s64 * left)5826 static void bdw_limit_period(struct perf_event *event, s64 *left)
5827 {
5828 if (erratum_hsw11(event)) {
5829 if (*left < 128)
5830 *left = 128;
5831 *left &= ~0x3fULL;
5832 }
5833 }
5834
nhm_limit_period(struct perf_event * event,s64 * left)5835 static void nhm_limit_period(struct perf_event *event, s64 *left)
5836 {
5837 *left = max(*left, 32LL);
5838 }
5839
glc_limit_period(struct perf_event * event,s64 * left)5840 static void glc_limit_period(struct perf_event *event, s64 *left)
5841 {
5842 if (event->attr.precise_ip == 3)
5843 *left = max(*left, 128LL);
5844 }
5845
5846 PMU_FORMAT_ATTR(event, "config:0-7" );
5847 PMU_FORMAT_ATTR(umask, "config:8-15" );
5848 PMU_FORMAT_ATTR(edge, "config:18" );
5849 PMU_FORMAT_ATTR(pc, "config:19" );
5850 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
5851 PMU_FORMAT_ATTR(inv, "config:23" );
5852 PMU_FORMAT_ATTR(cmask, "config:24-31" );
5853 PMU_FORMAT_ATTR(in_tx, "config:32" );
5854 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
5855 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
5856
5857 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5858
umask2_show(struct device * dev,struct device_attribute * attr,char * page)5859 static ssize_t umask2_show(struct device *dev,
5860 struct device_attribute *attr,
5861 char *page)
5862 {
5863 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
5864
5865 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
5866 return sprintf(page, "config:8-15,40-47\n");
5867
5868 /* Roll back to the old format if umask2 is not supported. */
5869 return sprintf(page, "config:8-15\n");
5870 }
5871
5872 static struct device_attribute format_attr_umask2 =
5873 __ATTR(umask, 0444, umask2_show, NULL);
5874
5875 static struct attribute *format_evtsel_ext_attrs[] = {
5876 &format_attr_umask2.attr,
5877 &format_attr_eq.attr,
5878 &format_attr_metrics_clear.attr,
5879 NULL
5880 };
5881
5882 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)5883 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5884 {
5885 struct device *dev = kobj_to_dev(kobj);
5886 u64 mask;
5887
5888 /*
5889 * The umask and umask2 have different formats but share the
5890 * same attr name. In update mode, the previous value of the
5891 * umask is unconditionally removed before is_visible. If
5892 * umask2 format is not enumerated, it's impossible to roll
5893 * back to the old format.
5894 * Does the check in umask2_show rather than is_visible.
5895 */
5896 if (i == 0)
5897 return attr->mode;
5898
5899 mask = hybrid(dev_get_drvdata(dev), config_mask);
5900 if (i == 1)
5901 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
5902
5903 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5904 if (i == 2) {
5905 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
5906
5907 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
5908 }
5909
5910 return 0;
5911 }
5912
5913 static struct attribute *intel_arch_formats_attr[] = {
5914 &format_attr_event.attr,
5915 &format_attr_umask.attr,
5916 &format_attr_edge.attr,
5917 &format_attr_pc.attr,
5918 &format_attr_inv.attr,
5919 &format_attr_cmask.attr,
5920 NULL,
5921 };
5922
intel_event_sysfs_show(char * page,u64 config)5923 ssize_t intel_event_sysfs_show(char *page, u64 config)
5924 {
5925 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
5926
5927 return x86_event_sysfs_show(page, config, event);
5928 }
5929
allocate_shared_regs(int cpu)5930 static struct intel_shared_regs *allocate_shared_regs(int cpu)
5931 {
5932 struct intel_shared_regs *regs;
5933 int i;
5934
5935 regs = kzalloc_node(sizeof(struct intel_shared_regs),
5936 GFP_KERNEL, cpu_to_node(cpu));
5937 if (regs) {
5938 /*
5939 * initialize the locks to keep lockdep happy
5940 */
5941 for (i = 0; i < EXTRA_REG_MAX; i++)
5942 raw_spin_lock_init(®s->regs[i].lock);
5943
5944 regs->core_id = -1;
5945 }
5946 return regs;
5947 }
5948
allocate_excl_cntrs(int cpu)5949 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
5950 {
5951 struct intel_excl_cntrs *c;
5952
5953 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
5954 GFP_KERNEL, cpu_to_node(cpu));
5955 if (c) {
5956 raw_spin_lock_init(&c->lock);
5957 c->core_id = -1;
5958 }
5959 return c;
5960 }
5961
5962
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)5963 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
5964 {
5965 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
5966
5967 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
5968 cpuc->shared_regs = allocate_shared_regs(cpu);
5969 if (!cpuc->shared_regs)
5970 goto err;
5971 }
5972
5973 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) {
5974 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
5975
5976 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
5977 if (!cpuc->constraint_list)
5978 goto err_shared_regs;
5979 }
5980
5981 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5982 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
5983 if (!cpuc->excl_cntrs)
5984 goto err_constraint_list;
5985
5986 cpuc->excl_thread_id = 0;
5987 }
5988
5989 return 0;
5990
5991 err_constraint_list:
5992 kfree(cpuc->constraint_list);
5993 cpuc->constraint_list = NULL;
5994
5995 err_shared_regs:
5996 kfree(cpuc->shared_regs);
5997 cpuc->shared_regs = NULL;
5998
5999 err:
6000 return -ENOMEM;
6001 }
6002
intel_pmu_cpu_prepare(int cpu)6003 static int intel_pmu_cpu_prepare(int cpu)
6004 {
6005 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6006 int ret;
6007
6008 ret = intel_cpuc_prepare(cpuc, cpu);
6009 if (ret)
6010 return ret;
6011
6012 ret = alloc_arch_pebs_buf_on_cpu(cpu);
6013 if (ret) {
6014 intel_cpuc_finish(cpuc);
6015 return ret;
6016 }
6017
6018 return 0;
6019 }
6020
flip_smm_bit(void * data)6021 static void flip_smm_bit(void *data)
6022 {
6023 unsigned long set = *(unsigned long *)data;
6024
6025 if (set > 0) {
6026 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
6027 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
6028 } else {
6029 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
6030 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
6031 }
6032 }
6033
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)6034 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
6035 u64 *fixed_cntr_mask,
6036 u64 *intel_ctrl)
6037 {
6038 unsigned int bit;
6039
6040 bit = fls64(*cntr_mask);
6041 if (bit > INTEL_PMC_MAX_GENERIC) {
6042 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
6043 bit, INTEL_PMC_MAX_GENERIC);
6044 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
6045 }
6046 *intel_ctrl = *cntr_mask;
6047
6048 bit = fls64(*fixed_cntr_mask);
6049 if (bit > INTEL_PMC_MAX_FIXED) {
6050 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
6051 bit, INTEL_PMC_MAX_FIXED);
6052 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
6053 }
6054
6055 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
6056 }
6057
6058 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
6059 u64 cntr_mask,
6060 u64 fixed_cntr_mask,
6061 u64 intel_ctrl);
6062
6063 enum dyn_constr_type {
6064 DYN_CONSTR_NONE,
6065 DYN_CONSTR_BR_CNTR,
6066 DYN_CONSTR_ACR_CNTR,
6067 DYN_CONSTR_ACR_CAUSE,
6068 DYN_CONSTR_PEBS,
6069 DYN_CONSTR_PDIST,
6070
6071 DYN_CONSTR_MAX,
6072 };
6073
6074 static const char * const dyn_constr_type_name[] = {
6075 [DYN_CONSTR_NONE] = "a normal event",
6076 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event",
6077 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event",
6078 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event",
6079 [DYN_CONSTR_PEBS] = "a PEBS event",
6080 [DYN_CONSTR_PDIST] = "a PEBS PDIST event",
6081 };
6082
__intel_pmu_check_dyn_constr(struct event_constraint * constr,enum dyn_constr_type type,u64 mask)6083 static void __intel_pmu_check_dyn_constr(struct event_constraint *constr,
6084 enum dyn_constr_type type, u64 mask)
6085 {
6086 struct event_constraint *c1, *c2;
6087 int new_weight, check_weight;
6088 u64 new_mask, check_mask;
6089
6090 for_each_event_constraint(c1, constr) {
6091 new_mask = c1->idxmsk64 & mask;
6092 new_weight = hweight64(new_mask);
6093
6094 /* ignore topdown perf metrics event */
6095 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN)
6096 continue;
6097
6098 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) {
6099 pr_info("The event 0x%llx is not supported as %s.\n",
6100 c1->code, dyn_constr_type_name[type]);
6101 }
6102
6103 if (new_weight <= 1)
6104 continue;
6105
6106 for_each_event_constraint(c2, c1 + 1) {
6107 bool check_fail = false;
6108
6109 check_mask = c2->idxmsk64 & mask;
6110 check_weight = hweight64(check_mask);
6111
6112 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN ||
6113 !check_weight)
6114 continue;
6115
6116 /* The same constraints or no overlap */
6117 if (new_mask == check_mask ||
6118 (new_mask ^ check_mask) == (new_mask | check_mask))
6119 continue;
6120
6121 /*
6122 * A scheduler issue may be triggered in the following cases.
6123 * - Two overlap constraints have the same weight.
6124 * E.g., A constraints: 0x3, B constraints: 0x6
6125 * event counter failure case
6126 * B PMC[2:1] 1
6127 * A PMC[1:0] 0
6128 * A PMC[1:0] FAIL
6129 * - Two overlap constraints have different weight.
6130 * The constraint has a low weight, but has high last bit.
6131 * E.g., A constraints: 0x7, B constraints: 0xC
6132 * event counter failure case
6133 * B PMC[3:2] 2
6134 * A PMC[2:0] 0
6135 * A PMC[2:0] 1
6136 * A PMC[2:0] FAIL
6137 */
6138 if (new_weight == check_weight) {
6139 check_fail = true;
6140 } else if (new_weight < check_weight) {
6141 if ((new_mask | check_mask) != check_mask &&
6142 fls64(new_mask) > fls64(check_mask))
6143 check_fail = true;
6144 } else {
6145 if ((new_mask | check_mask) != new_mask &&
6146 fls64(new_mask) < fls64(check_mask))
6147 check_fail = true;
6148 }
6149
6150 if (check_fail) {
6151 pr_warn("The two events 0x%llx and 0x%llx may not be "
6152 "fully scheduled under some circumstances as "
6153 "%s.\n",
6154 c1->code, c2->code, dyn_constr_type_name[type]);
6155 }
6156 }
6157 }
6158 }
6159
intel_pmu_check_dyn_constr(struct pmu * pmu,struct event_constraint * constr,u64 cntr_mask)6160 static void intel_pmu_check_dyn_constr(struct pmu *pmu,
6161 struct event_constraint *constr,
6162 u64 cntr_mask)
6163 {
6164 u64 gp_mask = GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
6165 enum dyn_constr_type i;
6166 u64 mask;
6167
6168 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) {
6169 mask = 0;
6170 switch (i) {
6171 case DYN_CONSTR_NONE:
6172 mask = cntr_mask;
6173 break;
6174 case DYN_CONSTR_BR_CNTR:
6175 if (x86_pmu.flags & PMU_FL_BR_CNTR)
6176 mask = x86_pmu.lbr_counters;
6177 break;
6178 case DYN_CONSTR_ACR_CNTR:
6179 mask = hybrid(pmu, acr_cntr_mask64) & gp_mask;
6180 break;
6181 case DYN_CONSTR_ACR_CAUSE:
6182 if (hybrid(pmu, acr_cntr_mask64) ==
6183 hybrid(pmu, acr_cause_mask64))
6184 continue;
6185 mask = hybrid(pmu, acr_cause_mask64) & gp_mask;
6186 break;
6187 case DYN_CONSTR_PEBS:
6188 if (x86_pmu.arch_pebs) {
6189 mask = hybrid(pmu, arch_pebs_cap).counters &
6190 gp_mask;
6191 }
6192 break;
6193 case DYN_CONSTR_PDIST:
6194 if (x86_pmu.arch_pebs) {
6195 mask = hybrid(pmu, arch_pebs_cap).pdists &
6196 gp_mask;
6197 }
6198 break;
6199 default:
6200 pr_warn("Unsupported dynamic constraint type %d\n", i);
6201 }
6202
6203 if (mask)
6204 __intel_pmu_check_dyn_constr(constr, i, mask);
6205 }
6206 }
6207
intel_pmu_check_event_constraints_all(struct pmu * pmu)6208 static void intel_pmu_check_event_constraints_all(struct pmu *pmu)
6209 {
6210 struct event_constraint *event_constraints = hybrid(pmu, event_constraints);
6211 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints);
6212 u64 cntr_mask = hybrid(pmu, cntr_mask64);
6213 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64);
6214 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
6215
6216 intel_pmu_check_event_constraints(event_constraints, cntr_mask,
6217 fixed_cntr_mask, intel_ctrl);
6218
6219 if (event_constraints)
6220 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask);
6221
6222 if (pebs_constraints)
6223 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask);
6224 }
6225
6226 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
6227
intel_pmu_broken_perf_cap(void)6228 static inline bool intel_pmu_broken_perf_cap(void)
6229 {
6230 /*
6231 * The Perf Metric (Bit 15) is always cleared on P-core of
6232 * RPL and MTL. Details can be found in RPL018 erratum.
6233 */
6234 if (boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE ||
6235 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_P ||
6236 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_S ||
6237 boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
6238 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
6239 return true;
6240
6241 return false;
6242 }
6243
__intel_update_pmu_xregs_caps(struct pmu * pmu)6244 static inline void __intel_update_pmu_xregs_caps(struct pmu *pmu)
6245 {
6246 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id());
6247
6248 /* Only support the extension when XSAVES is available. */
6249 if (!boot_cpu_has(X86_FEATURE_XSAVES))
6250 return;
6251
6252 if (!boot_cpu_has(X86_FEATURE_XMM) ||
6253 !cpu_has_xfeatures(XFEATURE_MASK_SSE, NULL))
6254 return;
6255
6256 /*
6257 * On current hybrid platforms, P-cores and E-cores expose the same
6258 * XSAVE feature set. Therefore, using the global x86_pmu.ext_regs_mask
6259 * is sufficient to represent the hardware-supported XSAVE features.
6260 */
6261 x86_pmu.ext_regs_mask |= XFEATURE_MASK_SSE;
6262
6263 if (boot_cpu_has(X86_FEATURE_AVX) &&
6264 cpu_has_xfeatures(XFEATURE_MASK_YMM, NULL))
6265 x86_pmu.ext_regs_mask |= XFEATURE_MASK_YMM;
6266 if (boot_cpu_has(X86_FEATURE_APX) &&
6267 cpu_has_xfeatures(XFEATURE_MASK_APX, NULL))
6268 x86_pmu.ext_regs_mask |= XFEATURE_MASK_APX;
6269 if (boot_cpu_has(X86_FEATURE_AVX512F)) {
6270 if (cpu_has_xfeatures(XFEATURE_MASK_OPMASK, NULL))
6271 x86_pmu.ext_regs_mask |= XFEATURE_MASK_OPMASK;
6272 if (cpu_has_xfeatures(XFEATURE_MASK_ZMM_Hi256, NULL))
6273 x86_pmu.ext_regs_mask |= XFEATURE_MASK_ZMM_Hi256;
6274 if (cpu_has_xfeatures(XFEATURE_MASK_Hi16_ZMM, NULL))
6275 x86_pmu.ext_regs_mask |= XFEATURE_MASK_Hi16_ZMM;
6276 }
6277 if (cpu_feature_enabled(X86_FEATURE_USER_SHSTK) &&
6278 cpu_has_xfeatures(XFEATURE_MASK_CET_USER, NULL))
6279 x86_pmu.ext_regs_mask |= XFEATURE_MASK_CET_USER;
6280
6281 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
6282 if (x86_pmu.ext_regs_mask > XFEATURE_MASK_SSE)
6283 dest_pmu->capabilities |= PERF_PMU_CAP_SIMD_REGS;
6284 }
6285
__intel_update_large_pebs_flags(struct pmu * pmu)6286 static inline void __intel_update_large_pebs_flags(struct pmu *pmu)
6287 {
6288 u64 caps = hybrid(pmu, arch_pebs_cap).caps;
6289
6290 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
6291 if (caps & ARCH_PEBS_LBR)
6292 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK;
6293 if (caps & ARCH_PEBS_CNTR_MASK)
6294 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ;
6295
6296 if (!(caps & ARCH_PEBS_AUX))
6297 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC;
6298 if (!(caps & ARCH_PEBS_GPR)) {
6299 x86_pmu.large_pebs_flags &=
6300 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
6301 }
6302 }
6303
6304 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED))
6305
update_pmu_cap_from_perfmonext(struct pmu * pmu)6306 static void update_pmu_cap_from_perfmonext(struct pmu *pmu)
6307 {
6308 unsigned int eax, ebx, ecx, edx;
6309 union cpuid35_eax eax_0;
6310 union cpuid35_ebx ebx_0;
6311 u64 cntrs_mask = 0;
6312 u64 pebs_mask = 0;
6313 u64 pdists_mask = 0;
6314
6315 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx);
6316
6317 if (ebx_0.split.umask2)
6318 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
6319 if (ebx_0.split.eq)
6320 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
6321 if (ebx_0.split.rdpmc_user_disable)
6322 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
6323
6324 if (eax_0.split.cntr_subleaf) {
6325 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
6326 &eax, &ebx, &ecx, &edx);
6327 hybrid(pmu, cntr_mask64) = eax;
6328 hybrid(pmu, fixed_cntr_mask64) = ebx;
6329 cntrs_mask = counter_mask(eax, ebx);
6330 }
6331
6332 if (eax_0.split.acr_subleaf) {
6333 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF,
6334 &eax, &ebx, &ecx, &edx);
6335 /* The mask of the counters which can be reloaded */
6336 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);
6337 /* The mask of the counters which can cause a reload of reloadable counters */
6338 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);
6339 }
6340
6341 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */
6342 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) {
6343 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF,
6344 &eax, &ebx, &ecx, &edx);
6345 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;
6346
6347 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF,
6348 &eax, &ebx, &ecx, &edx);
6349 pebs_mask = counter_mask(eax, ecx);
6350 pdists_mask = counter_mask(ebx, edx);
6351 hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
6352 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
6353
6354 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask))
6355 x86_pmu.arch_pebs = 0;
6356 else
6357 __intel_update_large_pebs_flags(pmu);
6358 } else {
6359 WARN_ON(x86_pmu.arch_pebs == 1);
6360 x86_pmu.arch_pebs = 0;
6361 }
6362 }
6363
intel_update_pmu_caps(struct pmu * pmu)6364 static void intel_update_pmu_caps(struct pmu *pmu)
6365 {
6366 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
6367 update_pmu_cap_from_perfmonext(pmu);
6368
6369 if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) {
6370 rdmsrq(MSR_IA32_PERF_CAPABILITIES,
6371 hybrid(pmu, intel_cap).capabilities);
6372
6373 /*
6374 * Restore perf_metrics on platforms with broken
6375 * perf_capablities.
6376 */
6377 if (intel_pmu_broken_perf_cap() &&
6378 hybrid_pmu(pmu)->pmu_type == hybrid_big)
6379 hybrid(pmu, intel_cap).perf_metrics = 1;
6380 }
6381 __intel_update_pmu_xregs_caps(pmu);
6382 }
6383
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)6384 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
6385 {
6386 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
6387 &pmu->intel_ctrl);
6388 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6389 pmu->unconstrained = (struct event_constraint)
6390 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6391 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6392
6393 if (pmu->intel_cap.perf_metrics)
6394 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
6395 else
6396 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
6397
6398 pmu->pmu.capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
6399
6400 intel_pmu_check_event_constraints_all(&pmu->pmu);
6401
6402 intel_pmu_check_extra_regs(pmu->extra_regs);
6403 }
6404
find_hybrid_pmu_for_cpu(void)6405 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
6406 {
6407 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
6408 enum intel_cpu_type cpu_type = c->topo.intel_type;
6409 int i;
6410
6411 /*
6412 * This is running on a CPU model that is known to have hybrid
6413 * configurations. But the CPU told us it is not hybrid, shame
6414 * on it. There should be a fixup function provided for these
6415 * troublesome CPUs (->get_hybrid_cpu_type).
6416 */
6417 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) {
6418 if (x86_pmu.get_hybrid_cpu_type)
6419 cpu_type = x86_pmu.get_hybrid_cpu_type();
6420 else
6421 return NULL;
6422 }
6423
6424 /*
6425 * This essentially just maps between the 'hybrid_cpu_type'
6426 * and 'hybrid_pmu_type' enums except for ARL-H processor
6427 * which needs to compare atom uarch native id since ARL-H
6428 * contains two different atom uarchs.
6429 */
6430 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
6431 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
6432 u32 native_id;
6433
6434 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big)
6435 return &x86_pmu.hybrid_pmu[i];
6436 if (cpu_type == INTEL_CPU_TYPE_ATOM) {
6437 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
6438 return &x86_pmu.hybrid_pmu[i];
6439
6440 native_id = c->topo.intel_native_model_id;
6441 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small)
6442 return &x86_pmu.hybrid_pmu[i];
6443 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny)
6444 return &x86_pmu.hybrid_pmu[i];
6445 }
6446 }
6447
6448 return NULL;
6449 }
6450
init_hybrid_pmu(int cpu)6451 static bool init_hybrid_pmu(int cpu)
6452 {
6453 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6454 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
6455
6456 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
6457 cpuc->pmu = NULL;
6458 return false;
6459 }
6460
6461 /* Only check and dump the PMU information for the first CPU */
6462 if (!cpumask_empty(&pmu->supported_cpus))
6463 goto end;
6464
6465 intel_update_pmu_caps(&pmu->pmu);
6466 intel_pmu_check_hybrid_pmus(pmu);
6467
6468 if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) {
6469 cpuc->pmu = NULL;
6470 return false;
6471 }
6472
6473 pr_info("%s PMU driver: ", pmu->name);
6474
6475 pr_cont("\n");
6476
6477 x86_pmu_show_pmu_cap(&pmu->pmu);
6478
6479 end:
6480 cpumask_set_cpu(cpu, &pmu->supported_cpus);
6481 cpuc->pmu = &pmu->pmu;
6482
6483 return true;
6484 }
6485
intel_pmu_cpu_starting(int cpu)6486 static void intel_pmu_cpu_starting(int cpu)
6487 {
6488 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6489 int core_id = topology_core_id(cpu);
6490 int i;
6491
6492 if (is_hybrid() && !init_hybrid_pmu(cpu))
6493 return;
6494
6495 init_debug_store_on_cpu(cpu);
6496 init_arch_pebs_on_cpu(cpu);
6497 /*
6498 * Deal with CPUs that don't clear their LBRs on power-up, and that may
6499 * even boot with LBRs enabled.
6500 */
6501 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
6502 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
6503 intel_pmu_lbr_reset();
6504
6505 cpuc->lbr_sel = NULL;
6506
6507 if (x86_pmu.flags & PMU_FL_TFA) {
6508 WARN_ON_ONCE(cpuc->tfa_shadow);
6509 cpuc->tfa_shadow = ~0ULL;
6510 intel_set_tfa(cpuc, false);
6511 }
6512
6513 if (x86_pmu.version > 1)
6514 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
6515
6516 /*
6517 * Disable perf metrics if any added CPU doesn't support it.
6518 *
6519 * Turn off the check for a hybrid architecture, because the
6520 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
6521 * the architecture features. The perf metrics is a model-specific
6522 * feature for now. The corresponding bit should always be 0 on
6523 * a hybrid platform, e.g., Alder Lake.
6524 */
6525 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
6526 union perf_capabilities perf_cap;
6527
6528 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
6529 if (!perf_cap.perf_metrics) {
6530 x86_pmu.intel_cap.perf_metrics = 0;
6531 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
6532 }
6533 }
6534
6535 if (!cpuc->shared_regs)
6536 return;
6537
6538 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
6539 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6540 struct intel_shared_regs *pc;
6541
6542 pc = per_cpu(cpu_hw_events, i).shared_regs;
6543 if (pc && pc->core_id == core_id) {
6544 cpuc->kfree_on_online[0] = cpuc->shared_regs;
6545 cpuc->shared_regs = pc;
6546 break;
6547 }
6548 }
6549 cpuc->shared_regs->core_id = core_id;
6550 cpuc->shared_regs->refcnt++;
6551 }
6552
6553 if (x86_pmu.lbr_sel_map)
6554 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6555
6556 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
6557 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6558 struct cpu_hw_events *sibling;
6559 struct intel_excl_cntrs *c;
6560
6561 sibling = &per_cpu(cpu_hw_events, i);
6562 c = sibling->excl_cntrs;
6563 if (c && c->core_id == core_id) {
6564 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
6565 cpuc->excl_cntrs = c;
6566 if (!sibling->excl_thread_id)
6567 cpuc->excl_thread_id = 1;
6568 break;
6569 }
6570 }
6571 cpuc->excl_cntrs->core_id = core_id;
6572 cpuc->excl_cntrs->refcnt++;
6573 }
6574 }
6575
free_excl_cntrs(struct cpu_hw_events * cpuc)6576 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
6577 {
6578 struct intel_excl_cntrs *c;
6579
6580 c = cpuc->excl_cntrs;
6581 if (c) {
6582 if (c->core_id == -1 || --c->refcnt == 0)
6583 kfree(c);
6584 cpuc->excl_cntrs = NULL;
6585 }
6586
6587 kfree(cpuc->constraint_list);
6588 cpuc->constraint_list = NULL;
6589 }
6590
intel_pmu_cpu_dying(int cpu)6591 static void intel_pmu_cpu_dying(int cpu)
6592 {
6593 fini_debug_store_on_cpu(cpu);
6594 fini_arch_pebs_on_cpu(cpu);
6595 }
6596
intel_cpuc_finish(struct cpu_hw_events * cpuc)6597 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
6598 {
6599 struct intel_shared_regs *pc;
6600
6601 pc = cpuc->shared_regs;
6602 if (pc) {
6603 if (pc->core_id == -1 || --pc->refcnt == 0)
6604 kfree(pc);
6605 cpuc->shared_regs = NULL;
6606 }
6607
6608 free_excl_cntrs(cpuc);
6609 }
6610
intel_pmu_cpu_dead(int cpu)6611 static void intel_pmu_cpu_dead(int cpu)
6612 {
6613 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6614 struct pmu *pmu = x86_get_static_pmu();
6615
6616 release_arch_pebs_buf_on_cpu(cpu);
6617 intel_cpuc_finish(cpuc);
6618
6619 if (is_hybrid() && cpuc->pmu && cpuc->pmu != pmu)
6620 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
6621 }
6622
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)6623 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
6624 struct task_struct *task, bool sched_in)
6625 {
6626 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
6627 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
6628 }
6629
intel_pmu_check_period(struct perf_event * event,u64 value)6630 static int intel_pmu_check_period(struct perf_event *event, u64 value)
6631 {
6632 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
6633 }
6634
intel_aux_output_init(void)6635 static void intel_aux_output_init(void)
6636 {
6637 /* Refer also intel_pmu_aux_output_match() */
6638 if (x86_pmu.intel_cap.pebs_output_pt_available)
6639 x86_pmu.assign = intel_pmu_assign_event;
6640 }
6641
intel_pmu_aux_output_match(struct perf_event * event)6642 static int intel_pmu_aux_output_match(struct perf_event *event)
6643 {
6644 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
6645 if (!x86_pmu.intel_cap.pebs_output_pt_available)
6646 return 0;
6647
6648 return is_intel_pt_event(event);
6649 }
6650
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)6651 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
6652 {
6653 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
6654
6655 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
6656 }
6657
6658 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
6659
6660 PMU_FORMAT_ATTR(offmodule_rsp, "config1:0-63");
6661
6662 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
6663
6664 PMU_FORMAT_ATTR(frontend, "config1:0-23");
6665
6666 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
6667
6668 static struct attribute *intel_arch3_formats_attr[] = {
6669 &format_attr_event.attr,
6670 &format_attr_umask.attr,
6671 &format_attr_edge.attr,
6672 &format_attr_pc.attr,
6673 &format_attr_any.attr,
6674 &format_attr_inv.attr,
6675 &format_attr_cmask.attr,
6676 NULL,
6677 };
6678
6679 static struct attribute *hsw_format_attr[] = {
6680 &format_attr_in_tx.attr,
6681 &format_attr_in_tx_cp.attr,
6682 &format_attr_offcore_rsp.attr,
6683 &format_attr_ldlat.attr,
6684 NULL
6685 };
6686
6687 static struct attribute *nhm_format_attr[] = {
6688 &format_attr_offcore_rsp.attr,
6689 &format_attr_ldlat.attr,
6690 NULL
6691 };
6692
6693 static struct attribute *slm_format_attr[] = {
6694 &format_attr_offcore_rsp.attr,
6695 NULL
6696 };
6697
6698 static struct attribute *cmt_format_attr[] = {
6699 &format_attr_offcore_rsp.attr,
6700 &format_attr_ldlat.attr,
6701 &format_attr_snoop_rsp.attr,
6702 NULL
6703 };
6704
6705 static struct attribute *skl_format_attr[] = {
6706 &format_attr_frontend.attr,
6707 NULL,
6708 };
6709
6710 static struct attribute *pnc_format_attr_rtm[] = {
6711 &format_attr_in_tx.attr,
6712 &format_attr_in_tx_cp.attr,
6713 &format_attr_offmodule_rsp.attr,
6714 &format_attr_ldlat.attr,
6715 NULL
6716 };
6717
6718 static struct attribute *pnc_format_attr[] = {
6719 &format_attr_offmodule_rsp.attr,
6720 &format_attr_ldlat.attr,
6721 NULL
6722 };
6723
6724 static __initconst const struct x86_pmu core_pmu = {
6725 .name = "core",
6726 .handle_irq = x86_pmu_handle_irq,
6727 .disable_all = x86_pmu_disable_all,
6728 .enable_all = core_pmu_enable_all,
6729 .enable = core_pmu_enable_event,
6730 .disable = x86_pmu_disable_event,
6731 .hw_config = core_pmu_hw_config,
6732 .schedule_events = x86_schedule_events,
6733 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6734 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6735 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6736 .event_map = intel_pmu_event_map,
6737 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6738 .apic = 1,
6739 .large_pebs_flags = LARGE_PEBS_FLAGS,
6740
6741 /*
6742 * Intel PMCs cannot be accessed sanely above 32-bit width,
6743 * so we install an artificial 1<<31 period regardless of
6744 * the generic event period:
6745 */
6746 .max_period = (1ULL<<31) - 1,
6747 .get_event_constraints = intel_get_event_constraints,
6748 .put_event_constraints = intel_put_event_constraints,
6749 .event_constraints = intel_core_event_constraints,
6750 .guest_get_msrs = core_guest_get_msrs,
6751 .format_attrs = intel_arch_formats_attr,
6752 .events_sysfs_show = intel_event_sysfs_show,
6753
6754 /*
6755 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
6756 * together with PMU version 1 and thus be using core_pmu with
6757 * shared_regs. We need following callbacks here to allocate
6758 * it properly.
6759 */
6760 .cpu_prepare = intel_pmu_cpu_prepare,
6761 .cpu_starting = intel_pmu_cpu_starting,
6762 .cpu_dying = intel_pmu_cpu_dying,
6763 .cpu_dead = intel_pmu_cpu_dead,
6764
6765 .check_period = intel_pmu_check_period,
6766
6767 .lbr_reset = intel_pmu_lbr_reset_64,
6768 .lbr_read = intel_pmu_lbr_read_64,
6769 .lbr_save = intel_pmu_lbr_save,
6770 .lbr_restore = intel_pmu_lbr_restore,
6771 };
6772
6773 static __initconst const struct x86_pmu intel_pmu = {
6774 .name = "Intel",
6775 .handle_irq = intel_pmu_handle_irq,
6776 .disable_all = intel_pmu_disable_all,
6777 .enable_all = intel_pmu_enable_all,
6778 .enable = intel_pmu_enable_event,
6779 .disable = intel_pmu_disable_event,
6780 .add = intel_pmu_add_event,
6781 .del = intel_pmu_del_event,
6782 .read = intel_pmu_read_event,
6783 .set_period = intel_pmu_set_period,
6784 .update = intel_pmu_update,
6785 .hw_config = intel_pmu_hw_config,
6786 .schedule_events = x86_schedule_events,
6787 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6788 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6789 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6790 .event_map = intel_pmu_event_map,
6791 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6792 .apic = 1,
6793 .large_pebs_flags = LARGE_PEBS_FLAGS,
6794 /*
6795 * Intel PMCs cannot be accessed sanely above 32 bit width,
6796 * so we install an artificial 1<<31 period regardless of
6797 * the generic event period:
6798 */
6799 .max_period = (1ULL << 31) - 1,
6800 .get_event_constraints = intel_get_event_constraints,
6801 .put_event_constraints = intel_put_event_constraints,
6802 .pebs_aliases = intel_pebs_aliases_core2,
6803
6804 .format_attrs = intel_arch3_formats_attr,
6805 .events_sysfs_show = intel_event_sysfs_show,
6806
6807 .cpu_prepare = intel_pmu_cpu_prepare,
6808 .cpu_starting = intel_pmu_cpu_starting,
6809 .cpu_dying = intel_pmu_cpu_dying,
6810 .cpu_dead = intel_pmu_cpu_dead,
6811
6812 .guest_get_msrs = intel_guest_get_msrs,
6813 .sched_task = intel_pmu_sched_task,
6814
6815 .check_period = intel_pmu_check_period,
6816
6817 .aux_output_match = intel_pmu_aux_output_match,
6818
6819 .lbr_reset = intel_pmu_lbr_reset_64,
6820 .lbr_read = intel_pmu_lbr_read_64,
6821 .lbr_save = intel_pmu_lbr_save,
6822 .lbr_restore = intel_pmu_lbr_restore,
6823
6824 /*
6825 * SMM has access to all 4 rings and while traditionally SMM code only
6826 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
6827 *
6828 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
6829 * between SMM or not, this results in what should be pure userspace
6830 * counters including SMM data.
6831 *
6832 * This is a clear privilege issue, therefore globally disable
6833 * counting SMM by default.
6834 */
6835 .attr_freeze_on_smi = 1,
6836 };
6837
intel_clovertown_quirk(void)6838 static __init void intel_clovertown_quirk(void)
6839 {
6840 /*
6841 * PEBS is unreliable due to:
6842 *
6843 * AJ67 - PEBS may experience CPL leaks
6844 * AJ68 - PEBS PMI may be delayed by one event
6845 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
6846 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
6847 *
6848 * AJ67 could be worked around by restricting the OS/USR flags.
6849 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
6850 *
6851 * AJ106 could possibly be worked around by not allowing LBR
6852 * usage from PEBS, including the fixup.
6853 * AJ68 could possibly be worked around by always programming
6854 * a pebs_event_reset[0] value and coping with the lost events.
6855 *
6856 * But taken together it might just make sense to not enable PEBS on
6857 * these chips.
6858 */
6859 pr_warn("PEBS disabled due to CPU errata\n");
6860 x86_pmu.ds_pebs = 0;
6861 x86_pmu.pebs_constraints = NULL;
6862 }
6863
6864 static const struct x86_cpu_id isolation_ucodes[] = {
6865 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
6866 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
6867 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
6868 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
6869 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
6870 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
6871 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
6872 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
6873 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
6874 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
6875 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
6876 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
6877 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
6878 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
6879 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
6880 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
6881 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
6882 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
6883 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
6884 {}
6885 };
6886
intel_check_pebs_isolation(void)6887 static void intel_check_pebs_isolation(void)
6888 {
6889 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
6890 }
6891
intel_pebs_isolation_quirk(void)6892 static __init void intel_pebs_isolation_quirk(void)
6893 {
6894 WARN_ON_ONCE(x86_pmu.check_microcode);
6895 x86_pmu.check_microcode = intel_check_pebs_isolation;
6896 intel_check_pebs_isolation();
6897 }
6898
6899 static const struct x86_cpu_id pebs_ucodes[] = {
6900 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
6901 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
6902 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
6903 {}
6904 };
6905
intel_snb_pebs_broken(void)6906 static bool intel_snb_pebs_broken(void)
6907 {
6908 return !x86_match_min_microcode_rev(pebs_ucodes);
6909 }
6910
intel_snb_check_microcode(void)6911 static void intel_snb_check_microcode(void)
6912 {
6913 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
6914 return;
6915
6916 /*
6917 * Serialized by the microcode lock..
6918 */
6919 if (x86_pmu.pebs_broken) {
6920 pr_info("PEBS enabled due to microcode update\n");
6921 x86_pmu.pebs_broken = 0;
6922 } else {
6923 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
6924 x86_pmu.pebs_broken = 1;
6925 }
6926 }
6927
is_lbr_from(unsigned long msr)6928 static bool is_lbr_from(unsigned long msr)
6929 {
6930 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
6931
6932 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
6933 }
6934
6935 /*
6936 * Under certain circumstances, access certain MSR may cause #GP.
6937 * The function tests if the input MSR can be safely accessed.
6938 */
check_msr(unsigned long msr,u64 mask)6939 static bool check_msr(unsigned long msr, u64 mask)
6940 {
6941 u64 val_old, val_new, val_tmp;
6942
6943 /*
6944 * Disable the check for real HW, so we don't
6945 * mess with potentially enabled registers:
6946 */
6947 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
6948 return true;
6949
6950 /*
6951 * Read the current value, change it and read it back to see if it
6952 * matches, this is needed to detect certain hardware emulators
6953 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
6954 */
6955 if (rdmsrq_safe(msr, &val_old))
6956 return false;
6957
6958 /*
6959 * Only change the bits which can be updated by wrmsrq.
6960 */
6961 val_tmp = val_old ^ mask;
6962
6963 if (is_lbr_from(msr))
6964 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
6965
6966 if (wrmsrq_safe(msr, val_tmp) ||
6967 rdmsrq_safe(msr, &val_new))
6968 return false;
6969
6970 /*
6971 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value
6972 * should equal rdmsrq()'s even with the quirk.
6973 */
6974 if (val_new != val_tmp)
6975 return false;
6976
6977 if (is_lbr_from(msr))
6978 val_old = lbr_from_signext_quirk_wr(val_old);
6979
6980 /* Here it's sure that the MSR can be safely accessed.
6981 * Restore the old value and return.
6982 */
6983 wrmsrq(msr, val_old);
6984
6985 return true;
6986 }
6987
intel_sandybridge_quirk(void)6988 static __init void intel_sandybridge_quirk(void)
6989 {
6990 x86_pmu.check_microcode = intel_snb_check_microcode;
6991 cpus_read_lock();
6992 intel_snb_check_microcode();
6993 cpus_read_unlock();
6994 }
6995
6996 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
6997 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
6998 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
6999 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
7000 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
7001 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
7002 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
7003 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
7004 };
7005
intel_arch_events_quirk(void)7006 static __init void intel_arch_events_quirk(void)
7007 {
7008 int bit;
7009
7010 /* disable event that reported as not present by cpuid */
7011 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
7012 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
7013 pr_warn("CPUID marked event: \'%s\' unavailable\n",
7014 intel_arch_events_map[bit].name);
7015 }
7016 }
7017
intel_nehalem_quirk(void)7018 static __init void intel_nehalem_quirk(void)
7019 {
7020 union cpuid10_ebx ebx;
7021
7022 ebx.full = x86_pmu.events_maskl;
7023 if (ebx.split.no_branch_misses_retired) {
7024 /*
7025 * Erratum AAJ80 detected, we work it around by using
7026 * the BR_MISP_EXEC.ANY event. This will over-count
7027 * branch-misses, but it's still much better than the
7028 * architectural event which is often completely bogus:
7029 */
7030 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
7031 ebx.split.no_branch_misses_retired = 0;
7032 x86_pmu.events_maskl = ebx.full;
7033 pr_info("CPU erratum AAJ80 worked around\n");
7034 }
7035 }
7036
7037 /*
7038 * enable software workaround for errata:
7039 * SNB: BJ122
7040 * IVB: BV98
7041 * HSW: HSD29
7042 *
7043 * Only needed when HT is enabled. However detecting
7044 * if HT is enabled is difficult (model specific). So instead,
7045 * we enable the workaround in the early boot, and verify if
7046 * it is needed in a later initcall phase once we have valid
7047 * topology information to check if HT is actually enabled
7048 */
intel_ht_bug(void)7049 static __init void intel_ht_bug(void)
7050 {
7051 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
7052
7053 x86_pmu.start_scheduling = intel_start_scheduling;
7054 x86_pmu.commit_scheduling = intel_commit_scheduling;
7055 x86_pmu.stop_scheduling = intel_stop_scheduling;
7056 }
7057
7058 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
7059 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
7060
7061 /* Haswell special events */
7062 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
7063 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
7064 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
7065 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
7066 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
7067 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
7068 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
7069 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
7070 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
7071 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
7072 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
7073 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
7074
7075 static struct attribute *hsw_events_attrs[] = {
7076 EVENT_PTR(td_slots_issued),
7077 EVENT_PTR(td_slots_retired),
7078 EVENT_PTR(td_fetch_bubbles),
7079 EVENT_PTR(td_total_slots),
7080 EVENT_PTR(td_total_slots_scale),
7081 EVENT_PTR(td_recovery_bubbles),
7082 EVENT_PTR(td_recovery_bubbles_scale),
7083 NULL
7084 };
7085
7086 static struct attribute *hsw_mem_events_attrs[] = {
7087 EVENT_PTR(mem_ld_hsw),
7088 EVENT_PTR(mem_st_hsw),
7089 NULL,
7090 };
7091
7092 static struct attribute *hsw_tsx_events_attrs[] = {
7093 EVENT_PTR(tx_start),
7094 EVENT_PTR(tx_commit),
7095 EVENT_PTR(tx_abort),
7096 EVENT_PTR(tx_capacity),
7097 EVENT_PTR(tx_conflict),
7098 EVENT_PTR(el_start),
7099 EVENT_PTR(el_commit),
7100 EVENT_PTR(el_abort),
7101 EVENT_PTR(el_capacity),
7102 EVENT_PTR(el_conflict),
7103 EVENT_PTR(cycles_t),
7104 EVENT_PTR(cycles_ct),
7105 NULL
7106 };
7107
7108 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
7109 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
7110 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
7111 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
7112
7113 static struct attribute *icl_events_attrs[] = {
7114 EVENT_PTR(mem_ld_hsw),
7115 EVENT_PTR(mem_st_hsw),
7116 NULL,
7117 };
7118
7119 static struct attribute *icl_td_events_attrs[] = {
7120 EVENT_PTR(slots),
7121 EVENT_PTR(td_retiring),
7122 EVENT_PTR(td_bad_spec),
7123 EVENT_PTR(td_fe_bound),
7124 EVENT_PTR(td_be_bound),
7125 NULL,
7126 };
7127
7128 static struct attribute *icl_tsx_events_attrs[] = {
7129 EVENT_PTR(tx_start),
7130 EVENT_PTR(tx_abort),
7131 EVENT_PTR(tx_commit),
7132 EVENT_PTR(tx_capacity_read),
7133 EVENT_PTR(tx_capacity_write),
7134 EVENT_PTR(tx_conflict),
7135 EVENT_PTR(el_start),
7136 EVENT_PTR(el_abort),
7137 EVENT_PTR(el_commit),
7138 EVENT_PTR(el_capacity_read),
7139 EVENT_PTR(el_capacity_write),
7140 EVENT_PTR(el_conflict),
7141 EVENT_PTR(cycles_t),
7142 EVENT_PTR(cycles_ct),
7143 NULL,
7144 };
7145
7146
7147 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
7148 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
7149
7150 static struct attribute *glc_events_attrs[] = {
7151 EVENT_PTR(mem_ld_hsw),
7152 EVENT_PTR(mem_st_spr),
7153 EVENT_PTR(mem_ld_aux),
7154 NULL,
7155 };
7156
7157 static struct attribute *glc_td_events_attrs[] = {
7158 EVENT_PTR(slots),
7159 EVENT_PTR(td_retiring),
7160 EVENT_PTR(td_bad_spec),
7161 EVENT_PTR(td_fe_bound),
7162 EVENT_PTR(td_be_bound),
7163 EVENT_PTR(td_heavy_ops),
7164 EVENT_PTR(td_br_mispredict),
7165 EVENT_PTR(td_fetch_lat),
7166 EVENT_PTR(td_mem_bound),
7167 NULL,
7168 };
7169
7170 static struct attribute *glc_tsx_events_attrs[] = {
7171 EVENT_PTR(tx_start),
7172 EVENT_PTR(tx_abort),
7173 EVENT_PTR(tx_commit),
7174 EVENT_PTR(tx_capacity_read),
7175 EVENT_PTR(tx_capacity_write),
7176 EVENT_PTR(tx_conflict),
7177 EVENT_PTR(cycles_t),
7178 EVENT_PTR(cycles_ct),
7179 NULL,
7180 };
7181
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)7182 static ssize_t freeze_on_smi_show(struct device *cdev,
7183 struct device_attribute *attr,
7184 char *buf)
7185 {
7186 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
7187 }
7188
7189 static DEFINE_MUTEX(freeze_on_smi_mutex);
7190
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)7191 static ssize_t freeze_on_smi_store(struct device *cdev,
7192 struct device_attribute *attr,
7193 const char *buf, size_t count)
7194 {
7195 unsigned long val;
7196 ssize_t ret;
7197
7198 ret = kstrtoul(buf, 0, &val);
7199 if (ret)
7200 return ret;
7201
7202 if (val > 1)
7203 return -EINVAL;
7204
7205 mutex_lock(&freeze_on_smi_mutex);
7206
7207 if (x86_pmu.attr_freeze_on_smi == val)
7208 goto done;
7209
7210 x86_pmu.attr_freeze_on_smi = val;
7211
7212 cpus_read_lock();
7213 on_each_cpu(flip_smm_bit, &val, 1);
7214 cpus_read_unlock();
7215 done:
7216 mutex_unlock(&freeze_on_smi_mutex);
7217
7218 return count;
7219 }
7220
update_tfa_sched(void * ignored)7221 static void update_tfa_sched(void *ignored)
7222 {
7223 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
7224
7225 /*
7226 * check if PMC3 is used
7227 * and if so force schedule out for all event types all contexts
7228 */
7229 if (test_bit(3, cpuc->active_mask))
7230 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
7231 }
7232
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)7233 static ssize_t show_sysctl_tfa(struct device *cdev,
7234 struct device_attribute *attr,
7235 char *buf)
7236 {
7237 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
7238 }
7239
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)7240 static ssize_t set_sysctl_tfa(struct device *cdev,
7241 struct device_attribute *attr,
7242 const char *buf, size_t count)
7243 {
7244 bool val;
7245 ssize_t ret;
7246
7247 ret = kstrtobool(buf, &val);
7248 if (ret)
7249 return ret;
7250
7251 /* no change */
7252 if (val == allow_tsx_force_abort)
7253 return count;
7254
7255 allow_tsx_force_abort = val;
7256
7257 cpus_read_lock();
7258 on_each_cpu(update_tfa_sched, NULL, 1);
7259 cpus_read_unlock();
7260
7261 return count;
7262 }
7263
7264
7265 static DEVICE_ATTR_RW(freeze_on_smi);
7266
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)7267 static ssize_t branches_show(struct device *cdev,
7268 struct device_attribute *attr,
7269 char *buf)
7270 {
7271 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
7272 }
7273
7274 static DEVICE_ATTR_RO(branches);
7275
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)7276 static ssize_t branch_counter_nr_show(struct device *cdev,
7277 struct device_attribute *attr,
7278 char *buf)
7279 {
7280 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
7281 }
7282
7283 static DEVICE_ATTR_RO(branch_counter_nr);
7284
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)7285 static ssize_t branch_counter_width_show(struct device *cdev,
7286 struct device_attribute *attr,
7287 char *buf)
7288 {
7289 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
7290 }
7291
7292 static DEVICE_ATTR_RO(branch_counter_width);
7293
7294 static struct attribute *lbr_attrs[] = {
7295 &dev_attr_branches.attr,
7296 &dev_attr_branch_counter_nr.attr,
7297 &dev_attr_branch_counter_width.attr,
7298 NULL
7299 };
7300
7301 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)7302 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7303 {
7304 /* branches */
7305 if (i == 0)
7306 return x86_pmu.lbr_nr ? attr->mode : 0;
7307
7308 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
7309 }
7310
7311 static char pmu_name_str[30];
7312
7313 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
7314
7315 static struct attribute *intel_pmu_caps_attrs[] = {
7316 &dev_attr_pmu_name.attr.attr,
7317 NULL
7318 };
7319
7320 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
7321 show_sysctl_tfa,
7322 set_sysctl_tfa);
7323
7324 static struct attribute *intel_pmu_attrs[] = {
7325 &dev_attr_freeze_on_smi.attr,
7326 &dev_attr_allow_tsx_force_abort.attr,
7327 NULL,
7328 };
7329
7330 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)7331 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7332 {
7333 if (attr == &dev_attr_allow_tsx_force_abort.attr)
7334 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
7335
7336 return attr->mode;
7337 }
7338
7339 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)7340 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7341 {
7342 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
7343 }
7344
7345 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)7346 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7347 {
7348 return intel_pmu_has_pebs() ? attr->mode : 0;
7349 }
7350
7351 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)7352 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7353 {
7354 if (attr == &event_attr_mem_ld_aux.attr.attr)
7355 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
7356
7357 return pebs_is_visible(kobj, attr, i);
7358 }
7359
7360 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)7361 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7362 {
7363 return x86_pmu.version >= 2 ? attr->mode : 0;
7364 }
7365
7366 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)7367 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7368 {
7369 /*
7370 * Hide the perf metrics topdown events
7371 * if the feature is not enumerated.
7372 */
7373 if (x86_pmu.num_topdown_events)
7374 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
7375
7376 return attr->mode;
7377 }
7378
7379 PMU_FORMAT_ATTR(acr_mask, "config2:0-63");
7380
7381 static struct attribute *format_acr_attrs[] = {
7382 &format_attr_acr_mask.attr,
7383 NULL
7384 };
7385
7386 static umode_t
acr_is_visible(struct kobject * kobj,struct attribute * attr,int i)7387 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7388 {
7389 struct device *dev = kobj_to_dev(kobj);
7390
7391 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0;
7392 }
7393
7394 static struct attribute_group group_events_td = {
7395 .name = "events",
7396 .is_visible = td_is_visible,
7397 };
7398
7399 static struct attribute_group group_events_mem = {
7400 .name = "events",
7401 .is_visible = mem_is_visible,
7402 };
7403
7404 static struct attribute_group group_events_tsx = {
7405 .name = "events",
7406 .is_visible = tsx_is_visible,
7407 };
7408
7409 static struct attribute_group group_caps_gen = {
7410 .name = "caps",
7411 .attrs = intel_pmu_caps_attrs,
7412 };
7413
7414 static struct attribute_group group_caps_lbr = {
7415 .name = "caps",
7416 .attrs = lbr_attrs,
7417 .is_visible = lbr_is_visible,
7418 };
7419
7420 static struct attribute_group group_format_extra = {
7421 .name = "format",
7422 .is_visible = exra_is_visible,
7423 };
7424
7425 static struct attribute_group group_format_extra_skl = {
7426 .name = "format",
7427 .is_visible = exra_is_visible,
7428 };
7429
7430 static struct attribute_group group_format_evtsel_ext = {
7431 .name = "format",
7432 .attrs = format_evtsel_ext_attrs,
7433 .is_visible = evtsel_ext_is_visible,
7434 };
7435
7436 static struct attribute_group group_format_acr = {
7437 .name = "format",
7438 .attrs = format_acr_attrs,
7439 .is_visible = acr_is_visible,
7440 };
7441
7442 static struct attribute_group group_default = {
7443 .attrs = intel_pmu_attrs,
7444 .is_visible = default_is_visible,
7445 };
7446
7447 static const struct attribute_group *attr_update[] = {
7448 &group_events_td,
7449 &group_events_mem,
7450 &group_events_tsx,
7451 &group_caps_gen,
7452 &group_caps_lbr,
7453 &group_format_extra,
7454 &group_format_extra_skl,
7455 &group_format_evtsel_ext,
7456 &group_format_acr,
7457 &group_default,
7458 NULL,
7459 };
7460
7461 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
7462 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
7463 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
7464 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
7465 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
7466 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
7467 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
7468 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
7469 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
7470
7471 static struct attribute *adl_hybrid_events_attrs[] = {
7472 EVENT_PTR(slots_adl),
7473 EVENT_PTR(td_retiring_adl),
7474 EVENT_PTR(td_bad_spec_adl),
7475 EVENT_PTR(td_fe_bound_adl),
7476 EVENT_PTR(td_be_bound_adl),
7477 EVENT_PTR(td_heavy_ops_adl),
7478 EVENT_PTR(td_br_mis_adl),
7479 EVENT_PTR(td_fetch_lat_adl),
7480 EVENT_PTR(td_mem_bound_adl),
7481 NULL,
7482 };
7483
7484 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
7485 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
7486 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
7487
7488 static struct attribute *lnl_hybrid_events_attrs[] = {
7489 EVENT_PTR(slots_adl),
7490 EVENT_PTR(td_retiring_lnl),
7491 EVENT_PTR(td_bad_spec_adl),
7492 EVENT_PTR(td_fe_bound_lnl),
7493 EVENT_PTR(td_be_bound_lnl),
7494 EVENT_PTR(td_heavy_ops_adl),
7495 EVENT_PTR(td_br_mis_adl),
7496 EVENT_PTR(td_fetch_lat_adl),
7497 EVENT_PTR(td_mem_bound_adl),
7498 NULL
7499 };
7500
7501 /* The event string must be in PMU IDX order. */
7502 EVENT_ATTR_STR_HYBRID(topdown-retiring,
7503 td_retiring_arl_h,
7504 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
7505 hybrid_big_small_tiny);
7506 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
7507 td_bad_spec_arl_h,
7508 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
7509 hybrid_big_small_tiny);
7510 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
7511 td_fe_bound_arl_h,
7512 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
7513 hybrid_big_small_tiny);
7514 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
7515 td_be_bound_arl_h,
7516 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
7517 hybrid_big_small_tiny);
7518
7519 static struct attribute *arl_h_hybrid_events_attrs[] = {
7520 EVENT_PTR(slots_adl),
7521 EVENT_PTR(td_retiring_arl_h),
7522 EVENT_PTR(td_bad_spec_arl_h),
7523 EVENT_PTR(td_fe_bound_arl_h),
7524 EVENT_PTR(td_be_bound_arl_h),
7525 EVENT_PTR(td_heavy_ops_adl),
7526 EVENT_PTR(td_br_mis_adl),
7527 EVENT_PTR(td_fetch_lat_adl),
7528 EVENT_PTR(td_mem_bound_adl),
7529 NULL,
7530 };
7531
7532 /* Must be in IDX order */
7533 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
7534 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
7535 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
7536
7537 static struct attribute *adl_hybrid_mem_attrs[] = {
7538 EVENT_PTR(mem_ld_adl),
7539 EVENT_PTR(mem_st_adl),
7540 EVENT_PTR(mem_ld_aux_adl),
7541 NULL,
7542 };
7543
7544 static struct attribute *mtl_hybrid_mem_attrs[] = {
7545 EVENT_PTR(mem_ld_adl),
7546 EVENT_PTR(mem_st_adl),
7547 NULL
7548 };
7549
7550 EVENT_ATTR_STR_HYBRID(mem-loads,
7551 mem_ld_arl_h,
7552 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
7553 hybrid_big_small_tiny);
7554 EVENT_ATTR_STR_HYBRID(mem-stores,
7555 mem_st_arl_h,
7556 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
7557 hybrid_big_small_tiny);
7558
7559 static struct attribute *arl_h_hybrid_mem_attrs[] = {
7560 EVENT_PTR(mem_ld_arl_h),
7561 EVENT_PTR(mem_st_arl_h),
7562 NULL,
7563 };
7564
7565 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
7566 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
7567 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
7568 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
7569 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
7570 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
7571 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
7572 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
7573
7574 static struct attribute *adl_hybrid_tsx_attrs[] = {
7575 EVENT_PTR(tx_start_adl),
7576 EVENT_PTR(tx_abort_adl),
7577 EVENT_PTR(tx_commit_adl),
7578 EVENT_PTR(tx_capacity_read_adl),
7579 EVENT_PTR(tx_capacity_write_adl),
7580 EVENT_PTR(tx_conflict_adl),
7581 EVENT_PTR(cycles_t_adl),
7582 EVENT_PTR(cycles_ct_adl),
7583 NULL,
7584 };
7585
7586 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
7587 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
7588 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
7589 FORMAT_ATTR_HYBRID(offmodule_rsp, hybrid_big_small_tiny);
7590 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
7591 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
7592
7593 #define ADL_HYBRID_RTM_FORMAT_ATTR \
7594 FORMAT_HYBRID_PTR(in_tx), \
7595 FORMAT_HYBRID_PTR(in_tx_cp)
7596
7597 #define ADL_HYBRID_FORMAT_ATTR \
7598 FORMAT_HYBRID_PTR(offcore_rsp), \
7599 FORMAT_HYBRID_PTR(ldlat), \
7600 FORMAT_HYBRID_PTR(frontend)
7601
7602 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
7603 ADL_HYBRID_RTM_FORMAT_ATTR,
7604 ADL_HYBRID_FORMAT_ATTR,
7605 NULL
7606 };
7607
7608 static struct attribute *adl_hybrid_extra_attr[] = {
7609 ADL_HYBRID_FORMAT_ATTR,
7610 NULL
7611 };
7612
7613 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
7614
7615 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
7616 ADL_HYBRID_RTM_FORMAT_ATTR,
7617 ADL_HYBRID_FORMAT_ATTR,
7618 FORMAT_HYBRID_PTR(snoop_rsp),
7619 NULL
7620 };
7621
7622 static struct attribute *mtl_hybrid_extra_attr[] = {
7623 ADL_HYBRID_FORMAT_ATTR,
7624 FORMAT_HYBRID_PTR(snoop_rsp),
7625 NULL
7626 };
7627
7628 static struct attribute *nvl_hybrid_extra_attr_rtm[] = {
7629 ADL_HYBRID_RTM_FORMAT_ATTR,
7630 FORMAT_HYBRID_PTR(offmodule_rsp),
7631 FORMAT_HYBRID_PTR(ldlat),
7632 FORMAT_HYBRID_PTR(frontend),
7633 FORMAT_HYBRID_PTR(snoop_rsp),
7634 NULL
7635 };
7636
7637 static struct attribute *nvl_hybrid_extra_attr[] = {
7638 FORMAT_HYBRID_PTR(offmodule_rsp),
7639 FORMAT_HYBRID_PTR(ldlat),
7640 FORMAT_HYBRID_PTR(frontend),
7641 FORMAT_HYBRID_PTR(snoop_rsp),
7642 NULL
7643 };
7644
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)7645 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
7646 {
7647 struct device *dev = kobj_to_dev(kobj);
7648 struct x86_hybrid_pmu *pmu =
7649 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7650 struct perf_pmu_events_hybrid_attr *pmu_attr =
7651 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
7652
7653 return pmu->pmu_type & pmu_attr->pmu_type;
7654 }
7655
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)7656 static umode_t hybrid_events_is_visible(struct kobject *kobj,
7657 struct attribute *attr, int i)
7658 {
7659 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
7660 }
7661
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)7662 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
7663 {
7664 int cpu = cpumask_first(&pmu->supported_cpus);
7665
7666 return (cpu >= nr_cpu_ids) ? -1 : cpu;
7667 }
7668
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)7669 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
7670 struct attribute *attr, int i)
7671 {
7672 struct device *dev = kobj_to_dev(kobj);
7673 struct x86_hybrid_pmu *pmu =
7674 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7675 int cpu = hybrid_find_supported_cpu(pmu);
7676
7677 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
7678 }
7679
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)7680 static umode_t hybrid_format_is_visible(struct kobject *kobj,
7681 struct attribute *attr, int i)
7682 {
7683 struct device *dev = kobj_to_dev(kobj);
7684 struct x86_hybrid_pmu *pmu =
7685 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7686 struct perf_pmu_format_hybrid_attr *pmu_attr =
7687 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
7688 int cpu = hybrid_find_supported_cpu(pmu);
7689
7690 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
7691 }
7692
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)7693 static umode_t hybrid_td_is_visible(struct kobject *kobj,
7694 struct attribute *attr, int i)
7695 {
7696 struct device *dev = kobj_to_dev(kobj);
7697 struct x86_hybrid_pmu *pmu =
7698 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7699
7700 if (!is_attr_for_this_pmu(kobj, attr))
7701 return 0;
7702
7703
7704 /* Only the big core supports perf metrics */
7705 if (pmu->pmu_type == hybrid_big)
7706 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
7707
7708 return attr->mode;
7709 }
7710
7711 static struct attribute_group hybrid_group_events_td = {
7712 .name = "events",
7713 .is_visible = hybrid_td_is_visible,
7714 };
7715
7716 static struct attribute_group hybrid_group_events_mem = {
7717 .name = "events",
7718 .is_visible = hybrid_events_is_visible,
7719 };
7720
7721 static struct attribute_group hybrid_group_events_tsx = {
7722 .name = "events",
7723 .is_visible = hybrid_tsx_is_visible,
7724 };
7725
7726 static struct attribute_group hybrid_group_format_extra = {
7727 .name = "format",
7728 .is_visible = hybrid_format_is_visible,
7729 };
7730
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)7731 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
7732 struct device_attribute *attr,
7733 char *buf)
7734 {
7735 struct x86_hybrid_pmu *pmu =
7736 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7737
7738 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(&pmu->supported_cpus));
7739 }
7740
7741 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
7742 static struct attribute *intel_hybrid_cpus_attrs[] = {
7743 &dev_attr_cpus.attr,
7744 NULL,
7745 };
7746
7747 static struct attribute_group hybrid_group_cpus = {
7748 .attrs = intel_hybrid_cpus_attrs,
7749 };
7750
7751 static const struct attribute_group *hybrid_attr_update[] = {
7752 &hybrid_group_events_td,
7753 &hybrid_group_events_mem,
7754 &hybrid_group_events_tsx,
7755 &group_caps_gen,
7756 &group_caps_lbr,
7757 &hybrid_group_format_extra,
7758 &group_format_evtsel_ext,
7759 &group_format_acr,
7760 &group_default,
7761 &hybrid_group_cpus,
7762 NULL,
7763 };
7764
7765 static struct attribute *empty_attrs;
7766
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)7767 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
7768 u64 cntr_mask,
7769 u64 fixed_cntr_mask,
7770 u64 intel_ctrl)
7771 {
7772 struct event_constraint *c;
7773
7774 if (!event_constraints)
7775 return;
7776
7777 /*
7778 * event on fixed counter2 (REF_CYCLES) only works on this
7779 * counter, so do not extend mask to generic counters
7780 */
7781 for_each_event_constraint(c, event_constraints) {
7782 /*
7783 * Don't extend the topdown slots and metrics
7784 * events to the generic counters.
7785 */
7786 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
7787 /*
7788 * Disable topdown slots and metrics events,
7789 * if slots event is not in CPUID.
7790 */
7791 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
7792 c->idxmsk64 = 0;
7793 c->weight = hweight64(c->idxmsk64);
7794 continue;
7795 }
7796
7797 if (c->cmask == FIXED_EVENT_FLAGS) {
7798 /* Disabled fixed counters which are not in CPUID */
7799 c->idxmsk64 &= intel_ctrl;
7800
7801 /*
7802 * Don't extend the pseudo-encoding to the
7803 * generic counters
7804 */
7805 if (!use_fixed_pseudo_encoding(c->code))
7806 c->idxmsk64 |= cntr_mask;
7807 }
7808 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
7809 c->weight = hweight64(c->idxmsk64);
7810 }
7811 }
7812
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)7813 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
7814 {
7815 struct extra_reg *er;
7816
7817 /*
7818 * Access extra MSR may cause #GP under certain circumstances.
7819 * E.g. KVM doesn't support offcore event
7820 * Check all extra_regs here.
7821 */
7822 if (!extra_regs)
7823 return;
7824
7825 for (er = extra_regs; er->msr; er++) {
7826 er->extra_msr_access = check_msr(er->msr, 0x11UL);
7827 /* Disable LBR select mapping */
7828 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
7829 x86_pmu.lbr_sel_map = NULL;
7830 }
7831 }
7832
intel_pmu_v6_addr_offset(int index,bool eventsel)7833 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
7834 {
7835 return MSR_IA32_PMC_V6_STEP * index;
7836 }
7837
7838 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
7839 { hybrid_small, "cpu_atom" },
7840 { hybrid_big, "cpu_core" },
7841 { hybrid_tiny, "cpu_lowpower" },
7842 };
7843
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)7844 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
7845 {
7846 unsigned long pmus_mask = pmus;
7847 struct x86_hybrid_pmu *pmu;
7848 int idx = 0, bit;
7849
7850 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
7851 x86_pmu.hybrid_pmu = kzalloc_objs(struct x86_hybrid_pmu,
7852 x86_pmu.num_hybrid_pmus);
7853 if (!x86_pmu.hybrid_pmu) {
7854 x86_pmu.num_hybrid_pmus = 0;
7855 return -ENOMEM;
7856 }
7857
7858 static_branch_enable(&perf_is_hybrid);
7859 x86_pmu.filter = intel_pmu_filter;
7860
7861 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
7862 pmu = &x86_pmu.hybrid_pmu[idx++];
7863 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
7864 pmu->name = intel_hybrid_pmu_type_map[bit].name;
7865
7866 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7867 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7868 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7869 pmu->config_mask = X86_RAW_EVENT_MASK;
7870 pmu->unconstrained = (struct event_constraint)
7871 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7872 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7873
7874 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
7875 if (pmu->pmu_type & hybrid_small_tiny) {
7876 pmu->intel_cap.perf_metrics = 0;
7877 pmu->mid_ack = true;
7878 } else if (pmu->pmu_type & hybrid_big) {
7879 pmu->intel_cap.perf_metrics = 1;
7880 pmu->late_ack = true;
7881 }
7882 }
7883
7884 return 0;
7885 }
7886
intel_pmu_ref_cycles_ext(void)7887 static __always_inline void intel_pmu_ref_cycles_ext(void)
7888 {
7889 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
7890 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
7891 }
7892
intel_pmu_init_glc(struct pmu * pmu)7893 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
7894 {
7895 x86_pmu.late_ack = true;
7896 x86_pmu.limit_period = glc_limit_period;
7897 x86_pmu.pebs_aliases = NULL;
7898 x86_pmu.pebs_prec_dist = true;
7899 x86_pmu.pebs_block = true;
7900 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7901 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7902 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7903 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7904 x86_pmu.lbr_pt_coexist = true;
7905 x86_pmu.num_topdown_events = 8;
7906 static_call_update(intel_pmu_update_topdown_event,
7907 &icl_update_topdown_event);
7908 static_call_update(intel_pmu_set_topdown_event_period,
7909 &icl_set_topdown_event_period);
7910
7911 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7912 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7913 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
7914 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
7915
7916 intel_pmu_ref_cycles_ext();
7917 }
7918
intel_pmu_init_glc_hybrid(struct pmu * pmu)7919 static __always_inline void intel_pmu_init_glc_hybrid(struct pmu *pmu)
7920 {
7921 intel_pmu_init_glc(pmu);
7922
7923 /* ADL has different extra MSR values from Server for the L3 or node OCR/OMR events. */
7924 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7925 memcpy(hybrid_var(pmu, hw_cache_extra_regs), adl_glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7926 }
7927
intel_pmu_init_grt(struct pmu * pmu)7928 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
7929 {
7930 x86_pmu.mid_ack = true;
7931 x86_pmu.limit_period = glc_limit_period;
7932 x86_pmu.pebs_aliases = NULL;
7933 x86_pmu.pebs_prec_dist = true;
7934 x86_pmu.pebs_block = true;
7935 x86_pmu.lbr_pt_coexist = true;
7936 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7937 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7938
7939 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7940 memcpy(hybrid_var(pmu, hw_cache_extra_regs), grt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7941 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7942 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
7943 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
7944 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
7945
7946 intel_pmu_ref_cycles_ext();
7947 }
7948
intel_pmu_init_cmt(struct pmu * pmu)7949 static __always_inline void intel_pmu_init_cmt(struct pmu *pmu)
7950 {
7951 intel_pmu_init_grt(pmu);
7952 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7953 cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7954 hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;
7955 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
7956 }
7957
intel_pmu_init_lnc(struct pmu * pmu)7958 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
7959 {
7960 intel_pmu_init_glc(pmu);
7961 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
7962 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
7963 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
7964
7965 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7966 memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7967 }
7968
intel_pmu_init_pnc(struct pmu * pmu)7969 static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
7970 {
7971 intel_pmu_init_glc(pmu);
7972 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7973 x86_pmu.flags |= PMU_FL_HAS_OMR;
7974 memcpy(hybrid_var(pmu, hw_cache_event_ids),
7975 pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7976 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7977 pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7978 hybrid(pmu, event_constraints) = intel_pnc_event_constraints;
7979 hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;
7980 hybrid(pmu, extra_regs) = intel_pnc_extra_regs;
7981 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7982 }
7983
intel_pmu_init_cyc(struct pmu * pmu)7984 static __always_inline void intel_pmu_init_cyc(struct pmu *pmu)
7985 {
7986 intel_pmu_init_pnc(pmu);
7987 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7988 cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7989 }
7990
intel_pmu_init_skt(struct pmu * pmu)7991 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
7992 {
7993 intel_pmu_init_cmt(pmu);
7994 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
7995 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7996 skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7997 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7998 }
7999
8000 /* Hybrid client variant. */
intel_pmu_init_dkt_hybrid(struct pmu * pmu)8001 static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
8002 {
8003 intel_pmu_init_skt(pmu);
8004 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
8005 }
8006
8007 /*
8008 * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR
8009 * events require different extra MSR values. Keep a separate init
8010 * function for the non-hybrid server variant.
8011 */
intel_pmu_init_dkt(struct pmu * pmu)8012 static __always_inline void intel_pmu_init_dkt(struct pmu *pmu)
8013 {
8014 intel_pmu_init_dkt_hybrid(pmu);
8015 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
8016 dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8017 }
8018
intel_pmu_init_arw(struct pmu * pmu)8019 static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
8020 {
8021 intel_pmu_init_grt(pmu);
8022 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
8023 x86_pmu.flags |= PMU_FL_HAS_OMR;
8024 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
8025 arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8026 hybrid(pmu, event_constraints) = intel_arw_event_constraints;
8027 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
8028 hybrid(pmu, extra_regs) = intel_arw_extra_regs;
8029 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
8030 }
8031
intel_pmu_init(void)8032 __init int intel_pmu_init(void)
8033 {
8034 struct attribute **extra_skl_attr = &empty_attrs;
8035 struct attribute **extra_attr = &empty_attrs;
8036 struct attribute **td_attr = &empty_attrs;
8037 struct attribute **mem_attr = &empty_attrs;
8038 struct attribute **tsx_attr = &empty_attrs;
8039 struct x86_hybrid_pmu *pmu;
8040 unsigned int fixed_mask;
8041 union cpuid10_edx edx;
8042 union cpuid10_eax eax;
8043 union cpuid10_ebx ebx;
8044 int version, i, ret;
8045 bool pmem = false;
8046 char *name;
8047
8048 /* Architectural Perfmon was introduced starting with Core "Yonah" */
8049 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
8050 switch (boot_cpu_data.x86) {
8051 case 6:
8052 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH)
8053 return p6_pmu_init();
8054 break;
8055 case 11:
8056 return knc_pmu_init();
8057 case 15:
8058 return p4_pmu_init();
8059 }
8060
8061 pr_cont("unsupported CPU family %d model %d ",
8062 boot_cpu_data.x86, boot_cpu_data.x86_model);
8063 return -ENODEV;
8064 }
8065
8066 /*
8067 * Check whether the Architectural PerfMon supports
8068 * Branch Misses Retired hw_event or not.
8069 */
8070 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
8071 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
8072 return -ENODEV;
8073
8074 version = eax.split.version_id;
8075 if (version < 2)
8076 x86_pmu = core_pmu;
8077 else
8078 x86_pmu = intel_pmu;
8079
8080 x86_pmu.version = version;
8081 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
8082 x86_pmu.cntval_bits = eax.split.bit_width;
8083 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
8084
8085 x86_pmu.events_maskl = ebx.full;
8086 x86_pmu.events_mask_len = eax.split.mask_length;
8087
8088 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
8089 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
8090 x86_pmu.config_mask = X86_RAW_EVENT_MASK;
8091
8092 /*
8093 * Quirk: v2 perfmon does not report fixed-purpose events, so
8094 * assume at least 3 events, when not running in a hypervisor:
8095 */
8096 if (version > 1 && version < 5) {
8097 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
8098
8099 x86_pmu.fixed_cntr_mask64 =
8100 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
8101 } else if (version >= 5)
8102 x86_pmu.fixed_cntr_mask64 = fixed_mask;
8103
8104 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8105 u64 capabilities;
8106
8107 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities);
8108 x86_pmu.intel_cap.capabilities = capabilities;
8109 }
8110
8111 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
8112 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
8113 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
8114 }
8115
8116 intel_pebs_init();
8117
8118 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
8119
8120 /* The perf side of core PMU is ready to support the mediated vPMU. */
8121 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
8122
8123 /*
8124 * Many features on and after V6 require dynamic constraint,
8125 * e.g., Arch PEBS, ACR.
8126 */
8127 if (version >= 6) {
8128 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT;
8129 x86_pmu.late_setup = intel_pmu_late_setup;
8130 }
8131
8132 /*
8133 * Install the hw-cache-events table:
8134 */
8135 switch (boot_cpu_data.x86_vfm) {
8136 case INTEL_CORE_YONAH:
8137 pr_cont("Core events, ");
8138 name = "core";
8139 break;
8140
8141 case INTEL_CORE2_MEROM:
8142 x86_add_quirk(intel_clovertown_quirk);
8143 fallthrough;
8144
8145 case INTEL_CORE2_MEROM_L:
8146 case INTEL_CORE2_PENRYN:
8147 case INTEL_CORE2_DUNNINGTON:
8148 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
8149 sizeof(hw_cache_event_ids));
8150
8151 intel_pmu_lbr_init_core();
8152
8153 x86_pmu.event_constraints = intel_core2_event_constraints;
8154 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
8155 pr_cont("Core2 events, ");
8156 name = "core2";
8157 break;
8158
8159 case INTEL_NEHALEM:
8160 case INTEL_NEHALEM_EP:
8161 case INTEL_NEHALEM_EX:
8162 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
8163 sizeof(hw_cache_event_ids));
8164 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
8165 sizeof(hw_cache_extra_regs));
8166
8167 intel_pmu_lbr_init_nhm();
8168
8169 x86_pmu.event_constraints = intel_nehalem_event_constraints;
8170 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
8171 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
8172 x86_pmu.extra_regs = intel_nehalem_extra_regs;
8173 x86_pmu.limit_period = nhm_limit_period;
8174
8175 mem_attr = nhm_mem_events_attrs;
8176
8177 /* UOPS_ISSUED.STALLED_CYCLES */
8178 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8179 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8180 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8181 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8182 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
8183
8184 intel_pmu_pebs_data_source_nhm();
8185 x86_add_quirk(intel_nehalem_quirk);
8186 x86_pmu.pebs_no_tlb = 1;
8187 extra_attr = nhm_format_attr;
8188
8189 pr_cont("Nehalem events, ");
8190 name = "nehalem";
8191 break;
8192
8193 case INTEL_ATOM_BONNELL:
8194 case INTEL_ATOM_BONNELL_MID:
8195 case INTEL_ATOM_SALTWELL:
8196 case INTEL_ATOM_SALTWELL_MID:
8197 case INTEL_ATOM_SALTWELL_TABLET:
8198 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
8199 sizeof(hw_cache_event_ids));
8200
8201 intel_pmu_lbr_init_atom();
8202
8203 x86_pmu.event_constraints = intel_gen_event_constraints;
8204 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
8205 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
8206 pr_cont("Atom events, ");
8207 name = "bonnell";
8208 break;
8209
8210 case INTEL_ATOM_SILVERMONT:
8211 case INTEL_ATOM_SILVERMONT_D:
8212 case INTEL_ATOM_SILVERMONT_MID:
8213 case INTEL_ATOM_AIRMONT:
8214 case INTEL_ATOM_AIRMONT_NP:
8215 case INTEL_ATOM_SILVERMONT_MID2:
8216 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
8217 sizeof(hw_cache_event_ids));
8218 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
8219 sizeof(hw_cache_extra_regs));
8220
8221 intel_pmu_lbr_init_slm();
8222
8223 x86_pmu.event_constraints = intel_slm_event_constraints;
8224 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
8225 x86_pmu.extra_regs = intel_slm_extra_regs;
8226 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8227 td_attr = slm_events_attrs;
8228 extra_attr = slm_format_attr;
8229 pr_cont("Silvermont events, ");
8230 name = "silvermont";
8231 break;
8232
8233 case INTEL_ATOM_GOLDMONT:
8234 case INTEL_ATOM_GOLDMONT_D:
8235 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
8236 sizeof(hw_cache_event_ids));
8237 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
8238 sizeof(hw_cache_extra_regs));
8239
8240 intel_pmu_lbr_init_skl();
8241
8242 x86_pmu.event_constraints = intel_slm_event_constraints;
8243 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
8244 x86_pmu.extra_regs = intel_glm_extra_regs;
8245 /*
8246 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8247 * for precise cycles.
8248 * :pp is identical to :ppp
8249 */
8250 x86_pmu.pebs_aliases = NULL;
8251 x86_pmu.pebs_prec_dist = true;
8252 x86_pmu.lbr_pt_coexist = true;
8253 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8254 td_attr = glm_events_attrs;
8255 extra_attr = slm_format_attr;
8256 pr_cont("Goldmont events, ");
8257 name = "goldmont";
8258 break;
8259
8260 case INTEL_ATOM_GOLDMONT_PLUS:
8261 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
8262 sizeof(hw_cache_event_ids));
8263 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
8264 sizeof(hw_cache_extra_regs));
8265
8266 intel_pmu_lbr_init_skl();
8267
8268 x86_pmu.event_constraints = intel_slm_event_constraints;
8269 x86_pmu.extra_regs = intel_glm_extra_regs;
8270 /*
8271 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8272 * for precise cycles.
8273 */
8274 x86_pmu.pebs_aliases = NULL;
8275 x86_pmu.pebs_prec_dist = true;
8276 x86_pmu.lbr_pt_coexist = true;
8277 x86_pmu.pebs_capable = ~0ULL;
8278 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8279 x86_pmu.flags |= PMU_FL_PEBS_ALL;
8280 x86_pmu.get_event_constraints = glp_get_event_constraints;
8281 td_attr = glm_events_attrs;
8282 /* Goldmont Plus has 4-wide pipeline */
8283 event_attr_td_total_slots_scale_glm.event_str = "4";
8284 extra_attr = slm_format_attr;
8285 pr_cont("Goldmont plus events, ");
8286 name = "goldmont_plus";
8287 break;
8288
8289 case INTEL_ATOM_TREMONT_D:
8290 case INTEL_ATOM_TREMONT:
8291 case INTEL_ATOM_TREMONT_L:
8292 x86_pmu.late_ack = true;
8293 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
8294 sizeof(hw_cache_event_ids));
8295 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
8296 sizeof(hw_cache_extra_regs));
8297 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8298
8299 intel_pmu_lbr_init_skl();
8300
8301 x86_pmu.event_constraints = intel_slm_event_constraints;
8302 x86_pmu.extra_regs = intel_tnt_extra_regs;
8303 /*
8304 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8305 * for precise cycles.
8306 */
8307 x86_pmu.pebs_aliases = NULL;
8308 x86_pmu.pebs_prec_dist = true;
8309 x86_pmu.lbr_pt_coexist = true;
8310 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8311 x86_pmu.get_event_constraints = tnt_get_event_constraints;
8312 td_attr = tnt_events_attrs;
8313 extra_attr = slm_format_attr;
8314 pr_cont("Tremont events, ");
8315 name = "Tremont";
8316 break;
8317
8318 case INTEL_ATOM_GRACEMONT:
8319 intel_pmu_init_grt(NULL);
8320 intel_pmu_pebs_data_source_grt();
8321 x86_pmu.pebs_latency_data = grt_latency_data;
8322 x86_pmu.get_event_constraints = tnt_get_event_constraints;
8323 td_attr = tnt_events_attrs;
8324 mem_attr = grt_mem_attrs;
8325 extra_attr = nhm_format_attr;
8326 pr_cont("Gracemont events, ");
8327 name = "gracemont";
8328 break;
8329
8330 case INTEL_ATOM_CRESTMONT:
8331 case INTEL_ATOM_CRESTMONT_X:
8332 intel_pmu_init_cmt(NULL);
8333 intel_pmu_pebs_data_source_cmt();
8334 x86_pmu.pebs_latency_data = cmt_latency_data;
8335 x86_pmu.get_event_constraints = cmt_get_event_constraints;
8336 td_attr = cmt_events_attrs;
8337 mem_attr = grt_mem_attrs;
8338 extra_attr = cmt_format_attr;
8339 pr_cont("Crestmont events, ");
8340 name = "crestmont";
8341 break;
8342
8343 case INTEL_ATOM_DARKMONT_X:
8344 intel_pmu_init_dkt(NULL);
8345 intel_pmu_pebs_data_source_cmt();
8346 x86_pmu.pebs_latency_data = cmt_latency_data;
8347 x86_pmu.get_event_constraints = cmt_get_event_constraints;
8348 td_attr = skt_events_attrs;
8349 mem_attr = grt_mem_attrs;
8350 extra_attr = cmt_format_attr;
8351 pr_cont("Darkmont events, ");
8352 name = "darkmont";
8353 break;
8354
8355 case INTEL_WESTMERE:
8356 case INTEL_WESTMERE_EP:
8357 case INTEL_WESTMERE_EX:
8358 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
8359 sizeof(hw_cache_event_ids));
8360 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
8361 sizeof(hw_cache_extra_regs));
8362
8363 intel_pmu_lbr_init_nhm();
8364
8365 x86_pmu.event_constraints = intel_westmere_event_constraints;
8366 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
8367 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
8368 x86_pmu.extra_regs = intel_westmere_extra_regs;
8369 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8370
8371 mem_attr = nhm_mem_events_attrs;
8372
8373 /* UOPS_ISSUED.STALLED_CYCLES */
8374 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8375 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8376 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8377 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8378 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
8379
8380 intel_pmu_pebs_data_source_nhm();
8381 extra_attr = nhm_format_attr;
8382 pr_cont("Westmere events, ");
8383 name = "westmere";
8384 break;
8385
8386 case INTEL_SANDYBRIDGE:
8387 case INTEL_SANDYBRIDGE_X:
8388 x86_add_quirk(intel_sandybridge_quirk);
8389 x86_add_quirk(intel_ht_bug);
8390 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
8391 sizeof(hw_cache_event_ids));
8392 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
8393 sizeof(hw_cache_extra_regs));
8394
8395 intel_pmu_lbr_init_snb();
8396
8397 x86_pmu.event_constraints = intel_snb_event_constraints;
8398 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
8399 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
8400 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
8401 x86_pmu.extra_regs = intel_snbep_extra_regs;
8402 else
8403 x86_pmu.extra_regs = intel_snb_extra_regs;
8404
8405
8406 /* all extra regs are per-cpu when HT is on */
8407 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8408 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8409
8410 td_attr = snb_events_attrs;
8411 mem_attr = snb_mem_events_attrs;
8412
8413 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
8414 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8415 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8416 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
8417 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8418 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
8419
8420 extra_attr = nhm_format_attr;
8421
8422 pr_cont("SandyBridge events, ");
8423 name = "sandybridge";
8424 break;
8425
8426 case INTEL_IVYBRIDGE:
8427 case INTEL_IVYBRIDGE_X:
8428 x86_add_quirk(intel_ht_bug);
8429 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
8430 sizeof(hw_cache_event_ids));
8431 /* dTLB-load-misses on IVB is different than SNB */
8432 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
8433
8434 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
8435 sizeof(hw_cache_extra_regs));
8436
8437 intel_pmu_lbr_init_snb();
8438
8439 x86_pmu.event_constraints = intel_ivb_event_constraints;
8440 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
8441 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8442 x86_pmu.pebs_prec_dist = true;
8443 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
8444 x86_pmu.extra_regs = intel_snbep_extra_regs;
8445 else
8446 x86_pmu.extra_regs = intel_snb_extra_regs;
8447 /* all extra regs are per-cpu when HT is on */
8448 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8449 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8450
8451 td_attr = snb_events_attrs;
8452 mem_attr = snb_mem_events_attrs;
8453
8454 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
8455 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8456 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8457
8458 extra_attr = nhm_format_attr;
8459
8460 pr_cont("IvyBridge events, ");
8461 name = "ivybridge";
8462 break;
8463
8464
8465 case INTEL_HASWELL:
8466 case INTEL_HASWELL_X:
8467 case INTEL_HASWELL_L:
8468 case INTEL_HASWELL_G:
8469 x86_add_quirk(intel_ht_bug);
8470 x86_add_quirk(intel_pebs_isolation_quirk);
8471 x86_pmu.late_ack = true;
8472 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8473 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8474
8475 intel_pmu_lbr_init_hsw();
8476
8477 x86_pmu.event_constraints = intel_hsw_event_constraints;
8478 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
8479 x86_pmu.extra_regs = intel_snbep_extra_regs;
8480 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8481 x86_pmu.pebs_prec_dist = true;
8482 /* all extra regs are per-cpu when HT is on */
8483 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8484 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8485
8486 x86_pmu.hw_config = hsw_hw_config;
8487 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8488 x86_pmu.limit_period = hsw_limit_period;
8489 x86_pmu.lbr_double_abort = true;
8490 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8491 hsw_format_attr : nhm_format_attr;
8492 td_attr = hsw_events_attrs;
8493 mem_attr = hsw_mem_events_attrs;
8494 tsx_attr = hsw_tsx_events_attrs;
8495 pr_cont("Haswell events, ");
8496 name = "haswell";
8497 break;
8498
8499 case INTEL_BROADWELL:
8500 case INTEL_BROADWELL_D:
8501 case INTEL_BROADWELL_G:
8502 case INTEL_BROADWELL_X:
8503 x86_add_quirk(intel_pebs_isolation_quirk);
8504 x86_pmu.late_ack = true;
8505 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8506 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8507
8508 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
8509 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
8510 BDW_L3_MISS|HSW_SNOOP_DRAM;
8511 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
8512 HSW_SNOOP_DRAM;
8513 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
8514 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
8515 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
8516 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
8517
8518 intel_pmu_lbr_init_hsw();
8519
8520 x86_pmu.event_constraints = intel_bdw_event_constraints;
8521 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
8522 x86_pmu.extra_regs = intel_snbep_extra_regs;
8523 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8524 x86_pmu.pebs_prec_dist = true;
8525 /* all extra regs are per-cpu when HT is on */
8526 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8527 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8528
8529 x86_pmu.hw_config = hsw_hw_config;
8530 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8531 x86_pmu.limit_period = bdw_limit_period;
8532 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8533 hsw_format_attr : nhm_format_attr;
8534 td_attr = hsw_events_attrs;
8535 mem_attr = hsw_mem_events_attrs;
8536 tsx_attr = hsw_tsx_events_attrs;
8537 pr_cont("Broadwell events, ");
8538 name = "broadwell";
8539 break;
8540
8541 case INTEL_XEON_PHI_KNL:
8542 case INTEL_XEON_PHI_KNM:
8543 memcpy(hw_cache_event_ids,
8544 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8545 memcpy(hw_cache_extra_regs,
8546 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8547 intel_pmu_lbr_init_knl();
8548
8549 x86_pmu.event_constraints = intel_slm_event_constraints;
8550 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
8551 x86_pmu.extra_regs = intel_knl_extra_regs;
8552
8553 /* all extra regs are per-cpu when HT is on */
8554 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8555 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8556 extra_attr = slm_format_attr;
8557 pr_cont("Knights Landing/Mill events, ");
8558 name = "knights-landing";
8559 break;
8560
8561 case INTEL_SKYLAKE_X:
8562 pmem = true;
8563 fallthrough;
8564 case INTEL_SKYLAKE_L:
8565 case INTEL_SKYLAKE:
8566 case INTEL_KABYLAKE_L:
8567 case INTEL_KABYLAKE:
8568 case INTEL_COMETLAKE_L:
8569 case INTEL_COMETLAKE:
8570 x86_add_quirk(intel_pebs_isolation_quirk);
8571 x86_pmu.late_ack = true;
8572 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8573 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8574 intel_pmu_lbr_init_skl();
8575
8576 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
8577 event_attr_td_recovery_bubbles.event_str_noht =
8578 "event=0xd,umask=0x1,cmask=1";
8579 event_attr_td_recovery_bubbles.event_str_ht =
8580 "event=0xd,umask=0x1,cmask=1,any=1";
8581
8582 x86_pmu.event_constraints = intel_skl_event_constraints;
8583 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
8584 x86_pmu.extra_regs = intel_skl_extra_regs;
8585 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
8586 x86_pmu.pebs_prec_dist = true;
8587 /* all extra regs are per-cpu when HT is on */
8588 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8589 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8590
8591 x86_pmu.hw_config = hsw_hw_config;
8592 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8593 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8594 hsw_format_attr : nhm_format_attr;
8595 extra_skl_attr = skl_format_attr;
8596 td_attr = hsw_events_attrs;
8597 mem_attr = hsw_mem_events_attrs;
8598 tsx_attr = hsw_tsx_events_attrs;
8599 intel_pmu_pebs_data_source_skl(pmem);
8600
8601 /*
8602 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
8603 * TSX force abort hooks are not required on these systems. Only deploy
8604 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
8605 */
8606 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
8607 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
8608 x86_pmu.flags |= PMU_FL_TFA;
8609 x86_pmu.get_event_constraints = tfa_get_event_constraints;
8610 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
8611 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
8612 }
8613
8614 pr_cont("Skylake events, ");
8615 name = "skylake";
8616 break;
8617
8618 case INTEL_ICELAKE_X:
8619 case INTEL_ICELAKE_D:
8620 memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8621 x86_pmu.pebs_ept = 1;
8622 pmem = true;
8623 goto snc_common;
8624 case INTEL_ICELAKE_L:
8625 case INTEL_ICELAKE:
8626 case INTEL_TIGERLAKE_L:
8627 case INTEL_TIGERLAKE:
8628 case INTEL_ROCKETLAKE:
8629 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8630 snc_common:
8631 x86_pmu.late_ack = true;
8632 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8633 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8634 intel_pmu_lbr_init_skl();
8635
8636 x86_pmu.event_constraints = intel_icl_event_constraints;
8637 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
8638 x86_pmu.extra_regs = intel_icl_extra_regs;
8639 x86_pmu.pebs_aliases = NULL;
8640 x86_pmu.pebs_prec_dist = true;
8641 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8642 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8643
8644 x86_pmu.hw_config = hsw_hw_config;
8645 x86_pmu.get_event_constraints = icl_get_event_constraints;
8646 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8647 hsw_format_attr : nhm_format_attr;
8648 extra_skl_attr = skl_format_attr;
8649 mem_attr = icl_events_attrs;
8650 td_attr = icl_td_events_attrs;
8651 tsx_attr = icl_tsx_events_attrs;
8652 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
8653 x86_pmu.lbr_pt_coexist = true;
8654 intel_pmu_pebs_data_source_skl(pmem);
8655 x86_pmu.num_topdown_events = 4;
8656 static_call_update(intel_pmu_update_topdown_event,
8657 &icl_update_topdown_event);
8658 static_call_update(intel_pmu_set_topdown_event_period,
8659 &icl_set_topdown_event_period);
8660 pr_cont("Icelake events, ");
8661 name = "icelake";
8662 break;
8663
8664 case INTEL_SAPPHIRERAPIDS_X:
8665 case INTEL_EMERALDRAPIDS_X:
8666 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
8667 x86_pmu.extra_regs = intel_glc_extra_regs;
8668 pr_cont("Sapphire Rapids events, ");
8669 name = "sapphire_rapids";
8670 goto glc_common;
8671
8672 case INTEL_GRANITERAPIDS_X:
8673 case INTEL_GRANITERAPIDS_D:
8674 x86_pmu.extra_regs = intel_rwc_extra_regs;
8675 pr_cont("Granite Rapids events, ");
8676 name = "granite_rapids";
8677 goto glc_common;
8678
8679 case INTEL_DIAMONDRAPIDS_X:
8680 intel_pmu_init_pnc(NULL);
8681 x86_pmu.pebs_latency_data = pnc_latency_data;
8682 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8683 pnc_format_attr_rtm : pnc_format_attr;
8684
8685 pr_cont("Panthercove events, ");
8686 name = "panthercove";
8687 goto glc_base;
8688
8689 glc_common:
8690 intel_pmu_init_glc(NULL);
8691 intel_pmu_pebs_data_source_skl(true);
8692 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8693 hsw_format_attr : nhm_format_attr;
8694 glc_base:
8695 x86_pmu.pebs_ept = 1;
8696 x86_pmu.hw_config = hsw_hw_config;
8697 x86_pmu.get_event_constraints = glc_get_event_constraints;
8698 extra_skl_attr = skl_format_attr;
8699 mem_attr = glc_events_attrs;
8700 td_attr = glc_td_events_attrs;
8701 tsx_attr = glc_tsx_events_attrs;
8702 break;
8703
8704 case INTEL_ALDERLAKE:
8705 case INTEL_ALDERLAKE_L:
8706 case INTEL_RAPTORLAKE:
8707 case INTEL_RAPTORLAKE_P:
8708 case INTEL_RAPTORLAKE_S:
8709 /*
8710 * Alder Lake has 2 types of CPU, core and atom.
8711 *
8712 * Initialize the common PerfMon capabilities here.
8713 */
8714 ret = intel_pmu_init_hybrid(hybrid_big_small);
8715 if (ret)
8716 return ret;
8717
8718 x86_pmu.pebs_latency_data = grt_latency_data;
8719 x86_pmu.get_event_constraints = adl_get_event_constraints;
8720 x86_pmu.hw_config = adl_hw_config;
8721 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
8722
8723 td_attr = adl_hybrid_events_attrs;
8724 mem_attr = adl_hybrid_mem_attrs;
8725 tsx_attr = adl_hybrid_tsx_attrs;
8726 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8727 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
8728
8729 /* Initialize big core specific PerfMon capabilities.*/
8730 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8731 intel_pmu_init_glc_hybrid(&pmu->pmu);
8732 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
8733 pmu->cntr_mask64 <<= 2;
8734 pmu->cntr_mask64 |= 0x3;
8735 pmu->fixed_cntr_mask64 <<= 1;
8736 pmu->fixed_cntr_mask64 |= 0x1;
8737 } else {
8738 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
8739 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
8740 }
8741
8742 /*
8743 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
8744 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
8745 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
8746 * mistakenly add extra counters for P-cores. Correct the number of
8747 * counters here.
8748 */
8749 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
8750 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
8751 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
8752 }
8753
8754 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
8755 pmu->unconstrained = (struct event_constraint)
8756 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
8757 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
8758
8759 pmu->extra_regs = intel_glc_extra_regs;
8760
8761 /* Initialize Atom core specific PerfMon capabilities.*/
8762 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8763 intel_pmu_init_grt(&pmu->pmu);
8764
8765 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
8766 intel_pmu_pebs_data_source_adl();
8767 pr_cont("Alderlake Hybrid events, ");
8768 name = "alderlake_hybrid";
8769 break;
8770
8771 case INTEL_METEORLAKE:
8772 case INTEL_METEORLAKE_L:
8773 case INTEL_ARROWLAKE_U:
8774 ret = intel_pmu_init_hybrid(hybrid_big_small);
8775 if (ret)
8776 return ret;
8777
8778 x86_pmu.pebs_latency_data = cmt_latency_data;
8779 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8780 x86_pmu.hw_config = adl_hw_config;
8781
8782 td_attr = adl_hybrid_events_attrs;
8783 mem_attr = mtl_hybrid_mem_attrs;
8784 tsx_attr = adl_hybrid_tsx_attrs;
8785 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8786 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8787
8788 /* Initialize big core specific PerfMon capabilities.*/
8789 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8790 intel_pmu_init_glc_hybrid(&pmu->pmu);
8791 pmu->extra_regs = intel_rwc_extra_regs;
8792
8793 /* Initialize Atom core specific PerfMon capabilities.*/
8794 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8795 intel_pmu_init_cmt(&pmu->pmu);
8796
8797 intel_pmu_pebs_data_source_mtl();
8798 pr_cont("Meteorlake Hybrid events, ");
8799 name = "meteorlake_hybrid";
8800 break;
8801
8802 case INTEL_PANTHERLAKE_L:
8803 case INTEL_WILDCATLAKE_L:
8804 pr_cont("Pantherlake Hybrid events, ");
8805 name = "pantherlake_hybrid";
8806
8807 ret = intel_pmu_init_hybrid(hybrid_big_small);
8808 if (ret)
8809 return ret;
8810
8811 /* Initialize big core specific PerfMon capabilities.*/
8812 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8813 intel_pmu_init_lnc(&pmu->pmu);
8814 /* Initialize Atom core specific PerfMon capabilities.*/
8815 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8816 intel_pmu_init_dkt_hybrid(&pmu->pmu);
8817
8818 goto lnl_common;
8819
8820 case INTEL_ARROWLAKE:
8821 pr_cont("Arrowlake Hybrid events, ");
8822 name = "arrowlake_hybrid";
8823
8824 ret = intel_pmu_init_hybrid(hybrid_big_small);
8825 if (ret)
8826 return ret;
8827
8828 /* Initialize big core specific PerfMon capabilities.*/
8829 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8830 intel_pmu_init_lnc(&pmu->pmu);
8831 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
8832 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8833 /* Initialize Atom core specific PerfMon capabilities.*/
8834 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8835 intel_pmu_init_skt(&pmu->pmu);
8836
8837 goto lnl_common;
8838
8839 case INTEL_LUNARLAKE_M:
8840 pr_cont("Lunarlake Hybrid events, ");
8841 name = "lunarlake_hybrid";
8842
8843 ret = intel_pmu_init_hybrid(hybrid_big_small);
8844 if (ret)
8845 return ret;
8846
8847 /* Initialize big core specific PerfMon capabilities.*/
8848 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8849 intel_pmu_init_lnc(&pmu->pmu);
8850 /* Initialize Atom core specific PerfMon capabilities.*/
8851 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8852 intel_pmu_init_skt(&pmu->pmu);
8853
8854 lnl_common:
8855
8856 x86_pmu.pebs_latency_data = lnl_latency_data;
8857 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8858 x86_pmu.hw_config = adl_hw_config;
8859
8860 td_attr = lnl_hybrid_events_attrs;
8861 mem_attr = mtl_hybrid_mem_attrs;
8862 tsx_attr = adl_hybrid_tsx_attrs;
8863 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8864 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8865
8866 intel_pmu_pebs_data_source_lnl();
8867 break;
8868
8869 case INTEL_ARROWLAKE_H:
8870 ret = intel_pmu_init_hybrid(hybrid_big_small_tiny);
8871 if (ret)
8872 return ret;
8873
8874 x86_pmu.pebs_latency_data = arl_h_latency_data;
8875 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
8876 x86_pmu.hw_config = arl_h_hw_config;
8877
8878 td_attr = arl_h_hybrid_events_attrs;
8879 mem_attr = arl_h_hybrid_mem_attrs;
8880 tsx_attr = adl_hybrid_tsx_attrs;
8881 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8882 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8883
8884 /* Initialize big core specific PerfMon capabilities. */
8885 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8886 intel_pmu_init_lnc(&pmu->pmu);
8887 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
8888 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8889
8890 /* Initialize Atom core specific PerfMon capabilities. */
8891 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8892 intel_pmu_init_skt(&pmu->pmu);
8893
8894 /* Initialize Lower Power Atom specific PerfMon capabilities. */
8895 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
8896 intel_pmu_init_cmt(&pmu->pmu);
8897
8898 intel_pmu_pebs_data_source_arl_h();
8899 pr_cont("ArrowLake-H Hybrid events, ");
8900 name = "arrowlake_h_hybrid";
8901 break;
8902
8903 case INTEL_NOVALAKE:
8904 case INTEL_NOVALAKE_L:
8905 pr_cont("Novalake Hybrid events, ");
8906 name = "novalake_hybrid";
8907 ret = intel_pmu_init_hybrid(hybrid_big_small);
8908 if (ret)
8909 return ret;
8910
8911 x86_pmu.pebs_latency_data = nvl_latency_data;
8912 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8913 x86_pmu.hw_config = adl_hw_config;
8914
8915 td_attr = lnl_hybrid_events_attrs;
8916 mem_attr = mtl_hybrid_mem_attrs;
8917 tsx_attr = adl_hybrid_tsx_attrs;
8918 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8919 nvl_hybrid_extra_attr_rtm : nvl_hybrid_extra_attr;
8920
8921 /* Initialize big core specific PerfMon capabilities.*/
8922 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8923 intel_pmu_init_cyc(&pmu->pmu);
8924
8925 /* Initialize Atom core specific PerfMon capabilities.*/
8926 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8927 intel_pmu_init_arw(&pmu->pmu);
8928 break;
8929
8930 default:
8931 switch (x86_pmu.version) {
8932 case 1:
8933 x86_pmu.event_constraints = intel_v1_event_constraints;
8934 pr_cont("generic architected perfmon v1, ");
8935 name = "generic_arch_v1";
8936 break;
8937 case 2:
8938 case 3:
8939 case 4:
8940 /*
8941 * default constraints for v2 and up
8942 */
8943 x86_pmu.event_constraints = intel_gen_event_constraints;
8944 pr_cont("generic architected perfmon, ");
8945 name = "generic_arch_v2+";
8946 break;
8947 default:
8948 /*
8949 * The default constraints for v5 and up can support up to
8950 * 16 fixed counters. For the fixed counters 4 and later,
8951 * the pseudo-encoding is applied.
8952 * The constraints may be cut according to the CPUID enumeration
8953 * by inserting the EVENT_CONSTRAINT_END.
8954 */
8955 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
8956 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
8957 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
8958 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
8959 pr_cont("generic architected perfmon, ");
8960 name = "generic_arch_v5+";
8961 break;
8962 }
8963 }
8964
8965 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
8966
8967 if (!is_hybrid()) {
8968 group_events_td.attrs = td_attr;
8969 group_events_mem.attrs = mem_attr;
8970 group_events_tsx.attrs = tsx_attr;
8971 group_format_extra.attrs = extra_attr;
8972 group_format_extra_skl.attrs = extra_skl_attr;
8973
8974 x86_pmu.attr_update = attr_update;
8975 } else {
8976 hybrid_group_events_td.attrs = td_attr;
8977 hybrid_group_events_mem.attrs = mem_attr;
8978 hybrid_group_events_tsx.attrs = tsx_attr;
8979 hybrid_group_format_extra.attrs = extra_attr;
8980
8981 x86_pmu.attr_update = hybrid_attr_update;
8982 }
8983
8984 /*
8985 * The archPerfmonExt (0x23) includes an enhanced enumeration of
8986 * PMU architectural features with a per-core view. For non-hybrid,
8987 * each core has the same PMU capabilities. It's good enough to
8988 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu
8989 * is used to keep the common capabilities. Still keep the values
8990 * from the leaf 0xa. The core specific update will be done later
8991 * when a new type is online.
8992 */
8993 if (!is_hybrid())
8994 intel_update_pmu_caps(NULL);
8995
8996 if (x86_pmu.arch_pebs) {
8997 static_call_update(intel_pmu_disable_event_ext,
8998 intel_pmu_disable_event_ext);
8999 static_call_update(intel_pmu_enable_event_ext,
9000 intel_pmu_enable_event_ext);
9001 pr_cont("Architectural PEBS, ");
9002 }
9003
9004 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
9005 &x86_pmu.fixed_cntr_mask64,
9006 &x86_pmu.intel_ctrl);
9007
9008 /* AnyThread may be deprecated on arch perfmon v5 or later */
9009 if (version >= 5 && edx.split.anythread_deprecated) {
9010 x86_pmu.format_attrs = intel_arch_formats_attr;
9011 pr_cont("AnyThread deprecated, ");
9012 }
9013
9014 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
9015 intel_pmu_arch_lbr_init();
9016
9017 intel_pmu_check_event_constraints_all(NULL);
9018
9019 /*
9020 * Access LBR MSR may cause #GP under certain circumstances.
9021 * Check all LBR MSR here.
9022 * Disable LBR access if any LBR MSRs can not be accessed.
9023 */
9024 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
9025 x86_pmu.lbr_nr = 0;
9026 for (i = 0; i < x86_pmu.lbr_nr; i++) {
9027 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
9028 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
9029 x86_pmu.lbr_nr = 0;
9030 }
9031
9032 if (x86_pmu.lbr_nr) {
9033 intel_pmu_lbr_init();
9034
9035 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
9036
9037 /* only support branch_stack snapshot for perfmon >= v2 */
9038 if (x86_pmu.disable_all == intel_pmu_disable_all) {
9039 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
9040 static_call_update(perf_snapshot_branch_stack,
9041 intel_pmu_snapshot_arch_branch_stack);
9042 } else {
9043 static_call_update(perf_snapshot_branch_stack,
9044 intel_pmu_snapshot_branch_stack);
9045 }
9046 }
9047 }
9048
9049 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
9050
9051 /* Support full width counters using alternative MSR range */
9052 if (x86_pmu.intel_cap.full_width_write) {
9053 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
9054 x86_pmu.perfctr = MSR_IA32_PMC0;
9055 pr_cont("full-width counters, ");
9056 }
9057
9058 /* Support V6+ MSR Aliasing */
9059 if (x86_pmu.version >= 6) {
9060 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
9061 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
9062 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
9063 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
9064 }
9065
9066 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
9067 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
9068
9069 if (x86_pmu.intel_cap.pebs_timing_info)
9070 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
9071
9072 intel_aux_output_init();
9073
9074 return 0;
9075 }
9076
9077 /*
9078 * HT bug: phase 2 init
9079 * Called once we have valid topology information to check
9080 * whether or not HT is enabled
9081 * If HT is off, then we disable the workaround
9082 */
fixup_ht_bug(void)9083 static __init int fixup_ht_bug(void)
9084 {
9085 int c;
9086 /*
9087 * problem not present on this CPU model, nothing to do
9088 */
9089 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
9090 return 0;
9091
9092 if (topology_max_smt_threads() > 1) {
9093 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
9094 return 0;
9095 }
9096
9097 cpus_read_lock();
9098
9099 hardlockup_detector_perf_stop();
9100
9101 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
9102
9103 x86_pmu.start_scheduling = NULL;
9104 x86_pmu.commit_scheduling = NULL;
9105 x86_pmu.stop_scheduling = NULL;
9106
9107 hardlockup_detector_perf_restart();
9108
9109 for_each_online_cpu(c)
9110 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
9111
9112 cpus_read_unlock();
9113 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
9114 return 0;
9115 }
9116 subsys_initcall(fixup_ht_bug)
9117