1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes
83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes
84 * Panther Lake-H (SOC) 0xe322 32 hard yes yes yes
85 * Panther Lake-P (SOC) 0xe422 32 hard yes yes yes
86 * Wildcat Lake-U (SOC) 0x4d22 32 hard yes yes yes
87 * Diamond Rapids (SOC) 0x5827 32 hard yes yes yes
88 * Nova Lake-S (PCH) 0x6e23 32 hard yes yes yes
89 *
90 * Features supported by this driver:
91 * Software PEC no
92 * Hardware PEC yes
93 * Block buffer yes
94 * Block process call transaction yes
95 * I2C block read transaction yes (doesn't use the block buffer)
96 * Target mode no
97 * SMBus Host Notify yes
98 * Interrupt processing yes
99 *
100 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
101 */
102
103 #define DRV_NAME "i801_smbus"
104
105 #include <linux/interrupt.h>
106 #include <linux/module.h>
107 #include <linux/pci.h>
108 #include <linux/kernel.h>
109 #include <linux/stddef.h>
110 #include <linux/delay.h>
111 #include <linux/ioport.h>
112 #include <linux/init.h>
113 #include <linux/i2c.h>
114 #include <linux/i2c-mux.h>
115 #include <linux/i2c-smbus.h>
116 #include <linux/acpi.h>
117 #include <linux/io.h>
118 #include <linux/dmi.h>
119 #include <linux/slab.h>
120 #include <linux/string.h>
121 #include <linux/completion.h>
122 #include <linux/err.h>
123 #include <linux/platform_device.h>
124 #include <linux/platform_data/itco_wdt.h>
125 #include <linux/platform_data/x86/p2sb.h>
126 #include <linux/pm_runtime.h>
127 #include <linux/mutex.h>
128
129 #ifdef CONFIG_I2C_I801_MUX
130 #include <linux/gpio/machine.h>
131 #include <linux/platform_data/i2c-mux-gpio.h>
132 #endif
133
134 /* I801 SMBus address offsets */
135 #define SMBHSTSTS(p) (0 + (p)->smba)
136 #define SMBHSTCNT(p) (2 + (p)->smba)
137 #define SMBHSTCMD(p) (3 + (p)->smba)
138 #define SMBHSTADD(p) (4 + (p)->smba)
139 #define SMBHSTDAT0(p) (5 + (p)->smba)
140 #define SMBHSTDAT1(p) (6 + (p)->smba)
141 #define SMBBLKDAT(p) (7 + (p)->smba)
142 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
143 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
144 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
145 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
146 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
147 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
148
149 /* PCI Address Constants */
150 #define SMBBAR_MMIO 0
151 #define SMBBAR 4
152 #define SMBHSTCFG 0x040
153 #define TCOBASE 0x050
154 #define TCOCTL 0x054
155
156 #define SBREG_SMBCTRL 0xc6000c
157 #define SBREG_SMBCTRL_DNV 0xcf000c
158
159 /* Host configuration bits for SMBHSTCFG */
160 #define SMBHSTCFG_HST_EN BIT(0)
161 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
162 #define SMBHSTCFG_I2C_EN BIT(2)
163 #define SMBHSTCFG_SPD_WD BIT(4)
164
165 /* TCO configuration bits for TCOCTL */
166 #define TCOCTL_EN BIT(8)
167
168 /* Auxiliary status register bits, ICH4+ only */
169 #define SMBAUXSTS_CRCE BIT(0)
170 #define SMBAUXSTS_STCO BIT(1)
171
172 /* Auxiliary control register bits, ICH4+ only */
173 #define SMBAUXCTL_CRC BIT(0)
174 #define SMBAUXCTL_E32B BIT(1)
175
176 /* I801 command constants */
177 #define I801_QUICK 0x00
178 #define I801_BYTE 0x04
179 #define I801_BYTE_DATA 0x08
180 #define I801_WORD_DATA 0x0C
181 #define I801_PROC_CALL 0x10
182 #define I801_BLOCK_DATA 0x14
183 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
184 #define I801_BLOCK_PROC_CALL 0x1C
185
186 /* I801 Host Control register bits */
187 #define SMBHSTCNT_INTREN BIT(0)
188 #define SMBHSTCNT_KILL BIT(1)
189 #define SMBHSTCNT_LAST_BYTE BIT(5)
190 #define SMBHSTCNT_START BIT(6)
191 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
192
193 /* I801 Hosts Status register bits */
194 #define SMBHSTSTS_BYTE_DONE BIT(7)
195 #define SMBHSTSTS_INUSE_STS BIT(6)
196 #define SMBHSTSTS_SMBALERT_STS BIT(5)
197 #define SMBHSTSTS_FAILED BIT(4)
198 #define SMBHSTSTS_BUS_ERR BIT(3)
199 #define SMBHSTSTS_DEV_ERR BIT(2)
200 #define SMBHSTSTS_INTR BIT(1)
201 #define SMBHSTSTS_HOST_BUSY BIT(0)
202
203 /* Host Notify Status register bits */
204 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
205
206 /* Host Notify Command register bits */
207 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
208 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
209
210 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
211 SMBHSTSTS_DEV_ERR)
212
213 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
214 STATUS_ERROR_FLAGS)
215
216 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1)
217
218 /* Older devices have their ID defined in <linux/pci_ids.h> */
219 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
220 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
221 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
222 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
223 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
224 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
225 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
226 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
227 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
228 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
229 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
230 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
231 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
232 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
233 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
234 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
235 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
236 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
237 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
238 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
239 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
240 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
241 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
242 #define PCI_DEVICE_ID_INTEL_WILDCAT_LAKE_U_SMBUS 0x4d22
243 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
244 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
245 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
246 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796
247 #define PCI_DEVICE_ID_INTEL_DIAMOND_RAPIDS_SMBUS 0x5827
248 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
249 #define PCI_DEVICE_ID_INTEL_NOVA_LAKE_S_SMBUS 0x6e23
250 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722
251 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
252 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
253 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
254 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
255 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
256 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
257 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
258 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
259 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
260 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
261 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
262 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
263 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
264 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
265 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
266 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
267 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
268 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
269 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
270 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
271 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
272 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
273 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_H_SMBUS 0xe322
274 #define PCI_DEVICE_ID_INTEL_PANTHER_LAKE_P_SMBUS 0xe422
275
276 struct i801_mux_config {
277 char *gpio_chip;
278 unsigned values[3];
279 int n_values;
280 unsigned gpios[2]; /* Relative to gpio_chip->base */
281 int n_gpios;
282 };
283
284 struct i801_priv {
285 struct i2c_adapter adapter;
286 void __iomem *smba;
287 unsigned char original_hstcfg;
288 unsigned char original_hstcnt;
289 unsigned char original_slvcmd;
290 struct pci_dev *pci_dev;
291 unsigned int features;
292
293 /* isr processing */
294 struct completion done;
295 u8 status;
296
297 /* Command state used by isr for byte-by-byte block transactions */
298 u8 cmd;
299 bool is_read;
300 int count;
301 int len;
302 u8 *data;
303
304 #ifdef CONFIG_I2C_I801_MUX
305 struct platform_device *mux_pdev;
306 struct gpiod_lookup_table *lookup;
307 struct notifier_block mux_notifier_block;
308 #endif
309 struct platform_device *tco_pdev;
310
311 /*
312 * If set to true the host controller registers are reserved for
313 * ACPI AML use.
314 */
315 bool acpi_reserved;
316 };
317
318 #define FEATURE_SMBUS_PEC BIT(0)
319 #define FEATURE_BLOCK_BUFFER BIT(1)
320 #define FEATURE_BLOCK_PROC BIT(2)
321 #define FEATURE_I2C_BLOCK_READ BIT(3)
322 #define FEATURE_IRQ BIT(4)
323 #define FEATURE_HOST_NOTIFY BIT(5)
324 /* Not really a feature, but it's convenient to handle it as such */
325 #define FEATURE_IDF BIT(15)
326 #define FEATURE_TCO_SPT BIT(16)
327 #define FEATURE_TCO_CNL BIT(17)
328
329 static const char *i801_feature_names[] = {
330 "SMBus PEC",
331 "Block buffer",
332 "Block process call",
333 "I2C block read",
334 "Interrupt",
335 "SMBus Host Notify",
336 };
337
338 static unsigned int disable_features;
339 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
340 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
341 "\t\t 0x01 disable SMBus PEC\n"
342 "\t\t 0x02 disable the block buffer\n"
343 "\t\t 0x08 disable the I2C block read functionality\n"
344 "\t\t 0x10 don't use interrupts\n"
345 "\t\t 0x20 disable SMBus Host Notify ");
346
347 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)348 static int i801_wait_intr(struct i801_priv *priv)
349 {
350 unsigned long timeout = jiffies + priv->adapter.timeout;
351 int status, busy;
352
353 do {
354 usleep_range(250, 500);
355 status = ioread8(SMBHSTSTS(priv));
356 busy = status & SMBHSTSTS_HOST_BUSY;
357 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
358 if (!busy && status)
359 return status & STATUS_ERROR_FLAGS;
360 } while (time_is_after_eq_jiffies(timeout));
361
362 return -ETIMEDOUT;
363 }
364
365 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)366 static int i801_wait_byte_done(struct i801_priv *priv)
367 {
368 unsigned long timeout = jiffies + priv->adapter.timeout;
369 int status;
370
371 do {
372 usleep_range(250, 500);
373 status = ioread8(SMBHSTSTS(priv));
374 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
375 return status & STATUS_ERROR_FLAGS;
376 } while (time_is_after_eq_jiffies(timeout));
377
378 return -ETIMEDOUT;
379 }
380
i801_get_block_len(struct i801_priv * priv)381 static int i801_get_block_len(struct i801_priv *priv)
382 {
383 u8 len = ioread8(SMBHSTDAT0(priv));
384
385 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
386 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len);
387 return -EPROTO;
388 }
389
390 return len;
391 }
392
i801_check_and_clear_pec_error(struct i801_priv * priv)393 static int i801_check_and_clear_pec_error(struct i801_priv *priv)
394 {
395 u8 status;
396
397 if (!(priv->features & FEATURE_SMBUS_PEC))
398 return 0;
399
400 status = ioread8(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
401 if (status) {
402 iowrite8(status, SMBAUXSTS(priv));
403 return -EBADMSG;
404 }
405
406 return 0;
407 }
408
409 /* Make sure the SMBus host is ready to start transmitting.
410 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)411 static int i801_check_pre(struct i801_priv *priv)
412 {
413 int status, result;
414
415 status = ioread8(SMBHSTSTS(priv));
416 if (status & SMBHSTSTS_HOST_BUSY) {
417 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
418 return -EBUSY;
419 }
420
421 status &= STATUS_FLAGS;
422 if (status) {
423 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
424 iowrite8(status, SMBHSTSTS(priv));
425 }
426
427 /*
428 * Clear CRC status if needed.
429 * During normal operation, i801_check_post() takes care
430 * of it after every operation. We do it here only in case
431 * the hardware was already in this state when the driver
432 * started.
433 */
434 result = i801_check_and_clear_pec_error(priv);
435 if (result)
436 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n");
437
438 return 0;
439 }
440
i801_check_post(struct i801_priv * priv,int status)441 static int i801_check_post(struct i801_priv *priv, int status)
442 {
443 int result = 0;
444
445 /*
446 * If the SMBus is still busy, we give up
447 */
448 if (unlikely(status < 0)) {
449 /* try to stop the current command */
450 iowrite8(SMBHSTCNT_KILL, SMBHSTCNT(priv));
451 status = i801_wait_intr(priv);
452 iowrite8(0, SMBHSTCNT(priv));
453
454 /* Check if it worked */
455 if (status < 0 || !(status & SMBHSTSTS_FAILED))
456 pci_dbg(priv->pci_dev, "Failed terminating the transaction\n");
457 return -ETIMEDOUT;
458 }
459
460 if (status & SMBHSTSTS_FAILED) {
461 result = -EIO;
462 pci_err(priv->pci_dev, "Transaction failed\n");
463 }
464 if (status & SMBHSTSTS_DEV_ERR) {
465 /*
466 * This may be a PEC error, check and clear it.
467 *
468 * AUXSTS is handled differently from HSTSTS.
469 * For HSTSTS, i801_isr() or i801_wait_intr()
470 * has already cleared the error bits in hardware,
471 * and we are passed a copy of the original value
472 * in "status".
473 * For AUXSTS, the hardware register is left
474 * for us to handle here.
475 * This is asymmetric, slightly iffy, but safe,
476 * since all this code is serialized and the CRCE
477 * bit is harmless as long as it's cleared before
478 * the next operation.
479 */
480 result = i801_check_and_clear_pec_error(priv);
481 if (result) {
482 pci_dbg(priv->pci_dev, "PEC error\n");
483 } else {
484 result = -ENXIO;
485 pci_dbg(priv->pci_dev, "No response\n");
486 }
487 }
488 if (status & SMBHSTSTS_BUS_ERR) {
489 result = -EAGAIN;
490 pci_dbg(priv->pci_dev, "Lost arbitration\n");
491 }
492
493 return result;
494 }
495
i801_transaction(struct i801_priv * priv,int xact)496 static int i801_transaction(struct i801_priv *priv, int xact)
497 {
498 unsigned long result;
499 const struct i2c_adapter *adap = &priv->adapter;
500
501 if (priv->features & FEATURE_IRQ) {
502 reinit_completion(&priv->done);
503 iowrite8(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
504 SMBHSTCNT(priv));
505 result = wait_for_completion_timeout(&priv->done, adap->timeout);
506 return result ? priv->status : -ETIMEDOUT;
507 }
508
509 iowrite8(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
510
511 return i801_wait_intr(priv);
512 }
513
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)514 static int i801_block_transaction_by_block(struct i801_priv *priv,
515 union i2c_smbus_data *data,
516 char read_write, int command)
517 {
518 int len, status, xact;
519
520 switch (command) {
521 case I2C_SMBUS_BLOCK_PROC_CALL:
522 xact = I801_BLOCK_PROC_CALL;
523 break;
524 case I2C_SMBUS_BLOCK_DATA:
525 xact = I801_BLOCK_DATA;
526 break;
527 default:
528 return -EOPNOTSUPP;
529 }
530
531 /* Set block buffer mode */
532 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
533
534 if (read_write == I2C_SMBUS_WRITE) {
535 len = data->block[0];
536 iowrite8(len, SMBHSTDAT0(priv));
537 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */
538 iowrite8_rep(SMBBLKDAT(priv), data->block + 1, len);
539 }
540
541 status = i801_transaction(priv, xact);
542 if (status)
543 goto out;
544
545 if (read_write == I2C_SMBUS_READ ||
546 command == I2C_SMBUS_BLOCK_PROC_CALL) {
547 len = i801_get_block_len(priv);
548 if (len < 0) {
549 status = len;
550 goto out;
551 }
552
553 data->block[0] = len;
554 ioread8(SMBHSTCNT(priv)); /* reset the data buffer index */
555 ioread8_rep(SMBBLKDAT(priv), data->block + 1, len);
556 }
557 out:
558 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
559 return status;
560 }
561
i801_isr_byte_done(struct i801_priv * priv)562 static void i801_isr_byte_done(struct i801_priv *priv)
563 {
564 if (priv->is_read) {
565 /*
566 * At transfer start i801_smbus_block_transaction() marks
567 * the block length as invalid. Check for this sentinel value
568 * and read the block length from SMBHSTDAT0.
569 */
570 if (priv->len == SMBUS_LEN_SENTINEL) {
571 priv->len = i801_get_block_len(priv);
572 if (priv->len < 0)
573 /* FIXME: Recover */
574 priv->len = I2C_SMBUS_BLOCK_MAX;
575
576 priv->data[-1] = priv->len;
577 }
578
579 /* Read next byte */
580 if (priv->count < priv->len)
581 priv->data[priv->count++] = ioread8(SMBBLKDAT(priv));
582 else
583 pci_dbg(priv->pci_dev, "Discarding extra byte on block read\n");
584
585 /* Set LAST_BYTE for last byte of read transaction */
586 if (priv->count == priv->len - 1)
587 iowrite8(priv->cmd | SMBHSTCNT_LAST_BYTE,
588 SMBHSTCNT(priv));
589 } else if (priv->count < priv->len - 1) {
590 /* Write next byte, except for IRQ after last byte */
591 iowrite8(priv->data[++priv->count], SMBBLKDAT(priv));
592 }
593 }
594
i801_host_notify_isr(struct i801_priv * priv)595 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
596 {
597 unsigned short addr;
598
599 addr = ioread8(SMBNTFDADD(priv)) >> 1;
600
601 /*
602 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
603 * always returns 0. Our current implementation doesn't provide
604 * data, so we just ignore it.
605 */
606 i2c_handle_smbus_host_notify(&priv->adapter, addr);
607
608 /* clear Host Notify bit and return */
609 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
610 return IRQ_HANDLED;
611 }
612
613 /*
614 * There are three kinds of interrupts:
615 *
616 * 1) i801 signals transaction completion with one of these interrupts:
617 * INTR - Success
618 * DEV_ERR - Invalid command, NAK or communication timeout
619 * BUS_ERR - SMI# transaction collision
620 * FAILED - transaction was canceled due to a KILL request
621 * When any of these occur, update ->status and signal completion.
622 *
623 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
624 * occurs for each byte of a byte-by-byte to prepare the next byte.
625 *
626 * 3) Host Notify interrupts
627 */
i801_isr(int irq,void * dev_id)628 static irqreturn_t i801_isr(int irq, void *dev_id)
629 {
630 struct i801_priv *priv = dev_id;
631 u16 pcists;
632 u8 status;
633
634 /* Confirm this is our interrupt */
635 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
636 if (!(pcists & PCI_STATUS_INTERRUPT))
637 return IRQ_NONE;
638
639 if (priv->features & FEATURE_HOST_NOTIFY) {
640 status = ioread8(SMBSLVSTS(priv));
641 if (status & SMBSLVSTS_HST_NTFY_STS)
642 return i801_host_notify_isr(priv);
643 }
644
645 status = ioread8(SMBHSTSTS(priv));
646 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
647 i801_isr_byte_done(priv);
648
649 /*
650 * Clear IRQ sources: SMB_ALERT status is set after signal assertion
651 * independently of the interrupt generation being blocked or not
652 * so clear it always when the status is set.
653 */
654 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
655 iowrite8(status, SMBHSTSTS(priv));
656
657 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
658 if (status) {
659 priv->status = status & STATUS_ERROR_FLAGS;
660 complete(&priv->done);
661 }
662
663 return IRQ_HANDLED;
664 }
665
666 /*
667 * For "byte-by-byte" block transactions:
668 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
669 * I2C read uses cmd=I801_I2C_BLOCK_DATA
670 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)671 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
672 union i2c_smbus_data *data,
673 char read_write, int command)
674 {
675 int i, len;
676 int smbcmd;
677 int status;
678 unsigned long result;
679 const struct i2c_adapter *adap = &priv->adapter;
680
681 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
682 return -EOPNOTSUPP;
683
684 len = data->block[0];
685
686 if (read_write == I2C_SMBUS_WRITE) {
687 iowrite8(len, SMBHSTDAT0(priv));
688 iowrite8(data->block[1], SMBBLKDAT(priv));
689 }
690
691 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
692 read_write == I2C_SMBUS_READ)
693 smbcmd = I801_I2C_BLOCK_DATA;
694 else
695 smbcmd = I801_BLOCK_DATA;
696
697 if (priv->features & FEATURE_IRQ) {
698 priv->is_read = (read_write == I2C_SMBUS_READ);
699 if (len == 1 && priv->is_read)
700 smbcmd |= SMBHSTCNT_LAST_BYTE;
701 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
702 priv->len = len;
703 priv->count = 0;
704 priv->data = &data->block[1];
705
706 reinit_completion(&priv->done);
707 iowrite8(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
708 result = wait_for_completion_timeout(&priv->done, adap->timeout);
709 return result ? priv->status : -ETIMEDOUT;
710 }
711
712 if (len == 1 && read_write == I2C_SMBUS_READ)
713 smbcmd |= SMBHSTCNT_LAST_BYTE;
714 iowrite8(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
715
716 for (i = 1; i <= len; i++) {
717 status = i801_wait_byte_done(priv);
718 if (status)
719 return status;
720
721 /*
722 * At transfer start i801_smbus_block_transaction() marks
723 * the block length as invalid. Check for this sentinel value
724 * and read the block length from SMBHSTDAT0.
725 */
726 if (len == SMBUS_LEN_SENTINEL) {
727 len = i801_get_block_len(priv);
728 if (len < 0) {
729 /* Recover */
730 while (ioread8(SMBHSTSTS(priv)) &
731 SMBHSTSTS_HOST_BUSY)
732 iowrite8(SMBHSTSTS_BYTE_DONE,
733 SMBHSTSTS(priv));
734 iowrite8(SMBHSTSTS_INTR, SMBHSTSTS(priv));
735 return -EPROTO;
736 }
737 data->block[0] = len;
738 }
739
740 if (read_write == I2C_SMBUS_READ) {
741 data->block[i] = ioread8(SMBBLKDAT(priv));
742 if (i == len - 1)
743 iowrite8(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
744 }
745
746 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
747 iowrite8(data->block[i+1], SMBBLKDAT(priv));
748
749 /* signals SMBBLKDAT ready */
750 iowrite8(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
751 }
752
753 return i801_wait_intr(priv);
754 }
755
i801_set_hstadd(struct i801_priv * priv,u8 addr,char read_write)756 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
757 {
758 iowrite8((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
759 }
760
761 /* Single value transaction function */
i801_simple_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)762 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
763 u8 addr, u8 hstcmd, char read_write, int command)
764 {
765 int xact, ret;
766
767 switch (command) {
768 case I2C_SMBUS_QUICK:
769 i801_set_hstadd(priv, addr, read_write);
770 xact = I801_QUICK;
771 break;
772 case I2C_SMBUS_BYTE:
773 i801_set_hstadd(priv, addr, read_write);
774 if (read_write == I2C_SMBUS_WRITE)
775 iowrite8(hstcmd, SMBHSTCMD(priv));
776 xact = I801_BYTE;
777 break;
778 case I2C_SMBUS_BYTE_DATA:
779 i801_set_hstadd(priv, addr, read_write);
780 if (read_write == I2C_SMBUS_WRITE)
781 iowrite8(data->byte, SMBHSTDAT0(priv));
782 iowrite8(hstcmd, SMBHSTCMD(priv));
783 xact = I801_BYTE_DATA;
784 break;
785 case I2C_SMBUS_WORD_DATA:
786 i801_set_hstadd(priv, addr, read_write);
787 if (read_write == I2C_SMBUS_WRITE) {
788 iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
789 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
790 }
791 iowrite8(hstcmd, SMBHSTCMD(priv));
792 xact = I801_WORD_DATA;
793 break;
794 case I2C_SMBUS_PROC_CALL:
795 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
796 iowrite8(data->word & 0xff, SMBHSTDAT0(priv));
797 iowrite8((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
798 iowrite8(hstcmd, SMBHSTCMD(priv));
799 read_write = I2C_SMBUS_READ;
800 xact = I801_PROC_CALL;
801 break;
802 default:
803 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
804 return -EOPNOTSUPP;
805 }
806
807 ret = i801_transaction(priv, xact);
808 if (ret || read_write == I2C_SMBUS_WRITE)
809 return ret;
810
811 switch (command) {
812 case I2C_SMBUS_BYTE:
813 case I2C_SMBUS_BYTE_DATA:
814 data->byte = ioread8(SMBHSTDAT0(priv));
815 break;
816 case I2C_SMBUS_WORD_DATA:
817 case I2C_SMBUS_PROC_CALL:
818 data->word = ioread8(SMBHSTDAT0(priv)) +
819 (ioread8(SMBHSTDAT1(priv)) << 8);
820 break;
821 }
822
823 return 0;
824 }
825
i801_smbus_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)826 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
827 u8 addr, u8 hstcmd, char read_write, int command)
828 {
829 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
830 /* Mark block length as invalid */
831 data->block[0] = SMBUS_LEN_SENTINEL;
832 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
833 return -EPROTO;
834
835 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
836 /* Needs to be flagged as write transaction */
837 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
838 else
839 i801_set_hstadd(priv, addr, read_write);
840 iowrite8(hstcmd, SMBHSTCMD(priv));
841
842 if (priv->features & FEATURE_BLOCK_BUFFER)
843 return i801_block_transaction_by_block(priv, data, read_write, command);
844 else
845 return i801_block_transaction_byte_by_byte(priv, data, read_write, command);
846 }
847
i801_i2c_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)848 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
849 u8 addr, u8 hstcmd, char read_write, int command)
850 {
851 int result;
852 u8 hostc;
853
854 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
855 return -EPROTO;
856 /*
857 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here,
858 * even when reading. However if SPD Write Disable is set (Lynx Point and later),
859 * the read will fail if we don't set the R/#W bit.
860 */
861 i801_set_hstadd(priv, addr,
862 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE);
863
864 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */
865 if (read_write == I2C_SMBUS_READ)
866 iowrite8(hstcmd, SMBHSTDAT1(priv));
867 else
868 iowrite8(hstcmd, SMBHSTCMD(priv));
869
870 if (read_write == I2C_SMBUS_WRITE) {
871 /* set I2C_EN bit in configuration register */
872 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
873 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN);
874 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
875 pci_err(priv->pci_dev, "I2C block read is unsupported!\n");
876 return -EOPNOTSUPP;
877 }
878
879 /* Block buffer isn't supported for I2C block transactions */
880 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command);
881
882 /* restore saved configuration register value */
883 if (read_write == I2C_SMBUS_WRITE)
884 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
885
886 return result;
887 }
888
889 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)890 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
891 unsigned short flags, char read_write, u8 command,
892 int size, union i2c_smbus_data *data)
893 {
894 int hwpec, ret;
895 struct i801_priv *priv = i2c_get_adapdata(adap);
896
897 if (priv->acpi_reserved)
898 return -EBUSY;
899
900 pm_runtime_get_sync(&priv->pci_dev->dev);
901
902 ret = i801_check_pre(priv);
903 if (ret)
904 goto out;
905
906 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
907 && size != I2C_SMBUS_QUICK
908 && size != I2C_SMBUS_I2C_BLOCK_DATA;
909
910 if (hwpec) /* enable/disable hardware PEC */
911 iowrite8(ioread8(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
912 else
913 iowrite8(ioread8(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
914 SMBAUXCTL(priv));
915
916 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL)
917 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size);
918 else if (size == I2C_SMBUS_I2C_BLOCK_DATA)
919 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size);
920 else
921 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
922
923 ret = i801_check_post(priv, ret);
924
925 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
926 * time, so we forcibly disable it after every transaction.
927 */
928 if (hwpec)
929 iowrite8(ioread8(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
930 out:
931 /*
932 * Unlock the SMBus device for use by BIOS/ACPI,
933 * and clear status flags if not done already.
934 */
935 iowrite8(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
936
937 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
938 return ret;
939 }
940
941
i801_func(struct i2c_adapter * adapter)942 static u32 i801_func(struct i2c_adapter *adapter)
943 {
944 struct i801_priv *priv = i2c_get_adapdata(adapter);
945
946 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
947 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
948 I2C_FUNC_SMBUS_PROC_CALL |
949 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
950 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
951 ((priv->features & FEATURE_BLOCK_PROC) ?
952 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
953 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
954 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
955 ((priv->features & FEATURE_HOST_NOTIFY) ?
956 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
957 }
958
i801_enable_host_notify(struct i2c_adapter * adapter)959 static void i801_enable_host_notify(struct i2c_adapter *adapter)
960 {
961 struct i801_priv *priv = i2c_get_adapdata(adapter);
962
963 if (!(priv->features & FEATURE_HOST_NOTIFY))
964 return;
965
966 /*
967 * Enable host notify interrupt and block the generation of interrupt
968 * from the SMB_ALERT signal because the driver does not support
969 * SMBus Alert.
970 */
971 iowrite8(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
972 priv->original_slvcmd, SMBSLVCMD(priv));
973
974 /* clear Host Notify bit to allow a new notification */
975 iowrite8(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
976 }
977
i801_disable_host_notify(struct i801_priv * priv)978 static void i801_disable_host_notify(struct i801_priv *priv)
979 {
980 if (!(priv->features & FEATURE_HOST_NOTIFY))
981 return;
982
983 iowrite8(priv->original_slvcmd, SMBSLVCMD(priv));
984 }
985
986 static const struct i2c_algorithm smbus_algorithm = {
987 .smbus_xfer = i801_access,
988 .functionality = i801_func,
989 };
990
991 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
992 FEATURE_HOST_NOTIFY)
993 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \
994 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ)
995
996 static const struct pci_device_id i801_ids[] = {
997 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
998 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
999 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
1000 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
1001 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
1002 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
1003 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
1004 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
1005 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
1006 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
1007 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
1008 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
1009 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
1010 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
1011 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
1012 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
1013 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
1014 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
1015 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
1016 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
1017 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
1018 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
1019 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
1020 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
1021 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
1022 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
1023 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
1024 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
1025 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
1026 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
1027 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
1028 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
1029 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
1030 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
1031 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
1032 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
1033 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1034 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1035 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1036 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
1039 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1040 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1041 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1042 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1049 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1059 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1060 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5) },
1061 { PCI_DEVICE_DATA(INTEL, DIAMOND_RAPIDS_SMBUS, FEATURES_ICH5) },
1062 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1063 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1064 { PCI_DEVICE_DATA(INTEL, PANTHER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1065 { PCI_DEVICE_DATA(INTEL, WILDCAT_LAKE_U_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1066 { PCI_DEVICE_DATA(INTEL, NOVA_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1067 { 0, }
1068 };
1069
1070 MODULE_DEVICE_TABLE(pci, i801_ids);
1071
1072 #if defined CONFIG_X86 && defined CONFIG_DMI
1073 static unsigned char apanel_addr __ro_after_init;
1074
1075 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1076 static __init const void __iomem *bios_signature(const void __iomem *bios)
1077 {
1078 ssize_t offset;
1079 const unsigned char signature[] = "FJKEYINF";
1080
1081 for (offset = 0; offset < 0x10000; offset += 0x10) {
1082 if (check_signature(bios + offset, signature,
1083 sizeof(signature)-1))
1084 return bios + offset;
1085 }
1086 return NULL;
1087 }
1088
input_apanel_init(void)1089 static void __init input_apanel_init(void)
1090 {
1091 void __iomem *bios;
1092 const void __iomem *p;
1093
1094 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1095 p = bios_signature(bios);
1096 if (p) {
1097 /* just use the first address */
1098 apanel_addr = readb(p + 8 + 3) >> 1;
1099 }
1100 iounmap(bios);
1101 }
1102
1103 struct dmi_onboard_device_info {
1104 const char *name;
1105 u8 type;
1106 unsigned short i2c_addr;
1107 const char *i2c_type;
1108 };
1109
1110 static const struct dmi_onboard_device_info dmi_devices[] = {
1111 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1112 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1113 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1114 };
1115
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1116 static void dmi_check_onboard_device(u8 type, const char *name,
1117 struct i2c_adapter *adap)
1118 {
1119 int i;
1120 struct i2c_board_info info;
1121
1122 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1123 /* & ~0x80, ignore enabled/disabled bit */
1124 if ((type & ~0x80) != dmi_devices[i].type)
1125 continue;
1126 if (strcasecmp(name, dmi_devices[i].name))
1127 continue;
1128
1129 memset(&info, 0, sizeof(struct i2c_board_info));
1130 info.addr = dmi_devices[i].i2c_addr;
1131 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1132 i2c_new_client_device(adap, &info);
1133 break;
1134 }
1135 }
1136
1137 /* We use our own function to check for onboard devices instead of
1138 dmi_find_device() as some buggy BIOS's have the devices we are interested
1139 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1140 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1141 {
1142 int i, count;
1143
1144 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE)
1145 return;
1146
1147 count = (dm->length - sizeof(struct dmi_header)) / 2;
1148 for (i = 0; i < count; i++) {
1149 const u8 *d = (char *)(dm + 1) + (i * 2);
1150 const char *name = ((char *) dm) + dm->length;
1151 u8 type = d[0];
1152 u8 s = d[1];
1153
1154 if (!s)
1155 continue;
1156 s--;
1157 while (s > 0 && name[0]) {
1158 name += strlen(name) + 1;
1159 s--;
1160 }
1161 if (name[0] == 0) /* Bogus string reference */
1162 continue;
1163
1164 dmi_check_onboard_device(type, name, adap);
1165 }
1166 }
1167
1168 /* Register optional targets */
i801_probe_optional_targets(struct i801_priv * priv)1169 static void i801_probe_optional_targets(struct i801_priv *priv)
1170 {
1171 /* Only register targets on main SMBus channel */
1172 if (priv->features & FEATURE_IDF)
1173 return;
1174
1175 if (apanel_addr) {
1176 struct i2c_board_info info = {
1177 .addr = apanel_addr,
1178 .type = "fujitsu_apanel",
1179 };
1180
1181 i2c_new_client_device(&priv->adapter, &info);
1182 }
1183
1184 if (dmi_name_in_vendors("FUJITSU"))
1185 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1186
1187 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1188 #ifdef CONFIG_I2C_I801_MUX
1189 if (!priv->mux_pdev)
1190 #endif
1191 i2c_register_spd_write_enable(&priv->adapter);
1192 }
1193 #else
input_apanel_init(void)1194 static void __init input_apanel_init(void) {}
i801_probe_optional_targets(struct i801_priv * priv)1195 static void i801_probe_optional_targets(struct i801_priv *priv) {}
1196 #endif /* CONFIG_X86 && CONFIG_DMI */
1197
1198 #ifdef CONFIG_I2C_I801_MUX
1199 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1200 .gpio_chip = "gpio_ich",
1201 .values = { 0x02, 0x03 },
1202 .n_values = 2,
1203 .gpios = { 52, 53 },
1204 .n_gpios = 2,
1205 };
1206
1207 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1208 .gpio_chip = "gpio_ich",
1209 .values = { 0x02, 0x03, 0x01 },
1210 .n_values = 3,
1211 .gpios = { 52, 53 },
1212 .n_gpios = 2,
1213 };
1214
1215 static const struct dmi_system_id mux_dmi_table[] = {
1216 {
1217 .matches = {
1218 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1219 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1220 },
1221 .driver_data = &i801_mux_config_asus_z8_d12,
1222 },
1223 {
1224 .matches = {
1225 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1226 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1227 },
1228 .driver_data = &i801_mux_config_asus_z8_d12,
1229 },
1230 {
1231 .matches = {
1232 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1233 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1234 },
1235 .driver_data = &i801_mux_config_asus_z8_d12,
1236 },
1237 {
1238 .matches = {
1239 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1240 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1241 },
1242 .driver_data = &i801_mux_config_asus_z8_d12,
1243 },
1244 {
1245 .matches = {
1246 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1247 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1248 },
1249 .driver_data = &i801_mux_config_asus_z8_d12,
1250 },
1251 {
1252 .matches = {
1253 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1254 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1255 },
1256 .driver_data = &i801_mux_config_asus_z8_d12,
1257 },
1258 {
1259 .matches = {
1260 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1261 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1262 },
1263 .driver_data = &i801_mux_config_asus_z8_d18,
1264 },
1265 {
1266 .matches = {
1267 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1268 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1269 },
1270 .driver_data = &i801_mux_config_asus_z8_d18,
1271 },
1272 {
1273 .matches = {
1274 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1275 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1276 },
1277 .driver_data = &i801_mux_config_asus_z8_d12,
1278 },
1279 { }
1280 };
1281
i801_notifier_call(struct notifier_block * nb,unsigned long action,void * data)1282 static int i801_notifier_call(struct notifier_block *nb, unsigned long action,
1283 void *data)
1284 {
1285 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block);
1286 struct device *dev = data;
1287
1288 if (action != BUS_NOTIFY_ADD_DEVICE ||
1289 dev->type != &i2c_adapter_type ||
1290 i2c_root_adapter(dev) != &priv->adapter)
1291 return NOTIFY_DONE;
1292
1293 /* Call i2c_register_spd for muxed child segments */
1294 i2c_register_spd_write_enable(to_i2c_adapter(dev));
1295
1296 return NOTIFY_OK;
1297 }
1298
1299 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1300 static void i801_add_mux(struct i801_priv *priv)
1301 {
1302 struct device *dev = &priv->adapter.dev;
1303 const struct i801_mux_config *mux_config;
1304 struct i2c_mux_gpio_platform_data gpio_data;
1305 struct gpiod_lookup_table *lookup;
1306 const struct dmi_system_id *id;
1307 int i;
1308
1309 id = dmi_first_match(mux_dmi_table);
1310 if (!id)
1311 return;
1312
1313 mux_config = id->driver_data;
1314
1315 /* Prepare the platform data */
1316 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1317 gpio_data.parent = priv->adapter.nr;
1318 gpio_data.values = mux_config->values;
1319 gpio_data.n_values = mux_config->n_values;
1320 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1321
1322 /* Register GPIO descriptor lookup table */
1323 lookup = devm_kzalloc(dev,
1324 struct_size(lookup, table, mux_config->n_gpios + 1),
1325 GFP_KERNEL);
1326 if (!lookup)
1327 return;
1328 lookup->dev_id = "i2c-mux-gpio";
1329 for (i = 0; i < mux_config->n_gpios; i++)
1330 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1331 mux_config->gpios[i], "mux", 0);
1332 gpiod_add_lookup_table(lookup);
1333
1334 priv->mux_notifier_block.notifier_call = i801_notifier_call;
1335 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block))
1336 return;
1337 /*
1338 * Register the mux device, we use PLATFORM_DEVID_NONE here
1339 * because since we are referring to the GPIO chip by name we are
1340 * anyways in deep trouble if there is more than one of these
1341 * devices, and there should likely only be one platform controller
1342 * hub.
1343 */
1344 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1345 PLATFORM_DEVID_NONE, &gpio_data,
1346 sizeof(struct i2c_mux_gpio_platform_data));
1347 if (IS_ERR(priv->mux_pdev)) {
1348 gpiod_remove_lookup_table(lookup);
1349 devm_kfree(dev, lookup);
1350 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1351 } else {
1352 priv->lookup = lookup;
1353 }
1354 }
1355
i801_del_mux(struct i801_priv * priv)1356 static void i801_del_mux(struct i801_priv *priv)
1357 {
1358 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block);
1359 platform_device_unregister(priv->mux_pdev);
1360 gpiod_remove_lookup_table(priv->lookup);
1361 }
1362 #else
i801_add_mux(struct i801_priv * priv)1363 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1364 static inline void i801_del_mux(struct i801_priv *priv) { }
1365 #endif
1366
1367 static struct platform_device *
i801_add_tco_spt(struct pci_dev * pci_dev,struct resource * tco_res)1368 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res)
1369 {
1370 static const struct itco_wdt_platform_data pldata = {
1371 .name = "Intel PCH",
1372 .version = 4,
1373 };
1374 struct resource *res;
1375 int ret;
1376
1377 /*
1378 * We must access the NO_REBOOT bit over the Primary to Sideband
1379 * (P2SB) bridge.
1380 */
1381
1382 res = &tco_res[1];
1383 ret = p2sb_bar(pci_dev->bus, 0, res);
1384 if (ret)
1385 return ERR_PTR(ret);
1386
1387 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1388 res->start += SBREG_SMBCTRL_DNV;
1389 else
1390 res->start += SBREG_SMBCTRL;
1391
1392 res->end = res->start + 3;
1393
1394 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1395 tco_res, 2, &pldata, sizeof(pldata));
1396 }
1397
1398 static struct platform_device *
i801_add_tco_cnl(struct pci_dev * pci_dev,struct resource * tco_res)1399 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res)
1400 {
1401 static const struct itco_wdt_platform_data pldata = {
1402 .name = "Intel PCH",
1403 .version = 6,
1404 };
1405
1406 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1407 tco_res, 1, &pldata, sizeof(pldata));
1408 }
1409
i801_add_tco(struct i801_priv * priv)1410 static void i801_add_tco(struct i801_priv *priv)
1411 {
1412 struct pci_dev *pci_dev = priv->pci_dev;
1413 struct resource tco_res[2], *res;
1414 u32 tco_base, tco_ctl;
1415
1416 /* If we have ACPI based watchdog use that instead */
1417 if (acpi_has_watchdog())
1418 return;
1419
1420 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1421 return;
1422
1423 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1424 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1425 if (!(tco_ctl & TCOCTL_EN))
1426 return;
1427
1428 memset(tco_res, 0, sizeof(tco_res));
1429 /*
1430 * Always populate the main iTCO IO resource here. The second entry
1431 * for NO_REBOOT MMIO is filled by the SPT specific function.
1432 */
1433 res = &tco_res[0];
1434 res->start = tco_base & ~1;
1435 res->end = res->start + 32 - 1;
1436 res->flags = IORESOURCE_IO;
1437
1438 if (priv->features & FEATURE_TCO_CNL)
1439 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res);
1440 else
1441 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res);
1442
1443 if (IS_ERR(priv->tco_pdev))
1444 pci_warn(pci_dev, "failed to create iTCO device\n");
1445 }
1446
1447 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1448 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1449 acpi_physical_address address)
1450 {
1451 return address >= pci_resource_start(priv->pci_dev, SMBBAR) &&
1452 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1453 }
1454
1455 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1456 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1457 u64 *value, void *handler_context, void *region_context)
1458 {
1459 struct i801_priv *priv = handler_context;
1460 struct pci_dev *pdev = priv->pci_dev;
1461 acpi_status status;
1462
1463 /*
1464 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1465 * further access from the driver itself. This device is now owned
1466 * by the system firmware.
1467 */
1468 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1469
1470 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1471 priv->acpi_reserved = true;
1472
1473 pci_warn(pdev, "BIOS is accessing SMBus registers\n");
1474 pci_warn(pdev, "Driver SMBus register access inhibited\n");
1475
1476 /*
1477 * BIOS is accessing the host controller so prevent it from
1478 * suspending automatically from now on.
1479 */
1480 pm_runtime_get_sync(&pdev->dev);
1481 }
1482
1483 if ((function & ACPI_IO_MASK) == ACPI_READ)
1484 status = acpi_os_read_port(address, (u32 *)value, bits);
1485 else
1486 status = acpi_os_write_port(address, (u32)*value, bits);
1487
1488 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1489
1490 return status;
1491 }
1492
i801_acpi_probe(struct i801_priv * priv)1493 static int i801_acpi_probe(struct i801_priv *priv)
1494 {
1495 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1496 acpi_status status;
1497
1498 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1499 i801_acpi_io_handler, NULL, priv);
1500 if (ACPI_SUCCESS(status))
1501 return 0;
1502
1503 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1504 }
1505
i801_acpi_remove(struct i801_priv * priv)1506 static void i801_acpi_remove(struct i801_priv *priv)
1507 {
1508 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1509
1510 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1511 }
1512 #else
i801_acpi_probe(struct i801_priv * priv)1513 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1514 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1515 #endif
1516
i801_setup_hstcfg(struct i801_priv * priv)1517 static void i801_setup_hstcfg(struct i801_priv *priv)
1518 {
1519 unsigned char hstcfg = priv->original_hstcfg;
1520
1521 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1522 hstcfg |= SMBHSTCFG_HST_EN;
1523 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1524 }
1525
i801_restore_regs(struct i801_priv * priv)1526 static void i801_restore_regs(struct i801_priv *priv)
1527 {
1528 iowrite8(priv->original_hstcnt, SMBHSTCNT(priv));
1529 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1530 }
1531
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1532 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1533 {
1534 int err, i, bar = SMBBAR;
1535 struct i801_priv *priv;
1536
1537 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1538 if (!priv)
1539 return -ENOMEM;
1540
1541 i2c_set_adapdata(&priv->adapter, priv);
1542 priv->adapter.owner = THIS_MODULE;
1543 priv->adapter.class = I2C_CLASS_HWMON;
1544 priv->adapter.algo = &smbus_algorithm;
1545 priv->adapter.dev.parent = &dev->dev;
1546 acpi_use_parent_companion(&priv->adapter.dev);
1547 priv->adapter.retries = 3;
1548
1549 priv->pci_dev = dev;
1550 priv->features = id->driver_data;
1551
1552 /* Disable features on user request */
1553 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1554 if (priv->features & disable_features & (1 << i))
1555 pci_notice(dev, "%s disabled by user\n", i801_feature_names[i]);
1556 }
1557 priv->features &= ~disable_features;
1558
1559 /* The block process call uses block buffer mode */
1560 if (!(priv->features & FEATURE_BLOCK_BUFFER))
1561 priv->features &= ~FEATURE_BLOCK_PROC;
1562
1563 /*
1564 * Do not call pcim_enable_device(), because the device has to remain
1565 * enabled on driver detach. See i801_remove() for the reasoning.
1566 */
1567 err = pci_enable_device(dev);
1568 if (err) {
1569 pci_err(dev, "Failed to enable SMBus PCI device (%d)\n", err);
1570 return err;
1571 }
1572
1573 /* Determine the address of the SMBus area */
1574 if (!pci_resource_start(dev, SMBBAR)) {
1575 pci_err(dev, "SMBus base address uninitialized, upgrade BIOS\n");
1576 return -ENODEV;
1577 }
1578
1579 if (i801_acpi_probe(priv))
1580 return -ENODEV;
1581
1582 if (pci_resource_flags(dev, SMBBAR_MMIO) & IORESOURCE_MEM)
1583 bar = SMBBAR_MMIO;
1584
1585 priv->smba = pcim_iomap_region(dev, bar, DRV_NAME);
1586 if (IS_ERR(priv->smba)) {
1587 pci_err(dev, "Failed to request SMBus region %pr\n",
1588 pci_resource_n(dev, bar));
1589 i801_acpi_remove(priv);
1590 return PTR_ERR(priv->smba);
1591 }
1592
1593 pci_read_config_byte(dev, SMBHSTCFG, &priv->original_hstcfg);
1594 i801_setup_hstcfg(priv);
1595 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1596 pci_info(dev, "Enabling SMBus device\n");
1597
1598 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1599 pci_dbg(dev, "SMBus using interrupt SMI#\n");
1600 /* Disable SMBus interrupt feature if SMBus using SMI# */
1601 priv->features &= ~FEATURE_IRQ;
1602 }
1603 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1604 pci_info(dev, "SPD Write Disable is set\n");
1605
1606 /* Clear special mode bits */
1607 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1608 iowrite8(ioread8(SMBAUXCTL(priv)) &
1609 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1610
1611 /* Default timeout in interrupt mode: 200 ms */
1612 priv->adapter.timeout = HZ / 5;
1613
1614 if (dev->irq == IRQ_NOTCONNECTED)
1615 priv->features &= ~FEATURE_IRQ;
1616
1617 if (priv->features & FEATURE_IRQ) {
1618 u16 pcists;
1619
1620 /* Complain if an interrupt is already pending */
1621 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1622 if (pcists & PCI_STATUS_INTERRUPT)
1623 pci_warn(dev, "An interrupt is pending!\n");
1624 }
1625
1626 if (priv->features & FEATURE_IRQ) {
1627 init_completion(&priv->done);
1628
1629 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1630 IRQF_SHARED, DRV_NAME, priv);
1631 if (err) {
1632 pci_err(dev, "Failed to allocate irq %d: %d\n", dev->irq, err);
1633 priv->features &= ~FEATURE_IRQ;
1634 }
1635 }
1636 pci_info(dev, "SMBus using %s\n",
1637 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1638
1639 /* Host notification uses an interrupt */
1640 if (!(priv->features & FEATURE_IRQ))
1641 priv->features &= ~FEATURE_HOST_NOTIFY;
1642
1643 /* Remember original Interrupt and Host Notify settings */
1644 priv->original_hstcnt = ioread8(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1645 if (priv->features & FEATURE_HOST_NOTIFY)
1646 priv->original_slvcmd = ioread8(SMBSLVCMD(priv));
1647
1648 i801_add_tco(priv);
1649
1650 /*
1651 * adapter.name is used by platform code to find the main I801 adapter
1652 * to instantiante i2c_clients, do not change.
1653 */
1654 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1655 "SMBus %s adapter at %s",
1656 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1657 pci_name(dev));
1658
1659 err = i2c_add_adapter(&priv->adapter);
1660 if (err) {
1661 platform_device_unregister(priv->tco_pdev);
1662 i801_acpi_remove(priv);
1663 i801_restore_regs(priv);
1664 return err;
1665 }
1666
1667 i801_enable_host_notify(&priv->adapter);
1668
1669 /* We ignore errors - multiplexing is optional */
1670 i801_add_mux(priv);
1671 i801_probe_optional_targets(priv);
1672
1673 pci_set_drvdata(dev, priv);
1674
1675 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1676 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1677 pm_runtime_use_autosuspend(&dev->dev);
1678 pm_runtime_put_autosuspend(&dev->dev);
1679 pm_runtime_allow(&dev->dev);
1680
1681 return 0;
1682 }
1683
i801_remove(struct pci_dev * dev)1684 static void i801_remove(struct pci_dev *dev)
1685 {
1686 struct i801_priv *priv = pci_get_drvdata(dev);
1687
1688 i801_disable_host_notify(priv);
1689 i801_del_mux(priv);
1690 i2c_del_adapter(&priv->adapter);
1691 i801_acpi_remove(priv);
1692
1693 platform_device_unregister(priv->tco_pdev);
1694
1695 /* if acpi_reserved is set then usage_count is incremented already */
1696 if (!priv->acpi_reserved)
1697 pm_runtime_get_noresume(&dev->dev);
1698
1699 i801_restore_regs(priv);
1700
1701 /*
1702 * do not call pci_disable_device(dev) since it can cause hard hangs on
1703 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1704 */
1705 }
1706
i801_shutdown(struct pci_dev * dev)1707 static void i801_shutdown(struct pci_dev *dev)
1708 {
1709 struct i801_priv *priv = pci_get_drvdata(dev);
1710
1711 i801_disable_host_notify(priv);
1712 /* Restore config registers to avoid hard hang on some systems */
1713 i801_restore_regs(priv);
1714 }
1715
i801_suspend(struct device * dev)1716 static int i801_suspend(struct device *dev)
1717 {
1718 struct i801_priv *priv = dev_get_drvdata(dev);
1719
1720 i2c_mark_adapter_suspended(&priv->adapter);
1721 i801_restore_regs(priv);
1722
1723 return 0;
1724 }
1725
i801_resume(struct device * dev)1726 static int i801_resume(struct device *dev)
1727 {
1728 struct i801_priv *priv = dev_get_drvdata(dev);
1729
1730 i801_setup_hstcfg(priv);
1731 i801_enable_host_notify(&priv->adapter);
1732 i2c_mark_adapter_resumed(&priv->adapter);
1733
1734 return 0;
1735 }
1736
1737 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1738
1739 static struct pci_driver i801_driver = {
1740 .name = DRV_NAME,
1741 .id_table = i801_ids,
1742 .probe = i801_probe,
1743 .remove = i801_remove,
1744 .shutdown = i801_shutdown,
1745 .driver = {
1746 .pm = pm_sleep_ptr(&i801_pm_ops),
1747 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1748 },
1749 };
1750
i2c_i801_init(struct pci_driver * drv)1751 static int __init i2c_i801_init(struct pci_driver *drv)
1752 {
1753 if (dmi_name_in_vendors("FUJITSU"))
1754 input_apanel_init();
1755 return pci_register_driver(drv);
1756 }
1757
1758 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1759 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1760 MODULE_DESCRIPTION("I801 SMBus driver");
1761 MODULE_LICENSE("GPL");
1762
1763 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver);
1764