1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes
79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes
80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes
81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes
82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes
83 * Arrow Lake-H (SOC) 0x7722 32 hard yes yes yes
84 *
85 * Features supported by this driver:
86 * Software PEC no
87 * Hardware PEC yes
88 * Block buffer yes
89 * Block process call transaction yes
90 * I2C block read transaction yes (doesn't use the block buffer)
91 * Target mode no
92 * SMBus Host Notify yes
93 * Interrupt processing yes
94 *
95 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
96 */
97
98 #define DRV_NAME "i801_smbus"
99
100 #include <linux/interrupt.h>
101 #include <linux/module.h>
102 #include <linux/pci.h>
103 #include <linux/kernel.h>
104 #include <linux/stddef.h>
105 #include <linux/delay.h>
106 #include <linux/ioport.h>
107 #include <linux/init.h>
108 #include <linux/i2c.h>
109 #include <linux/i2c-mux.h>
110 #include <linux/i2c-smbus.h>
111 #include <linux/acpi.h>
112 #include <linux/io.h>
113 #include <linux/dmi.h>
114 #include <linux/slab.h>
115 #include <linux/string.h>
116 #include <linux/completion.h>
117 #include <linux/err.h>
118 #include <linux/platform_device.h>
119 #include <linux/platform_data/itco_wdt.h>
120 #include <linux/platform_data/x86/p2sb.h>
121 #include <linux/pm_runtime.h>
122 #include <linux/mutex.h>
123
124 #ifdef CONFIG_I2C_I801_MUX
125 #include <linux/gpio/machine.h>
126 #include <linux/platform_data/i2c-mux-gpio.h>
127 #endif
128
129 /* I801 SMBus address offsets */
130 #define SMBHSTSTS(p) (0 + (p)->smba)
131 #define SMBHSTCNT(p) (2 + (p)->smba)
132 #define SMBHSTCMD(p) (3 + (p)->smba)
133 #define SMBHSTADD(p) (4 + (p)->smba)
134 #define SMBHSTDAT0(p) (5 + (p)->smba)
135 #define SMBHSTDAT1(p) (6 + (p)->smba)
136 #define SMBBLKDAT(p) (7 + (p)->smba)
137 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
138 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
139 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
140 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
141 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
142 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
143
144 /* PCI Address Constants */
145 #define SMBBAR 4
146 #define SMBHSTCFG 0x040
147 #define TCOBASE 0x050
148 #define TCOCTL 0x054
149
150 #define SBREG_SMBCTRL 0xc6000c
151 #define SBREG_SMBCTRL_DNV 0xcf000c
152
153 /* Host configuration bits for SMBHSTCFG */
154 #define SMBHSTCFG_HST_EN BIT(0)
155 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
156 #define SMBHSTCFG_I2C_EN BIT(2)
157 #define SMBHSTCFG_SPD_WD BIT(4)
158
159 /* TCO configuration bits for TCOCTL */
160 #define TCOCTL_EN BIT(8)
161
162 /* Auxiliary status register bits, ICH4+ only */
163 #define SMBAUXSTS_CRCE BIT(0)
164 #define SMBAUXSTS_STCO BIT(1)
165
166 /* Auxiliary control register bits, ICH4+ only */
167 #define SMBAUXCTL_CRC BIT(0)
168 #define SMBAUXCTL_E32B BIT(1)
169
170 /* I801 command constants */
171 #define I801_QUICK 0x00
172 #define I801_BYTE 0x04
173 #define I801_BYTE_DATA 0x08
174 #define I801_WORD_DATA 0x0C
175 #define I801_PROC_CALL 0x10
176 #define I801_BLOCK_DATA 0x14
177 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
178 #define I801_BLOCK_PROC_CALL 0x1C
179
180 /* I801 Host Control register bits */
181 #define SMBHSTCNT_INTREN BIT(0)
182 #define SMBHSTCNT_KILL BIT(1)
183 #define SMBHSTCNT_LAST_BYTE BIT(5)
184 #define SMBHSTCNT_START BIT(6)
185 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
186
187 /* I801 Hosts Status register bits */
188 #define SMBHSTSTS_BYTE_DONE BIT(7)
189 #define SMBHSTSTS_INUSE_STS BIT(6)
190 #define SMBHSTSTS_SMBALERT_STS BIT(5)
191 #define SMBHSTSTS_FAILED BIT(4)
192 #define SMBHSTSTS_BUS_ERR BIT(3)
193 #define SMBHSTSTS_DEV_ERR BIT(2)
194 #define SMBHSTSTS_INTR BIT(1)
195 #define SMBHSTSTS_HOST_BUSY BIT(0)
196
197 /* Host Notify Status register bits */
198 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
199
200 /* Host Notify Command register bits */
201 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
202 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
203
204 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
205 SMBHSTSTS_DEV_ERR)
206
207 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
208 STATUS_ERROR_FLAGS)
209
210 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1)
211
212 /* Older devices have their ID defined in <linux/pci_ids.h> */
213 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
214 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
215 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
216 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
217 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
218 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
219 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
221 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
222 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
223 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
224 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
225 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
226 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
227 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
228 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
229 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
230 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
231 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
232 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
233 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
234 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
235 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
236 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
237 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
238 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
239 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796
240 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
241 #define PCI_DEVICE_ID_INTEL_ARROW_LAKE_H_SMBUS 0x7722
242 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23
243 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
244 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22
245 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23
246 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
247 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
248 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
249 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
250 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
251 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
252 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
253 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
254 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
255 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
256 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
257 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
258 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
259 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
260 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
261 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
262 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
263 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22
264
265 struct i801_mux_config {
266 char *gpio_chip;
267 unsigned values[3];
268 int n_values;
269 unsigned gpios[2]; /* Relative to gpio_chip->base */
270 int n_gpios;
271 };
272
273 struct i801_priv {
274 struct i2c_adapter adapter;
275 unsigned long smba;
276 unsigned char original_hstcfg;
277 unsigned char original_hstcnt;
278 unsigned char original_slvcmd;
279 struct pci_dev *pci_dev;
280 unsigned int features;
281
282 /* isr processing */
283 struct completion done;
284 u8 status;
285
286 /* Command state used by isr for byte-by-byte block transactions */
287 u8 cmd;
288 bool is_read;
289 int count;
290 int len;
291 u8 *data;
292
293 #ifdef CONFIG_I2C_I801_MUX
294 struct platform_device *mux_pdev;
295 struct gpiod_lookup_table *lookup;
296 struct notifier_block mux_notifier_block;
297 #endif
298 struct platform_device *tco_pdev;
299
300 /*
301 * If set to true the host controller registers are reserved for
302 * ACPI AML use.
303 */
304 bool acpi_reserved;
305 };
306
307 #define FEATURE_SMBUS_PEC BIT(0)
308 #define FEATURE_BLOCK_BUFFER BIT(1)
309 #define FEATURE_BLOCK_PROC BIT(2)
310 #define FEATURE_I2C_BLOCK_READ BIT(3)
311 #define FEATURE_IRQ BIT(4)
312 #define FEATURE_HOST_NOTIFY BIT(5)
313 /* Not really a feature, but it's convenient to handle it as such */
314 #define FEATURE_IDF BIT(15)
315 #define FEATURE_TCO_SPT BIT(16)
316 #define FEATURE_TCO_CNL BIT(17)
317
318 static const char *i801_feature_names[] = {
319 "SMBus PEC",
320 "Block buffer",
321 "Block process call",
322 "I2C block read",
323 "Interrupt",
324 "SMBus Host Notify",
325 };
326
327 static unsigned int disable_features;
328 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
329 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
330 "\t\t 0x01 disable SMBus PEC\n"
331 "\t\t 0x02 disable the block buffer\n"
332 "\t\t 0x08 disable the I2C block read functionality\n"
333 "\t\t 0x10 don't use interrupts\n"
334 "\t\t 0x20 disable SMBus Host Notify ");
335
i801_get_block_len(struct i801_priv * priv)336 static int i801_get_block_len(struct i801_priv *priv)
337 {
338 u8 len = inb_p(SMBHSTDAT0(priv));
339
340 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
341 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len);
342 return -EPROTO;
343 }
344
345 return len;
346 }
347
i801_check_and_clear_pec_error(struct i801_priv * priv)348 static int i801_check_and_clear_pec_error(struct i801_priv *priv)
349 {
350 u8 status;
351
352 if (!(priv->features & FEATURE_SMBUS_PEC))
353 return 0;
354
355 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
356 if (status) {
357 outb_p(status, SMBAUXSTS(priv));
358 return -EBADMSG;
359 }
360
361 return 0;
362 }
363
364 /* Make sure the SMBus host is ready to start transmitting.
365 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)366 static int i801_check_pre(struct i801_priv *priv)
367 {
368 int status, result;
369
370 status = inb_p(SMBHSTSTS(priv));
371 if (status & SMBHSTSTS_HOST_BUSY) {
372 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
373 return -EBUSY;
374 }
375
376 status &= STATUS_FLAGS;
377 if (status) {
378 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
379 outb_p(status, SMBHSTSTS(priv));
380 }
381
382 /*
383 * Clear CRC status if needed.
384 * During normal operation, i801_check_post() takes care
385 * of it after every operation. We do it here only in case
386 * the hardware was already in this state when the driver
387 * started.
388 */
389 result = i801_check_and_clear_pec_error(priv);
390 if (result)
391 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n");
392
393 return 0;
394 }
395
i801_check_post(struct i801_priv * priv,int status)396 static int i801_check_post(struct i801_priv *priv, int status)
397 {
398 int result = 0;
399
400 /*
401 * If the SMBus is still busy, we give up
402 */
403 if (unlikely(status < 0)) {
404 /* try to stop the current command */
405 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
406 usleep_range(1000, 2000);
407 outb_p(0, SMBHSTCNT(priv));
408
409 /* Check if it worked */
410 status = inb_p(SMBHSTSTS(priv));
411 if ((status & SMBHSTSTS_HOST_BUSY) ||
412 !(status & SMBHSTSTS_FAILED))
413 dev_dbg(&priv->pci_dev->dev,
414 "Failed terminating the transaction\n");
415 return -ETIMEDOUT;
416 }
417
418 if (status & SMBHSTSTS_FAILED) {
419 result = -EIO;
420 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
421 }
422 if (status & SMBHSTSTS_DEV_ERR) {
423 /*
424 * This may be a PEC error, check and clear it.
425 *
426 * AUXSTS is handled differently from HSTSTS.
427 * For HSTSTS, i801_isr() or i801_wait_intr()
428 * has already cleared the error bits in hardware,
429 * and we are passed a copy of the original value
430 * in "status".
431 * For AUXSTS, the hardware register is left
432 * for us to handle here.
433 * This is asymmetric, slightly iffy, but safe,
434 * since all this code is serialized and the CRCE
435 * bit is harmless as long as it's cleared before
436 * the next operation.
437 */
438 result = i801_check_and_clear_pec_error(priv);
439 if (result) {
440 pci_dbg(priv->pci_dev, "PEC error\n");
441 } else {
442 result = -ENXIO;
443 pci_dbg(priv->pci_dev, "No response\n");
444 }
445 }
446 if (status & SMBHSTSTS_BUS_ERR) {
447 result = -EAGAIN;
448 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
449 }
450
451 return result;
452 }
453
454 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)455 static int i801_wait_intr(struct i801_priv *priv)
456 {
457 unsigned long timeout = jiffies + priv->adapter.timeout;
458 int status, busy;
459
460 do {
461 usleep_range(250, 500);
462 status = inb_p(SMBHSTSTS(priv));
463 busy = status & SMBHSTSTS_HOST_BUSY;
464 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
465 if (!busy && status)
466 return status & STATUS_ERROR_FLAGS;
467 } while (time_is_after_eq_jiffies(timeout));
468
469 return -ETIMEDOUT;
470 }
471
472 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)473 static int i801_wait_byte_done(struct i801_priv *priv)
474 {
475 unsigned long timeout = jiffies + priv->adapter.timeout;
476 int status;
477
478 do {
479 usleep_range(250, 500);
480 status = inb_p(SMBHSTSTS(priv));
481 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
482 return status & STATUS_ERROR_FLAGS;
483 } while (time_is_after_eq_jiffies(timeout));
484
485 return -ETIMEDOUT;
486 }
487
i801_transaction(struct i801_priv * priv,int xact)488 static int i801_transaction(struct i801_priv *priv, int xact)
489 {
490 unsigned long result;
491 const struct i2c_adapter *adap = &priv->adapter;
492
493 if (priv->features & FEATURE_IRQ) {
494 reinit_completion(&priv->done);
495 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
496 SMBHSTCNT(priv));
497 result = wait_for_completion_timeout(&priv->done, adap->timeout);
498 return result ? priv->status : -ETIMEDOUT;
499 }
500
501 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
502
503 return i801_wait_intr(priv);
504 }
505
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)506 static int i801_block_transaction_by_block(struct i801_priv *priv,
507 union i2c_smbus_data *data,
508 char read_write, int command)
509 {
510 int i, len, status, xact;
511
512 switch (command) {
513 case I2C_SMBUS_BLOCK_PROC_CALL:
514 xact = I801_BLOCK_PROC_CALL;
515 break;
516 case I2C_SMBUS_BLOCK_DATA:
517 xact = I801_BLOCK_DATA;
518 break;
519 default:
520 return -EOPNOTSUPP;
521 }
522
523 /* Set block buffer mode */
524 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
525
526 if (read_write == I2C_SMBUS_WRITE) {
527 len = data->block[0];
528 outb_p(len, SMBHSTDAT0(priv));
529 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
530 for (i = 0; i < len; i++)
531 outb_p(data->block[i+1], SMBBLKDAT(priv));
532 }
533
534 status = i801_transaction(priv, xact);
535 if (status)
536 goto out;
537
538 if (read_write == I2C_SMBUS_READ ||
539 command == I2C_SMBUS_BLOCK_PROC_CALL) {
540 len = i801_get_block_len(priv);
541 if (len < 0) {
542 status = len;
543 goto out;
544 }
545
546 data->block[0] = len;
547 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
548 for (i = 0; i < len; i++)
549 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
550 }
551 out:
552 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
553 return status;
554 }
555
i801_isr_byte_done(struct i801_priv * priv)556 static void i801_isr_byte_done(struct i801_priv *priv)
557 {
558 if (priv->is_read) {
559 /*
560 * At transfer start i801_smbus_block_transaction() marks
561 * the block length as invalid. Check for this sentinel value
562 * and read the block length from SMBHSTDAT0.
563 */
564 if (priv->len == SMBUS_LEN_SENTINEL) {
565 priv->len = i801_get_block_len(priv);
566 if (priv->len < 0)
567 /* FIXME: Recover */
568 priv->len = I2C_SMBUS_BLOCK_MAX;
569
570 priv->data[-1] = priv->len;
571 }
572
573 /* Read next byte */
574 if (priv->count < priv->len)
575 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
576 else
577 dev_dbg(&priv->pci_dev->dev,
578 "Discarding extra byte on block read\n");
579
580 /* Set LAST_BYTE for last byte of read transaction */
581 if (priv->count == priv->len - 1)
582 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
583 SMBHSTCNT(priv));
584 } else if (priv->count < priv->len - 1) {
585 /* Write next byte, except for IRQ after last byte */
586 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
587 }
588 }
589
i801_host_notify_isr(struct i801_priv * priv)590 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
591 {
592 unsigned short addr;
593
594 addr = inb_p(SMBNTFDADD(priv)) >> 1;
595
596 /*
597 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
598 * always returns 0. Our current implementation doesn't provide
599 * data, so we just ignore it.
600 */
601 i2c_handle_smbus_host_notify(&priv->adapter, addr);
602
603 /* clear Host Notify bit and return */
604 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
605 return IRQ_HANDLED;
606 }
607
608 /*
609 * There are three kinds of interrupts:
610 *
611 * 1) i801 signals transaction completion with one of these interrupts:
612 * INTR - Success
613 * DEV_ERR - Invalid command, NAK or communication timeout
614 * BUS_ERR - SMI# transaction collision
615 * FAILED - transaction was canceled due to a KILL request
616 * When any of these occur, update ->status and signal completion.
617 *
618 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
619 * occurs for each byte of a byte-by-byte to prepare the next byte.
620 *
621 * 3) Host Notify interrupts
622 */
i801_isr(int irq,void * dev_id)623 static irqreturn_t i801_isr(int irq, void *dev_id)
624 {
625 struct i801_priv *priv = dev_id;
626 u16 pcists;
627 u8 status;
628
629 /* Confirm this is our interrupt */
630 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
631 if (!(pcists & PCI_STATUS_INTERRUPT))
632 return IRQ_NONE;
633
634 if (priv->features & FEATURE_HOST_NOTIFY) {
635 status = inb_p(SMBSLVSTS(priv));
636 if (status & SMBSLVSTS_HST_NTFY_STS)
637 return i801_host_notify_isr(priv);
638 }
639
640 status = inb_p(SMBHSTSTS(priv));
641 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
642 i801_isr_byte_done(priv);
643
644 /*
645 * Clear IRQ sources: SMB_ALERT status is set after signal assertion
646 * independently of the interrupt generation being blocked or not
647 * so clear it always when the status is set.
648 */
649 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
650 outb_p(status, SMBHSTSTS(priv));
651
652 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
653 if (status) {
654 priv->status = status & STATUS_ERROR_FLAGS;
655 complete(&priv->done);
656 }
657
658 return IRQ_HANDLED;
659 }
660
661 /*
662 * For "byte-by-byte" block transactions:
663 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
664 * I2C read uses cmd=I801_I2C_BLOCK_DATA
665 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)666 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
667 union i2c_smbus_data *data,
668 char read_write, int command)
669 {
670 int i, len;
671 int smbcmd;
672 int status;
673 unsigned long result;
674 const struct i2c_adapter *adap = &priv->adapter;
675
676 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
677 return -EOPNOTSUPP;
678
679 len = data->block[0];
680
681 if (read_write == I2C_SMBUS_WRITE) {
682 outb_p(len, SMBHSTDAT0(priv));
683 outb_p(data->block[1], SMBBLKDAT(priv));
684 }
685
686 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
687 read_write == I2C_SMBUS_READ)
688 smbcmd = I801_I2C_BLOCK_DATA;
689 else
690 smbcmd = I801_BLOCK_DATA;
691
692 if (priv->features & FEATURE_IRQ) {
693 priv->is_read = (read_write == I2C_SMBUS_READ);
694 if (len == 1 && priv->is_read)
695 smbcmd |= SMBHSTCNT_LAST_BYTE;
696 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
697 priv->len = len;
698 priv->count = 0;
699 priv->data = &data->block[1];
700
701 reinit_completion(&priv->done);
702 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
703 result = wait_for_completion_timeout(&priv->done, adap->timeout);
704 return result ? priv->status : -ETIMEDOUT;
705 }
706
707 if (len == 1 && read_write == I2C_SMBUS_READ)
708 smbcmd |= SMBHSTCNT_LAST_BYTE;
709 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
710
711 for (i = 1; i <= len; i++) {
712 status = i801_wait_byte_done(priv);
713 if (status)
714 return status;
715
716 /*
717 * At transfer start i801_smbus_block_transaction() marks
718 * the block length as invalid. Check for this sentinel value
719 * and read the block length from SMBHSTDAT0.
720 */
721 if (len == SMBUS_LEN_SENTINEL) {
722 len = i801_get_block_len(priv);
723 if (len < 0) {
724 /* Recover */
725 while (inb_p(SMBHSTSTS(priv)) &
726 SMBHSTSTS_HOST_BUSY)
727 outb_p(SMBHSTSTS_BYTE_DONE,
728 SMBHSTSTS(priv));
729 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
730 return -EPROTO;
731 }
732 data->block[0] = len;
733 }
734
735 if (read_write == I2C_SMBUS_READ) {
736 data->block[i] = inb_p(SMBBLKDAT(priv));
737 if (i == len - 1)
738 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
739 }
740
741 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
742 outb_p(data->block[i+1], SMBBLKDAT(priv));
743
744 /* signals SMBBLKDAT ready */
745 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
746 }
747
748 return i801_wait_intr(priv);
749 }
750
i801_set_hstadd(struct i801_priv * priv,u8 addr,char read_write)751 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
752 {
753 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
754 }
755
756 /* Single value transaction function */
i801_simple_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)757 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
758 u8 addr, u8 hstcmd, char read_write, int command)
759 {
760 int xact, ret;
761
762 switch (command) {
763 case I2C_SMBUS_QUICK:
764 i801_set_hstadd(priv, addr, read_write);
765 xact = I801_QUICK;
766 break;
767 case I2C_SMBUS_BYTE:
768 i801_set_hstadd(priv, addr, read_write);
769 if (read_write == I2C_SMBUS_WRITE)
770 outb_p(hstcmd, SMBHSTCMD(priv));
771 xact = I801_BYTE;
772 break;
773 case I2C_SMBUS_BYTE_DATA:
774 i801_set_hstadd(priv, addr, read_write);
775 if (read_write == I2C_SMBUS_WRITE)
776 outb_p(data->byte, SMBHSTDAT0(priv));
777 outb_p(hstcmd, SMBHSTCMD(priv));
778 xact = I801_BYTE_DATA;
779 break;
780 case I2C_SMBUS_WORD_DATA:
781 i801_set_hstadd(priv, addr, read_write);
782 if (read_write == I2C_SMBUS_WRITE) {
783 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
784 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
785 }
786 outb_p(hstcmd, SMBHSTCMD(priv));
787 xact = I801_WORD_DATA;
788 break;
789 case I2C_SMBUS_PROC_CALL:
790 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
791 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
792 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
793 outb_p(hstcmd, SMBHSTCMD(priv));
794 read_write = I2C_SMBUS_READ;
795 xact = I801_PROC_CALL;
796 break;
797 default:
798 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command);
799 return -EOPNOTSUPP;
800 }
801
802 ret = i801_transaction(priv, xact);
803 if (ret || read_write == I2C_SMBUS_WRITE)
804 return ret;
805
806 switch (command) {
807 case I2C_SMBUS_BYTE:
808 case I2C_SMBUS_BYTE_DATA:
809 data->byte = inb_p(SMBHSTDAT0(priv));
810 break;
811 case I2C_SMBUS_WORD_DATA:
812 case I2C_SMBUS_PROC_CALL:
813 data->word = inb_p(SMBHSTDAT0(priv)) +
814 (inb_p(SMBHSTDAT1(priv)) << 8);
815 break;
816 }
817
818 return 0;
819 }
820
i801_smbus_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)821 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
822 u8 addr, u8 hstcmd, char read_write, int command)
823 {
824 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
825 /* Mark block length as invalid */
826 data->block[0] = SMBUS_LEN_SENTINEL;
827 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
828 return -EPROTO;
829
830 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
831 /* Needs to be flagged as write transaction */
832 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
833 else
834 i801_set_hstadd(priv, addr, read_write);
835 outb_p(hstcmd, SMBHSTCMD(priv));
836
837 if (priv->features & FEATURE_BLOCK_BUFFER)
838 return i801_block_transaction_by_block(priv, data, read_write, command);
839 else
840 return i801_block_transaction_byte_by_byte(priv, data, read_write, command);
841 }
842
i801_i2c_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,u8 addr,u8 hstcmd,char read_write,int command)843 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
844 u8 addr, u8 hstcmd, char read_write, int command)
845 {
846 int result;
847 u8 hostc;
848
849 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
850 return -EPROTO;
851 /*
852 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here,
853 * even when reading. However if SPD Write Disable is set (Lynx Point and later),
854 * the read will fail if we don't set the R/#W bit.
855 */
856 i801_set_hstadd(priv, addr,
857 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE);
858
859 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */
860 if (read_write == I2C_SMBUS_READ)
861 outb_p(hstcmd, SMBHSTDAT1(priv));
862 else
863 outb_p(hstcmd, SMBHSTCMD(priv));
864
865 if (read_write == I2C_SMBUS_WRITE) {
866 /* set I2C_EN bit in configuration register */
867 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
868 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN);
869 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
870 pci_err(priv->pci_dev, "I2C block read is unsupported!\n");
871 return -EOPNOTSUPP;
872 }
873
874 /* Block buffer isn't supported for I2C block transactions */
875 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command);
876
877 /* restore saved configuration register value */
878 if (read_write == I2C_SMBUS_WRITE)
879 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
880
881 return result;
882 }
883
884 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)885 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
886 unsigned short flags, char read_write, u8 command,
887 int size, union i2c_smbus_data *data)
888 {
889 int hwpec, ret;
890 struct i801_priv *priv = i2c_get_adapdata(adap);
891
892 if (priv->acpi_reserved)
893 return -EBUSY;
894
895 pm_runtime_get_sync(&priv->pci_dev->dev);
896
897 ret = i801_check_pre(priv);
898 if (ret)
899 goto out;
900
901 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
902 && size != I2C_SMBUS_QUICK
903 && size != I2C_SMBUS_I2C_BLOCK_DATA;
904
905 if (hwpec) /* enable/disable hardware PEC */
906 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
907 else
908 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
909 SMBAUXCTL(priv));
910
911 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL)
912 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size);
913 else if (size == I2C_SMBUS_I2C_BLOCK_DATA)
914 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size);
915 else
916 ret = i801_simple_transaction(priv, data, addr, command, read_write, size);
917
918 ret = i801_check_post(priv, ret);
919
920 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
921 * time, so we forcibly disable it after every transaction.
922 */
923 if (hwpec)
924 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
925 out:
926 /*
927 * Unlock the SMBus device for use by BIOS/ACPI,
928 * and clear status flags if not done already.
929 */
930 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
931
932 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
933 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
934 return ret;
935 }
936
937
i801_func(struct i2c_adapter * adapter)938 static u32 i801_func(struct i2c_adapter *adapter)
939 {
940 struct i801_priv *priv = i2c_get_adapdata(adapter);
941
942 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
943 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
944 I2C_FUNC_SMBUS_PROC_CALL |
945 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
946 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
947 ((priv->features & FEATURE_BLOCK_PROC) ?
948 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
949 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
950 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
951 ((priv->features & FEATURE_HOST_NOTIFY) ?
952 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
953 }
954
i801_enable_host_notify(struct i2c_adapter * adapter)955 static void i801_enable_host_notify(struct i2c_adapter *adapter)
956 {
957 struct i801_priv *priv = i2c_get_adapdata(adapter);
958
959 if (!(priv->features & FEATURE_HOST_NOTIFY))
960 return;
961
962 /*
963 * Enable host notify interrupt and block the generation of interrupt
964 * from the SMB_ALERT signal because the driver does not support
965 * SMBus Alert.
966 */
967 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
968 priv->original_slvcmd, SMBSLVCMD(priv));
969
970 /* clear Host Notify bit to allow a new notification */
971 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
972 }
973
i801_disable_host_notify(struct i801_priv * priv)974 static void i801_disable_host_notify(struct i801_priv *priv)
975 {
976 if (!(priv->features & FEATURE_HOST_NOTIFY))
977 return;
978
979 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
980 }
981
982 static const struct i2c_algorithm smbus_algorithm = {
983 .smbus_xfer = i801_access,
984 .functionality = i801_func,
985 };
986
987 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
988 FEATURE_HOST_NOTIFY)
989 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \
990 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ)
991
992 static const struct pci_device_id i801_ids[] = {
993 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) },
994 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) },
995 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) },
996 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) },
997 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) },
998 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) },
999 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) },
1000 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) },
1001 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) },
1002 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) },
1003 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) },
1004 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) },
1005 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) },
1006 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) },
1007 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) },
1008 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) },
1009 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) },
1010 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) },
1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) },
1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) },
1013 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) },
1014 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) },
1015 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) },
1016 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) },
1017 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) },
1018 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) },
1019 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) },
1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) },
1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) },
1022 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) },
1023 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) },
1024 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) },
1025 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) },
1026 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) },
1027 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) },
1028 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) },
1029 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1030 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1031 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1033 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1034 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) },
1035 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1036 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1038 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1045 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057 { PCI_DEVICE_DATA(INTEL, ARROW_LAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058 { 0, }
1059 };
1060
1061 MODULE_DEVICE_TABLE(pci, i801_ids);
1062
1063 #if defined CONFIG_X86 && defined CONFIG_DMI
1064 static unsigned char apanel_addr __ro_after_init;
1065
1066 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1067 static __init const void __iomem *bios_signature(const void __iomem *bios)
1068 {
1069 ssize_t offset;
1070 const unsigned char signature[] = "FJKEYINF";
1071
1072 for (offset = 0; offset < 0x10000; offset += 0x10) {
1073 if (check_signature(bios + offset, signature,
1074 sizeof(signature)-1))
1075 return bios + offset;
1076 }
1077 return NULL;
1078 }
1079
input_apanel_init(void)1080 static void __init input_apanel_init(void)
1081 {
1082 void __iomem *bios;
1083 const void __iomem *p;
1084
1085 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1086 p = bios_signature(bios);
1087 if (p) {
1088 /* just use the first address */
1089 apanel_addr = readb(p + 8 + 3) >> 1;
1090 }
1091 iounmap(bios);
1092 }
1093
1094 struct dmi_onboard_device_info {
1095 const char *name;
1096 u8 type;
1097 unsigned short i2c_addr;
1098 const char *i2c_type;
1099 };
1100
1101 static const struct dmi_onboard_device_info dmi_devices[] = {
1102 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1103 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1104 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1105 };
1106
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1107 static void dmi_check_onboard_device(u8 type, const char *name,
1108 struct i2c_adapter *adap)
1109 {
1110 int i;
1111 struct i2c_board_info info;
1112
1113 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1114 /* & ~0x80, ignore enabled/disabled bit */
1115 if ((type & ~0x80) != dmi_devices[i].type)
1116 continue;
1117 if (strcasecmp(name, dmi_devices[i].name))
1118 continue;
1119
1120 memset(&info, 0, sizeof(struct i2c_board_info));
1121 info.addr = dmi_devices[i].i2c_addr;
1122 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1123 i2c_new_client_device(adap, &info);
1124 break;
1125 }
1126 }
1127
1128 /* We use our own function to check for onboard devices instead of
1129 dmi_find_device() as some buggy BIOS's have the devices we are interested
1130 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1131 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1132 {
1133 int i, count;
1134
1135 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE)
1136 return;
1137
1138 count = (dm->length - sizeof(struct dmi_header)) / 2;
1139 for (i = 0; i < count; i++) {
1140 const u8 *d = (char *)(dm + 1) + (i * 2);
1141 const char *name = ((char *) dm) + dm->length;
1142 u8 type = d[0];
1143 u8 s = d[1];
1144
1145 if (!s)
1146 continue;
1147 s--;
1148 while (s > 0 && name[0]) {
1149 name += strlen(name) + 1;
1150 s--;
1151 }
1152 if (name[0] == 0) /* Bogus string reference */
1153 continue;
1154
1155 dmi_check_onboard_device(type, name, adap);
1156 }
1157 }
1158
1159 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1160 static const char *const acpi_smo8800_ids[] = {
1161 "SMO8800",
1162 "SMO8801",
1163 "SMO8810",
1164 "SMO8811",
1165 "SMO8820",
1166 "SMO8821",
1167 "SMO8830",
1168 "SMO8831",
1169 };
1170
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1171 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1172 u32 nesting_level,
1173 void *context,
1174 void **return_value)
1175 {
1176 struct acpi_device_info *info;
1177 acpi_status status;
1178 char *hid;
1179 int i;
1180
1181 status = acpi_get_object_info(obj_handle, &info);
1182 if (ACPI_FAILURE(status))
1183 return AE_OK;
1184
1185 if (!(info->valid & ACPI_VALID_HID))
1186 goto smo88xx_not_found;
1187
1188 hid = info->hardware_id.string;
1189 if (!hid)
1190 goto smo88xx_not_found;
1191
1192 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1193 if (i < 0)
1194 goto smo88xx_not_found;
1195
1196 kfree(info);
1197
1198 *return_value = NULL;
1199 return AE_CTRL_TERMINATE;
1200
1201 smo88xx_not_found:
1202 kfree(info);
1203 return AE_OK;
1204 }
1205
is_dell_system_with_lis3lv02d(void)1206 static bool is_dell_system_with_lis3lv02d(void)
1207 {
1208 void *err = ERR_PTR(-ENOENT);
1209
1210 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1211 return false;
1212
1213 /*
1214 * Check that ACPI device SMO88xx is present and is functioning.
1215 * Function acpi_get_devices() already filters all ACPI devices
1216 * which are not present or are not functioning.
1217 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1218 * accelerometer but unfortunately ACPI does not provide any other
1219 * information (like I2C address).
1220 */
1221 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1222
1223 return !IS_ERR(err);
1224 }
1225
1226 /*
1227 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1228 * so it is needed to define mapping table based on DMI product names.
1229 */
1230 static const struct {
1231 const char *dmi_product_name;
1232 unsigned short i2c_addr;
1233 } dell_lis3lv02d_devices[] = {
1234 /*
1235 * Dell platform team told us that these Latitude devices have
1236 * ST microelectronics accelerometer at I2C address 0x29.
1237 */
1238 { "Latitude E5250", 0x29 },
1239 { "Latitude E5450", 0x29 },
1240 { "Latitude E5550", 0x29 },
1241 { "Latitude E6440", 0x29 },
1242 { "Latitude E6440 ATG", 0x29 },
1243 { "Latitude E6540", 0x29 },
1244 /*
1245 * Additional individual entries were added after verification.
1246 */
1247 { "Latitude 5480", 0x29 },
1248 { "Precision 3540", 0x29 },
1249 { "Vostro V131", 0x1d },
1250 { "Vostro 5568", 0x29 },
1251 { "XPS 15 7590", 0x29 },
1252 };
1253
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1254 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1255 {
1256 struct i2c_board_info info;
1257 const char *dmi_product_name;
1258 int i;
1259
1260 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1261 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1262 if (strcmp(dmi_product_name,
1263 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1264 break;
1265 }
1266
1267 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1268 dev_warn(&priv->pci_dev->dev,
1269 "Accelerometer lis3lv02d is present on SMBus but its"
1270 " address is unknown, skipping registration\n");
1271 return;
1272 }
1273
1274 memset(&info, 0, sizeof(struct i2c_board_info));
1275 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1276 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1277 i2c_new_client_device(&priv->adapter, &info);
1278 }
1279
1280 /* Register optional targets */
i801_probe_optional_targets(struct i801_priv * priv)1281 static void i801_probe_optional_targets(struct i801_priv *priv)
1282 {
1283 /* Only register targets on main SMBus channel */
1284 if (priv->features & FEATURE_IDF)
1285 return;
1286
1287 if (apanel_addr) {
1288 struct i2c_board_info info = {
1289 .addr = apanel_addr,
1290 .type = "fujitsu_apanel",
1291 };
1292
1293 i2c_new_client_device(&priv->adapter, &info);
1294 }
1295
1296 if (dmi_name_in_vendors("FUJITSU"))
1297 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1298
1299 if (is_dell_system_with_lis3lv02d())
1300 register_dell_lis3lv02d_i2c_device(priv);
1301
1302 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1303 #ifdef CONFIG_I2C_I801_MUX
1304 if (!priv->mux_pdev)
1305 #endif
1306 i2c_register_spd(&priv->adapter);
1307 }
1308 #else
input_apanel_init(void)1309 static void __init input_apanel_init(void) {}
i801_probe_optional_targets(struct i801_priv * priv)1310 static void i801_probe_optional_targets(struct i801_priv *priv) {}
1311 #endif /* CONFIG_X86 && CONFIG_DMI */
1312
1313 #ifdef CONFIG_I2C_I801_MUX
1314 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1315 .gpio_chip = "gpio_ich",
1316 .values = { 0x02, 0x03 },
1317 .n_values = 2,
1318 .gpios = { 52, 53 },
1319 .n_gpios = 2,
1320 };
1321
1322 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1323 .gpio_chip = "gpio_ich",
1324 .values = { 0x02, 0x03, 0x01 },
1325 .n_values = 3,
1326 .gpios = { 52, 53 },
1327 .n_gpios = 2,
1328 };
1329
1330 static const struct dmi_system_id mux_dmi_table[] = {
1331 {
1332 .matches = {
1333 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1334 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1335 },
1336 .driver_data = &i801_mux_config_asus_z8_d12,
1337 },
1338 {
1339 .matches = {
1340 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1341 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1342 },
1343 .driver_data = &i801_mux_config_asus_z8_d12,
1344 },
1345 {
1346 .matches = {
1347 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1348 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1349 },
1350 .driver_data = &i801_mux_config_asus_z8_d12,
1351 },
1352 {
1353 .matches = {
1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1355 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1356 },
1357 .driver_data = &i801_mux_config_asus_z8_d12,
1358 },
1359 {
1360 .matches = {
1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1362 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1363 },
1364 .driver_data = &i801_mux_config_asus_z8_d12,
1365 },
1366 {
1367 .matches = {
1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1369 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1370 },
1371 .driver_data = &i801_mux_config_asus_z8_d12,
1372 },
1373 {
1374 .matches = {
1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1377 },
1378 .driver_data = &i801_mux_config_asus_z8_d18,
1379 },
1380 {
1381 .matches = {
1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1383 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1384 },
1385 .driver_data = &i801_mux_config_asus_z8_d18,
1386 },
1387 {
1388 .matches = {
1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1390 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1391 },
1392 .driver_data = &i801_mux_config_asus_z8_d12,
1393 },
1394 { }
1395 };
1396
i801_notifier_call(struct notifier_block * nb,unsigned long action,void * data)1397 static int i801_notifier_call(struct notifier_block *nb, unsigned long action,
1398 void *data)
1399 {
1400 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block);
1401 struct device *dev = data;
1402
1403 if (action != BUS_NOTIFY_ADD_DEVICE ||
1404 dev->type != &i2c_adapter_type ||
1405 i2c_root_adapter(dev) != &priv->adapter)
1406 return NOTIFY_DONE;
1407
1408 /* Call i2c_register_spd for muxed child segments */
1409 i2c_register_spd(to_i2c_adapter(dev));
1410
1411 return NOTIFY_OK;
1412 }
1413
1414 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1415 static void i801_add_mux(struct i801_priv *priv)
1416 {
1417 struct device *dev = &priv->adapter.dev;
1418 const struct i801_mux_config *mux_config;
1419 struct i2c_mux_gpio_platform_data gpio_data;
1420 struct gpiod_lookup_table *lookup;
1421 const struct dmi_system_id *id;
1422 int i;
1423
1424 id = dmi_first_match(mux_dmi_table);
1425 if (!id)
1426 return;
1427
1428 mux_config = id->driver_data;
1429
1430 /* Prepare the platform data */
1431 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1432 gpio_data.parent = priv->adapter.nr;
1433 gpio_data.values = mux_config->values;
1434 gpio_data.n_values = mux_config->n_values;
1435 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1436
1437 /* Register GPIO descriptor lookup table */
1438 lookup = devm_kzalloc(dev,
1439 struct_size(lookup, table, mux_config->n_gpios + 1),
1440 GFP_KERNEL);
1441 if (!lookup)
1442 return;
1443 lookup->dev_id = "i2c-mux-gpio";
1444 for (i = 0; i < mux_config->n_gpios; i++)
1445 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1446 mux_config->gpios[i], "mux", 0);
1447 gpiod_add_lookup_table(lookup);
1448
1449 priv->mux_notifier_block.notifier_call = i801_notifier_call;
1450 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block))
1451 return;
1452 /*
1453 * Register the mux device, we use PLATFORM_DEVID_NONE here
1454 * because since we are referring to the GPIO chip by name we are
1455 * anyways in deep trouble if there is more than one of these
1456 * devices, and there should likely only be one platform controller
1457 * hub.
1458 */
1459 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1460 PLATFORM_DEVID_NONE, &gpio_data,
1461 sizeof(struct i2c_mux_gpio_platform_data));
1462 if (IS_ERR(priv->mux_pdev)) {
1463 gpiod_remove_lookup_table(lookup);
1464 devm_kfree(dev, lookup);
1465 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1466 } else {
1467 priv->lookup = lookup;
1468 }
1469 }
1470
i801_del_mux(struct i801_priv * priv)1471 static void i801_del_mux(struct i801_priv *priv)
1472 {
1473 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block);
1474 platform_device_unregister(priv->mux_pdev);
1475 gpiod_remove_lookup_table(priv->lookup);
1476 }
1477 #else
i801_add_mux(struct i801_priv * priv)1478 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1479 static inline void i801_del_mux(struct i801_priv *priv) { }
1480 #endif
1481
1482 static struct platform_device *
i801_add_tco_spt(struct pci_dev * pci_dev,struct resource * tco_res)1483 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res)
1484 {
1485 static const struct itco_wdt_platform_data pldata = {
1486 .name = "Intel PCH",
1487 .version = 4,
1488 };
1489 struct resource *res;
1490 int ret;
1491
1492 /*
1493 * We must access the NO_REBOOT bit over the Primary to Sideband
1494 * (P2SB) bridge.
1495 */
1496
1497 res = &tco_res[1];
1498 ret = p2sb_bar(pci_dev->bus, 0, res);
1499 if (ret)
1500 return ERR_PTR(ret);
1501
1502 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1503 res->start += SBREG_SMBCTRL_DNV;
1504 else
1505 res->start += SBREG_SMBCTRL;
1506
1507 res->end = res->start + 3;
1508
1509 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1510 tco_res, 2, &pldata, sizeof(pldata));
1511 }
1512
1513 static struct platform_device *
i801_add_tco_cnl(struct pci_dev * pci_dev,struct resource * tco_res)1514 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res)
1515 {
1516 static const struct itco_wdt_platform_data pldata = {
1517 .name = "Intel PCH",
1518 .version = 6,
1519 };
1520
1521 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1522 tco_res, 1, &pldata, sizeof(pldata));
1523 }
1524
i801_add_tco(struct i801_priv * priv)1525 static void i801_add_tco(struct i801_priv *priv)
1526 {
1527 struct pci_dev *pci_dev = priv->pci_dev;
1528 struct resource tco_res[2], *res;
1529 u32 tco_base, tco_ctl;
1530
1531 /* If we have ACPI based watchdog use that instead */
1532 if (acpi_has_watchdog())
1533 return;
1534
1535 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1536 return;
1537
1538 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1539 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1540 if (!(tco_ctl & TCOCTL_EN))
1541 return;
1542
1543 memset(tco_res, 0, sizeof(tco_res));
1544 /*
1545 * Always populate the main iTCO IO resource here. The second entry
1546 * for NO_REBOOT MMIO is filled by the SPT specific function.
1547 */
1548 res = &tco_res[0];
1549 res->start = tco_base & ~1;
1550 res->end = res->start + 32 - 1;
1551 res->flags = IORESOURCE_IO;
1552
1553 if (priv->features & FEATURE_TCO_CNL)
1554 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res);
1555 else
1556 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res);
1557
1558 if (IS_ERR(priv->tco_pdev))
1559 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1560 }
1561
1562 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1563 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1564 acpi_physical_address address)
1565 {
1566 return address >= priv->smba &&
1567 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1568 }
1569
1570 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1571 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1572 u64 *value, void *handler_context, void *region_context)
1573 {
1574 struct i801_priv *priv = handler_context;
1575 struct pci_dev *pdev = priv->pci_dev;
1576 acpi_status status;
1577
1578 /*
1579 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1580 * further access from the driver itself. This device is now owned
1581 * by the system firmware.
1582 */
1583 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1584
1585 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1586 priv->acpi_reserved = true;
1587
1588 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1589 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1590
1591 /*
1592 * BIOS is accessing the host controller so prevent it from
1593 * suspending automatically from now on.
1594 */
1595 pm_runtime_get_sync(&pdev->dev);
1596 }
1597
1598 if ((function & ACPI_IO_MASK) == ACPI_READ)
1599 status = acpi_os_read_port(address, (u32 *)value, bits);
1600 else
1601 status = acpi_os_write_port(address, (u32)*value, bits);
1602
1603 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT);
1604
1605 return status;
1606 }
1607
i801_acpi_probe(struct i801_priv * priv)1608 static int i801_acpi_probe(struct i801_priv *priv)
1609 {
1610 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1611 acpi_status status;
1612
1613 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1614 i801_acpi_io_handler, NULL, priv);
1615 if (ACPI_SUCCESS(status))
1616 return 0;
1617
1618 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1619 }
1620
i801_acpi_remove(struct i801_priv * priv)1621 static void i801_acpi_remove(struct i801_priv *priv)
1622 {
1623 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1624
1625 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1626 }
1627 #else
i801_acpi_probe(struct i801_priv * priv)1628 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1629 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1630 #endif
1631
i801_setup_hstcfg(struct i801_priv * priv)1632 static void i801_setup_hstcfg(struct i801_priv *priv)
1633 {
1634 unsigned char hstcfg = priv->original_hstcfg;
1635
1636 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1637 hstcfg |= SMBHSTCFG_HST_EN;
1638 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1639 }
1640
i801_restore_regs(struct i801_priv * priv)1641 static void i801_restore_regs(struct i801_priv *priv)
1642 {
1643 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1644 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1645 }
1646
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1647 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1648 {
1649 int err, i;
1650 struct i801_priv *priv;
1651
1652 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1653 if (!priv)
1654 return -ENOMEM;
1655
1656 i2c_set_adapdata(&priv->adapter, priv);
1657 priv->adapter.owner = THIS_MODULE;
1658 priv->adapter.class = I2C_CLASS_HWMON;
1659 priv->adapter.algo = &smbus_algorithm;
1660 priv->adapter.dev.parent = &dev->dev;
1661 acpi_use_parent_companion(&priv->adapter.dev);
1662 priv->adapter.retries = 3;
1663
1664 priv->pci_dev = dev;
1665 priv->features = id->driver_data;
1666
1667 /* Disable features on user request */
1668 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1669 if (priv->features & disable_features & (1 << i))
1670 dev_notice(&dev->dev, "%s disabled by user\n",
1671 i801_feature_names[i]);
1672 }
1673 priv->features &= ~disable_features;
1674
1675 /* The block process call uses block buffer mode */
1676 if (!(priv->features & FEATURE_BLOCK_BUFFER))
1677 priv->features &= ~FEATURE_BLOCK_PROC;
1678
1679 err = pcim_enable_device(dev);
1680 if (err) {
1681 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1682 err);
1683 return err;
1684 }
1685 pcim_pin_device(dev);
1686
1687 /* Determine the address of the SMBus area */
1688 priv->smba = pci_resource_start(dev, SMBBAR);
1689 if (!priv->smba) {
1690 dev_err(&dev->dev,
1691 "SMBus base address uninitialized, upgrade BIOS\n");
1692 return -ENODEV;
1693 }
1694
1695 if (i801_acpi_probe(priv))
1696 return -ENODEV;
1697
1698 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1699 if (err) {
1700 dev_err(&dev->dev,
1701 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1702 priv->smba,
1703 (unsigned long long)pci_resource_end(dev, SMBBAR));
1704 i801_acpi_remove(priv);
1705 return err;
1706 }
1707
1708 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1709 i801_setup_hstcfg(priv);
1710 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1711 dev_info(&dev->dev, "Enabling SMBus device\n");
1712
1713 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1714 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1715 /* Disable SMBus interrupt feature if SMBus using SMI# */
1716 priv->features &= ~FEATURE_IRQ;
1717 }
1718 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1719 dev_info(&dev->dev, "SPD Write Disable is set\n");
1720
1721 /* Clear special mode bits */
1722 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1723 outb_p(inb_p(SMBAUXCTL(priv)) &
1724 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1725
1726 /* Default timeout in interrupt mode: 200 ms */
1727 priv->adapter.timeout = HZ / 5;
1728
1729 if (dev->irq == IRQ_NOTCONNECTED)
1730 priv->features &= ~FEATURE_IRQ;
1731
1732 if (priv->features & FEATURE_IRQ) {
1733 u16 pcists;
1734
1735 /* Complain if an interrupt is already pending */
1736 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1737 if (pcists & PCI_STATUS_INTERRUPT)
1738 dev_warn(&dev->dev, "An interrupt is pending!\n");
1739 }
1740
1741 if (priv->features & FEATURE_IRQ) {
1742 init_completion(&priv->done);
1743
1744 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1745 IRQF_SHARED, DRV_NAME, priv);
1746 if (err) {
1747 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1748 dev->irq, err);
1749 priv->features &= ~FEATURE_IRQ;
1750 }
1751 }
1752 dev_info(&dev->dev, "SMBus using %s\n",
1753 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1754
1755 /* Host notification uses an interrupt */
1756 if (!(priv->features & FEATURE_IRQ))
1757 priv->features &= ~FEATURE_HOST_NOTIFY;
1758
1759 /* Remember original Interrupt and Host Notify settings */
1760 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1761 if (priv->features & FEATURE_HOST_NOTIFY)
1762 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1763
1764 i801_add_tco(priv);
1765
1766 /*
1767 * adapter.name is used by platform code to find the main I801 adapter
1768 * to instantiante i2c_clients, do not change.
1769 */
1770 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1771 "SMBus %s adapter at %04lx",
1772 (priv->features & FEATURE_IDF) ? "I801 IDF" : "I801",
1773 priv->smba);
1774
1775 err = i2c_add_adapter(&priv->adapter);
1776 if (err) {
1777 platform_device_unregister(priv->tco_pdev);
1778 i801_acpi_remove(priv);
1779 i801_restore_regs(priv);
1780 return err;
1781 }
1782
1783 i801_enable_host_notify(&priv->adapter);
1784
1785 /* We ignore errors - multiplexing is optional */
1786 i801_add_mux(priv);
1787 i801_probe_optional_targets(priv);
1788
1789 pci_set_drvdata(dev, priv);
1790
1791 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1792 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1793 pm_runtime_use_autosuspend(&dev->dev);
1794 pm_runtime_put_autosuspend(&dev->dev);
1795 pm_runtime_allow(&dev->dev);
1796
1797 return 0;
1798 }
1799
i801_remove(struct pci_dev * dev)1800 static void i801_remove(struct pci_dev *dev)
1801 {
1802 struct i801_priv *priv = pci_get_drvdata(dev);
1803
1804 i801_disable_host_notify(priv);
1805 i801_del_mux(priv);
1806 i2c_del_adapter(&priv->adapter);
1807 i801_acpi_remove(priv);
1808
1809 platform_device_unregister(priv->tco_pdev);
1810
1811 /* if acpi_reserved is set then usage_count is incremented already */
1812 if (!priv->acpi_reserved)
1813 pm_runtime_get_noresume(&dev->dev);
1814
1815 i801_restore_regs(priv);
1816
1817 /*
1818 * do not call pci_disable_device(dev) since it can cause hard hangs on
1819 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1820 */
1821 }
1822
i801_shutdown(struct pci_dev * dev)1823 static void i801_shutdown(struct pci_dev *dev)
1824 {
1825 struct i801_priv *priv = pci_get_drvdata(dev);
1826
1827 i801_disable_host_notify(priv);
1828 /* Restore config registers to avoid hard hang on some systems */
1829 i801_restore_regs(priv);
1830 }
1831
i801_suspend(struct device * dev)1832 static int i801_suspend(struct device *dev)
1833 {
1834 struct i801_priv *priv = dev_get_drvdata(dev);
1835
1836 i2c_mark_adapter_suspended(&priv->adapter);
1837 i801_restore_regs(priv);
1838
1839 return 0;
1840 }
1841
i801_resume(struct device * dev)1842 static int i801_resume(struct device *dev)
1843 {
1844 struct i801_priv *priv = dev_get_drvdata(dev);
1845
1846 i801_setup_hstcfg(priv);
1847 i801_enable_host_notify(&priv->adapter);
1848 i2c_mark_adapter_resumed(&priv->adapter);
1849
1850 return 0;
1851 }
1852
1853 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1854
1855 static struct pci_driver i801_driver = {
1856 .name = DRV_NAME,
1857 .id_table = i801_ids,
1858 .probe = i801_probe,
1859 .remove = i801_remove,
1860 .shutdown = i801_shutdown,
1861 .driver = {
1862 .pm = pm_sleep_ptr(&i801_pm_ops),
1863 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1864 },
1865 };
1866
i2c_i801_init(struct pci_driver * drv)1867 static int __init i2c_i801_init(struct pci_driver *drv)
1868 {
1869 if (dmi_name_in_vendors("FUJITSU"))
1870 input_apanel_init();
1871 return pci_register_driver(drv);
1872 }
1873
1874 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1875 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1876 MODULE_DESCRIPTION("I801 SMBus driver");
1877 MODULE_LICENSE("GPL");
1878
1879 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver);
1880