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Searched refs:SM (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/net/wireless/ath/ath9k/
H A Dar9003_rtt.c77 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); in ar9003_hw_rtt_load_hist_entry()
80 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_load_hist_entry()
81 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_load_hist_entry()
82 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_load_hist_entry()
86 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_load_hist_entry()
95 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); in ar9003_hw_rtt_load_hist_entry()
146 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_fill_hist_entry()
147 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_fill_hist_entry()
148 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_fill_hist_entry()
153 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_fill_hist_entry()
H A Dar9002_phy.c239 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9002_hw_spur_mitigate()
268 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar9002_hw_spur_mitigate()
269 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar9002_hw_spur_mitigate()
320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
321 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
324 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
326 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
462 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); in ar9002_hw_set_bt_ant_diversity()
463 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9002_hw_set_bt_ant_diversity()
464 regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9002_hw_set_bt_ant_diversity()
[all …]
H A Deeprom_9287.c443 regval = SM(pdGainOverlap_t2, in ath9k_hw_set_ar9287_power_cal_table()
445 | SM(gainBoundaries[0], in ath9k_hw_set_ar9287_power_cal_table()
447 | SM(gainBoundaries[1], in ath9k_hw_set_ar9287_power_cal_table()
449 | SM(gainBoundaries[2], in ath9k_hw_set_ar9287_power_cal_table()
451 | SM(gainBoundaries[3], in ath9k_hw_set_ar9287_power_cal_table()
872 SM(pModal->iqCalICh[i], in ath9k_hw_ar9287_set_board_values()
874 SM(pModal->iqCalQCh[i], in ath9k_hw_ar9287_set_board_values()
905 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_ar9287_set_board_values()
906 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) in ath9k_hw_ar9287_set_board_values()
907 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) in ath9k_hw_ar9287_set_board_values()
[all …]
H A Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); in ath9k_hw_set_txq_interrupts()
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); in ath9k_hw_updatetxtriglevel()
391 SM(cwMin, AR_D_LCL_IFS_CWMIN) | in ath9k_hw_resettxqueue()
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
396 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | in ath9k_hw_resettxqueue()
397 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | in ath9k_hw_resettxqueue()
[all …]
H A Dar5008_phy.c474 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar5008_hw_spur_mitigate()
484 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar5008_hw_spur_mitigate()
485 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar5008_hw_spur_mitigate()
918 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
921 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
923 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
926 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
928 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
941 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
943 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
[all …]
H A Deeprom_4k.c347 SM(pdGainOverlap_t2, in ath9k_hw_set_4k_power_cal_table()
349 | SM(gainBoundaries[0], in ath9k_hw_set_4k_power_cal_table()
351 | SM(gainBoundaries[1], in ath9k_hw_set_4k_power_cal_table()
353 | SM(gainBoundaries[2], in ath9k_hw_set_4k_power_cal_table()
355 | SM(gainBoundaries[3], in ath9k_hw_set_4k_power_cal_table()
709 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | in ath9k_hw_4k_set_gain()
710 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF), in ath9k_hw_4k_set_gain()
785 regVal |= SM(ant_div_control1, in ath9k_hw_4k_set_board_values()
787 regVal |= SM(ant_div_control2, in ath9k_hw_4k_set_board_values()
789 regVal |= SM((ant_div_control2 >> 2), in ath9k_hw_4k_set_board_values()
[all …]
H A Deeprom_def.c440 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN), in ath9k_hw_def_set_gain()
443 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN), in ath9k_hw_def_set_gain()
457 SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN), in ath9k_hw_def_set_gain()
460 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN), in ath9k_hw_def_set_gain()
499 SM(pModal->iqCalICh[i], in ath9k_hw_def_set_board_values()
501 SM(pModal->iqCalQCh[i], in ath9k_hw_def_set_board_values()
568 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) in ath9k_hw_def_set_board_values()
569 | SM(pModal->txEndToXpaOff, in ath9k_hw_def_set_board_values()
571 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
573 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
[all …]
H A Dar9003_eeprom.c4463 val = SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) | in ar9003_hw_selfgen_tpc_txpower()
4464 SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) | in ar9003_hw_selfgen_tpc_txpower()
4465 SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT); in ar9003_hw_selfgen_tpc_txpower()
4467 val = SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) | in ar9003_hw_selfgen_tpc_txpower()
4468 SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) | in ar9003_hw_selfgen_tpc_txpower()
4469 SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT); in ar9003_hw_selfgen_tpc_txpower()
/linux/drivers/net/wireless/ath/ath6kl/
H A Dhif.c213 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
216 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
577 SM(INT_STATUS_ENABLE_ERROR, 0x01) | in ath6kl_hif_enable_intrs()
578 SM(INT_STATUS_ENABLE_CPU, 0x01) | in ath6kl_hif_enable_intrs()
579 SM(INT_STATUS_ENABLE_COUNTER, 0x01); in ath6kl_hif_enable_intrs()
585 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
592 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | in ath6kl_hif_enable_intrs()
593 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); in ath6kl_hif_enable_intrs()
599 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
H A Dtarget.h133 #define SM(f, v) (((v) << f##_S) & f) macro
H A Dinit.c1471 param |= SM(SYSTEM_SLEEP_DISABLE, 1); in ath6kl_init_upload()
1489 param = SM(CPU_CLOCK_STANDARD, 1); in ath6kl_init_upload()
1499 param = SM(LPO_CAL_ENABLE, 1); in ath6kl_init_upload()
/linux/Documentation/devicetree/bindings/display/
H A Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/linux/arch/m68k/fpsp040/
H A Ddecbin.S31 | adds and muls in FP0. Set the sign according to SM.
40 | added if SM = 1 and subtracted if SM = 0. Scale the
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE}
H A Dbindec.S903 bges mant_p |if pos, don't set SM
904 moveql #2,%d0 |move 2 in to d0 for SM
/linux/drivers/iio/chemical/
H A DKconfig20 tristate "Atlas Scientific OEM SM sensors"
28 Atlas Scientific OEM SM sensors:
29 * pH SM sensor
30 * EC SM sensor
31 * ORP SM sensor
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916-samsung-j3ltetw.dts8 model = "Samsung Galaxy J3 (2016) (SM-J320YZ)";
H A Dmsm8939-samsung-a7.dts217 /* NOTE: On some variants e.g. SM-A700FD it's GPIO 91 */
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4212-tab3-wifi8.dts14 model = "Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) based on Exynos4212";
H A Dexynos4212-tab3-3g8.dts14 model = "Samsung Galaxy Tab 3 8.0 3G (SM-T311) based on Exynos4212";
H A Dexynos4212-tab3-lte8.dts14 model = "Samsung Galaxy Tab 3 8.0 LTE (SM-T315) based on Exynos4212";
H A Dexynos5422-samsung-k3g.dts3 * Samsung Galaxy S5 (SM-G900H) device-tree source
16 model = "Samsung Galaxy S5 (SM-G900H)";
/linux/sound/soc/codecs/
H A Dtac5xx2-sdw.c65 #define FU11_L_MUTE_REG TAC_MUTE_REG(SM, FU11, LEFT)
66 #define FU11_R_MUTE_REG TAC_MUTE_REG(SM, FU11, RIGHT)
67 #define FU113_L_MUTE_REG TAC_MUTE_REG(SM, FU113, LEFT)
68 #define FU113_R_MUTE_REG TAC_MUTE_REG(SM, FU113, RIGHT)
74 #define IT11_USAGE_REG TAC_USAGE_REG(SM, IT11)
77 #define OT113_USAGE_REG TAC_USAGE_REG(SM, OT113)
82 #define XU12_BYPASS_REG TAC_XU_BYPASS_REG(SM, XU12)
526 TAC_DOUBLE_Q78_TLV("DMIC Capture Volume", SM, FU113),
/linux/Documentation/admin-guide/nfs/
H A Dnfs-rdma.rst172 If you are using InfiniBand, make sure there is a Subnet Manager (SM)
173 running on the network. If your IB switch has an embedded SM, you can
174 use it. Otherwise, you will need to run an SM, such as OpenSM, on one
177 If an SM is running on your network, you should see the following:
/linux/Documentation/arch/arm64/
H A Dsme.rst21 * PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
90 * On syscall PSTATE.SM will be cleared and the SVE registers will be handled
97 PSTATE.SM cleared.
108 * Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0.
446 * PSTATE.SM, if this is 1 then the PE is in streaming mode. When the value
447 of PSTATE.SM is changed then it is implementation defined if the subset
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-osd3358-sm-red.dts18 model = "Octavo Systems OSD3358-SM-RED";

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