1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * NXP LPC32XX NAND SLC driver
4 *
5 * Authors:
6 * Kevin Wells <kevin.wells@nxp.com>
7 * Roland Stigge <stigge@antcom.de>
8 *
9 * Copyright © 2011 NXP Semiconductors
10 * Copyright © 2012 Roland Stigge
11 */
12
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/mm.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/of.h>
28 #include <linux/mtd/lpc32xx_slc.h>
29
30 #define LPC32XX_MODNAME "lpc32xx-nand"
31
32 /**********************************************************************
33 * SLC NAND controller register offsets
34 **********************************************************************/
35
36 #define SLC_DATA(x) (x + 0x000)
37 #define SLC_ADDR(x) (x + 0x004)
38 #define SLC_CMD(x) (x + 0x008)
39 #define SLC_STOP(x) (x + 0x00C)
40 #define SLC_CTRL(x) (x + 0x010)
41 #define SLC_CFG(x) (x + 0x014)
42 #define SLC_STAT(x) (x + 0x018)
43 #define SLC_INT_STAT(x) (x + 0x01C)
44 #define SLC_IEN(x) (x + 0x020)
45 #define SLC_ISR(x) (x + 0x024)
46 #define SLC_ICR(x) (x + 0x028)
47 #define SLC_TAC(x) (x + 0x02C)
48 #define SLC_TC(x) (x + 0x030)
49 #define SLC_ECC(x) (x + 0x034)
50 #define SLC_DMA_DATA(x) (x + 0x038)
51
52 /**********************************************************************
53 * slc_ctrl register definitions
54 **********************************************************************/
55 #define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
56 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
57 #define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
58
59 /**********************************************************************
60 * slc_cfg register definitions
61 **********************************************************************/
62 #define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
63 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
64 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
65 #define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
66 #define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
67 #define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
68
69 /**********************************************************************
70 * slc_stat register definitions
71 **********************************************************************/
72 #define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
73 #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
74 #define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
75
76 /**********************************************************************
77 * slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
78 **********************************************************************/
79 #define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
80 #define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
81
82 /**********************************************************************
83 * slc_tac register definitions
84 **********************************************************************/
85 /* Computation of clock cycles on basis of controller and device clock rates */
86 #define SLCTAC_CLOCKS(c, n, s) (min_t(u32, DIV_ROUND_UP(c, n) - 1, 0xF) << s)
87
88 /* Clock setting for RDY write sample wait time in 2*n clocks */
89 #define SLCTAC_WDR(n) (((n) & 0xF) << 28)
90 /* Write pulse width in clock cycles, 1 to 16 clocks */
91 #define SLCTAC_WWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 24))
92 /* Write hold time of control and data signals, 1 to 16 clocks */
93 #define SLCTAC_WHOLD(c, n) (SLCTAC_CLOCKS(c, n, 20))
94 /* Write setup time of control and data signals, 1 to 16 clocks */
95 #define SLCTAC_WSETUP(c, n) (SLCTAC_CLOCKS(c, n, 16))
96 /* Clock setting for RDY read sample wait time in 2*n clocks */
97 #define SLCTAC_RDR(n) (((n) & 0xF) << 12)
98 /* Read pulse width in clock cycles, 1 to 16 clocks */
99 #define SLCTAC_RWIDTH(c, n) (SLCTAC_CLOCKS(c, n, 8))
100 /* Read hold time of control and data signals, 1 to 16 clocks */
101 #define SLCTAC_RHOLD(c, n) (SLCTAC_CLOCKS(c, n, 4))
102 /* Read setup time of control and data signals, 1 to 16 clocks */
103 #define SLCTAC_RSETUP(c, n) (SLCTAC_CLOCKS(c, n, 0))
104
105 /**********************************************************************
106 * slc_ecc register definitions
107 **********************************************************************/
108 /* ECC line party fetch macro */
109 #define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
110 #define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
111
112 /*
113 * DMA requires storage space for the DMA local buffer and the hardware ECC
114 * storage area. The DMA local buffer is only used if DMA mapping fails
115 * during runtime.
116 */
117 #define LPC32XX_DMA_DATA_SIZE 4096
118 #define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
119
120 /* Number of bytes used for ECC stored in NAND per 256 bytes */
121 #define LPC32XX_SLC_DEV_ECC_BYTES 3
122
123 /*
124 * If the NAND base clock frequency can't be fetched, this frequency will be
125 * used instead as the base. This rate is used to setup the timing registers
126 * used for NAND accesses.
127 */
128 #define LPC32XX_DEF_BUS_RATE 133250000
129
130 /* Milliseconds for DMA FIFO timeout (unlikely anyway) */
131 #define LPC32XX_DMA_TIMEOUT 100
132
133 /*
134 * NAND ECC Layout for small page NAND devices
135 * Note: For large and huge page devices, the default layouts are used
136 */
lpc32xx_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)137 static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
138 struct mtd_oob_region *oobregion)
139 {
140 if (section)
141 return -ERANGE;
142
143 oobregion->length = 6;
144 oobregion->offset = 10;
145
146 return 0;
147 }
148
lpc32xx_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)149 static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
150 struct mtd_oob_region *oobregion)
151 {
152 if (section > 1)
153 return -ERANGE;
154
155 if (!section) {
156 oobregion->offset = 0;
157 oobregion->length = 4;
158 } else {
159 oobregion->offset = 6;
160 oobregion->length = 4;
161 }
162
163 return 0;
164 }
165
166 static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
167 .ecc = lpc32xx_ooblayout_ecc,
168 .free = lpc32xx_ooblayout_free,
169 };
170
171 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
172 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
173
174 /*
175 * Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
176 * Note: Large page devices used the default layout
177 */
178 static struct nand_bbt_descr bbt_smallpage_main_descr = {
179 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
180 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
181 .offs = 0,
182 .len = 4,
183 .veroffs = 6,
184 .maxblocks = 4,
185 .pattern = bbt_pattern
186 };
187
188 static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
189 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
190 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
191 .offs = 0,
192 .len = 4,
193 .veroffs = 6,
194 .maxblocks = 4,
195 .pattern = mirror_pattern
196 };
197
198 /*
199 * NAND platform configuration structure
200 */
201 struct lpc32xx_nand_cfg_slc {
202 uint32_t wdr_clks;
203 uint32_t wwidth;
204 uint32_t whold;
205 uint32_t wsetup;
206 uint32_t rdr_clks;
207 uint32_t rwidth;
208 uint32_t rhold;
209 uint32_t rsetup;
210 struct mtd_partition *parts;
211 unsigned num_parts;
212 };
213
214 struct lpc32xx_nand_host {
215 struct nand_chip nand_chip;
216 struct lpc32xx_slc_platform_data *pdata;
217 struct clk *clk;
218 struct gpio_desc *wp_gpio;
219 void __iomem *io_base;
220 struct lpc32xx_nand_cfg_slc *ncfg;
221
222 struct completion comp;
223 struct dma_chan *dma_chan;
224 uint32_t dma_buf_len;
225 struct dma_slave_config dma_slave_config;
226 struct scatterlist sgl;
227
228 /*
229 * DMA and CPU addresses of ECC work area and data buffer
230 */
231 uint32_t *ecc_buf;
232 uint8_t *data_buf;
233 dma_addr_t io_base_dma;
234 };
235
lpc32xx_nand_setup(struct lpc32xx_nand_host * host)236 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
237 {
238 uint32_t clkrate, tmp;
239
240 /* Reset SLC controller */
241 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
242 udelay(1000);
243
244 /* Basic setup */
245 writel(0, SLC_CFG(host->io_base));
246 writel(0, SLC_IEN(host->io_base));
247 writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
248 SLC_ICR(host->io_base));
249
250 /* Get base clock for SLC block */
251 clkrate = clk_get_rate(host->clk);
252 if (clkrate == 0)
253 clkrate = LPC32XX_DEF_BUS_RATE;
254
255 /* Compute clock setup values */
256 tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
257 SLCTAC_WWIDTH(clkrate, host->ncfg->wwidth) |
258 SLCTAC_WHOLD(clkrate, host->ncfg->whold) |
259 SLCTAC_WSETUP(clkrate, host->ncfg->wsetup) |
260 SLCTAC_RDR(host->ncfg->rdr_clks) |
261 SLCTAC_RWIDTH(clkrate, host->ncfg->rwidth) |
262 SLCTAC_RHOLD(clkrate, host->ncfg->rhold) |
263 SLCTAC_RSETUP(clkrate, host->ncfg->rsetup);
264 writel(tmp, SLC_TAC(host->io_base));
265 }
266
267 /*
268 * Hardware specific access to control lines
269 */
lpc32xx_nand_cmd_ctrl(struct nand_chip * chip,int cmd,unsigned int ctrl)270 static void lpc32xx_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
271 unsigned int ctrl)
272 {
273 uint32_t tmp;
274 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
275
276 /* Does CE state need to be changed? */
277 tmp = readl(SLC_CFG(host->io_base));
278 if (ctrl & NAND_NCE)
279 tmp |= SLCCFG_CE_LOW;
280 else
281 tmp &= ~SLCCFG_CE_LOW;
282 writel(tmp, SLC_CFG(host->io_base));
283
284 if (cmd != NAND_CMD_NONE) {
285 if (ctrl & NAND_CLE)
286 writel(cmd, SLC_CMD(host->io_base));
287 else
288 writel(cmd, SLC_ADDR(host->io_base));
289 }
290 }
291
292 /*
293 * Read the Device Ready pin
294 */
lpc32xx_nand_device_ready(struct nand_chip * chip)295 static int lpc32xx_nand_device_ready(struct nand_chip *chip)
296 {
297 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
298 int rdy = 0;
299
300 if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
301 rdy = 1;
302
303 return rdy;
304 }
305
306 /*
307 * Enable NAND write protect
308 */
lpc32xx_wp_enable(struct lpc32xx_nand_host * host)309 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
310 {
311 if (host->wp_gpio)
312 gpiod_set_value_cansleep(host->wp_gpio, 1);
313 }
314
315 /*
316 * Disable NAND write protect
317 */
lpc32xx_wp_disable(struct lpc32xx_nand_host * host)318 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
319 {
320 if (host->wp_gpio)
321 gpiod_set_value_cansleep(host->wp_gpio, 0);
322 }
323
324 /*
325 * Prepares SLC for transfers with H/W ECC enabled
326 */
lpc32xx_nand_ecc_enable(struct nand_chip * chip,int mode)327 static void lpc32xx_nand_ecc_enable(struct nand_chip *chip, int mode)
328 {
329 /* Hardware ECC is enabled automatically in hardware as needed */
330 }
331
332 /*
333 * Calculates the ECC for the data
334 */
lpc32xx_nand_ecc_calculate(struct nand_chip * chip,const unsigned char * buf,unsigned char * code)335 static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip,
336 const unsigned char *buf,
337 unsigned char *code)
338 {
339 /*
340 * ECC is calculated automatically in hardware during syndrome read
341 * and write operations, so it doesn't need to be calculated here.
342 */
343 return 0;
344 }
345
346 /*
347 * Read a single byte from NAND device
348 */
lpc32xx_nand_read_byte(struct nand_chip * chip)349 static uint8_t lpc32xx_nand_read_byte(struct nand_chip *chip)
350 {
351 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
352
353 return (uint8_t)readl(SLC_DATA(host->io_base));
354 }
355
356 /*
357 * Simple device read without ECC
358 */
lpc32xx_nand_read_buf(struct nand_chip * chip,u_char * buf,int len)359 static void lpc32xx_nand_read_buf(struct nand_chip *chip, u_char *buf, int len)
360 {
361 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
362
363 /* Direct device read with no ECC */
364 while (len-- > 0)
365 *buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
366 }
367
368 /*
369 * Simple device write without ECC
370 */
lpc32xx_nand_write_buf(struct nand_chip * chip,const uint8_t * buf,int len)371 static void lpc32xx_nand_write_buf(struct nand_chip *chip, const uint8_t *buf,
372 int len)
373 {
374 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
375
376 /* Direct device write with no ECC */
377 while (len-- > 0)
378 writel((uint32_t)*buf++, SLC_DATA(host->io_base));
379 }
380
381 /*
382 * Read the OOB data from the device without ECC using FIFO method
383 */
lpc32xx_nand_read_oob_syndrome(struct nand_chip * chip,int page)384 static int lpc32xx_nand_read_oob_syndrome(struct nand_chip *chip, int page)
385 {
386 struct mtd_info *mtd = nand_to_mtd(chip);
387
388 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
389 }
390
391 /*
392 * Write the OOB data to the device without ECC using FIFO method
393 */
lpc32xx_nand_write_oob_syndrome(struct nand_chip * chip,int page)394 static int lpc32xx_nand_write_oob_syndrome(struct nand_chip *chip, int page)
395 {
396 struct mtd_info *mtd = nand_to_mtd(chip);
397
398 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
399 mtd->oobsize);
400 }
401
402 /*
403 * Fills in the ECC fields in the OOB buffer with the hardware generated ECC
404 */
lpc32xx_slc_ecc_copy(uint8_t * spare,const uint32_t * ecc,int count)405 static void lpc32xx_slc_ecc_copy(uint8_t *spare, const uint32_t *ecc, int count)
406 {
407 int i;
408
409 for (i = 0; i < (count * 3); i += 3) {
410 uint32_t ce = ecc[i / 3];
411 ce = ~(ce << 2) & 0xFFFFFF;
412 spare[i + 2] = (uint8_t)(ce & 0xFF);
413 ce >>= 8;
414 spare[i + 1] = (uint8_t)(ce & 0xFF);
415 ce >>= 8;
416 spare[i] = (uint8_t)(ce & 0xFF);
417 }
418 }
419
lpc32xx_dma_complete_func(void * completion)420 static void lpc32xx_dma_complete_func(void *completion)
421 {
422 complete(completion);
423 }
424
lpc32xx_xmit_dma(struct mtd_info * mtd,dma_addr_t dma,void * mem,int len,enum dma_transfer_direction dir)425 static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
426 void *mem, int len, enum dma_transfer_direction dir)
427 {
428 struct nand_chip *chip = mtd_to_nand(mtd);
429 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
430 struct dma_async_tx_descriptor *desc;
431 int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
432 int res;
433 unsigned long time_left;
434
435 host->dma_slave_config.direction = dir;
436 host->dma_slave_config.src_addr = dma;
437 host->dma_slave_config.dst_addr = dma;
438 host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
439 host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
440 host->dma_slave_config.src_maxburst = 4;
441 host->dma_slave_config.dst_maxburst = 4;
442 /* DMA controller does flow control: */
443 host->dma_slave_config.device_fc = false;
444 if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
445 dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
446 return -ENXIO;
447 }
448
449 sg_init_one(&host->sgl, mem, len);
450
451 res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
452 DMA_BIDIRECTIONAL);
453 if (res != 1) {
454 dev_err(mtd->dev.parent, "Failed to map sg list\n");
455 return -ENXIO;
456 }
457 desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
458 flags);
459 if (!desc) {
460 dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
461 goto out1;
462 }
463
464 init_completion(&host->comp);
465 desc->callback = lpc32xx_dma_complete_func;
466 desc->callback_param = &host->comp;
467
468 dmaengine_submit(desc);
469 dma_async_issue_pending(host->dma_chan);
470
471 time_left = wait_for_completion_timeout(&host->comp,
472 msecs_to_jiffies(1000));
473 if (!time_left) {
474 dmaengine_terminate_sync(host->dma_chan);
475 res = -ETIMEDOUT;
476 } else {
477 res = 0;
478 }
479
480 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
481 DMA_BIDIRECTIONAL);
482
483 return res;
484 out1:
485 dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
486 DMA_BIDIRECTIONAL);
487 return -ENXIO;
488 }
489
490 /*
491 * DMA read/write transfers with ECC support
492 */
lpc32xx_xfer(struct mtd_info * mtd,uint8_t * buf,int eccsubpages,int read)493 static int lpc32xx_xfer(struct mtd_info *mtd, uint8_t *buf, int eccsubpages,
494 int read)
495 {
496 struct nand_chip *chip = mtd_to_nand(mtd);
497 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
498 int i, status = 0;
499 unsigned long timeout;
500 int res;
501 enum dma_transfer_direction dir =
502 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
503 uint8_t *dma_buf;
504 bool dma_mapped;
505
506 if ((void *)buf <= high_memory) {
507 dma_buf = buf;
508 dma_mapped = true;
509 } else {
510 dma_buf = host->data_buf;
511 dma_mapped = false;
512 if (!read)
513 memcpy(host->data_buf, buf, mtd->writesize);
514 }
515
516 if (read) {
517 writel(readl(SLC_CFG(host->io_base)) |
518 SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
519 SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
520 } else {
521 writel((readl(SLC_CFG(host->io_base)) |
522 SLCCFG_ECC_EN | SLCCFG_DMA_ECC | SLCCFG_DMA_BURST) &
523 ~SLCCFG_DMA_DIR,
524 SLC_CFG(host->io_base));
525 }
526
527 /* Clear initial ECC */
528 writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
529
530 /* Transfer size is data area only */
531 writel(mtd->writesize, SLC_TC(host->io_base));
532
533 /* Start transfer in the NAND controller */
534 writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
535 SLC_CTRL(host->io_base));
536
537 for (i = 0; i < chip->ecc.steps; i++) {
538 /* Data */
539 res = lpc32xx_xmit_dma(mtd, SLC_DMA_DATA(host->io_base_dma),
540 dma_buf + i * chip->ecc.size,
541 mtd->writesize / chip->ecc.steps, dir);
542 if (res)
543 return res;
544
545 /* Always _read_ ECC */
546 if (i == chip->ecc.steps - 1)
547 break;
548 if (!read) /* ECC availability delayed on write */
549 udelay(10);
550 res = lpc32xx_xmit_dma(mtd, SLC_ECC(host->io_base_dma),
551 &host->ecc_buf[i], 4, DMA_DEV_TO_MEM);
552 if (res)
553 return res;
554 }
555
556 /*
557 * According to NXP, the DMA can be finished here, but the NAND
558 * controller may still have buffered data. After porting to using the
559 * dmaengine DMA driver (amba-pl080), the condition (DMA_FIFO empty)
560 * appears to be always true, according to tests. Keeping the check for
561 * safety reasons for now.
562 */
563 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
564 dev_warn(mtd->dev.parent, "FIFO not empty!\n");
565 timeout = jiffies + msecs_to_jiffies(LPC32XX_DMA_TIMEOUT);
566 while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
567 time_before(jiffies, timeout))
568 cpu_relax();
569 if (!time_before(jiffies, timeout)) {
570 dev_err(mtd->dev.parent, "FIFO held data too long\n");
571 status = -EIO;
572 }
573 }
574
575 /* Read last calculated ECC value */
576 if (!read)
577 udelay(10);
578 host->ecc_buf[chip->ecc.steps - 1] =
579 readl(SLC_ECC(host->io_base));
580
581 /* Flush DMA */
582 dmaengine_terminate_all(host->dma_chan);
583
584 if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
585 readl(SLC_TC(host->io_base))) {
586 /* Something is left in the FIFO, something is wrong */
587 dev_err(mtd->dev.parent, "DMA FIFO failure\n");
588 status = -EIO;
589 }
590
591 /* Stop DMA & HW ECC */
592 writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
593 SLC_CTRL(host->io_base));
594 writel(readl(SLC_CFG(host->io_base)) &
595 ~(SLCCFG_DMA_DIR | SLCCFG_ECC_EN | SLCCFG_DMA_ECC |
596 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
597
598 if (!dma_mapped && read)
599 memcpy(buf, host->data_buf, mtd->writesize);
600
601 return status;
602 }
603
604 /*
605 * Read the data and OOB data from the device, use ECC correction with the
606 * data, disable ECC for the OOB data
607 */
lpc32xx_nand_read_page_syndrome(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)608 static int lpc32xx_nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
609 int oob_required, int page)
610 {
611 struct mtd_info *mtd = nand_to_mtd(chip);
612 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
613 struct mtd_oob_region oobregion = { };
614 int stat, i, status, error;
615 uint8_t *oobecc, tmpecc[LPC32XX_ECC_SAVE_SIZE];
616
617 /* Issue read command */
618 nand_read_page_op(chip, page, 0, NULL, 0);
619
620 /* Read data and oob, calculate ECC */
621 status = lpc32xx_xfer(mtd, buf, chip->ecc.steps, 1);
622
623 /* Get OOB data */
624 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
625
626 /* Convert to stored ECC format */
627 lpc32xx_slc_ecc_copy(tmpecc, (uint32_t *) host->ecc_buf, chip->ecc.steps);
628
629 /* Pointer to ECC data retrieved from NAND spare area */
630 error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
631 if (error)
632 return error;
633
634 oobecc = chip->oob_poi + oobregion.offset;
635
636 for (i = 0; i < chip->ecc.steps; i++) {
637 stat = chip->ecc.correct(chip, buf, oobecc,
638 &tmpecc[i * chip->ecc.bytes]);
639 if (stat < 0)
640 mtd->ecc_stats.failed++;
641 else
642 mtd->ecc_stats.corrected += stat;
643
644 buf += chip->ecc.size;
645 oobecc += chip->ecc.bytes;
646 }
647
648 return status;
649 }
650
651 /*
652 * Read the data and OOB data from the device, no ECC correction with the
653 * data or OOB data
654 */
lpc32xx_nand_read_page_raw_syndrome(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)655 static int lpc32xx_nand_read_page_raw_syndrome(struct nand_chip *chip,
656 uint8_t *buf, int oob_required,
657 int page)
658 {
659 struct mtd_info *mtd = nand_to_mtd(chip);
660
661 /* Issue read command */
662 nand_read_page_op(chip, page, 0, NULL, 0);
663
664 /* Raw reads can just use the FIFO interface */
665 chip->legacy.read_buf(chip, buf, chip->ecc.size * chip->ecc.steps);
666 chip->legacy.read_buf(chip, chip->oob_poi, mtd->oobsize);
667
668 return 0;
669 }
670
671 /*
672 * Write the data and OOB data to the device, use ECC with the data,
673 * disable ECC for the OOB data
674 */
lpc32xx_nand_write_page_syndrome(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)675 static int lpc32xx_nand_write_page_syndrome(struct nand_chip *chip,
676 const uint8_t *buf,
677 int oob_required, int page)
678 {
679 struct mtd_info *mtd = nand_to_mtd(chip);
680 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
681 struct mtd_oob_region oobregion = { };
682 uint8_t *pb;
683 int error;
684
685 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
686
687 /* Write data, calculate ECC on outbound data */
688 error = lpc32xx_xfer(mtd, (uint8_t *)buf, chip->ecc.steps, 0);
689 if (error)
690 return error;
691
692 /*
693 * The calculated ECC needs some manual work done to it before
694 * committing it to NAND. Process the calculated ECC and place
695 * the resultant values directly into the OOB buffer. */
696 error = mtd_ooblayout_ecc(mtd, 0, &oobregion);
697 if (error)
698 return error;
699
700 pb = chip->oob_poi + oobregion.offset;
701 lpc32xx_slc_ecc_copy(pb, (uint32_t *)host->ecc_buf, chip->ecc.steps);
702
703 /* Write ECC data to device */
704 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
705
706 return nand_prog_page_end_op(chip);
707 }
708
709 /*
710 * Write the data and OOB data to the device, no ECC correction with the
711 * data or OOB data
712 */
lpc32xx_nand_write_page_raw_syndrome(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)713 static int lpc32xx_nand_write_page_raw_syndrome(struct nand_chip *chip,
714 const uint8_t *buf,
715 int oob_required, int page)
716 {
717 struct mtd_info *mtd = nand_to_mtd(chip);
718
719 /* Raw writes can just use the FIFO interface */
720 nand_prog_page_begin_op(chip, page, 0, buf,
721 chip->ecc.size * chip->ecc.steps);
722 chip->legacy.write_buf(chip, chip->oob_poi, mtd->oobsize);
723
724 return nand_prog_page_end_op(chip);
725 }
726
lpc32xx_nand_dma_setup(struct lpc32xx_nand_host * host)727 static int lpc32xx_nand_dma_setup(struct lpc32xx_nand_host *host)
728 {
729 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
730 dma_cap_mask_t mask;
731
732 host->dma_chan = dma_request_chan(mtd->dev.parent, "rx-tx");
733 if (IS_ERR(host->dma_chan)) {
734 /* fallback to request using platform data */
735 if (!host->pdata || !host->pdata->dma_filter) {
736 dev_err(mtd->dev.parent, "no DMA platform data\n");
737 return -ENOENT;
738 }
739
740 dma_cap_zero(mask);
741 dma_cap_set(DMA_SLAVE, mask);
742 host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-slc");
743
744 if (!host->dma_chan) {
745 dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
746 return -EBUSY;
747 }
748 }
749
750 return 0;
751 }
752
lpc32xx_parse_dt(struct device * dev)753 static struct lpc32xx_nand_cfg_slc *lpc32xx_parse_dt(struct device *dev)
754 {
755 struct lpc32xx_nand_cfg_slc *ncfg;
756 struct device_node *np = dev->of_node;
757
758 ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
759 if (!ncfg)
760 return NULL;
761
762 of_property_read_u32(np, "nxp,wdr-clks", &ncfg->wdr_clks);
763 of_property_read_u32(np, "nxp,wwidth", &ncfg->wwidth);
764 of_property_read_u32(np, "nxp,whold", &ncfg->whold);
765 of_property_read_u32(np, "nxp,wsetup", &ncfg->wsetup);
766 of_property_read_u32(np, "nxp,rdr-clks", &ncfg->rdr_clks);
767 of_property_read_u32(np, "nxp,rwidth", &ncfg->rwidth);
768 of_property_read_u32(np, "nxp,rhold", &ncfg->rhold);
769 of_property_read_u32(np, "nxp,rsetup", &ncfg->rsetup);
770
771 if (!ncfg->wdr_clks || !ncfg->wwidth || !ncfg->whold ||
772 !ncfg->wsetup || !ncfg->rdr_clks || !ncfg->rwidth ||
773 !ncfg->rhold || !ncfg->rsetup) {
774 dev_err(dev, "chip parameters not specified correctly\n");
775 return NULL;
776 }
777
778 return ncfg;
779 }
780
lpc32xx_nand_attach_chip(struct nand_chip * chip)781 static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
782 {
783 struct mtd_info *mtd = nand_to_mtd(chip);
784 struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
785
786 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
787 return 0;
788
789 /* OOB and ECC CPU and DMA work areas */
790 host->ecc_buf = (uint32_t *)(host->data_buf + LPC32XX_DMA_DATA_SIZE);
791
792 /*
793 * Small page FLASH has a unique OOB layout, but large and huge
794 * page FLASH use the standard layout. Small page FLASH uses a
795 * custom BBT marker layout.
796 */
797 if (mtd->writesize <= 512)
798 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
799
800 chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
801 /* These sizes remain the same regardless of page size */
802 chip->ecc.size = 256;
803 chip->ecc.strength = 1;
804 chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
805 chip->ecc.prepad = 0;
806 chip->ecc.postpad = 0;
807 chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
808 chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
809 chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
810 chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
811 chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
812 chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
813 chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
814 chip->ecc.correct = rawnand_sw_hamming_correct;
815 chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
816
817 /*
818 * Use a custom BBT marker setup for small page FLASH that
819 * won't interfere with the ECC layout. Large and huge page
820 * FLASH use the standard layout.
821 */
822 if ((chip->bbt_options & NAND_BBT_USE_FLASH) &&
823 mtd->writesize <= 512) {
824 chip->bbt_td = &bbt_smallpage_main_descr;
825 chip->bbt_md = &bbt_smallpage_mirror_descr;
826 }
827
828 return 0;
829 }
830
831 static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
832 .attach_chip = lpc32xx_nand_attach_chip,
833 };
834
835 /*
836 * Probe for NAND controller
837 */
lpc32xx_nand_probe(struct platform_device * pdev)838 static int lpc32xx_nand_probe(struct platform_device *pdev)
839 {
840 struct lpc32xx_nand_host *host;
841 struct mtd_info *mtd;
842 struct nand_chip *chip;
843 struct resource *rc;
844 int res;
845
846 /* Allocate memory for the device structure (and zero it) */
847 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
848 if (!host)
849 return -ENOMEM;
850
851 host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);
852 if (IS_ERR(host->io_base))
853 return PTR_ERR(host->io_base);
854
855 host->io_base_dma = rc->start;
856 if (pdev->dev.of_node)
857 host->ncfg = lpc32xx_parse_dt(&pdev->dev);
858 if (!host->ncfg) {
859 dev_err(&pdev->dev,
860 "Missing or bad NAND config from device tree\n");
861 return -ENOENT;
862 }
863
864 /* Start with WP disabled, if available */
865 host->wp_gpio = devm_gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
866 res = PTR_ERR_OR_ZERO(host->wp_gpio);
867 if (res) {
868 if (res != -EPROBE_DEFER)
869 dev_err(&pdev->dev, "WP GPIO is not available: %d\n",
870 res);
871 return res;
872 }
873
874 gpiod_set_consumer_name(host->wp_gpio, "NAND WP");
875
876 host->pdata = dev_get_platdata(&pdev->dev);
877
878 chip = &host->nand_chip;
879 mtd = nand_to_mtd(chip);
880 nand_set_controller_data(chip, host);
881 nand_set_flash_node(chip, pdev->dev.of_node);
882 mtd->owner = THIS_MODULE;
883 mtd->dev.parent = &pdev->dev;
884
885 /* Get NAND clock */
886 host->clk = devm_clk_get_enabled(&pdev->dev, NULL);
887 if (IS_ERR(host->clk)) {
888 dev_err(&pdev->dev, "Clock failure\n");
889 res = -ENOENT;
890 goto enable_wp;
891 }
892
893 /* Set NAND IO addresses and command/ready functions */
894 chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
895 chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
896 chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
897 chip->legacy.dev_ready = lpc32xx_nand_device_ready;
898 chip->legacy.chip_delay = 20; /* 20us command delay time */
899
900 /* Init NAND controller */
901 lpc32xx_nand_setup(host);
902
903 platform_set_drvdata(pdev, host);
904
905 /* NAND callbacks for LPC32xx SLC hardware */
906 chip->legacy.read_byte = lpc32xx_nand_read_byte;
907 chip->legacy.read_buf = lpc32xx_nand_read_buf;
908 chip->legacy.write_buf = lpc32xx_nand_write_buf;
909
910 /*
911 * Allocate a large enough buffer for a single huge page plus
912 * extra space for the spare area and ECC storage area
913 */
914 host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
915 host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len,
916 GFP_KERNEL);
917 if (host->data_buf == NULL) {
918 res = -ENOMEM;
919 goto enable_wp;
920 }
921
922 res = lpc32xx_nand_dma_setup(host);
923 if (res) {
924 res = -EIO;
925 goto enable_wp;
926 }
927
928 /* Find NAND device */
929 chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
930 res = nand_scan(chip, 1);
931 if (res)
932 goto release_dma;
933
934 mtd->name = "nxp_lpc3220_slc";
935 res = mtd_device_register(mtd, host->ncfg->parts,
936 host->ncfg->num_parts);
937 if (res)
938 goto cleanup_nand;
939
940 return 0;
941
942 cleanup_nand:
943 nand_cleanup(chip);
944 release_dma:
945 dma_release_channel(host->dma_chan);
946 enable_wp:
947 lpc32xx_wp_enable(host);
948
949 return res;
950 }
951
952 /*
953 * Remove NAND device.
954 */
lpc32xx_nand_remove(struct platform_device * pdev)955 static void lpc32xx_nand_remove(struct platform_device *pdev)
956 {
957 uint32_t tmp;
958 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
959 struct nand_chip *chip = &host->nand_chip;
960 int ret;
961
962 ret = mtd_device_unregister(nand_to_mtd(chip));
963 WARN_ON(ret);
964 nand_cleanup(chip);
965 dma_release_channel(host->dma_chan);
966
967 /* Force CE high */
968 tmp = readl(SLC_CTRL(host->io_base));
969 tmp &= ~SLCCFG_CE_LOW;
970 writel(tmp, SLC_CTRL(host->io_base));
971
972 lpc32xx_wp_enable(host);
973 }
974
lpc32xx_nand_resume(struct platform_device * pdev)975 static int lpc32xx_nand_resume(struct platform_device *pdev)
976 {
977 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
978 int ret;
979
980 /* Re-enable NAND clock */
981 ret = clk_prepare_enable(host->clk);
982 if (ret)
983 return ret;
984
985 /* Fresh init of NAND controller */
986 lpc32xx_nand_setup(host);
987
988 /* Disable write protect */
989 lpc32xx_wp_disable(host);
990
991 return 0;
992 }
993
lpc32xx_nand_suspend(struct platform_device * pdev,pm_message_t pm)994 static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
995 {
996 uint32_t tmp;
997 struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
998
999 /* Force CE high */
1000 tmp = readl(SLC_CTRL(host->io_base));
1001 tmp &= ~SLCCFG_CE_LOW;
1002 writel(tmp, SLC_CTRL(host->io_base));
1003
1004 /* Enable write protect for safety */
1005 lpc32xx_wp_enable(host);
1006
1007 /* Disable clock */
1008 clk_disable_unprepare(host->clk);
1009
1010 return 0;
1011 }
1012
1013 static const struct of_device_id lpc32xx_nand_match[] = {
1014 { .compatible = "nxp,lpc3220-slc" },
1015 { /* sentinel */ },
1016 };
1017 MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
1018
1019 static struct platform_driver lpc32xx_nand_driver = {
1020 .probe = lpc32xx_nand_probe,
1021 .remove = lpc32xx_nand_remove,
1022 .resume = pm_ptr(lpc32xx_nand_resume),
1023 .suspend = pm_ptr(lpc32xx_nand_suspend),
1024 .driver = {
1025 .name = LPC32XX_MODNAME,
1026 .of_match_table = lpc32xx_nand_match,
1027 },
1028 };
1029
1030 module_platform_driver(lpc32xx_nand_driver);
1031
1032 MODULE_LICENSE("GPL");
1033 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
1034 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
1035 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
1036