1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Skyworks Si521xx PCIe clock generator driver
4 *
5 * The following series can be supported:
6 * - Si52144 - 4x DIFF
7 * - Si52146 - 6x DIFF
8 * - Si52147 - 9x DIFF
9 * Currently tested:
10 * - Si52144
11 *
12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
13 */
14
15 #include <linux/bitfield.h>
16 #include <linux/bitrev.h>
17 #include <linux/clk-provider.h>
18 #include <linux/i2c.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/regmap.h>
22
23 /* OE1 and OE2 register */
24 #define SI521XX_REG_OE(n) (((n) & 0x1) + 1)
25 #define SI521XX_REG_ID 0x3
26 #define SI521XX_REG_ID_PROG GENMASK(7, 4)
27 #define SI521XX_REG_ID_VENDOR GENMASK(3, 0)
28 #define SI521XX_REG_BC 0x4
29 #define SI521XX_REG_DA 0x5
30 #define SI521XX_REG_DA_AMP_SEL BIT(7)
31 #define SI521XX_REG_DA_AMP_MASK GENMASK(6, 4)
32 #define SI521XX_REG_DA_AMP_MIN 300000
33 #define SI521XX_REG_DA_AMP_DEFAULT 800000
34 #define SI521XX_REG_DA_AMP_MAX 1000000
35 #define SI521XX_REG_DA_AMP_STEP 100000
36 #define SI521XX_REG_DA_AMP(UV) \
37 FIELD_PREP(SI521XX_REG_DA_AMP_MASK, \
38 ((UV) - SI521XX_REG_DA_AMP_MIN) / SI521XX_REG_DA_AMP_STEP)
39 #define SI521XX_REG_DA_UNKNOWN BIT(3) /* Always set */
40
41 /* Count of populated OE bits in control register ref, 1 and 2 */
42 #define SI521XX_OE_MAP(cr1, cr2) (((cr2) << 8) | (cr1))
43 #define SI521XX_OE_MAP_GET_OE(oe, map) (((map) >> (((oe) - 1) * 8)) & 0xff)
44
45 #define SI521XX_DIFF_MULT 4
46 #define SI521XX_DIFF_DIV 1
47
48 /* Supported Skyworks Si521xx models. */
49 enum si521xx_model {
50 SI52144 = 0x44,
51 SI52146 = 0x46,
52 SI52147 = 0x47,
53 };
54
55 struct si521xx;
56
57 struct si_clk {
58 struct clk_hw hw;
59 struct si521xx *si;
60 u8 reg;
61 u8 bit;
62 };
63
64 struct si521xx {
65 struct i2c_client *client;
66 struct regmap *regmap;
67 struct si_clk clk_dif[9];
68 u16 chip_info;
69 u8 pll_amplitude;
70 };
71
72 /*
73 * Si521xx i2c regmap
74 */
75 static const struct regmap_range si521xx_readable_ranges[] = {
76 regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_DA),
77 };
78
79 static const struct regmap_access_table si521xx_readable_table = {
80 .yes_ranges = si521xx_readable_ranges,
81 .n_yes_ranges = ARRAY_SIZE(si521xx_readable_ranges),
82 };
83
84 static const struct regmap_range si521xx_writeable_ranges[] = {
85 regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_OE(1)),
86 regmap_reg_range(SI521XX_REG_BC, SI521XX_REG_DA),
87 };
88
89 static const struct regmap_access_table si521xx_writeable_table = {
90 .yes_ranges = si521xx_writeable_ranges,
91 .n_yes_ranges = ARRAY_SIZE(si521xx_writeable_ranges),
92 };
93
si521xx_regmap_i2c_write(void * context,unsigned int reg,unsigned int val)94 static int si521xx_regmap_i2c_write(void *context, unsigned int reg,
95 unsigned int val)
96 {
97 struct i2c_client *i2c = context;
98 const u8 data[2] = { reg, val };
99 const int count = ARRAY_SIZE(data);
100 int ret;
101
102 ret = i2c_master_send(i2c, data, count);
103 if (ret == count)
104 return 0;
105 else if (ret < 0)
106 return ret;
107 else
108 return -EIO;
109 }
110
si521xx_regmap_i2c_read(void * context,unsigned int reg,unsigned int * val)111 static int si521xx_regmap_i2c_read(void *context, unsigned int reg,
112 unsigned int *val)
113 {
114 struct i2c_client *i2c = context;
115 struct i2c_msg xfer[2];
116 u8 txdata = reg;
117 u8 rxdata[2];
118 int ret;
119
120 xfer[0].addr = i2c->addr;
121 xfer[0].flags = 0;
122 xfer[0].len = 1;
123 xfer[0].buf = (void *)&txdata;
124
125 xfer[1].addr = i2c->addr;
126 xfer[1].flags = I2C_M_RD;
127 xfer[1].len = 2;
128 xfer[1].buf = (void *)rxdata;
129
130 ret = i2c_transfer(i2c->adapter, xfer, 2);
131 if (ret < 0)
132 return ret;
133 if (ret != 2)
134 return -EIO;
135
136 /*
137 * Byte 0 is transfer length, which is always 1 due
138 * to BCP register programming to 1 in si521xx_probe(),
139 * ignore it and use data from Byte 1.
140 */
141 *val = rxdata[1];
142 return 0;
143 }
144
145 static const struct regmap_config si521xx_regmap_config = {
146 .reg_bits = 8,
147 .val_bits = 8,
148 .cache_type = REGCACHE_FLAT,
149 .max_register = SI521XX_REG_DA,
150 .rd_table = &si521xx_readable_table,
151 .wr_table = &si521xx_writeable_table,
152 .reg_write = si521xx_regmap_i2c_write,
153 .reg_read = si521xx_regmap_i2c_read,
154 };
155
si521xx_diff_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)156 static unsigned long si521xx_diff_recalc_rate(struct clk_hw *hw,
157 unsigned long parent_rate)
158 {
159 unsigned long long rate;
160
161 rate = (unsigned long long)parent_rate * SI521XX_DIFF_MULT;
162 do_div(rate, SI521XX_DIFF_DIV);
163 return (unsigned long)rate;
164 }
165
si521xx_diff_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)166 static int si521xx_diff_determine_rate(struct clk_hw *hw,
167 struct clk_rate_request *req)
168 {
169 unsigned long best_parent;
170
171 best_parent = (req->rate / SI521XX_DIFF_MULT) * SI521XX_DIFF_DIV;
172 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
173
174 req->rate = (req->best_parent_rate / SI521XX_DIFF_DIV) * SI521XX_DIFF_MULT;
175
176 return 0;
177 }
178
si521xx_diff_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)179 static int si521xx_diff_set_rate(struct clk_hw *hw, unsigned long rate,
180 unsigned long parent_rate)
181 {
182 /*
183 * We must report success but we can do so unconditionally because
184 * si521xx_diff_round_rate returns values that ensure this call is a
185 * nop.
186 */
187
188 return 0;
189 }
190
191 #define to_si521xx_clk(_hw) container_of(_hw, struct si_clk, hw)
192
si521xx_diff_prepare(struct clk_hw * hw)193 static int si521xx_diff_prepare(struct clk_hw *hw)
194 {
195 struct si_clk *si_clk = to_si521xx_clk(hw);
196 struct si521xx *si = si_clk->si;
197
198 regmap_set_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
199
200 return 0;
201 }
202
si521xx_diff_unprepare(struct clk_hw * hw)203 static void si521xx_diff_unprepare(struct clk_hw *hw)
204 {
205 struct si_clk *si_clk = to_si521xx_clk(hw);
206 struct si521xx *si = si_clk->si;
207
208 regmap_clear_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
209 }
210
211 static const struct clk_ops si521xx_diff_clk_ops = {
212 .determine_rate = si521xx_diff_determine_rate,
213 .set_rate = si521xx_diff_set_rate,
214 .recalc_rate = si521xx_diff_recalc_rate,
215 .prepare = si521xx_diff_prepare,
216 .unprepare = si521xx_diff_unprepare,
217 };
218
si521xx_get_common_config(struct si521xx * si)219 static int si521xx_get_common_config(struct si521xx *si)
220 {
221 struct i2c_client *client = si->client;
222 struct device_node *np = client->dev.of_node;
223 unsigned int amp;
224 int ret;
225
226 /* Set defaults */
227 si->pll_amplitude = SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT);
228
229 /* Output clock amplitude */
230 ret = of_property_read_u32(np, "skyworks,out-amplitude-microvolt",
231 &);
232 if (!ret) {
233 if (amp < SI521XX_REG_DA_AMP_MIN || amp > SI521XX_REG_DA_AMP_MAX ||
234 amp % SI521XX_REG_DA_AMP_STEP) {
235 return dev_err_probe(&client->dev, -EINVAL,
236 "Invalid skyworks,out-amplitude-microvolt value\n");
237 }
238 si->pll_amplitude = SI521XX_REG_DA_AMP(amp);
239 }
240
241 return 0;
242 }
243
si521xx_update_config(struct si521xx * si)244 static void si521xx_update_config(struct si521xx *si)
245 {
246 /* If amplitude is non-default, update it. */
247 if (si->pll_amplitude == SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT))
248 return;
249
250 regmap_update_bits(si->regmap, SI521XX_REG_DA,
251 SI521XX_REG_DA_AMP_MASK, si->pll_amplitude);
252 }
253
si521xx_diff_idx_to_reg_bit(const u16 chip_info,const int idx,struct si_clk * clk)254 static void si521xx_diff_idx_to_reg_bit(const u16 chip_info, const int idx,
255 struct si_clk *clk)
256 {
257 unsigned long mask;
258 int oe, b, ctr = 0;
259
260 for (oe = 1; oe <= 2; oe++) {
261 mask = bitrev8(SI521XX_OE_MAP_GET_OE(oe, chip_info));
262 for_each_set_bit(b, &mask, 8) {
263 if (ctr++ != idx)
264 continue;
265 clk->reg = SI521XX_REG_OE(oe);
266 clk->bit = 7 - b;
267 return;
268 }
269 }
270 }
271
272 static struct clk_hw *
si521xx_of_clk_get(struct of_phandle_args * clkspec,void * data)273 si521xx_of_clk_get(struct of_phandle_args *clkspec, void *data)
274 {
275 struct si521xx *si = data;
276 unsigned int idx = clkspec->args[0];
277
278 return &si->clk_dif[idx].hw;
279 }
280
si521xx_probe(struct i2c_client * client)281 static int si521xx_probe(struct i2c_client *client)
282 {
283 const u16 chip_info = (u16)(uintptr_t)i2c_get_match_data(client);
284 const struct clk_parent_data clk_parent_data = { .index = 0 };
285 const u8 data[3] = { SI521XX_REG_BC, 1, 1 };
286 unsigned char name[16] = "DIFF0";
287 struct clk_init_data init = {};
288 struct si521xx *si;
289 int i, ret;
290
291 if (!chip_info)
292 return -EINVAL;
293
294 si = devm_kzalloc(&client->dev, sizeof(*si), GFP_KERNEL);
295 if (!si)
296 return -ENOMEM;
297
298 i2c_set_clientdata(client, si);
299 si->client = client;
300
301 /* Fetch common configuration from DT (if specified) */
302 ret = si521xx_get_common_config(si);
303 if (ret)
304 return ret;
305
306 si->regmap = devm_regmap_init(&client->dev, NULL, client,
307 &si521xx_regmap_config);
308 if (IS_ERR(si->regmap))
309 return dev_err_probe(&client->dev, PTR_ERR(si->regmap),
310 "Failed to allocate register map\n");
311
312 /* Always read back 1 Byte via I2C */
313 ret = i2c_master_send(client, data, ARRAY_SIZE(data));
314 if (ret < 0)
315 return ret;
316
317 /* Register clock */
318 for (i = 0; i < hweight16(chip_info); i++) {
319 memset(&init, 0, sizeof(init));
320 snprintf(name, sizeof(name), "DIFF%d", i);
321 init.name = name;
322 init.ops = &si521xx_diff_clk_ops;
323 init.parent_data = &clk_parent_data;
324 init.num_parents = 1;
325 init.flags = CLK_SET_RATE_PARENT;
326
327 si->clk_dif[i].hw.init = &init;
328 si->clk_dif[i].si = si;
329
330 si521xx_diff_idx_to_reg_bit(chip_info, i, &si->clk_dif[i]);
331
332 ret = devm_clk_hw_register(&client->dev, &si->clk_dif[i].hw);
333 if (ret)
334 return ret;
335 }
336
337 ret = devm_of_clk_add_hw_provider(&client->dev, si521xx_of_clk_get, si);
338 if (!ret)
339 si521xx_update_config(si);
340
341 return ret;
342 }
343
si521xx_suspend(struct device * dev)344 static int __maybe_unused si521xx_suspend(struct device *dev)
345 {
346 struct si521xx *si = dev_get_drvdata(dev);
347
348 regcache_cache_only(si->regmap, true);
349 regcache_mark_dirty(si->regmap);
350
351 return 0;
352 }
353
si521xx_resume(struct device * dev)354 static int __maybe_unused si521xx_resume(struct device *dev)
355 {
356 struct si521xx *si = dev_get_drvdata(dev);
357 int ret;
358
359 regcache_cache_only(si->regmap, false);
360 ret = regcache_sync(si->regmap);
361 if (ret)
362 dev_err(dev, "Failed to restore register map: %d\n", ret);
363 return ret;
364 }
365
366 static const struct i2c_device_id si521xx_id[] = {
367 { .name = "si52144", .driver_data = SI521XX_OE_MAP(0x5, 0xc0) },
368 { .name = "si52146", .driver_data = SI521XX_OE_MAP(0x15, 0xe0) },
369 { .name = "si52147", .driver_data = SI521XX_OE_MAP(0x17, 0xf8) },
370 { }
371 };
372 MODULE_DEVICE_TABLE(i2c, si521xx_id);
373
374 static const struct of_device_id clk_si521xx_of_match[] = {
375 { .compatible = "skyworks,si52144", .data = (void *)SI521XX_OE_MAP(0x5, 0xc0) },
376 { .compatible = "skyworks,si52146", .data = (void *)SI521XX_OE_MAP(0x15, 0xe0) },
377 { .compatible = "skyworks,si52147", .data = (void *)SI521XX_OE_MAP(0x15, 0xf8) },
378 { }
379 };
380 MODULE_DEVICE_TABLE(of, clk_si521xx_of_match);
381
382 static SIMPLE_DEV_PM_OPS(si521xx_pm_ops, si521xx_suspend, si521xx_resume);
383
384 static struct i2c_driver si521xx_driver = {
385 .driver = {
386 .name = "clk-si521xx",
387 .pm = &si521xx_pm_ops,
388 .of_match_table = clk_si521xx_of_match,
389 },
390 .probe = si521xx_probe,
391 .id_table = si521xx_id,
392 };
393 module_i2c_driver(si521xx_driver);
394
395 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
396 MODULE_DESCRIPTION("Skyworks Si521xx PCIe clock generator driver");
397 MODULE_LICENSE("GPL");
398