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Searched refs:SH_MEM_BASES (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c964 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_dma_vm_flush()
H A Dcikd.h1163 #define SH_MEM_BASES 0x8C28 macro
H A Dcik.c5510 WREG32(SH_MEM_BASES, 0); in cik_pcie_gart_enable()
5706 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1306 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v9_4_3_xcc_constants_init()
1309 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, in gfx_v9_4_3_xcc_constants_init()
H A Dgfx_v12_0.c1686 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v12_0_constants_init()
1688 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, in gfx_v12_0_constants_init()
H A Dgfx_v9_0.c2638 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v9_0_constants_init()
2640 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, in gfx_v9_0_constants_init()
H A Dgfx_v11_0.c1966 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v11_0_constants_init()
1968 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, in gfx_v11_0_constants_init()
H A Dgfx_v10_0.c5207 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v10_0_constants_init()
5209 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, in gfx_v10_0_constants_init()