1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Standard PCI Hot Plug Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/pci.h>
20 #include <linux/interrupt.h>
21
22 #include "shpchp.h"
23
24 /* Slot Available Register I field definition */
25 #define SLOT_33MHZ 0x0000001f
26 #define SLOT_66MHZ_PCIX 0x00001f00
27 #define SLOT_100MHZ_PCIX 0x001f0000
28 #define SLOT_133MHZ_PCIX 0x1f000000
29
30 /* Slot Available Register II field definition */
31 #define SLOT_66MHZ 0x0000001f
32 #define SLOT_66MHZ_PCIX_266 0x00000f00
33 #define SLOT_100MHZ_PCIX_266 0x0000f000
34 #define SLOT_133MHZ_PCIX_266 0x000f0000
35 #define SLOT_66MHZ_PCIX_533 0x00f00000
36 #define SLOT_100MHZ_PCIX_533 0x0f000000
37 #define SLOT_133MHZ_PCIX_533 0xf0000000
38
39 /* Slot Configuration */
40 #define SLOT_NUM 0x0000001F
41 #define FIRST_DEV_NUM 0x00001F00
42 #define PSN 0x07FF0000
43 #define UPDOWN 0x20000000
44 #define MRLSENSOR 0x40000000
45 #define ATTN_BUTTON 0x80000000
46
47 /*
48 * Interrupt Locator Register definitions
49 */
50 #define CMD_INTR_PENDING (1 << 0)
51 #define SLOT_INTR_PENDING(i) (1 << (i + 1))
52
53 /*
54 * Controller SERR-INT Register
55 */
56 #define GLOBAL_INTR_MASK (1 << 0)
57 #define GLOBAL_SERR_MASK (1 << 1)
58 #define COMMAND_INTR_MASK (1 << 2)
59 #define ARBITER_SERR_MASK (1 << 3)
60 #define COMMAND_DETECTED (1 << 16)
61 #define ARBITER_DETECTED (1 << 17)
62 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
63
64 /*
65 * Logical Slot Register definitions
66 */
67 #define SLOT_REG(i) (SLOT1 + (4 * i))
68
69 #define SLOT_STATE_SHIFT (0)
70 #define SLOT_STATE_MASK (3 << 0)
71 #define SLOT_STATE_PWRONLY (1)
72 #define SLOT_STATE_ENABLED (2)
73 #define SLOT_STATE_DISABLED (3)
74 #define PWR_LED_STATE_SHIFT (2)
75 #define PWR_LED_STATE_MASK (3 << 2)
76 #define ATN_LED_STATE_SHIFT (4)
77 #define ATN_LED_STATE_MASK (3 << 4)
78 #define ATN_LED_STATE_ON (1)
79 #define ATN_LED_STATE_BLINK (2)
80 #define ATN_LED_STATE_OFF (3)
81 #define POWER_FAULT (1 << 6)
82 #define ATN_BUTTON (1 << 7)
83 #define MRL_SENSOR (1 << 8)
84 #define MHZ66_CAP (1 << 9)
85 #define PRSNT_SHIFT (10)
86 #define PRSNT_MASK (3 << 10)
87 #define PCIX_CAP_SHIFT (12)
88 #define PCIX_CAP_MASK_PI1 (3 << 12)
89 #define PCIX_CAP_MASK_PI2 (7 << 12)
90 #define PRSNT_CHANGE_DETECTED (1 << 16)
91 #define ISO_PFAULT_DETECTED (1 << 17)
92 #define BUTTON_PRESS_DETECTED (1 << 18)
93 #define MRL_CHANGE_DETECTED (1 << 19)
94 #define CON_PFAULT_DETECTED (1 << 20)
95 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
96 #define ISO_PFAULT_INTR_MASK (1 << 25)
97 #define BUTTON_PRESS_INTR_MASK (1 << 26)
98 #define MRL_CHANGE_INTR_MASK (1 << 27)
99 #define CON_PFAULT_INTR_MASK (1 << 28)
100 #define MRL_CHANGE_SERR_MASK (1 << 29)
101 #define CON_PFAULT_SERR_MASK (1 << 30)
102 #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
103
104 /*
105 * SHPC Command Code definitions
106 *
107 * Slot Operation 00h - 3Fh
108 * Set Bus Segment Speed/Mode A 40h - 47h
109 * Power-Only All Slots 48h
110 * Enable All Slots 49h
111 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
112 * Reserved Command Codes 60h - BFh
113 * Vendor Specific Commands C0h - FFh
114 */
115 #define SET_SLOT_PWR 0x01 /* Slot Operation */
116 #define SET_SLOT_ENABLE 0x02
117 #define SET_SLOT_DISABLE 0x03
118 #define SET_PWR_ON 0x04
119 #define SET_PWR_BLINK 0x08
120 #define SET_PWR_OFF 0x0c
121 #define SET_ATTN_ON 0x10
122 #define SET_ATTN_BLINK 0x20
123 #define SET_ATTN_OFF 0x30
124 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
125 #define SETA_PCI_66MHZ 0x41
126 #define SETA_PCIX_66MHZ 0x42
127 #define SETA_PCIX_100MHZ 0x43
128 #define SETA_PCIX_133MHZ 0x44
129 #define SETA_RESERVED1 0x45
130 #define SETA_RESERVED2 0x46
131 #define SETA_RESERVED3 0x47
132 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
133 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
134 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
135 #define SETB_PCI_66MHZ 0x51
136 #define SETB_PCIX_66MHZ_PM 0x52
137 #define SETB_PCIX_100MHZ_PM 0x53
138 #define SETB_PCIX_133MHZ_PM 0x54
139 #define SETB_PCIX_66MHZ_EM 0x55
140 #define SETB_PCIX_100MHZ_EM 0x56
141 #define SETB_PCIX_133MHZ_EM 0x57
142 #define SETB_PCIX_66MHZ_266 0x58
143 #define SETB_PCIX_100MHZ_266 0x59
144 #define SETB_PCIX_133MHZ_266 0x5a
145 #define SETB_PCIX_66MHZ_533 0x5b
146 #define SETB_PCIX_100MHZ_533 0x5c
147 #define SETB_PCIX_133MHZ_533 0x5d
148 #define SETB_RESERVED1 0x5e
149 #define SETB_RESERVED2 0x5f
150
151 /*
152 * SHPC controller command error code
153 */
154 #define SWITCH_OPEN 0x1
155 #define INVALID_CMD 0x2
156 #define INVALID_SPEED_MODE 0x4
157
158 /*
159 * For accessing SHPC Working Register Set via PCI Configuration Space
160 */
161 #define DWORD_SELECT 0x2
162 #define DWORD_DATA 0x4
163
164 /* Field Offset in Logical Slot Register - byte boundary */
165 #define SLOT_EVENT_LATCH 0x2
166 #define SLOT_SERR_INT_MASK 0x3
167
168 static irqreturn_t shpc_isr(int irq, void *dev_id);
169 static void start_int_poll_timer(struct controller *ctrl, int sec);
170
shpc_readb(struct controller * ctrl,int reg)171 static inline u8 shpc_readb(struct controller *ctrl, int reg)
172 {
173 return readb(ctrl->creg + reg);
174 }
175
shpc_readw(struct controller * ctrl,int reg)176 static inline u16 shpc_readw(struct controller *ctrl, int reg)
177 {
178 return readw(ctrl->creg + reg);
179 }
180
shpc_writew(struct controller * ctrl,int reg,u16 val)181 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
182 {
183 writew(val, ctrl->creg + reg);
184 }
185
shpc_readl(struct controller * ctrl,int reg)186 static inline u32 shpc_readl(struct controller *ctrl, int reg)
187 {
188 return readl(ctrl->creg + reg);
189 }
190
shpc_writel(struct controller * ctrl,int reg,u32 val)191 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
192 {
193 writel(val, ctrl->creg + reg);
194 }
195
shpc_indirect_read(struct controller * ctrl,int index,u32 * value)196 static inline int shpc_indirect_read(struct controller *ctrl, int index,
197 u32 *value)
198 {
199 int rc;
200 u32 cap_offset = ctrl->cap_offset;
201 struct pci_dev *pdev = ctrl->pci_dev;
202
203 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
204 if (rc)
205 return rc;
206 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
207 }
208
209 /*
210 * This is the interrupt polling timeout function.
211 */
int_poll_timeout(struct timer_list * t)212 static void int_poll_timeout(struct timer_list *t)
213 {
214 struct controller *ctrl = from_timer(ctrl, t, poll_timer);
215
216 /* Poll for interrupt events. regs == NULL => polling */
217 shpc_isr(0, ctrl);
218
219 if (!shpchp_poll_time)
220 shpchp_poll_time = 2; /* default polling interval is 2 sec */
221
222 start_int_poll_timer(ctrl, shpchp_poll_time);
223 }
224
225 /*
226 * This function starts the interrupt polling timer.
227 */
start_int_poll_timer(struct controller * ctrl,int sec)228 static void start_int_poll_timer(struct controller *ctrl, int sec)
229 {
230 /* Clamp to sane value */
231 if ((sec <= 0) || (sec > 60))
232 sec = 2;
233
234 ctrl->poll_timer.expires = jiffies + sec * HZ;
235 add_timer(&ctrl->poll_timer);
236 }
237
is_ctrl_busy(struct controller * ctrl)238 static inline int is_ctrl_busy(struct controller *ctrl)
239 {
240 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
241 return cmd_status & 0x1;
242 }
243
244 /*
245 * Returns 1 if SHPC finishes executing a command within 1 sec,
246 * otherwise returns 0.
247 */
shpc_poll_ctrl_busy(struct controller * ctrl)248 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
249 {
250 int i;
251
252 if (!is_ctrl_busy(ctrl))
253 return 1;
254
255 /* Check every 0.1 sec for a total of 1 sec */
256 for (i = 0; i < 10; i++) {
257 msleep(100);
258 if (!is_ctrl_busy(ctrl))
259 return 1;
260 }
261
262 return 0;
263 }
264
shpc_wait_cmd(struct controller * ctrl)265 static inline int shpc_wait_cmd(struct controller *ctrl)
266 {
267 int retval = 0;
268 unsigned long timeout = msecs_to_jiffies(1000);
269 int rc;
270
271 if (shpchp_poll_mode)
272 rc = shpc_poll_ctrl_busy(ctrl);
273 else
274 rc = wait_event_interruptible_timeout(ctrl->queue,
275 !is_ctrl_busy(ctrl), timeout);
276 if (!rc && is_ctrl_busy(ctrl)) {
277 retval = -EIO;
278 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
279 } else if (rc < 0) {
280 retval = -EINTR;
281 ctrl_info(ctrl, "Command was interrupted by a signal\n");
282 }
283
284 return retval;
285 }
286
shpc_write_cmd(struct slot * slot,u8 t_slot,u8 cmd)287 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
288 {
289 struct controller *ctrl = slot->ctrl;
290 u16 cmd_status;
291 int retval = 0;
292 u16 temp_word;
293
294 mutex_lock(&slot->ctrl->cmd_lock);
295
296 if (!shpc_poll_ctrl_busy(ctrl)) {
297 /* After 1 sec and the controller is still busy */
298 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
299 retval = -EBUSY;
300 goto out;
301 }
302
303 ++t_slot;
304 temp_word = (t_slot << 8) | (cmd & 0xFF);
305 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
306
307 /* To make sure the Controller Busy bit is 0 before we send out the
308 * command.
309 */
310 shpc_writew(ctrl, CMD, temp_word);
311
312 /*
313 * Wait for command completion.
314 */
315 retval = shpc_wait_cmd(slot->ctrl);
316 if (retval)
317 goto out;
318
319 cmd_status = shpchp_check_cmd_status(slot->ctrl);
320 if (cmd_status) {
321 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
322 cmd, cmd_status);
323 retval = -EIO;
324 }
325 out:
326 mutex_unlock(&slot->ctrl->cmd_lock);
327 return retval;
328 }
329
shpchp_check_cmd_status(struct controller * ctrl)330 int shpchp_check_cmd_status(struct controller *ctrl)
331 {
332 int retval = 0;
333 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
334
335 switch (cmd_status >> 1) {
336 case 0:
337 retval = 0;
338 break;
339 case 1:
340 retval = SWITCH_OPEN;
341 ctrl_err(ctrl, "Switch opened!\n");
342 break;
343 case 2:
344 retval = INVALID_CMD;
345 ctrl_err(ctrl, "Invalid HPC command!\n");
346 break;
347 case 4:
348 retval = INVALID_SPEED_MODE;
349 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
350 break;
351 default:
352 retval = cmd_status;
353 }
354
355 return retval;
356 }
357
358
shpchp_get_attention_status(struct slot * slot,u8 * status)359 int shpchp_get_attention_status(struct slot *slot, u8 *status)
360 {
361 struct controller *ctrl = slot->ctrl;
362 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
363 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
364
365 switch (state) {
366 case ATN_LED_STATE_ON:
367 *status = 1; /* On */
368 break;
369 case ATN_LED_STATE_BLINK:
370 *status = 2; /* Blink */
371 break;
372 case ATN_LED_STATE_OFF:
373 *status = 0; /* Off */
374 break;
375 default:
376 *status = 0xFF; /* Reserved */
377 break;
378 }
379
380 return 0;
381 }
382
shpchp_get_power_status(struct slot * slot,u8 * status)383 int shpchp_get_power_status(struct slot *slot, u8 *status)
384 {
385 struct controller *ctrl = slot->ctrl;
386 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
387 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
388
389 switch (state) {
390 case SLOT_STATE_PWRONLY:
391 *status = 2; /* Powered only */
392 break;
393 case SLOT_STATE_ENABLED:
394 *status = 1; /* Enabled */
395 break;
396 case SLOT_STATE_DISABLED:
397 *status = 0; /* Disabled */
398 break;
399 default:
400 *status = 0xFF; /* Reserved */
401 break;
402 }
403
404 return 0;
405 }
406
407
shpchp_get_latch_status(struct slot * slot,u8 * status)408 int shpchp_get_latch_status(struct slot *slot, u8 *status)
409 {
410 struct controller *ctrl = slot->ctrl;
411 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
412
413 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
414
415 return 0;
416 }
417
shpchp_get_adapter_status(struct slot * slot,u8 * status)418 int shpchp_get_adapter_status(struct slot *slot, u8 *status)
419 {
420 struct controller *ctrl = slot->ctrl;
421 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
422 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
423
424 *status = (state != 0x3) ? 1 : 0;
425
426 return 0;
427 }
428
shpchp_get_prog_int(struct slot * slot,u8 * prog_int)429 int shpchp_get_prog_int(struct slot *slot, u8 *prog_int)
430 {
431 struct controller *ctrl = slot->ctrl;
432
433 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
434
435 return 0;
436 }
437
shpchp_get_adapter_speed(struct slot * slot,enum pci_bus_speed * value)438 int shpchp_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
439 {
440 int retval = 0;
441 struct controller *ctrl = slot->ctrl;
442 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
443 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
444 u8 pi, pcix_cap;
445
446 retval = shpchp_get_prog_int(slot, &pi);
447 if (retval)
448 return retval;
449
450 switch (pi) {
451 case 1:
452 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
453 break;
454 case 2:
455 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
456 break;
457 default:
458 return -ENODEV;
459 }
460
461 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
462 __func__, slot_reg, pcix_cap, m66_cap);
463
464 switch (pcix_cap) {
465 case 0x0:
466 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
467 break;
468 case 0x1:
469 *value = PCI_SPEED_66MHz_PCIX;
470 break;
471 case 0x3:
472 *value = PCI_SPEED_133MHz_PCIX;
473 break;
474 case 0x4:
475 *value = PCI_SPEED_133MHz_PCIX_266;
476 break;
477 case 0x5:
478 *value = PCI_SPEED_133MHz_PCIX_533;
479 break;
480 case 0x2:
481 default:
482 *value = PCI_SPEED_UNKNOWN;
483 retval = -ENODEV;
484 break;
485 }
486
487 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
488 return retval;
489 }
490
shpchp_query_power_fault(struct slot * slot)491 int shpchp_query_power_fault(struct slot *slot)
492 {
493 struct controller *ctrl = slot->ctrl;
494 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
495
496 /* Note: Logic 0 => fault */
497 return !(slot_reg & POWER_FAULT);
498 }
499
shpchp_set_attention_status(struct slot * slot,u8 value)500 int shpchp_set_attention_status(struct slot *slot, u8 value)
501 {
502 u8 slot_cmd = 0;
503
504 switch (value) {
505 case 0:
506 slot_cmd = SET_ATTN_OFF; /* OFF */
507 break;
508 case 1:
509 slot_cmd = SET_ATTN_ON; /* ON */
510 break;
511 case 2:
512 slot_cmd = SET_ATTN_BLINK; /* BLINK */
513 break;
514 default:
515 return -1;
516 }
517
518 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
519 }
520
521
shpchp_green_led_on(struct slot * slot)522 void shpchp_green_led_on(struct slot *slot)
523 {
524 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
525 }
526
shpchp_green_led_off(struct slot * slot)527 void shpchp_green_led_off(struct slot *slot)
528 {
529 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
530 }
531
shpchp_green_led_blink(struct slot * slot)532 void shpchp_green_led_blink(struct slot *slot)
533 {
534 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
535 }
536
shpchp_release_ctlr(struct controller * ctrl)537 void shpchp_release_ctlr(struct controller *ctrl)
538 {
539 int i;
540 u32 slot_reg, serr_int;
541
542 /*
543 * Mask event interrupts and SERRs of all slots
544 */
545 for (i = 0; i < ctrl->num_slots; i++) {
546 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
547 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
548 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
549 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
550 CON_PFAULT_SERR_MASK);
551 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
552 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
553 }
554
555 cleanup_slots(ctrl);
556
557 /*
558 * Mask SERR and System Interrupt generation
559 */
560 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
561 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
562 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
563 serr_int &= ~SERR_INTR_RSVDZ_MASK;
564 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
565
566 if (shpchp_poll_mode)
567 del_timer(&ctrl->poll_timer);
568 else {
569 free_irq(ctrl->pci_dev->irq, ctrl);
570 pci_disable_msi(ctrl->pci_dev);
571 }
572
573 iounmap(ctrl->creg);
574 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
575 }
576
shpchp_power_on_slot(struct slot * slot)577 int shpchp_power_on_slot(struct slot *slot)
578 {
579 int retval;
580
581 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
582 if (retval)
583 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
584
585 return retval;
586 }
587
shpchp_slot_enable(struct slot * slot)588 int shpchp_slot_enable(struct slot *slot)
589 {
590 int retval;
591
592 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
593 retval = shpc_write_cmd(slot, slot->hp_slot,
594 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
595 if (retval)
596 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
597
598 return retval;
599 }
600
shpchp_slot_disable(struct slot * slot)601 int shpchp_slot_disable(struct slot *slot)
602 {
603 int retval;
604
605 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
606 retval = shpc_write_cmd(slot, slot->hp_slot,
607 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
608 if (retval)
609 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
610
611 return retval;
612 }
613
shpc_get_cur_bus_speed(struct controller * ctrl)614 static int shpc_get_cur_bus_speed(struct controller *ctrl)
615 {
616 int retval = 0;
617 struct pci_bus *bus = ctrl->pci_dev->subordinate;
618 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
619 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
620 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
621 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
622
623 if ((pi == 1) && (speed_mode > 4)) {
624 retval = -ENODEV;
625 goto out;
626 }
627
628 switch (speed_mode) {
629 case 0x0:
630 bus_speed = PCI_SPEED_33MHz;
631 break;
632 case 0x1:
633 bus_speed = PCI_SPEED_66MHz;
634 break;
635 case 0x2:
636 bus_speed = PCI_SPEED_66MHz_PCIX;
637 break;
638 case 0x3:
639 bus_speed = PCI_SPEED_100MHz_PCIX;
640 break;
641 case 0x4:
642 bus_speed = PCI_SPEED_133MHz_PCIX;
643 break;
644 case 0x5:
645 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
646 break;
647 case 0x6:
648 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
649 break;
650 case 0x7:
651 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
652 break;
653 case 0x8:
654 bus_speed = PCI_SPEED_66MHz_PCIX_266;
655 break;
656 case 0x9:
657 bus_speed = PCI_SPEED_100MHz_PCIX_266;
658 break;
659 case 0xa:
660 bus_speed = PCI_SPEED_133MHz_PCIX_266;
661 break;
662 case 0xb:
663 bus_speed = PCI_SPEED_66MHz_PCIX_533;
664 break;
665 case 0xc:
666 bus_speed = PCI_SPEED_100MHz_PCIX_533;
667 break;
668 case 0xd:
669 bus_speed = PCI_SPEED_133MHz_PCIX_533;
670 break;
671 default:
672 retval = -ENODEV;
673 break;
674 }
675
676 out:
677 bus->cur_bus_speed = bus_speed;
678 dbg("Current bus speed = %d\n", bus_speed);
679 return retval;
680 }
681
682
shpchp_set_bus_speed_mode(struct slot * slot,enum pci_bus_speed value)683 int shpchp_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value)
684 {
685 int retval;
686 struct controller *ctrl = slot->ctrl;
687 u8 pi, cmd;
688
689 pi = shpc_readb(ctrl, PROG_INTERFACE);
690 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
691 return -EINVAL;
692
693 switch (value) {
694 case PCI_SPEED_33MHz:
695 cmd = SETA_PCI_33MHZ;
696 break;
697 case PCI_SPEED_66MHz:
698 cmd = SETA_PCI_66MHZ;
699 break;
700 case PCI_SPEED_66MHz_PCIX:
701 cmd = SETA_PCIX_66MHZ;
702 break;
703 case PCI_SPEED_100MHz_PCIX:
704 cmd = SETA_PCIX_100MHZ;
705 break;
706 case PCI_SPEED_133MHz_PCIX:
707 cmd = SETA_PCIX_133MHZ;
708 break;
709 case PCI_SPEED_66MHz_PCIX_ECC:
710 cmd = SETB_PCIX_66MHZ_EM;
711 break;
712 case PCI_SPEED_100MHz_PCIX_ECC:
713 cmd = SETB_PCIX_100MHZ_EM;
714 break;
715 case PCI_SPEED_133MHz_PCIX_ECC:
716 cmd = SETB_PCIX_133MHZ_EM;
717 break;
718 case PCI_SPEED_66MHz_PCIX_266:
719 cmd = SETB_PCIX_66MHZ_266;
720 break;
721 case PCI_SPEED_100MHz_PCIX_266:
722 cmd = SETB_PCIX_100MHZ_266;
723 break;
724 case PCI_SPEED_133MHz_PCIX_266:
725 cmd = SETB_PCIX_133MHZ_266;
726 break;
727 case PCI_SPEED_66MHz_PCIX_533:
728 cmd = SETB_PCIX_66MHZ_533;
729 break;
730 case PCI_SPEED_100MHz_PCIX_533:
731 cmd = SETB_PCIX_100MHZ_533;
732 break;
733 case PCI_SPEED_133MHz_PCIX_533:
734 cmd = SETB_PCIX_133MHZ_533;
735 break;
736 default:
737 return -EINVAL;
738 }
739
740 retval = shpc_write_cmd(slot, 0, cmd);
741 if (retval)
742 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
743 else
744 shpc_get_cur_bus_speed(ctrl);
745
746 return retval;
747 }
748
shpc_isr(int irq,void * dev_id)749 static irqreturn_t shpc_isr(int irq, void *dev_id)
750 {
751 struct controller *ctrl = (struct controller *)dev_id;
752 u32 serr_int, slot_reg, intr_loc, intr_loc2;
753 int hp_slot;
754
755 /* Check to see if it was our interrupt */
756 intr_loc = shpc_readl(ctrl, INTR_LOC);
757 if (!intr_loc)
758 return IRQ_NONE;
759
760 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
761
762 if (!shpchp_poll_mode) {
763 /*
764 * Mask Global Interrupt Mask - see implementation
765 * note on p. 139 of SHPC spec rev 1.0
766 */
767 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
768 serr_int |= GLOBAL_INTR_MASK;
769 serr_int &= ~SERR_INTR_RSVDZ_MASK;
770 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
771
772 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
773 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
774 }
775
776 if (intr_loc & CMD_INTR_PENDING) {
777 /*
778 * Command Complete Interrupt Pending
779 * RO only - clear by writing 1 to the Command Completion
780 * Detect bit in Controller SERR-INT register
781 */
782 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
783 serr_int &= ~SERR_INTR_RSVDZ_MASK;
784 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
785
786 wake_up_interruptible(&ctrl->queue);
787 }
788
789 if (!(intr_loc & ~CMD_INTR_PENDING))
790 goto out;
791
792 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
793 /* To find out which slot has interrupt pending */
794 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
795 continue;
796
797 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
798 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
799 hp_slot, slot_reg);
800
801 if (slot_reg & MRL_CHANGE_DETECTED)
802 shpchp_handle_switch_change(hp_slot, ctrl);
803
804 if (slot_reg & BUTTON_PRESS_DETECTED)
805 shpchp_handle_attention_button(hp_slot, ctrl);
806
807 if (slot_reg & PRSNT_CHANGE_DETECTED)
808 shpchp_handle_presence_change(hp_slot, ctrl);
809
810 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
811 shpchp_handle_power_fault(hp_slot, ctrl);
812
813 /* Clear all slot events */
814 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
815 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
816 }
817 out:
818 if (!shpchp_poll_mode) {
819 /* Unmask Global Interrupt Mask */
820 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
821 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
822 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
823 }
824
825 return IRQ_HANDLED;
826 }
827
shpc_get_max_bus_speed(struct controller * ctrl)828 static int shpc_get_max_bus_speed(struct controller *ctrl)
829 {
830 int retval = 0;
831 struct pci_bus *bus = ctrl->pci_dev->subordinate;
832 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
833 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
834 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
835 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
836
837 if (pi == 2) {
838 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
839 bus_speed = PCI_SPEED_133MHz_PCIX_533;
840 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
841 bus_speed = PCI_SPEED_100MHz_PCIX_533;
842 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
843 bus_speed = PCI_SPEED_66MHz_PCIX_533;
844 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
845 bus_speed = PCI_SPEED_133MHz_PCIX_266;
846 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
847 bus_speed = PCI_SPEED_100MHz_PCIX_266;
848 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
849 bus_speed = PCI_SPEED_66MHz_PCIX_266;
850 }
851
852 if (bus_speed == PCI_SPEED_UNKNOWN) {
853 if (slot_avail1 & SLOT_133MHZ_PCIX)
854 bus_speed = PCI_SPEED_133MHz_PCIX;
855 else if (slot_avail1 & SLOT_100MHZ_PCIX)
856 bus_speed = PCI_SPEED_100MHz_PCIX;
857 else if (slot_avail1 & SLOT_66MHZ_PCIX)
858 bus_speed = PCI_SPEED_66MHz_PCIX;
859 else if (slot_avail2 & SLOT_66MHZ)
860 bus_speed = PCI_SPEED_66MHz;
861 else if (slot_avail1 & SLOT_33MHZ)
862 bus_speed = PCI_SPEED_33MHz;
863 else
864 retval = -ENODEV;
865 }
866
867 bus->max_bus_speed = bus_speed;
868 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
869
870 return retval;
871 }
872
shpc_init(struct controller * ctrl,struct pci_dev * pdev)873 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
874 {
875 int rc = -1, num_slots = 0;
876 u8 hp_slot;
877 u32 shpc_base_offset;
878 u32 tempdword, slot_reg, slot_config;
879 u8 i;
880
881 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
882 ctrl_dbg(ctrl, "Hotplug Controller:\n");
883
884 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
885 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
886 /* amd shpc driver doesn't use Base Offset; assume 0 */
887 ctrl->mmio_base = pci_resource_start(pdev, 0);
888 ctrl->mmio_size = pci_resource_len(pdev, 0);
889 } else {
890 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
891 if (!ctrl->cap_offset) {
892 ctrl_err(ctrl, "Cannot find PCI capability\n");
893 goto abort;
894 }
895 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
896
897 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
898 if (rc) {
899 ctrl_err(ctrl, "Cannot read base_offset\n");
900 goto abort;
901 }
902
903 rc = shpc_indirect_read(ctrl, 3, &tempdword);
904 if (rc) {
905 ctrl_err(ctrl, "Cannot read slot config\n");
906 goto abort;
907 }
908 num_slots = tempdword & SLOT_NUM;
909 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
910
911 for (i = 0; i < 9 + num_slots; i++) {
912 rc = shpc_indirect_read(ctrl, i, &tempdword);
913 if (rc) {
914 ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
915 i);
916 goto abort;
917 }
918 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
919 }
920
921 ctrl->mmio_base =
922 pci_resource_start(pdev, 0) + shpc_base_offset;
923 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
924 }
925
926 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
927 pdev->vendor, pdev->device, pdev->subsystem_vendor,
928 pdev->subsystem_device);
929
930 rc = pci_enable_device(pdev);
931 if (rc) {
932 ctrl_err(ctrl, "pci_enable_device failed\n");
933 goto abort;
934 }
935
936 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
937 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
938 rc = -1;
939 goto abort;
940 }
941
942 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
943 if (!ctrl->creg) {
944 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
945 ctrl->mmio_size, ctrl->mmio_base);
946 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
947 rc = -1;
948 goto abort;
949 }
950 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
951
952 mutex_init(&ctrl->crit_sect);
953 mutex_init(&ctrl->cmd_lock);
954
955 /* Setup wait queue */
956 init_waitqueue_head(&ctrl->queue);
957
958 /* Return PCI Controller Info */
959 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
960 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
961 ctrl->num_slots = slot_config & SLOT_NUM;
962 ctrl->first_slot = (slot_config & PSN) >> 16;
963 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
964
965 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
966 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
967 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
968 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
969 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
970 tempdword &= ~SERR_INTR_RSVDZ_MASK;
971 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
972 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
973 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
974
975 /* Mask the MRL sensor SERR Mask of individual slot in
976 * Slot SERR-INT Mask & clear all the existing event if any
977 */
978 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
979 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
980 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
981 hp_slot, slot_reg);
982 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
983 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
984 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
985 CON_PFAULT_SERR_MASK);
986 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
987 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
988 }
989
990 if (shpchp_poll_mode) {
991 /* Install interrupt polling timer. Start with 10 sec delay */
992 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
993 start_int_poll_timer(ctrl, 10);
994 } else {
995 /* Installs the interrupt handler */
996 rc = pci_enable_msi(pdev);
997 if (rc) {
998 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
999 ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
1000 } else {
1001 pci_set_master(pdev);
1002 }
1003
1004 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1005 MY_NAME, (void *)ctrl);
1006 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1007 ctrl->pci_dev->irq, rc);
1008 if (rc) {
1009 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
1010 ctrl->pci_dev->irq);
1011 goto abort_iounmap;
1012 }
1013 }
1014 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1015
1016 shpc_get_max_bus_speed(ctrl);
1017 shpc_get_cur_bus_speed(ctrl);
1018
1019 /*
1020 * Unmask all event interrupts of all slots
1021 */
1022 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1023 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1024 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1025 hp_slot, slot_reg);
1026 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1027 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1028 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1029 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1030 }
1031 if (!shpchp_poll_mode) {
1032 /* Unmask all general input interrupts and SERR */
1033 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1034 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1035 SERR_INTR_RSVDZ_MASK);
1036 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1038 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1039 }
1040
1041 return 0;
1042
1043 /* We end up here for the many possible ways to fail this API. */
1044 abort_iounmap:
1045 iounmap(ctrl->creg);
1046 abort:
1047 return rc;
1048 }
1049