1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
3
4 #ifndef __SOUNDWIRE_H
5 #define __SOUNDWIRE_H
6
7 #include <linux/bug.h>
8 #include <linux/lockdep_types.h>
9 #include <linux/irq.h>
10 #include <linux/irqdomain.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/bitfield.h>
13
14 struct sdw_bus;
15 struct sdw_slave;
16
17 /* SDW spec defines and enums, as defined by MIPI 1.1. Spec */
18
19 /* SDW Broadcast Device Number */
20 #define SDW_BROADCAST_DEV_NUM 15
21
22 /* SDW Enumeration Device Number */
23 #define SDW_ENUM_DEV_NUM 0
24
25 /* SDW Group Device Numbers */
26 #define SDW_GROUP12_DEV_NUM 12
27 #define SDW_GROUP13_DEV_NUM 13
28
29 /* SDW Master Device Number, not supported yet */
30 #define SDW_MASTER_DEV_NUM 14
31
32 #define SDW_NUM_DEV_ID_REGISTERS 6
33 /* frame shape defines */
34
35 /*
36 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to
37 * fill hole with 0, one more dummy entry is added
38 */
39 #define SDW_FRAME_ROWS 24
40 #define SDW_FRAME_COLS 8
41 #define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS)
42
43 #define SDW_FRAME_CTRL_BITS 48
44 #define SDW_MAX_DEVICES 11
45
46 #define SDW_MAX_PORTS 15
47 #define SDW_VALID_PORT_RANGE(n) ((n) < SDW_MAX_PORTS && (n) >= 1)
48
49 enum {
50 SDW_PORT_DIRN_SINK = 0,
51 SDW_PORT_DIRN_SOURCE,
52 SDW_PORT_DIRN_MAX,
53 };
54
55 /*
56 * constants for flow control, ports and transport
57 *
58 * these are bit masks as devices can have multiple capabilities
59 */
60
61 /*
62 * flow modes for SDW port. These can be isochronous, tx controlled,
63 * rx controlled or async
64 */
65 #define SDW_PORT_FLOW_MODE_ISOCH 0
66 #define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0)
67 #define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1)
68 #define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0)
69
70 /* sample packaging for block. It can be per port or per channel */
71 #define SDW_BLOCK_PACKG_PER_PORT BIT(0)
72 #define SDW_BLOCK_PACKG_PER_CH BIT(1)
73
74 /**
75 * enum sdw_slave_status - Slave status
76 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus.
77 * @SDW_SLAVE_ATTACHED: Slave is attached with bus.
78 * @SDW_SLAVE_ALERT: Some alert condition on the Slave
79 * @SDW_SLAVE_RESERVED: Reserved for future use
80 */
81 enum sdw_slave_status {
82 SDW_SLAVE_UNATTACHED = 0,
83 SDW_SLAVE_ATTACHED = 1,
84 SDW_SLAVE_ALERT = 2,
85 SDW_SLAVE_RESERVED = 3,
86 };
87
88 /**
89 * enum sdw_clk_stop_type: clock stop operations
90 *
91 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare
92 * @SDW_CLK_POST_PREPARE: post clock stop prepare
93 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
94 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
95 */
96 enum sdw_clk_stop_type {
97 SDW_CLK_PRE_PREPARE = 0,
98 SDW_CLK_POST_PREPARE,
99 SDW_CLK_PRE_DEPREPARE,
100 SDW_CLK_POST_DEPREPARE,
101 };
102
103 /**
104 * enum sdw_command_response - Command response as defined by SDW spec
105 * @SDW_CMD_OK: cmd was successful
106 * @SDW_CMD_IGNORED: cmd was ignored
107 * @SDW_CMD_FAIL: cmd was NACKed
108 * @SDW_CMD_TIMEOUT: cmd timedout
109 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above
110 *
111 * NOTE: The enum is different than actual Spec as response in the Spec is
112 * combination of ACK/NAK bits
113 *
114 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec
115 */
116 enum sdw_command_response {
117 SDW_CMD_OK = 0,
118 SDW_CMD_IGNORED = 1,
119 SDW_CMD_FAIL = 2,
120 SDW_CMD_TIMEOUT = 3,
121 SDW_CMD_FAIL_OTHER = 4,
122 };
123
124 /* block group count enum */
125 enum sdw_dpn_grouping {
126 SDW_BLK_GRP_CNT_1 = 0,
127 SDW_BLK_GRP_CNT_2 = 1,
128 SDW_BLK_GRP_CNT_3 = 2,
129 SDW_BLK_GRP_CNT_4 = 3,
130 };
131
132 /* block packing mode enum */
133 enum sdw_dpn_pkg_mode {
134 SDW_BLK_PKG_PER_PORT = 0,
135 SDW_BLK_PKG_PER_CHANNEL = 1
136 };
137
138 /**
139 * enum sdw_stream_type: data stream type
140 *
141 * @SDW_STREAM_PCM: PCM data stream
142 * @SDW_STREAM_PDM: PDM data stream
143 *
144 * spec doesn't define this, but is used in implementation
145 */
146 enum sdw_stream_type {
147 SDW_STREAM_PCM = 0,
148 SDW_STREAM_PDM = 1,
149 };
150
151 /**
152 * enum sdw_data_direction: Data direction
153 *
154 * @SDW_DATA_DIR_RX: Data into Port
155 * @SDW_DATA_DIR_TX: Data out of Port
156 */
157 enum sdw_data_direction {
158 SDW_DATA_DIR_RX = 0,
159 SDW_DATA_DIR_TX = 1,
160 };
161
162 /**
163 * enum sdw_port_data_mode: Data Port mode
164 *
165 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received
166 * and transmitted.
167 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce
168 * a pseudo random data pattern that is transferred
169 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of
170 * logic 0. The encoding will result in no signal transitions
171 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of
172 * logic 1. The encoding will result in signal transitions at every bitslot
173 * owned by this Port
174 */
175 enum sdw_port_data_mode {
176 SDW_PORT_DATA_MODE_NORMAL = 0,
177 SDW_PORT_DATA_MODE_PRBS = 1,
178 SDW_PORT_DATA_MODE_STATIC_0 = 2,
179 SDW_PORT_DATA_MODE_STATIC_1 = 3,
180 };
181
182 /*
183 * SDW properties, defined in MIPI DisCo spec v1.0
184 */
185 enum sdw_clk_stop_reset_behave {
186 SDW_CLK_STOP_KEEP_STATUS = 1,
187 };
188
189 /**
190 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
191 * read
192 * @SDW_P15_READ_IGNORED: Read is ignored
193 * @SDW_P15_CMD_OK: Command is ok
194 */
195 enum sdw_p15_behave {
196 SDW_P15_READ_IGNORED = 0,
197 SDW_P15_CMD_OK = 1,
198 };
199
200 /**
201 * enum sdw_dpn_type - Data port types
202 * @SDW_DPN_FULL: Full Data Port is supported
203 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec.
204 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3
205 * are not implemented.
206 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec.
207 * DPN_SampleCtrl2, DPN_HCtrl are not implemented.
208 */
209 enum sdw_dpn_type {
210 SDW_DPN_FULL = 0,
211 SDW_DPN_SIMPLE = 1,
212 SDW_DPN_REDUCED = 2,
213 };
214
215 /**
216 * enum sdw_clk_stop_mode - Clock Stop modes
217 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock
218 * restart
219 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode,
220 * not capable of continuing operation seamlessly when the clock restarts
221 */
222 enum sdw_clk_stop_mode {
223 SDW_CLK_STOP_MODE0 = 0,
224 SDW_CLK_STOP_MODE1 = 1,
225 };
226
227 /**
228 * struct sdw_dp0_prop - DP0 properties
229 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
230 * (inclusive)
231 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
232 * (inclusive)
233 * @num_words: number of wordlengths supported
234 * @words: wordlengths supported
235 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady
236 * response
237 * @simple_ch_prep_sm: If channel prepare sequence is required
238 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
239 * @imp_def_interrupts: If set, each bit corresponds to support for
240 * implementation-defined interrupts
241 *
242 * The wordlengths are specified by Spec as max, min AND number of
243 * discrete values, implementation can define based on the wordlengths they
244 * support
245 */
246 struct sdw_dp0_prop {
247 u32 max_word;
248 u32 min_word;
249 u32 num_words;
250 u32 *words;
251 bool BRA_flow_controlled;
252 bool simple_ch_prep_sm;
253 u32 ch_prep_timeout;
254 bool imp_def_interrupts;
255 };
256
257 /**
258 * struct sdw_dpn_audio_mode - Audio mode properties for DPn
259 * @bus_min_freq: Minimum bus frequency, in Hz
260 * @bus_max_freq: Maximum bus frequency, in Hz
261 * @bus_num_freq: Number of discrete frequencies supported
262 * @bus_freq: Discrete bus frequencies, in Hz
263 * @min_freq: Minimum sampling frequency, in Hz
264 * @max_freq: Maximum sampling bus frequency, in Hz
265 * @num_freq: Number of discrete sampling frequency supported
266 * @freq: Discrete sampling frequencies, in Hz
267 * @prep_ch_behave: Specifies the dependencies between Channel Prepare
268 * sequence and bus clock configuration
269 * If 0, Channel Prepare can happen at any Bus clock rate
270 * If 1, Channel Prepare sequence shall happen only after Bus clock is
271 * changed to a frequency supported by this mode or compatible modes
272 * described by the next field
273 * @glitchless: Bitmap describing possible glitchless transitions from this
274 * Audio Mode to other Audio Modes
275 */
276 struct sdw_dpn_audio_mode {
277 u32 bus_min_freq;
278 u32 bus_max_freq;
279 u32 bus_num_freq;
280 u32 *bus_freq;
281 u32 max_freq;
282 u32 min_freq;
283 u32 num_freq;
284 u32 *freq;
285 u32 prep_ch_behave;
286 u32 glitchless;
287 };
288
289 /**
290 * struct sdw_dpn_prop - Data Port DPn properties
291 * @num: port number
292 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64
293 * (inclusive)
294 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64
295 * (inclusive)
296 * @num_words: Number of discrete supported wordlengths
297 * @words: Discrete supported wordlength
298 * @type: Data port type. Full, Simplified or Reduced
299 * @max_grouping: Maximum number of samples that can be grouped together for
300 * a full data port
301 * @simple_ch_prep_sm: If the port supports simplified channel prepare state
302 * machine
303 * @ch_prep_timeout: Port-specific timeout value, in milliseconds
304 * @imp_def_interrupts: If set, each bit corresponds to support for
305 * implementation-defined interrupts
306 * @max_ch: Maximum channels supported
307 * @min_ch: Minimum channels supported
308 * @num_channels: Number of discrete channels supported
309 * @channels: Discrete channels supported
310 * @num_ch_combinations: Number of channel combinations supported
311 * @ch_combinations: Channel combinations supported
312 * @modes: SDW mode supported
313 * @max_async_buffer: Number of samples that this port can buffer in
314 * asynchronous modes
315 * @block_pack_mode: Type of block port mode supported
316 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register
317 * @port_encoding: Payload Channel Sample encoding schemes supported
318 * @audio_modes: Audio modes supported
319 */
320 struct sdw_dpn_prop {
321 u32 num;
322 u32 max_word;
323 u32 min_word;
324 u32 num_words;
325 u32 *words;
326 enum sdw_dpn_type type;
327 u32 max_grouping;
328 bool simple_ch_prep_sm;
329 u32 ch_prep_timeout;
330 u32 imp_def_interrupts;
331 u32 max_ch;
332 u32 min_ch;
333 u32 num_channels;
334 u32 *channels;
335 u32 num_ch_combinations;
336 u32 *ch_combinations;
337 u32 modes;
338 u32 max_async_buffer;
339 bool block_pack_mode;
340 bool read_only_wordlength;
341 u32 port_encoding;
342 struct sdw_dpn_audio_mode *audio_modes;
343 };
344
345 /**
346 * struct sdw_slave_prop - SoundWire Slave properties
347 * @mipi_revision: Spec version of the implementation
348 * @wake_capable: Wake-up events are supported
349 * @test_mode_capable: If test mode is supported
350 * @clk_stop_mode1: Clock-Stop Mode 1 is supported
351 * @simple_clk_stop_capable: Simple clock mode is supported
352 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State
353 * Machine transitions, in milliseconds
354 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine
355 * transitions, in milliseconds
356 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare
357 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1
358 * @high_PHY_capable: Slave is HighPHY capable
359 * @paging_support: Slave implements paging registers SCP_AddrPage1 and
360 * SCP_AddrPage2
361 * @bank_delay_support: Slave implements bank delay/bridge support registers
362 * SCP_BankDelay and SCP_NextFrame
363 * @p15_behave: Slave behavior when the Master attempts a read to the Port15
364 * alias
365 * @lane_control_support: Slave supports lane control
366 * @master_count: Number of Masters present on this Slave
367 * @source_ports: Bitmap identifying source ports
368 * @sink_ports: Bitmap identifying sink ports
369 * @dp0_prop: Data Port 0 properties
370 * @src_dpn_prop: Source Data Port N properties
371 * @sink_dpn_prop: Sink Data Port N properties
372 * @scp_int1_mask: SCP_INT1_MASK desired settings
373 * @quirks: bitmask identifying deltas from the MIPI specification
374 * @clock_reg_supported: the Peripheral implements the clock base and scale
375 * registers introduced with the SoundWire 1.2 specification. SDCA devices
376 * do not need to set this boolean property as the registers are required.
377 * @use_domain_irq: call actual IRQ handler on slave, as well as callback
378 */
379 struct sdw_slave_prop {
380 u32 mipi_revision;
381 bool wake_capable;
382 bool test_mode_capable;
383 bool clk_stop_mode1;
384 bool simple_clk_stop_capable;
385 u32 clk_stop_timeout;
386 u32 ch_prep_timeout;
387 enum sdw_clk_stop_reset_behave reset_behave;
388 bool high_PHY_capable;
389 bool paging_support;
390 bool bank_delay_support;
391 enum sdw_p15_behave p15_behave;
392 bool lane_control_support;
393 u32 master_count;
394 u32 source_ports;
395 u32 sink_ports;
396 struct sdw_dp0_prop *dp0_prop;
397 struct sdw_dpn_prop *src_dpn_prop;
398 struct sdw_dpn_prop *sink_dpn_prop;
399 u8 scp_int1_mask;
400 u32 quirks;
401 bool clock_reg_supported;
402 bool use_domain_irq;
403 };
404
405 #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0)
406
407 /**
408 * struct sdw_master_prop - Master properties
409 * @revision: MIPI spec version of the implementation
410 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported
411 * @max_clk_freq: Maximum Bus clock frequency, in Hz
412 * @num_clk_gears: Number of clock gears supported
413 * @clk_gears: Clock gears supported
414 * @num_clk_freq: Number of clock frequencies supported, in Hz
415 * @clk_freq: Clock frequencies supported, in Hz
416 * @default_frame_rate: Controller default Frame rate, in Hz
417 * @default_row: Number of rows
418 * @default_col: Number of columns
419 * @dynamic_frame: Dynamic frame shape supported
420 * @err_threshold: Number of times that software may retry sending a single
421 * command
422 * @mclk_freq: clock reference passed to SoundWire Master, in Hz.
423 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux
424 * @quirks: bitmask identifying optional behavior beyond the scope of the MIPI specification
425 */
426 struct sdw_master_prop {
427 u32 revision;
428 u32 clk_stop_modes;
429 u32 max_clk_freq;
430 u32 num_clk_gears;
431 u32 *clk_gears;
432 u32 num_clk_freq;
433 u32 *clk_freq;
434 u32 default_frame_rate;
435 u32 default_row;
436 u32 default_col;
437 bool dynamic_frame;
438 u32 err_threshold;
439 u32 mclk_freq;
440 bool hw_disabled;
441 u64 quirks;
442 };
443
444 /* Definitions for Master quirks */
445
446 /*
447 * In a number of platforms bus clashes are reported after a hardware
448 * reset but without any explanations or evidence of a real problem.
449 * The following quirk will discard all initial bus clash interrupts
450 * but will leave the detection on should real bus clashes happen
451 */
452 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH BIT(0)
453
454 /*
455 * Some Slave devices have known issues with incorrect parity errors
456 * reported after a hardware reset. However during integration unexplained
457 * parity errors can be reported by Slave devices, possibly due to electrical
458 * issues at the Master level.
459 * The following quirk will discard all initial parity errors but will leave
460 * the detection on should real parity errors happen.
461 */
462 #define SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY BIT(1)
463
464 int sdw_master_read_prop(struct sdw_bus *bus);
465 int sdw_slave_read_prop(struct sdw_slave *slave);
466
467 /*
468 * SDW Slave Structures and APIs
469 */
470
471 #define SDW_IGNORED_UNIQUE_ID 0xFF
472
473 /**
474 * struct sdw_slave_id - Slave ID
475 * @mfg_id: MIPI Manufacturer ID
476 * @part_id: Device Part ID
477 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec)
478 * @unique_id: Device unique ID
479 * @sdw_version: SDW version implemented
480 *
481 * The order of the IDs here does not follow the DisCo spec definitions
482 */
483 struct sdw_slave_id {
484 __u16 mfg_id;
485 __u16 part_id;
486 __u8 class_id;
487 __u8 unique_id;
488 __u8 sdw_version:4;
489 };
490
491 struct sdw_extended_slave_id {
492 int link_id;
493 struct sdw_slave_id id;
494 };
495
496 /*
497 * Helper macros to extract the MIPI-defined IDs
498 *
499 * Spec definition
500 * Register Bit Contents
501 * DevId_0 [7:4] 47:44 sdw_version
502 * DevId_0 [3:0] 43:40 unique_id
503 * DevId_1 39:32 mfg_id [15:8]
504 * DevId_2 31:24 mfg_id [7:0]
505 * DevId_3 23:16 part_id [15:8]
506 * DevId_4 15:08 part_id [7:0]
507 * DevId_5 07:00 class_id
508 *
509 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48
510 */
511 #define SDW_DISCO_LINK_ID_MASK GENMASK_ULL(51, 48)
512 #define SDW_VERSION_MASK GENMASK_ULL(47, 44)
513 #define SDW_UNIQUE_ID_MASK GENMASK_ULL(43, 40)
514 #define SDW_MFG_ID_MASK GENMASK_ULL(39, 24)
515 #define SDW_PART_ID_MASK GENMASK_ULL(23, 8)
516 #define SDW_CLASS_ID_MASK GENMASK_ULL(7, 0)
517
518 #define SDW_DISCO_LINK_ID(addr) FIELD_GET(SDW_DISCO_LINK_ID_MASK, addr)
519 #define SDW_VERSION(addr) FIELD_GET(SDW_VERSION_MASK, addr)
520 #define SDW_UNIQUE_ID(addr) FIELD_GET(SDW_UNIQUE_ID_MASK, addr)
521 #define SDW_MFG_ID(addr) FIELD_GET(SDW_MFG_ID_MASK, addr)
522 #define SDW_PART_ID(addr) FIELD_GET(SDW_PART_ID_MASK, addr)
523 #define SDW_CLASS_ID(addr) FIELD_GET(SDW_CLASS_ID_MASK, addr)
524
525 /**
526 * struct sdw_slave_intr_status - Slave interrupt status
527 * @sdca_cascade: set if the Slave device reports an SDCA interrupt
528 * @control_port: control port status
529 * @port: data port status
530 */
531 struct sdw_slave_intr_status {
532 bool sdca_cascade;
533 u8 control_port;
534 u8 port[15];
535 };
536
537 /**
538 * sdw_reg_bank - SoundWire register banks
539 * @SDW_BANK0: Soundwire register bank 0
540 * @SDW_BANK1: Soundwire register bank 1
541 */
542 enum sdw_reg_bank {
543 SDW_BANK0,
544 SDW_BANK1,
545 };
546
547 /**
548 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel
549 *
550 * @num: Port number
551 * @ch_mask: Active channel mask
552 * @prepare: Prepare (true) /de-prepare (false) channel
553 * @bank: Register bank, which bank Slave/Master driver should program for
554 * implementation defined registers. This is always updated to next_bank
555 * value read from bus params.
556 *
557 */
558 struct sdw_prepare_ch {
559 unsigned int num;
560 unsigned int ch_mask;
561 bool prepare;
562 unsigned int bank;
563 };
564
565 /**
566 * enum sdw_port_prep_ops: Prepare operations for Data Port
567 *
568 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port
569 * @SDW_OPS_PORT_PRE_DEPREP: Pre deprepare operation for the Port
570 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port
571 * @SDW_OPS_PORT_POST_DEPREP: Post deprepare operation for the Port
572 */
573 enum sdw_port_prep_ops {
574 SDW_OPS_PORT_PRE_PREP = 0,
575 SDW_OPS_PORT_PRE_DEPREP,
576 SDW_OPS_PORT_POST_PREP,
577 SDW_OPS_PORT_POST_DEPREP,
578 };
579
580 /**
581 * struct sdw_bus_params: Structure holding bus configuration
582 *
583 * @curr_bank: Current bank in use (BANK0/BANK1)
584 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
585 * set to !curr_bank
586 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz
587 * @curr_dr_freq: Current double rate clock frequency, in Hz
588 * @bandwidth: Current bandwidth
589 * @col: Active columns
590 * @row: Active rows
591 * @s_data_mode: NORMAL, STATIC or PRBS mode for all Slave ports
592 * @m_data_mode: NORMAL, STATIC or PRBS mode for all Master ports. The value
593 * should be the same to detect transmission issues, but can be different to
594 * test the interrupt reports
595 */
596 struct sdw_bus_params {
597 enum sdw_reg_bank curr_bank;
598 enum sdw_reg_bank next_bank;
599 unsigned int max_dr_freq;
600 unsigned int curr_dr_freq;
601 unsigned int bandwidth;
602 unsigned int col;
603 unsigned int row;
604 int s_data_mode;
605 int m_data_mode;
606 };
607
608 /**
609 * struct sdw_slave_ops: Slave driver callback ops
610 *
611 * @read_prop: Read Slave properties
612 * @interrupt_callback: Device interrupt notification (invoked in thread
613 * context)
614 * @update_status: Update Slave status
615 * @bus_config: Update the bus config for Slave
616 * @port_prep: Prepare the port with parameters
617 * @clk_stop: handle imp-def sequences before and after prepare and de-prepare
618 */
619 struct sdw_slave_ops {
620 int (*read_prop)(struct sdw_slave *sdw);
621 int (*interrupt_callback)(struct sdw_slave *slave,
622 struct sdw_slave_intr_status *status);
623 int (*update_status)(struct sdw_slave *slave,
624 enum sdw_slave_status status);
625 int (*bus_config)(struct sdw_slave *slave,
626 struct sdw_bus_params *params);
627 int (*port_prep)(struct sdw_slave *slave,
628 struct sdw_prepare_ch *prepare_ch,
629 enum sdw_port_prep_ops pre_ops);
630 int (*clk_stop)(struct sdw_slave *slave,
631 enum sdw_clk_stop_mode mode,
632 enum sdw_clk_stop_type type);
633
634 };
635
636 /**
637 * struct sdw_slave - SoundWire Slave
638 * @id: MIPI device ID
639 * @dev: Linux device
640 * @irq: IRQ number
641 * @status: Status reported by the Slave
642 * @bus: Bus handle
643 * @prop: Slave properties
644 * @debugfs: Slave debugfs
645 * @node: node for bus list
646 * @port_ready: Port ready completion flag for each Slave port
647 * @m_port_map: static Master port map for each Slave port
648 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky
649 * @dev_num_sticky: one-time static Device Number assigned by Bus
650 * @probed: boolean tracking driver state
651 * @enumeration_complete: completion utility to control potential races
652 * on startup between device enumeration and read/write access to the
653 * Slave device
654 * @initialization_complete: completion utility to control potential races
655 * on startup between device enumeration and settings being restored
656 * @unattach_request: mask field to keep track why the Slave re-attached and
657 * was re-initialized. This is useful to deal with potential race conditions
658 * between the Master suspending and the codec resuming, and make sure that
659 * when the Master triggered a reset the Slave is properly enumerated and
660 * initialized
661 * @first_interrupt_done: status flag tracking if the interrupt handling
662 * for a Slave happens for the first time after enumeration
663 * @is_mockup_device: status flag used to squelch errors in the command/control
664 * protocol for SoundWire mockup devices
665 * @sdw_dev_lock: mutex used to protect callbacks/remove races
666 */
667 struct sdw_slave {
668 struct sdw_slave_id id;
669 struct device dev;
670 int irq;
671 enum sdw_slave_status status;
672 struct sdw_bus *bus;
673 struct sdw_slave_prop prop;
674 #ifdef CONFIG_DEBUG_FS
675 struct dentry *debugfs;
676 #endif
677 struct list_head node;
678 struct completion port_ready[SDW_MAX_PORTS];
679 unsigned int m_port_map[SDW_MAX_PORTS];
680 u16 dev_num;
681 u16 dev_num_sticky;
682 bool probed;
683 struct completion enumeration_complete;
684 struct completion initialization_complete;
685 u32 unattach_request;
686 bool first_interrupt_done;
687 bool is_mockup_device;
688 struct mutex sdw_dev_lock; /* protect callbacks/remove races */
689 };
690
691 #define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev)
692
693 /**
694 * struct sdw_master_device - SoundWire 'Master Device' representation
695 * @dev: Linux device for this Master
696 * @bus: Bus handle shortcut
697 */
698 struct sdw_master_device {
699 struct device dev;
700 struct sdw_bus *bus;
701 };
702
703 #define dev_to_sdw_master_device(d) \
704 container_of(d, struct sdw_master_device, dev)
705
706 struct sdw_driver {
707 const char *name;
708
709 int (*probe)(struct sdw_slave *sdw,
710 const struct sdw_device_id *id);
711 int (*remove)(struct sdw_slave *sdw);
712 void (*shutdown)(struct sdw_slave *sdw);
713
714 const struct sdw_device_id *id_table;
715 const struct sdw_slave_ops *ops;
716
717 struct device_driver driver;
718 };
719
720 #define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \
721 { .mfg_id = (_mfg_id), .part_id = (_part_id), \
722 .sdw_version = (_version), .class_id = (_c_id), \
723 .driver_data = (unsigned long)(_drv_data) }
724
725 #define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \
726 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data))
727
728 int sdw_handle_slave_status(struct sdw_bus *bus,
729 enum sdw_slave_status status[]);
730
731 /*
732 * SDW master structures and APIs
733 */
734
735 /**
736 * struct sdw_port_params: Data Port parameters
737 *
738 * @num: Port number
739 * @bps: Word length of the Port
740 * @flow_mode: Port Data flow mode
741 * @data_mode: Test modes or normal mode
742 *
743 * This is used to program the Data Port based on Data Port stream
744 * parameters.
745 */
746 struct sdw_port_params {
747 unsigned int num;
748 unsigned int bps;
749 unsigned int flow_mode;
750 unsigned int data_mode;
751 };
752
753 /**
754 * struct sdw_transport_params: Data Port Transport Parameters
755 *
756 * @blk_grp_ctrl_valid: Port implements block group control
757 * @num: Port number
758 * @blk_grp_ctrl: Block group control value
759 * @sample_interval: Sample interval
760 * @offset1: Blockoffset of the payload data
761 * @offset2: Blockoffset of the payload data
762 * @hstart: Horizontal start of the payload data
763 * @hstop: Horizontal stop of the payload data
764 * @blk_pkg_mode: Block per channel or block per port
765 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single
766 * data lane is supported in bus
767 *
768 * This is used to program the Data Port based on Data Port transport
769 * parameters. All these parameters are banked and can be modified
770 * during a bank switch without any artifacts in audio stream.
771 */
772 struct sdw_transport_params {
773 bool blk_grp_ctrl_valid;
774 unsigned int port_num;
775 unsigned int blk_grp_ctrl;
776 unsigned int sample_interval;
777 unsigned int offset1;
778 unsigned int offset2;
779 unsigned int hstart;
780 unsigned int hstop;
781 unsigned int blk_pkg_mode;
782 unsigned int lane_ctrl;
783 };
784
785 /**
786 * struct sdw_enable_ch: Enable/disable Data Port channel
787 *
788 * @num: Port number
789 * @ch_mask: Active channel mask
790 * @enable: Enable (true) /disable (false) channel
791 */
792 struct sdw_enable_ch {
793 unsigned int port_num;
794 unsigned int ch_mask;
795 bool enable;
796 };
797
798 /**
799 * struct sdw_master_port_ops: Callback functions from bus to Master
800 * driver to set Master Data ports.
801 *
802 * @dpn_set_port_params: Set the Port parameters for the Master Port.
803 * Mandatory callback
804 * @dpn_set_port_transport_params: Set transport parameters for the Master
805 * Port. Mandatory callback
806 * @dpn_port_prep: Port prepare operations for the Master Data Port.
807 * @dpn_port_enable_ch: Enable the channels of Master Port.
808 */
809 struct sdw_master_port_ops {
810 int (*dpn_set_port_params)(struct sdw_bus *bus,
811 struct sdw_port_params *port_params,
812 unsigned int bank);
813 int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
814 struct sdw_transport_params *transport_params,
815 enum sdw_reg_bank bank);
816 int (*dpn_port_prep)(struct sdw_bus *bus,
817 struct sdw_prepare_ch *prepare_ch);
818 int (*dpn_port_enable_ch)(struct sdw_bus *bus,
819 struct sdw_enable_ch *enable_ch, unsigned int bank);
820 };
821
822 struct sdw_msg;
823
824 /**
825 * struct sdw_defer - SDW deffered message
826 * @length: message length
827 * @complete: message completion
828 * @msg: SDW message
829 */
830 struct sdw_defer {
831 int length;
832 struct completion complete;
833 struct sdw_msg *msg;
834 };
835
836 /**
837 * struct sdw_master_ops - Master driver ops
838 * @read_prop: Read Master properties
839 * @override_adr: Override value read from firmware (quirk for buggy firmware)
840 * @xfer_msg: Transfer message callback
841 * @xfer_msg_defer: Defer version of transfer message callback. The message is handled with the
842 * bus struct @sdw_defer
843 * @set_bus_conf: Set the bus configuration
844 * @pre_bank_switch: Callback for pre bank switch
845 * @post_bank_switch: Callback for post bank switch
846 * @read_ping_status: Read status from PING frames, reported with two bits per Device.
847 * Bits 31:24 are reserved.
848 * @get_device_num: Callback for vendor-specific device_number allocation
849 * @put_device_num: Callback for vendor-specific device_number release
850 * @new_peripheral_assigned: Callback to handle enumeration of new peripheral.
851 */
852 struct sdw_master_ops {
853 int (*read_prop)(struct sdw_bus *bus);
854 u64 (*override_adr)
855 (struct sdw_bus *bus, u64 addr);
856 enum sdw_command_response (*xfer_msg)
857 (struct sdw_bus *bus, struct sdw_msg *msg);
858 enum sdw_command_response (*xfer_msg_defer)
859 (struct sdw_bus *bus);
860 int (*set_bus_conf)(struct sdw_bus *bus,
861 struct sdw_bus_params *params);
862 int (*pre_bank_switch)(struct sdw_bus *bus);
863 int (*post_bank_switch)(struct sdw_bus *bus);
864 u32 (*read_ping_status)(struct sdw_bus *bus);
865 int (*get_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
866 void (*put_device_num)(struct sdw_bus *bus, struct sdw_slave *slave);
867 void (*new_peripheral_assigned)(struct sdw_bus *bus,
868 struct sdw_slave *slave,
869 int dev_num);
870 };
871
872 /**
873 * struct sdw_bus - SoundWire bus
874 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code.
875 * @md: Master device
876 * @controller_id: system-unique controller ID. If set to -1, the bus @id will be used.
877 * @link_id: Link id number, can be 0 to N, unique for each Controller
878 * @id: bus system-wide unique id
879 * @slaves: list of Slaves on this bus
880 * @assigned: Bitmap for Slave device numbers.
881 * Bit set implies used number, bit clear implies unused number.
882 * @bus_lock: bus lock
883 * @msg_lock: message lock
884 * @compute_params: points to Bus resource management implementation
885 * @ops: Master callback ops
886 * @port_ops: Master port callback ops
887 * @params: Current bus parameters
888 * @prop: Master properties
889 * @vendor_specific_prop: pointer to non-standard properties
890 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This
891 * is used to compute and program bus bandwidth, clock, frame shape,
892 * transport and port parameters
893 * @debugfs: Bus debugfs
894 * @domain: IRQ domain
895 * @defer_msg: Defer message
896 * @clk_stop_timeout: Clock stop timeout computed
897 * @bank_switch_timeout: Bank switch timeout computed
898 * @multi_link: Store bus property that indicates if multi links
899 * are supported. This flag is populated by drivers after reading
900 * appropriate firmware (ACPI/DT).
901 * @hw_sync_min_links: Number of links used by a stream above which
902 * hardware-based synchronization is required. This value is only
903 * meaningful if multi_link is set. If set to 1, hardware-based
904 * synchronization will be used even if a stream only uses a single
905 * SoundWire segment.
906 * @stream_refcount: number of streams currently using this bus
907 */
908 struct sdw_bus {
909 struct device *dev;
910 struct sdw_master_device *md;
911 int controller_id;
912 unsigned int link_id;
913 int id;
914 struct list_head slaves;
915 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES);
916 struct mutex bus_lock;
917 struct lock_class_key bus_lock_key;
918 struct mutex msg_lock;
919 struct lock_class_key msg_lock_key;
920 int (*compute_params)(struct sdw_bus *bus);
921 const struct sdw_master_ops *ops;
922 const struct sdw_master_port_ops *port_ops;
923 struct sdw_bus_params params;
924 struct sdw_master_prop prop;
925 void *vendor_specific_prop;
926 struct list_head m_rt_list;
927 #ifdef CONFIG_DEBUG_FS
928 struct dentry *debugfs;
929 #endif
930 struct irq_chip irq_chip;
931 struct irq_domain *domain;
932 struct sdw_defer defer_msg;
933 unsigned int clk_stop_timeout;
934 u32 bank_switch_timeout;
935 bool multi_link;
936 int hw_sync_min_links;
937 int stream_refcount;
938 };
939
940 int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
941 struct fwnode_handle *fwnode);
942 void sdw_bus_master_delete(struct sdw_bus *bus);
943
944 void sdw_show_ping_status(struct sdw_bus *bus, bool sync_delay);
945
946 /**
947 * sdw_port_config: Master or Slave Port configuration
948 *
949 * @num: Port number
950 * @ch_mask: channels mask for port
951 */
952 struct sdw_port_config {
953 unsigned int num;
954 unsigned int ch_mask;
955 };
956
957 /**
958 * sdw_stream_config: Master or Slave stream configuration
959 *
960 * @frame_rate: Audio frame rate of the stream, in Hz
961 * @ch_count: Channel count of the stream
962 * @bps: Number of bits per audio sample
963 * @direction: Data direction
964 * @type: Stream type PCM or PDM
965 */
966 struct sdw_stream_config {
967 unsigned int frame_rate;
968 unsigned int ch_count;
969 unsigned int bps;
970 enum sdw_data_direction direction;
971 enum sdw_stream_type type;
972 };
973
974 /**
975 * sdw_stream_state: Stream states
976 *
977 * @SDW_STREAM_ALLOCATED: New stream allocated.
978 * @SDW_STREAM_CONFIGURED: Stream configured
979 * @SDW_STREAM_PREPARED: Stream prepared
980 * @SDW_STREAM_ENABLED: Stream enabled
981 * @SDW_STREAM_DISABLED: Stream disabled
982 * @SDW_STREAM_DEPREPARED: Stream de-prepared
983 * @SDW_STREAM_RELEASED: Stream released
984 */
985 enum sdw_stream_state {
986 SDW_STREAM_ALLOCATED = 0,
987 SDW_STREAM_CONFIGURED = 1,
988 SDW_STREAM_PREPARED = 2,
989 SDW_STREAM_ENABLED = 3,
990 SDW_STREAM_DISABLED = 4,
991 SDW_STREAM_DEPREPARED = 5,
992 SDW_STREAM_RELEASED = 6,
993 };
994
995 /**
996 * sdw_stream_params: Stream parameters
997 *
998 * @rate: Sampling frequency, in Hz
999 * @ch_count: Number of channels
1000 * @bps: bits per channel sample
1001 */
1002 struct sdw_stream_params {
1003 unsigned int rate;
1004 unsigned int ch_count;
1005 unsigned int bps;
1006 };
1007
1008 /**
1009 * sdw_stream_runtime: Runtime stream parameters
1010 *
1011 * @name: SoundWire stream name
1012 * @params: Stream parameters
1013 * @state: Current state of the stream
1014 * @type: Stream type PCM or PDM
1015 * @master_list: List of Master runtime(s) in this stream.
1016 * master_list can contain only one m_rt per Master instance
1017 * for a stream
1018 * @m_rt_count: Count of Master runtime(s) in this stream
1019 */
1020 struct sdw_stream_runtime {
1021 const char *name;
1022 struct sdw_stream_params params;
1023 enum sdw_stream_state state;
1024 enum sdw_stream_type type;
1025 struct list_head master_list;
1026 int m_rt_count;
1027 };
1028
1029 struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name);
1030 void sdw_release_stream(struct sdw_stream_runtime *stream);
1031
1032 int sdw_compute_params(struct sdw_bus *bus);
1033
1034 int sdw_stream_add_master(struct sdw_bus *bus,
1035 struct sdw_stream_config *stream_config,
1036 const struct sdw_port_config *port_config,
1037 unsigned int num_ports,
1038 struct sdw_stream_runtime *stream);
1039 int sdw_stream_remove_master(struct sdw_bus *bus,
1040 struct sdw_stream_runtime *stream);
1041 int sdw_startup_stream(void *sdw_substream);
1042 int sdw_prepare_stream(struct sdw_stream_runtime *stream);
1043 int sdw_enable_stream(struct sdw_stream_runtime *stream);
1044 int sdw_disable_stream(struct sdw_stream_runtime *stream);
1045 int sdw_deprepare_stream(struct sdw_stream_runtime *stream);
1046 void sdw_shutdown_stream(void *sdw_substream);
1047 int sdw_bus_prep_clk_stop(struct sdw_bus *bus);
1048 int sdw_bus_clk_stop(struct sdw_bus *bus);
1049 int sdw_bus_exit_clk_stop(struct sdw_bus *bus);
1050
1051 int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id);
1052 void sdw_extract_slave_id(struct sdw_bus *bus, u64 addr, struct sdw_slave_id *id);
1053
1054 #if IS_ENABLED(CONFIG_SOUNDWIRE)
1055
1056 int sdw_stream_add_slave(struct sdw_slave *slave,
1057 struct sdw_stream_config *stream_config,
1058 const struct sdw_port_config *port_config,
1059 unsigned int num_ports,
1060 struct sdw_stream_runtime *stream);
1061 int sdw_stream_remove_slave(struct sdw_slave *slave,
1062 struct sdw_stream_runtime *stream);
1063
1064 /* messaging and data APIs */
1065 int sdw_read(struct sdw_slave *slave, u32 addr);
1066 int sdw_write(struct sdw_slave *slave, u32 addr, u8 value);
1067 int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value);
1068 int sdw_read_no_pm(struct sdw_slave *slave, u32 addr);
1069 int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1070 int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val);
1071 int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1072 int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val);
1073 int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1074 int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val);
1075
1076 #else
1077
sdw_stream_add_slave(struct sdw_slave * slave,struct sdw_stream_config * stream_config,const struct sdw_port_config * port_config,unsigned int num_ports,struct sdw_stream_runtime * stream)1078 static inline int sdw_stream_add_slave(struct sdw_slave *slave,
1079 struct sdw_stream_config *stream_config,
1080 const struct sdw_port_config *port_config,
1081 unsigned int num_ports,
1082 struct sdw_stream_runtime *stream)
1083 {
1084 WARN_ONCE(1, "SoundWire API is disabled");
1085 return -EINVAL;
1086 }
1087
sdw_stream_remove_slave(struct sdw_slave * slave,struct sdw_stream_runtime * stream)1088 static inline int sdw_stream_remove_slave(struct sdw_slave *slave,
1089 struct sdw_stream_runtime *stream)
1090 {
1091 WARN_ONCE(1, "SoundWire API is disabled");
1092 return -EINVAL;
1093 }
1094
1095 /* messaging and data APIs */
sdw_read(struct sdw_slave * slave,u32 addr)1096 static inline int sdw_read(struct sdw_slave *slave, u32 addr)
1097 {
1098 WARN_ONCE(1, "SoundWire API is disabled");
1099 return -EINVAL;
1100 }
1101
sdw_write(struct sdw_slave * slave,u32 addr,u8 value)1102 static inline int sdw_write(struct sdw_slave *slave, u32 addr, u8 value)
1103 {
1104 WARN_ONCE(1, "SoundWire API is disabled");
1105 return -EINVAL;
1106 }
1107
sdw_write_no_pm(struct sdw_slave * slave,u32 addr,u8 value)1108 static inline int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value)
1109 {
1110 WARN_ONCE(1, "SoundWire API is disabled");
1111 return -EINVAL;
1112 }
1113
sdw_read_no_pm(struct sdw_slave * slave,u32 addr)1114 static inline int sdw_read_no_pm(struct sdw_slave *slave, u32 addr)
1115 {
1116 WARN_ONCE(1, "SoundWire API is disabled");
1117 return -EINVAL;
1118 }
1119
sdw_nread(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1120 static inline int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1121 {
1122 WARN_ONCE(1, "SoundWire API is disabled");
1123 return -EINVAL;
1124 }
1125
sdw_nread_no_pm(struct sdw_slave * slave,u32 addr,size_t count,u8 * val)1126 static inline int sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
1127 {
1128 WARN_ONCE(1, "SoundWire API is disabled");
1129 return -EINVAL;
1130 }
1131
sdw_nwrite(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1132 static inline int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1133 {
1134 WARN_ONCE(1, "SoundWire API is disabled");
1135 return -EINVAL;
1136 }
1137
sdw_nwrite_no_pm(struct sdw_slave * slave,u32 addr,size_t count,const u8 * val)1138 static inline int sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, const u8 *val)
1139 {
1140 WARN_ONCE(1, "SoundWire API is disabled");
1141 return -EINVAL;
1142 }
1143
sdw_update(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1144 static inline int sdw_update(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1145 {
1146 WARN_ONCE(1, "SoundWire API is disabled");
1147 return -EINVAL;
1148 }
1149
sdw_update_no_pm(struct sdw_slave * slave,u32 addr,u8 mask,u8 val)1150 static inline int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
1151 {
1152 WARN_ONCE(1, "SoundWire API is disabled");
1153 return -EINVAL;
1154 }
1155
1156 #endif /* CONFIG_SOUNDWIRE */
1157
1158 #endif /* __SOUNDWIRE_H */
1159