Searched refs:SDMA0_REGISTER_OFFSET (Results 1 – 5 of 5) sorted by relevance
71 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_rptr()95 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_wptr()116 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_set_wptr()260 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()310 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()342 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable()375 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_resume()483 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()485 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()486 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()[all …]
1952 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
75 SDMA0_REGISTER_OFFSET,1300 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()1302 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()1305 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()1307 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
676 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},