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Searched refs:SDMA0 (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4.c60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
88 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
92 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
96 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
[all …]
H A Damdgpu_amdkfd_gfx_v10_3.c143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_arcturus.c81 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gfx_v12.c85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gfx_v11.c134 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dsoc21.c294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
H A Damdgpu_amdkfd_gfx_v10.c165 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gfx_v9.c194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dsoc15.c388 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
H A Damdgpu_psp.c2032 dev_mask = GET_MASK(SDMA0, instance_mask); in psp_ras_trigger_error()
/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
H A Dcikd.h860 #define SDMA0 (1 << 10) macro