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Searched refs:SDMA0 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4.c60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
88 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
92 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
96 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
[all …]
H A Damdgpu_amdkfd_gfx_v10_3.c143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dsdma_v4_4_2.c116 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v4_4_2_get_reg_offset()
1764 return amdgpu_dpm_reset_sdma(adev, 1 << GET_INST(SDMA0, instance_id)); in sdma_v4_4_2_soft_reset_engine()
2061 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); in sdma_v4_4_2_get_clockgating_state()
2066 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); in sdma_v4_4_2_get_clockgating_state()
2208 dev_inst = GET_INST(SDMA0, i); in sdma_v4_4_2_set_ring_funcs()
H A Dsdma_v7_1.c120 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v7_1_get_reg_offset()
1309 xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc, in sdma_v7_1_sw_init()
1317 GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc); in sdma_v7_1_sw_init()
1529 if (inst == GET_INST(SDMA0, instances)) in sdma_v7_1_process_trap_irq()
1679 dev_inst = GET_INST(SDMA0, i); in sdma_v7_1_set_ring_funcs()
H A Damdgpu_amdkfd_arcturus.c81 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dsoc24.c121 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
H A Dsoc21.c295 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
H A Damdgpu_amdkfd_gfx_v10.c165 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gfx_v9.c194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
H A Dcikd.h860 #define SDMA0 (1 << 10) macro