| /linux/include/dt-bindings/clock/ |
| H A D | rockchip,rk3506-cru.h | 211 #define SCLK_UART5 198 macro
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| H A D | px30-cru.h | 30 #define SCLK_UART5 28 macro
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| H A D | rockchip,rv1126b-cru.h | 42 #define SCLK_UART5 29 macro
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| H A D | rockchip,rk3528-cru.h | 46 #define SCLK_UART5 34 macro
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| H A D | rockchip,rv1126-cru.h | 98 #define SCLK_UART5 32 macro
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| H A D | rockchip,rk3576-cru.h | 162 #define SCLK_UART5 144 macro
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| H A D | rockchip,rk3588-cru.h | 202 #define SCLK_UART5 187 macro
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| H A D | rk3568-cru.h | 367 #define SCLK_UART5 303 macro
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3506.c | 648 COMPOSITE(SCLK_UART5, "sclk_uart5", sclk_uart_parents_p, 0,
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| H A D | clk-px30.c | 723 GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
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| H A D | clk-rv1126.c | 510 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
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| H A D | clk-rk3528.c | 360 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
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| H A D | clk-rv1126b.c | 282 COMPOSITE(SCLK_UART5, "sclk_uart5", mux_sclk_uart_src_p, 0,
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| H A D | clk-rk3568.c | 1268 GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
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| H A D | clk-rk3576.c | 678 COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0,
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| H A D | clk-rk3588.c | 1262 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rv1126.dtsi | 516 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3562.dtsi | 826 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk3528.dtsi | 761 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | px30.dtsi | 559 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk3576.dtsi | 2452 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk3588-base.dtsi | 2662 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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