1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd 4 * http://www.samsung.com 5 */ 6 7 #ifndef __LINUX_MFD_S2MPU02_H 8 #define __LINUX_MFD_S2MPU02_H 9 10 /* S2MPU02 registers */ 11 enum S2MPU02_reg { 12 S2MPU02_REG_ID, 13 S2MPU02_REG_INT1, 14 S2MPU02_REG_INT2, 15 S2MPU02_REG_INT3, 16 S2MPU02_REG_INT1M, 17 S2MPU02_REG_INT2M, 18 S2MPU02_REG_INT3M, 19 S2MPU02_REG_ST1, 20 S2MPU02_REG_ST2, 21 S2MPU02_REG_PWRONSRC, 22 S2MPU02_REG_OFFSRC, 23 S2MPU02_REG_BU_CHG, 24 S2MPU02_REG_RTCCTRL, 25 S2MPU02_REG_PMCTRL1, 26 S2MPU02_REG_RSVD1, 27 S2MPU02_REG_RSVD2, 28 S2MPU02_REG_RSVD3, 29 S2MPU02_REG_RSVD4, 30 S2MPU02_REG_RSVD5, 31 S2MPU02_REG_RSVD6, 32 S2MPU02_REG_RSVD7, 33 S2MPU02_REG_WRSTEN, 34 S2MPU02_REG_RSVD8, 35 S2MPU02_REG_RSVD9, 36 S2MPU02_REG_RSVD10, 37 S2MPU02_REG_B1CTRL1, 38 S2MPU02_REG_B1CTRL2, 39 S2MPU02_REG_B2CTRL1, 40 S2MPU02_REG_B2CTRL2, 41 S2MPU02_REG_B3CTRL1, 42 S2MPU02_REG_B3CTRL2, 43 S2MPU02_REG_B4CTRL1, 44 S2MPU02_REG_B4CTRL2, 45 S2MPU02_REG_B5CTRL1, 46 S2MPU02_REG_B5CTRL2, 47 S2MPU02_REG_B5CTRL3, 48 S2MPU02_REG_B5CTRL4, 49 S2MPU02_REG_B5CTRL5, 50 S2MPU02_REG_B6CTRL1, 51 S2MPU02_REG_B6CTRL2, 52 S2MPU02_REG_B7CTRL1, 53 S2MPU02_REG_B7CTRL2, 54 S2MPU02_REG_RAMP1, 55 S2MPU02_REG_RAMP2, 56 S2MPU02_REG_L1CTRL, 57 S2MPU02_REG_L2CTRL1, 58 S2MPU02_REG_L2CTRL2, 59 S2MPU02_REG_L2CTRL3, 60 S2MPU02_REG_L2CTRL4, 61 S2MPU02_REG_L3CTRL, 62 S2MPU02_REG_L4CTRL, 63 S2MPU02_REG_L5CTRL, 64 S2MPU02_REG_L6CTRL, 65 S2MPU02_REG_L7CTRL, 66 S2MPU02_REG_L8CTRL, 67 S2MPU02_REG_L9CTRL, 68 S2MPU02_REG_L10CTRL, 69 S2MPU02_REG_L11CTRL, 70 S2MPU02_REG_L12CTRL, 71 S2MPU02_REG_L13CTRL, 72 S2MPU02_REG_L14CTRL, 73 S2MPU02_REG_L15CTRL, 74 S2MPU02_REG_L16CTRL, 75 S2MPU02_REG_L17CTRL, 76 S2MPU02_REG_L18CTRL, 77 S2MPU02_REG_L19CTRL, 78 S2MPU02_REG_L20CTRL, 79 S2MPU02_REG_L21CTRL, 80 S2MPU02_REG_L22CTRL, 81 S2MPU02_REG_L23CTRL, 82 S2MPU02_REG_L24CTRL, 83 S2MPU02_REG_L25CTRL, 84 S2MPU02_REG_L26CTRL, 85 S2MPU02_REG_L27CTRL, 86 S2MPU02_REG_L28CTRL, 87 S2MPU02_REG_LDODSCH1, 88 S2MPU02_REG_LDODSCH2, 89 S2MPU02_REG_LDODSCH3, 90 S2MPU02_REG_LDODSCH4, 91 S2MPU02_REG_SELMIF, 92 S2MPU02_REG_RSVD11, 93 S2MPU02_REG_RSVD12, 94 S2MPU02_REG_RSVD13, 95 S2MPU02_REG_DVSSEL, 96 S2MPU02_REG_DVSPTR, 97 S2MPU02_REG_DVSDATA, 98 }; 99 100 /* S2MPU02 regulator ids */ 101 enum S2MPU02_regulators { 102 S2MPU02_LDO1, 103 S2MPU02_LDO2, 104 S2MPU02_LDO3, 105 S2MPU02_LDO4, 106 S2MPU02_LDO5, 107 S2MPU02_LDO6, 108 S2MPU02_LDO7, 109 S2MPU02_LDO8, 110 S2MPU02_LDO9, 111 S2MPU02_LDO10, 112 S2MPU02_LDO11, 113 S2MPU02_LDO12, 114 S2MPU02_LDO13, 115 S2MPU02_LDO14, 116 S2MPU02_LDO15, 117 S2MPU02_LDO16, 118 S2MPU02_LDO17, 119 S2MPU02_LDO18, 120 S2MPU02_LDO19, 121 S2MPU02_LDO20, 122 S2MPU02_LDO21, 123 S2MPU02_LDO22, 124 S2MPU02_LDO23, 125 S2MPU02_LDO24, 126 S2MPU02_LDO25, 127 S2MPU02_LDO26, 128 S2MPU02_LDO27, 129 S2MPU02_LDO28, 130 S2MPU02_BUCK1, 131 S2MPU02_BUCK2, 132 S2MPU02_BUCK3, 133 S2MPU02_BUCK4, 134 S2MPU02_BUCK5, 135 S2MPU02_BUCK6, 136 S2MPU02_BUCK7, 137 138 S2MPU02_REGULATOR_MAX, 139 }; 140 141 /* Regulator constraints for BUCKx */ 142 #define S2MPU02_BUCK1234_MIN_600MV 600000 143 #define S2MPU02_BUCK5_MIN_1081_25MV 1081250 144 #define S2MPU02_BUCK6_MIN_1700MV 1700000 145 #define S2MPU02_BUCK7_MIN_900MV 900000 146 147 #define S2MPU02_BUCK1234_STEP_6_25MV 6250 148 #define S2MPU02_BUCK5_STEP_6_25MV 6250 149 #define S2MPU02_BUCK6_STEP_2_50MV 2500 150 #define S2MPU02_BUCK7_STEP_6_25MV 6250 151 152 #define S2MPU02_BUCK1234_START_SEL 0x00 153 #define S2MPU02_BUCK5_START_SEL 0x4D 154 #define S2MPU02_BUCK6_START_SEL 0x28 155 #define S2MPU02_BUCK7_START_SEL 0x30 156 157 #define S2MPU02_BUCK_RAMP_DELAY 12500 158 159 /* Regulator constraints for different types of LDOx */ 160 #define S2MPU02_LDO_MIN_900MV 900000 161 #define S2MPU02_LDO_MIN_1050MV 1050000 162 #define S2MPU02_LDO_MIN_1600MV 1600000 163 #define S2MPU02_LDO_STEP_12_5MV 12500 164 #define S2MPU02_LDO_STEP_25MV 25000 165 #define S2MPU02_LDO_STEP_50MV 50000 166 167 #define S2MPU02_LDO_GROUP1_START_SEL 0x8 168 #define S2MPU02_LDO_GROUP2_START_SEL 0xA 169 #define S2MPU02_LDO_GROUP3_START_SEL 0x10 170 171 #define S2MPU02_LDO_VSEL_MASK 0x3F 172 #define S2MPU02_BUCK_VSEL_MASK 0xFF 173 #define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT) 174 #define S2MPU02_ENABLE_SHIFT 6 175 176 /* On/Off controlled by PWREN */ 177 #define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT) 178 #define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT) 179 #define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1) 180 #define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1) 181 182 /* RAMP delay for BUCK1234*/ 183 #define S2MPU02_BUCK1_RAMP_SHIFT 6 184 #define S2MPU02_BUCK2_RAMP_SHIFT 4 185 #define S2MPU02_BUCK3_RAMP_SHIFT 2 186 #define S2MPU02_BUCK4_RAMP_SHIFT 0 187 #define S2MPU02_BUCK1234_RAMP_MASK 0x3 188 189 #endif /* __LINUX_MFD_S2MPU02_H */ 190