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Searched refs:RTC (Results 1 – 25 of 161) sorted by relevance

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/linux/drivers/rtc/
H A DKconfig3 # RTC class/drivers configuration
19 Generic RTC class support. If you say yes here, you will
26 bool "Set system time from RTC on startup and resume"
30 the value read from a specified RTC device. This is useful to avoid
34 string "RTC used to set the system time"
38 The RTC device that will be used to (re)initialize the system
50 sleep states. Do not specify an RTC here unless it stays powered
54 bool "Set the RTC time based on NTP synchronization"
58 in the RTC specified by RTC_HCTOSYS_DEVICE approximately every 11
62 string "RTC used to synchronize NTP adjustment"
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/linux/drivers/firmware/arm_scmi/vendors/imx/
H A Dimx95.rst39 contains persistent storage (GPR), an RTC, and the ON/OFF button. The protocol
47 - Read/write the RTC time in seconds and ticks
49 - Get notifications on RTC update, alarm, or rollover.
52 For most SoC, there is one on-chip RTC (e.g. in BBNSM) and this is RTC ID 0.
53 Board code can add additional GPR and RTC.
55 GPR are not aggregated. The RTC time is also not aggregated. Setting these
57 each. However, RTC alarms are maintained for each LM and the hardware is
59 be given access rights to set an RTC alarm.
180 |uint32 index |Index of RTC |
189 |uint32 attributes |Bit[31:24] Bit width of RTC seconds. |
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/linux/Documentation/admin-guide/
H A Drtc.rst2 Real Time Clock (RTC) Drivers for Linux
16 Linux has two largely-compatible userspace RTC API families you may
19 * /dev/rtc ... is the RTC provided by PC compatible systems,
23 supported by a wide variety of RTC chips on all systems.
27 RTCs use the same API to make requests in both RTC frameworks (using
29 same functionality. For example, not every RTC is hooked up to an
91 the process of doing this, the kernel briefly turns off RTC periodic
94 whatever) then the kernel will keep its hands off the RTC, allowing you
97 The alarm and/or interrupt frequency are programmed into the RTC via
108 New portable "RTC Class" drivers: /dev/rtcN
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-rtc6 The rtc/ class subdirectory belongs to the RTC subsystem.
14 to each RTC device.
21 (RO) RTC-provided date in YYYY-MM-DD format
28 (RO) 1 if the RTC provided the system time at boot via the
37 from this RTC.
44 (RO) The name of the RTC corresponding to this sysfs directory
51 Valid time range for the RTC, as seconds from epoch, formatted
59 (RO) RTC-provided time as the number of seconds since the epoch
66 (RO) RTC-provided time in 24-hour notation (hh:mm:ss)
H A Drtc-cdev9 * RTC_RD_TIME, RTC_SET_TIME: Read or set the RTC time. Time
36 * RTC_VL_READ: Read the voltage inputs status of the RTC when
40 * RTC_VL_CLEAR: Clear the voltage status of the RTC. Some RTCs
45 also supported by the newer RTC class framework. However,
49 by the RTC class framework, but can't be supported by the older
/linux/Documentation/devicetree/bindings/spi/
H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
7 Master output is set on low clock and sensed by the RTC on the rising
8 edge. Master input is set by the RTC on the trailing edge and is sensed
/linux/Documentation/devicetree/bindings/rtc/
H A Disil,isl12026.txt1 ISL12026 I2C RTC/EEPROM
3 ISL12026 is an I2C RTC/EEPROM combination device. The RTC and control
5 at bus address 0x57. The canonical "reg" value will be for the RTC portion.
H A Drtc-palmas.txt1 Palmas RTC controller bindings
5 - "ti,palmas-rtc" for palma series of the RTC controller
6 - interrupts: Interrupt number of RTC submodule on device.
11 TPS80036 supports the backup battery for powering the RTC when main
H A Dmoxa,moxart-rtc.txt6 - rtc-sclk-gpios : RTC sclk gpio, with zero flags
7 - rtc-data-gpios : RTC data gpio, with zero flags
8 - rtc-reset-gpios : RTC reset gpio, with zero flags
H A Drtc-omap.txt5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
H A Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
6 Master output is set on low clock and sensed by the RTC on the rising
7 edge. Master input is set by the RTC on the trailing edge and is sensed
/linux/arch/sh/kernel/cpu/sh3/
H A Dsetup-sh7710.c28 RTC, WDT, REF, enumerator
51 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
52 INTC_VECT(RTC, 0x4c0),
58 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
H A Dsetup-sh7705.c31 RTC, WDT, REF_RCMI, enumerator
49 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
50 INTC_VECT(RTC, 0x4c0),
56 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
H A Dsetup-sh770x.c32 RTC, WDT, REF, enumerator
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
68 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
H A Dsetup-sh7720.c223 TMU0, TMU1, TMU2, RTC, enumerator
239 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
240 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
267 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8020.dtsi18 /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
20 * disable it. However, the RTC clock in CP slave is connected to the
H A Darmada-8040.dtsi26 /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
28 * disable it. However, the RTC clock in CP slave is connected to the
/linux/arch/sh/boards/mach-highlander/
H A Dirq-r7780mp.c23 RTC, /* RTC Alarm */ enumerator
37 INTC_IRQ(RTC, IRQ_RTC),
48 { SCIF0, SCIF1, RTC, 0, CF, 0, TP, SMBUS,
H A Dirq-r7785rp.c21 RTC, /* RTC Alarm */ enumerator
33 INTC_IRQ(RTC, IRQ_RTC),
48 RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-nas2big.dts31 /* The on-chip RTC is not powered (no supercap). */
92 * An external I2C RTC (Dallas DS1337S+) is used. This allows
93 * to power-up the board on an RTC alarm. The external RTC can
/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7750.c185 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF, enumerator
195 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
196 INTC_VECT(RTC, 0x4c0),
206 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
/linux/arch/sh/kernel/cpu/sh2a/
H A Dsetup-sh7203.c37 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1, enumerator
107 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
108 INTC_IRQ(RTC, 233),
155 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
160 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-sh7763.c240 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
254 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
255 INTC_VECT(RTC, 0x4c0),
306 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
317 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
H A Dsetup-sh7780.c304 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI, enumerator
315 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
316 INTC_VECT(RTC, 0x4c0),
360 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
366 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
27 as the "RTC domain" voltage regulator.

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