Searched refs:RST_NR_PER_BANK (Results 1 – 12 of 12) sorted by relevance
/linux/drivers/clk/mediatek/ |
H A D | clk-mt6735-infracfg.c | 20 #define RST_NR_PER_BANK 32 macro 52 [MT6735_INFRA_RST0_EMI_REG] = 0 * RST_NR_PER_BANK + 0, 53 [MT6735_INFRA_RST0_DRAMC0_AO] = 0 * RST_NR_PER_BANK + 1, 54 [MT6735_INFRA_RST0_AP_CIRQ_EINT] = 0 * RST_NR_PER_BANK + 3, 55 [MT6735_INFRA_RST0_APXGPT] = 0 * RST_NR_PER_BANK + 4, 56 [MT6735_INFRA_RST0_SCPSYS] = 0 * RST_NR_PER_BANK + 5, 57 [MT6735_INFRA_RST0_KP] = 0 * RST_NR_PER_BANK + 6, 58 [MT6735_INFRA_RST0_PMIC_WRAP] = 0 * RST_NR_PER_BANK + 7, 59 [MT6735_INFRA_RST0_CLDMA_AO_TOP] = 0 * RST_NR_PER_BANK + 8, 60 [MT6735_INFRA_RST0_USBSIF_TOP] = 0 * RST_NR_PER_BANK + 9, [all …]
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H A D | clk-mt6735-pericfg.c | 21 #define RST_NR_PER_BANK 32 macro 65 [MT6735_PERI_RST0_UART0] = 0 * RST_NR_PER_BANK + 0, 66 [MT6735_PERI_RST0_UART1] = 0 * RST_NR_PER_BANK + 1, 67 [MT6735_PERI_RST0_UART2] = 0 * RST_NR_PER_BANK + 2, 68 [MT6735_PERI_RST0_UART3] = 0 * RST_NR_PER_BANK + 3, 69 [MT6735_PERI_RST0_UART4] = 0 * RST_NR_PER_BANK + 4, 70 [MT6735_PERI_RST0_BTIF] = 0 * RST_NR_PER_BANK + 6, 71 [MT6735_PERI_RST0_DISP_PWM_PERI] = 0 * RST_NR_PER_BANK + 7, 72 [MT6735_PERI_RST0_PWM] = 0 * RST_NR_PER_BANK + 8, 73 [MT6735_PERI_RST0_AUXADC] = 0 * RST_NR_PER_BANK + 10, [all …]
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H A D | clk-mt6795-infracfg.c | 65 [MT6795_INFRA_RST0_SCPSYS_RST] = 0 * RST_NR_PER_BANK + 5, 66 [MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7, 67 [MT6795_INFRA_RST1_MIPI_DSI_RST] = 1 * RST_NR_PER_BANK + 4, 68 [MT6795_INFRA_RST1_MIPI_CSI_RST] = 1 * RST_NR_PER_BANK + 7, 69 [MT6795_INFRA_RST1_MM_IOMMU_RST] = 1 * RST_NR_PER_BANK + 15,
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H A D | reset.c | 27 data->desc->rst_bank_ofs[id / RST_NR_PER_BANK], in mtk_reset_update() 28 BIT(id % RST_NR_PER_BANK), val); in mtk_reset_update() 61 data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] + in mtk_reset_update_set_clr() 63 BIT(id % RST_NR_PER_BANK)); in mtk_reset_update_set_clr() 161 data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK; in mtk_register_reset_controller_with_dev()
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H A D | clk-mt8195-infra_ao.c | 202 [MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 203 [MT8195_INFRA_RST2_USBSIF_P1_SWRST] = 2 * RST_NR_PER_BANK + 18, 204 [MT8195_INFRA_RST2_PCIE_P0_SWRST] = 2 * RST_NR_PER_BANK + 26, 205 [MT8195_INFRA_RST2_PCIE_P1_SWRST] = 2 * RST_NR_PER_BANK + 27, 206 [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 207 [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
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H A D | clk-mt6735-vdecsys.c | 22 #define RST_NR_PER_BANK 32 macro 44 [MT6735_VDEC_RST0_VDEC] = 0 * RST_NR_PER_BANK + 0, 45 [MT6735_VDEC_RST1_SMI_LARB1] = 1 * RST_NR_PER_BANK + 0,
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H A D | clk-mt8188-infra_ao.c | 189 [MT8188_INFRA_RST1_THERMAL_MCU_RST] = 1 * RST_NR_PER_BANK + 2, 190 [MT8188_INFRA_RST1_THERMAL_CTRL_RST] = 1 * RST_NR_PER_BANK + 4, 191 [MT8188_INFRA_RST3_PTP_CTRL_RST] = 3 * RST_NR_PER_BANK + 5,
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H A D | clk-mt8192.c | 951 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 952 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15, 953 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 954 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1, 955 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
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H A D | reset.h | 12 #define RST_NR_PER_BANK 32 macro
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H A D | clk-mt8186-infra_ao.c | 204 [MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0, 205 [MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
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H A D | clk-mt7988-infracfg.c | 262 [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, 263 [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
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/linux/drivers/clk/ |
H A D | clk-en7523.c | 14 #define RST_NR_PER_BANK 32 macro 334 [EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0, 335 [EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1, 336 [EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2, 337 [EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4, 338 [EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6, 339 [EN7581_TIMER_RST] = RST_NR_PER_BANK + 8, 340 [EN7581_PCM1_RST] = RST_NR_PER_BANK + 11, 341 [EN7581_UART_RST] = RST_NR_PER_BANK + 12, 342 [EN7581_GPIO_RST] = RST_NR_PER_BANK + 13, [all …]
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