1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Renesas 9-series PCIe clock generator driver
4 *
5 * The following series can be supported:
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
7 * Currently supported:
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
11 *
12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
13 */
14
15 #include <linux/clk-provider.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/regmap.h>
20
21 #define RS9_REG_OE 0x0
22 #define RS9_REG_SS 0x1
23 #define RS9_REG_SS_AMP_0V6 0x0
24 #define RS9_REG_SS_AMP_0V7 0x1
25 #define RS9_REG_SS_AMP_0V8 0x2
26 #define RS9_REG_SS_AMP_0V9 0x3
27 #define RS9_REG_SS_AMP_DEFAULT RS9_REG_SS_AMP_0V8
28 #define RS9_REG_SS_AMP_MASK 0x3
29 #define RS9_REG_SS_SSC_100 0
30 #define RS9_REG_SS_SSC_M025 (1 << 3)
31 #define RS9_REG_SS_SSC_M050 (3 << 3)
32 #define RS9_REG_SS_SSC_DEFAULT RS9_REG_SS_SSC_100
33 #define RS9_REG_SS_SSC_MASK (3 << 3)
34 #define RS9_REG_SS_SSC_LOCK BIT(5)
35 #define RS9_REG_SR 0x2
36 #define RS9_REG_REF 0x3
37 #define RS9_REG_REF_OE BIT(4)
38 #define RS9_REG_REF_OD BIT(5)
39 #define RS9_REG_REF_SR_SLOWEST 0
40 #define RS9_REG_REF_SR_SLOW (1 << 6)
41 #define RS9_REG_REF_SR_FAST (2 << 6)
42 #define RS9_REG_REF_SR_FASTER (3 << 6)
43 #define RS9_REG_VID 0x5
44 #define RS9_REG_DID 0x6
45 #define RS9_REG_BCP 0x7
46
47 #define RS9_REG_VID_MASK GENMASK(3, 0)
48 #define RS9_REG_VID_IDT 0x01
49
50 #define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT)
51 #define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT)
52 #define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT)
53 #define RS9_REG_DID_TYPE_SHIFT 0x6
54
55 /* Structure to describe features of a particular 9-series model */
56 struct rs9_chip_info {
57 unsigned int num_clks;
58 u8 outshift;
59 u8 did;
60 };
61
62 struct rs9_driver_data {
63 struct i2c_client *client;
64 struct regmap *regmap;
65 const struct rs9_chip_info *chip_info;
66 struct clk_hw *clk_dif[8];
67 u8 pll_amplitude;
68 u8 pll_ssc;
69 u8 clk_dif_sr;
70 };
71
72 /*
73 * Renesas 9-series i2c regmap
74 */
75 static const struct regmap_range rs9_readable_ranges[] = {
76 regmap_reg_range(RS9_REG_OE, RS9_REG_REF),
77 regmap_reg_range(RS9_REG_VID, RS9_REG_BCP),
78 };
79
80 static const struct regmap_access_table rs9_readable_table = {
81 .yes_ranges = rs9_readable_ranges,
82 .n_yes_ranges = ARRAY_SIZE(rs9_readable_ranges),
83 };
84
85 static const struct regmap_range rs9_writeable_ranges[] = {
86 regmap_reg_range(RS9_REG_OE, RS9_REG_REF),
87 regmap_reg_range(RS9_REG_BCP, RS9_REG_BCP),
88 };
89
90 static const struct regmap_access_table rs9_writeable_table = {
91 .yes_ranges = rs9_writeable_ranges,
92 .n_yes_ranges = ARRAY_SIZE(rs9_writeable_ranges),
93 };
94
rs9_regmap_i2c_write(void * context,unsigned int reg,unsigned int val)95 static int rs9_regmap_i2c_write(void *context,
96 unsigned int reg, unsigned int val)
97 {
98 struct i2c_client *i2c = context;
99 const u8 data[3] = { reg, 1, val };
100 const int count = ARRAY_SIZE(data);
101 int ret;
102
103 ret = i2c_master_send(i2c, data, count);
104 if (ret == count)
105 return 0;
106 else if (ret < 0)
107 return ret;
108 else
109 return -EIO;
110 }
111
rs9_regmap_i2c_read(void * context,unsigned int reg,unsigned int * val)112 static int rs9_regmap_i2c_read(void *context,
113 unsigned int reg, unsigned int *val)
114 {
115 struct i2c_client *i2c = context;
116 struct i2c_msg xfer[2];
117 u8 txdata = reg;
118 u8 rxdata[2];
119 int ret;
120
121 xfer[0].addr = i2c->addr;
122 xfer[0].flags = 0;
123 xfer[0].len = 1;
124 xfer[0].buf = (void *)&txdata;
125
126 xfer[1].addr = i2c->addr;
127 xfer[1].flags = I2C_M_RD;
128 xfer[1].len = 2;
129 xfer[1].buf = (void *)rxdata;
130
131 ret = i2c_transfer(i2c->adapter, xfer, 2);
132 if (ret < 0)
133 return ret;
134 if (ret != 2)
135 return -EIO;
136
137 /*
138 * Byte 0 is transfer length, which is always 1 due
139 * to BCP register programming to 1 in rs9_probe(),
140 * ignore it and use data from Byte 1.
141 */
142 *val = rxdata[1];
143 return 0;
144 }
145
146 static const struct regmap_config rs9_regmap_config = {
147 .reg_bits = 8,
148 .val_bits = 8,
149 .cache_type = REGCACHE_FLAT,
150 .max_register = RS9_REG_BCP,
151 .num_reg_defaults_raw = 0x8,
152 .rd_table = &rs9_readable_table,
153 .wr_table = &rs9_writeable_table,
154 .reg_write = rs9_regmap_i2c_write,
155 .reg_read = rs9_regmap_i2c_read,
156 };
157
rs9_calc_dif(const struct rs9_driver_data * rs9,int idx)158 static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)
159 {
160 /*
161 * On 9FGV0241, the DIF OE0 is BIT(1) and DIF OE(1) is BIT(2),
162 * on 9FGV0441 and 9FGV0841 the DIF OE0 is BIT(0) and so on.
163 * Increment the index in the 9FGV0241 special case here.
164 */
165 return BIT(idx + rs9->chip_info->outshift);
166 }
167
rs9_get_output_config(struct rs9_driver_data * rs9,int idx)168 static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
169 {
170 struct i2c_client *client = rs9->client;
171 u8 dif = rs9_calc_dif(rs9, idx);
172 unsigned char name[5] = "DIF0";
173 struct device_node *np;
174 int ret;
175 u32 sr;
176
177 /* Set defaults */
178 rs9->clk_dif_sr |= dif;
179
180 snprintf(name, 5, "DIF%d", idx);
181 np = of_get_child_by_name(client->dev.of_node, name);
182 if (!np)
183 return 0;
184
185 /* Output clock slew rate */
186 ret = of_property_read_u32(np, "renesas,slew-rate", &sr);
187 of_node_put(np);
188 if (!ret) {
189 if (sr == 2000000) { /* 2V/ns */
190 rs9->clk_dif_sr &= ~dif;
191 } else if (sr == 3000000) { /* 3V/ns (default) */
192 rs9->clk_dif_sr |= dif;
193 } else
194 ret = dev_err_probe(&client->dev, -EINVAL,
195 "Invalid renesas,slew-rate value\n");
196 }
197
198 return ret;
199 }
200
rs9_get_common_config(struct rs9_driver_data * rs9)201 static int rs9_get_common_config(struct rs9_driver_data *rs9)
202 {
203 struct i2c_client *client = rs9->client;
204 struct device_node *np = client->dev.of_node;
205 unsigned int amp, ssc;
206 int ret;
207
208 /* Set defaults */
209 rs9->pll_amplitude = RS9_REG_SS_AMP_DEFAULT;
210 rs9->pll_ssc = RS9_REG_SS_SSC_DEFAULT;
211
212 /* Output clock amplitude */
213 ret = of_property_read_u32(np, "renesas,out-amplitude-microvolt",
214 &);
215 if (!ret) {
216 if (amp == 600000) /* 0.6V */
217 rs9->pll_amplitude = RS9_REG_SS_AMP_0V6;
218 else if (amp == 700000) /* 0.7V (default) */
219 rs9->pll_amplitude = RS9_REG_SS_AMP_0V7;
220 else if (amp == 800000) /* 0.8V */
221 rs9->pll_amplitude = RS9_REG_SS_AMP_0V8;
222 else if (amp == 900000) /* 0.9V */
223 rs9->pll_amplitude = RS9_REG_SS_AMP_0V9;
224 else
225 return dev_err_probe(&client->dev, -EINVAL,
226 "Invalid renesas,out-amplitude-microvolt value\n");
227 }
228
229 /* Output clock spread spectrum */
230 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc);
231 if (!ret) {
232 if (ssc == 100000) /* 100% ... no spread (default) */
233 rs9->pll_ssc = RS9_REG_SS_SSC_100;
234 else if (ssc == 99750) /* -0.25% ... down spread */
235 rs9->pll_ssc = RS9_REG_SS_SSC_M025;
236 else if (ssc == 99500) /* -0.50% ... down spread */
237 rs9->pll_ssc = RS9_REG_SS_SSC_M050;
238 else
239 return dev_err_probe(&client->dev, -EINVAL,
240 "Invalid renesas,out-spread-spectrum value\n");
241 }
242
243 return 0;
244 }
245
rs9_update_config(struct rs9_driver_data * rs9)246 static void rs9_update_config(struct rs9_driver_data *rs9)
247 {
248 int i;
249
250 /* If amplitude is non-default, update it. */
251 if (rs9->pll_amplitude != RS9_REG_SS_AMP_DEFAULT) {
252 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_AMP_MASK,
253 rs9->pll_amplitude);
254 }
255
256 /* If SSC is non-default, update it. */
257 if (rs9->pll_ssc != RS9_REG_SS_SSC_DEFAULT) {
258 regmap_update_bits(rs9->regmap, RS9_REG_SS, RS9_REG_SS_SSC_MASK,
259 rs9->pll_ssc);
260 }
261
262 for (i = 0; i < rs9->chip_info->num_clks; i++) {
263 u8 dif = rs9_calc_dif(rs9, i);
264
265 if (rs9->clk_dif_sr & dif)
266 continue;
267
268 regmap_update_bits(rs9->regmap, RS9_REG_SR, dif,
269 rs9->clk_dif_sr & dif);
270 }
271 }
272
273 static struct clk_hw *
rs9_of_clk_get(struct of_phandle_args * clkspec,void * data)274 rs9_of_clk_get(struct of_phandle_args *clkspec, void *data)
275 {
276 struct rs9_driver_data *rs9 = data;
277 unsigned int idx = clkspec->args[0];
278
279 return rs9->clk_dif[idx];
280 }
281
rs9_probe(struct i2c_client * client)282 static int rs9_probe(struct i2c_client *client)
283 {
284 unsigned char name[5] = "DIF0";
285 struct rs9_driver_data *rs9;
286 unsigned int vid, did;
287 struct clk_hw *hw;
288 int i, ret;
289
290 rs9 = devm_kzalloc(&client->dev, sizeof(*rs9), GFP_KERNEL);
291 if (!rs9)
292 return -ENOMEM;
293
294 i2c_set_clientdata(client, rs9);
295 rs9->client = client;
296 rs9->chip_info = i2c_get_match_data(client);
297 if (!rs9->chip_info)
298 return -EINVAL;
299
300 /* Fetch common configuration from DT (if specified) */
301 ret = rs9_get_common_config(rs9);
302 if (ret)
303 return ret;
304
305 /* Fetch DIFx output configuration from DT (if specified) */
306 for (i = 0; i < rs9->chip_info->num_clks; i++) {
307 ret = rs9_get_output_config(rs9, i);
308 if (ret)
309 return ret;
310 }
311
312 rs9->regmap = devm_regmap_init(&client->dev, NULL,
313 client, &rs9_regmap_config);
314 if (IS_ERR(rs9->regmap))
315 return dev_err_probe(&client->dev, PTR_ERR(rs9->regmap),
316 "Failed to allocate register map\n");
317
318 /* Always read back 1 Byte via I2C */
319 ret = regmap_write(rs9->regmap, RS9_REG_BCP, 1);
320 if (ret < 0)
321 return ret;
322
323 ret = regmap_read(rs9->regmap, RS9_REG_VID, &vid);
324 if (ret < 0)
325 return ret;
326
327 ret = regmap_read(rs9->regmap, RS9_REG_DID, &did);
328 if (ret < 0)
329 return ret;
330
331 vid &= RS9_REG_VID_MASK;
332 if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did)
333 return dev_err_probe(&client->dev, -ENODEV,
334 "Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n",
335 vid, did, RS9_REG_VID_IDT,
336 rs9->chip_info->did);
337
338 /* Register clock */
339 for (i = 0; i < rs9->chip_info->num_clks; i++) {
340 snprintf(name, 5, "DIF%d", i);
341 hw = devm_clk_hw_register_fixed_factor_index(&client->dev, name,
342 0, 0, 4, 1);
343 if (IS_ERR(hw))
344 return PTR_ERR(hw);
345
346 rs9->clk_dif[i] = hw;
347 }
348
349 ret = devm_of_clk_add_hw_provider(&client->dev, rs9_of_clk_get, rs9);
350 if (!ret)
351 rs9_update_config(rs9);
352
353 return ret;
354 }
355
rs9_suspend(struct device * dev)356 static int rs9_suspend(struct device *dev)
357 {
358 struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
359
360 regcache_cache_only(rs9->regmap, true);
361 regcache_mark_dirty(rs9->regmap);
362
363 return 0;
364 }
365
rs9_resume(struct device * dev)366 static int rs9_resume(struct device *dev)
367 {
368 struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
369 int ret;
370
371 regcache_cache_only(rs9->regmap, false);
372 ret = regcache_sync(rs9->regmap);
373 if (ret)
374 dev_err(dev, "Failed to restore register map: %d\n", ret);
375 return ret;
376 }
377
378 static const struct rs9_chip_info renesas_9fgv0241_info = {
379 .num_clks = 2,
380 .outshift = 1,
381 .did = RS9_REG_DID_TYPE_FGV | 0x02,
382 };
383
384 static const struct rs9_chip_info renesas_9fgv0441_info = {
385 .num_clks = 4,
386 .outshift = 0,
387 .did = RS9_REG_DID_TYPE_FGV | 0x04,
388 };
389
390 static const struct rs9_chip_info renesas_9fgv0841_info = {
391 .num_clks = 8,
392 .outshift = 0,
393 .did = RS9_REG_DID_TYPE_FGV | 0x08,
394 };
395
396 static const struct i2c_device_id rs9_id[] = {
397 { .name = "9fgv0241", .driver_data = (kernel_ulong_t)&renesas_9fgv0241_info },
398 { .name = "9fgv0441", .driver_data = (kernel_ulong_t)&renesas_9fgv0441_info },
399 { .name = "9fgv0841", .driver_data = (kernel_ulong_t)&renesas_9fgv0841_info },
400 { }
401 };
402 MODULE_DEVICE_TABLE(i2c, rs9_id);
403
404 static const struct of_device_id clk_rs9_of_match[] = {
405 { .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info },
406 { .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info },
407 { .compatible = "renesas,9fgv0841", .data = &renesas_9fgv0841_info },
408 { }
409 };
410 MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
411
412 static DEFINE_SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume);
413
414 static struct i2c_driver rs9_driver = {
415 .driver = {
416 .name = "clk-renesas-pcie-9series",
417 .pm = pm_sleep_ptr(&rs9_pm_ops),
418 .of_match_table = clk_rs9_of_match,
419 },
420 .probe = rs9_probe,
421 .id_table = rs9_id,
422 };
423 module_i2c_driver(rs9_driver);
424
425 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
426 MODULE_DESCRIPTION("Renesas 9-series PCIe clock generator driver");
427 MODULE_LICENSE("GPL");
428