Searched refs:RREG32_SMC (Results 1 – 10 of 10) sorted by relevance
116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc()124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc()139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock()148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock()157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running()158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running()176 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc()131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc()145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock()154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock()163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running()164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running()202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
330 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize()458 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) in trinity_gfx_powergating_enable()459 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()474 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()479 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()484 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()488 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()548 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()558 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value()570 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()[all …]
173 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()487 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm()502 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am()512 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am()1018 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int()2237 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings()2264 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()2602 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level()2611 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level()2625 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
60 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
856 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
2686 data = RREG32_SMC(offset); in si_program_cac_config_registers()
63 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); in amdgpu_kv_dpm_get_enable_mask()
2860 data = RREG32_SMC(offset); in si_program_cac_config_registers()7601 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); in si_dpm_set_interrupt_state()7606 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); in si_dpm_set_interrupt_state()7618 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); in si_dpm_set_interrupt_state()7623 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); in si_dpm_set_interrupt_state()
1463 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro1494 u32 tmp = RREG32_SMC(_Reg); \