xref: /linux/drivers/net/ethernet/rocker/rocker_hw.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * drivers/net/ethernet/rocker/rocker_hw.h - Rocker switch device driver
4  * Copyright (c) 2014-2016 Jiri Pirko <jiri@mellanox.com>
5  * Copyright (c) 2014 Scott Feldman <sfeldma@gmail.com>
6  */
7 
8 #ifndef _ROCKER_HW_H
9 #define _ROCKER_HW_H
10 
11 #include <linux/types.h>
12 
13 /* Return codes */
14 enum {
15 	ROCKER_OK = 0,
16 	ROCKER_ENOENT = 2,
17 	ROCKER_ENXIO = 6,
18 	ROCKER_ENOMEM = 12,
19 	ROCKER_EEXIST = 17,
20 	ROCKER_EINVAL = 22,
21 	ROCKER_EMSGSIZE = 90,
22 	ROCKER_ENOTSUP = 95,
23 	ROCKER_ENOBUFS = 105,
24 };
25 
26 #define ROCKER_FP_PORTS_MAX 62
27 
28 #define PCI_DEVICE_ID_REDHAT_ROCKER	0x0006
29 
30 #define ROCKER_PCI_BAR0_SIZE		0x2000
31 
32 /* MSI-X vectors */
33 enum {
34 	ROCKER_MSIX_VEC_CMD,
35 	ROCKER_MSIX_VEC_EVENT,
36 	ROCKER_MSIX_VEC_TEST,
37 	ROCKER_MSIX_VEC_RESERVED0,
38 	__ROCKER_MSIX_VEC_TX,
39 	__ROCKER_MSIX_VEC_RX,
40 #define ROCKER_MSIX_VEC_TX(port) \
41 	(__ROCKER_MSIX_VEC_TX + ((port) * 2))
42 #define ROCKER_MSIX_VEC_RX(port) \
43 	(__ROCKER_MSIX_VEC_RX + ((port) * 2))
44 #define ROCKER_MSIX_VEC_COUNT(portcnt) \
45 	(ROCKER_MSIX_VEC_RX((portcnt - 1)) + 1)
46 };
47 
48 /* Rocker bogus registers */
49 #define ROCKER_BOGUS_REG0		0x0000
50 #define ROCKER_BOGUS_REG1		0x0004
51 #define ROCKER_BOGUS_REG2		0x0008
52 #define ROCKER_BOGUS_REG3		0x000c
53 
54 /* Rocker test registers */
55 #define ROCKER_TEST_REG			0x0010
56 #define ROCKER_TEST_REG64		0x0018  /* 8-byte */
57 #define ROCKER_TEST_IRQ			0x0020
58 #define ROCKER_TEST_DMA_ADDR		0x0028  /* 8-byte */
59 #define ROCKER_TEST_DMA_SIZE		0x0030
60 #define ROCKER_TEST_DMA_CTRL		0x0034
61 
62 /* Rocker test register ctrl */
63 #define ROCKER_TEST_DMA_CTRL_CLEAR	BIT(0)
64 #define ROCKER_TEST_DMA_CTRL_FILL	BIT(1)
65 #define ROCKER_TEST_DMA_CTRL_INVERT	BIT(2)
66 
67 /* Rocker DMA ring register offsets */
68 #define ROCKER_DMA_DESC_ADDR(x)		(0x1000 + (x) * 32)  /* 8-byte */
69 #define ROCKER_DMA_DESC_SIZE(x)		(0x1008 + (x) * 32)
70 #define ROCKER_DMA_DESC_HEAD(x)		(0x100c + (x) * 32)
71 #define ROCKER_DMA_DESC_TAIL(x)		(0x1010 + (x) * 32)
72 #define ROCKER_DMA_DESC_CTRL(x)		(0x1014 + (x) * 32)
73 #define ROCKER_DMA_DESC_CREDITS(x)	(0x1018 + (x) * 32)
74 #define ROCKER_DMA_DESC_RES1(x)		(0x101c + (x) * 32)
75 
76 /* Rocker dma ctrl register bits */
77 #define ROCKER_DMA_DESC_CTRL_RESET	BIT(0)
78 
79 /* Rocker DMA ring types */
80 enum rocker_dma_type {
81 	ROCKER_DMA_CMD,
82 	ROCKER_DMA_EVENT,
83 	__ROCKER_DMA_TX,
84 	__ROCKER_DMA_RX,
85 #define ROCKER_DMA_TX(port) (__ROCKER_DMA_TX + (port) * 2)
86 #define ROCKER_DMA_RX(port) (__ROCKER_DMA_RX + (port) * 2)
87 };
88 
89 /* Rocker DMA ring size limits and default sizes */
90 #define ROCKER_DMA_SIZE_MIN		2ul
91 #define ROCKER_DMA_SIZE_MAX		65536ul
92 #define ROCKER_DMA_CMD_DEFAULT_SIZE	32ul
93 #define ROCKER_DMA_EVENT_DEFAULT_SIZE	32ul
94 #define ROCKER_DMA_TX_DEFAULT_SIZE	64ul
95 #define ROCKER_DMA_TX_DESC_SIZE		256
96 #define ROCKER_DMA_RX_DEFAULT_SIZE	64ul
97 #define ROCKER_DMA_RX_DESC_SIZE		256
98 
99 /* Rocker DMA descriptor struct */
100 struct rocker_desc {
101 	u64 buf_addr;
102 	u64 cookie;
103 	u16 buf_size;
104 	u16 tlv_size;
105 	u16 resv[5];
106 	u16 comp_err;
107 };
108 
109 #define ROCKER_DMA_DESC_COMP_ERR_GEN	BIT(15)
110 
111 /* Rocker DMA TLV struct */
112 struct rocker_tlv {
113 	u32 type;
114 	u16 len;
115 };
116 
117 /* TLVs */
118 enum {
119 	ROCKER_TLV_CMD_UNSPEC,
120 	ROCKER_TLV_CMD_TYPE,	/* u16 */
121 	ROCKER_TLV_CMD_INFO,	/* nest */
122 
123 	__ROCKER_TLV_CMD_MAX,
124 	ROCKER_TLV_CMD_MAX = __ROCKER_TLV_CMD_MAX - 1,
125 };
126 
127 enum {
128 	ROCKER_TLV_CMD_TYPE_UNSPEC,
129 	ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS,
130 	ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS,
131 	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD,
132 	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD,
133 	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL,
134 	ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS,
135 	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD,
136 	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD,
137 	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL,
138 	ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS,
139 
140 	ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS,
141 	ROCKER_TLV_CMD_TYPE_GET_PORT_STATS,
142 
143 	__ROCKER_TLV_CMD_TYPE_MAX,
144 	ROCKER_TLV_CMD_TYPE_MAX = __ROCKER_TLV_CMD_TYPE_MAX - 1,
145 };
146 
147 enum {
148 	ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC,
149 	ROCKER_TLV_CMD_PORT_SETTINGS_PPORT,		/* u32 */
150 	ROCKER_TLV_CMD_PORT_SETTINGS_SPEED,		/* u32 */
151 	ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX,		/* u8 */
152 	ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG,		/* u8 */
153 	ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR,		/* binary */
154 	ROCKER_TLV_CMD_PORT_SETTINGS_MODE,		/* u8 */
155 	ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING,		/* u8 */
156 	ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME,		/* binary */
157 	ROCKER_TLV_CMD_PORT_SETTINGS_MTU,		/* u16 */
158 
159 	__ROCKER_TLV_CMD_PORT_SETTINGS_MAX,
160 	ROCKER_TLV_CMD_PORT_SETTINGS_MAX =
161 			__ROCKER_TLV_CMD_PORT_SETTINGS_MAX - 1,
162 };
163 
164 enum {
165 	ROCKER_TLV_CMD_PORT_STATS_UNSPEC,
166 	ROCKER_TLV_CMD_PORT_STATS_PPORT,            /* u32 */
167 
168 	ROCKER_TLV_CMD_PORT_STATS_RX_PKTS,          /* u64 */
169 	ROCKER_TLV_CMD_PORT_STATS_RX_BYTES,         /* u64 */
170 	ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED,       /* u64 */
171 	ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS,        /* u64 */
172 
173 	ROCKER_TLV_CMD_PORT_STATS_TX_PKTS,          /* u64 */
174 	ROCKER_TLV_CMD_PORT_STATS_TX_BYTES,         /* u64 */
175 	ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED,       /* u64 */
176 	ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS,        /* u64 */
177 
178 	__ROCKER_TLV_CMD_PORT_STATS_MAX,
179 	ROCKER_TLV_CMD_PORT_STATS_MAX = __ROCKER_TLV_CMD_PORT_STATS_MAX - 1,
180 };
181 
182 enum rocker_port_mode {
183 	ROCKER_PORT_MODE_OF_DPA,
184 };
185 
186 enum {
187 	ROCKER_TLV_EVENT_UNSPEC,
188 	ROCKER_TLV_EVENT_TYPE,	/* u16 */
189 	ROCKER_TLV_EVENT_INFO,	/* nest */
190 
191 	__ROCKER_TLV_EVENT_MAX,
192 	ROCKER_TLV_EVENT_MAX = __ROCKER_TLV_EVENT_MAX - 1,
193 };
194 
195 enum {
196 	ROCKER_TLV_EVENT_TYPE_UNSPEC,
197 	ROCKER_TLV_EVENT_TYPE_LINK_CHANGED,
198 	ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN,
199 
200 	__ROCKER_TLV_EVENT_TYPE_MAX,
201 	ROCKER_TLV_EVENT_TYPE_MAX = __ROCKER_TLV_EVENT_TYPE_MAX - 1,
202 };
203 
204 enum {
205 	ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC,
206 	ROCKER_TLV_EVENT_LINK_CHANGED_PPORT,	/* u32 */
207 	ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP,	/* u8 */
208 
209 	__ROCKER_TLV_EVENT_LINK_CHANGED_MAX,
210 	ROCKER_TLV_EVENT_LINK_CHANGED_MAX =
211 			__ROCKER_TLV_EVENT_LINK_CHANGED_MAX - 1,
212 };
213 
214 enum {
215 	ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC,
216 	ROCKER_TLV_EVENT_MAC_VLAN_PPORT,	/* u32 */
217 	ROCKER_TLV_EVENT_MAC_VLAN_MAC,		/* binary */
218 	ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID,	/* __be16 */
219 
220 	__ROCKER_TLV_EVENT_MAC_VLAN_MAX,
221 	ROCKER_TLV_EVENT_MAC_VLAN_MAX = __ROCKER_TLV_EVENT_MAC_VLAN_MAX - 1,
222 };
223 
224 enum {
225 	ROCKER_TLV_RX_UNSPEC,
226 	ROCKER_TLV_RX_FLAGS,		/* u16, see ROCKER_RX_FLAGS_ */
227 	ROCKER_TLV_RX_CSUM,		/* u16 */
228 	ROCKER_TLV_RX_FRAG_ADDR,	/* u64 */
229 	ROCKER_TLV_RX_FRAG_MAX_LEN,	/* u16 */
230 	ROCKER_TLV_RX_FRAG_LEN,		/* u16 */
231 
232 	__ROCKER_TLV_RX_MAX,
233 	ROCKER_TLV_RX_MAX = __ROCKER_TLV_RX_MAX - 1,
234 };
235 
236 #define ROCKER_RX_FLAGS_IPV4			BIT(0)
237 #define ROCKER_RX_FLAGS_IPV6			BIT(1)
238 #define ROCKER_RX_FLAGS_CSUM_CALC		BIT(2)
239 #define ROCKER_RX_FLAGS_IPV4_CSUM_GOOD		BIT(3)
240 #define ROCKER_RX_FLAGS_IP_FRAG			BIT(4)
241 #define ROCKER_RX_FLAGS_TCP			BIT(5)
242 #define ROCKER_RX_FLAGS_UDP			BIT(6)
243 #define ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD	BIT(7)
244 #define ROCKER_RX_FLAGS_FWD_OFFLOAD		BIT(8)
245 
246 enum {
247 	ROCKER_TLV_TX_UNSPEC,
248 	ROCKER_TLV_TX_OFFLOAD,		/* u8, see ROCKER_TX_OFFLOAD_ */
249 	ROCKER_TLV_TX_L3_CSUM_OFF,	/* u16 */
250 	ROCKER_TLV_TX_TSO_MSS,		/* u16 */
251 	ROCKER_TLV_TX_TSO_HDR_LEN,	/* u16 */
252 	ROCKER_TLV_TX_FRAGS,		/* array */
253 
254 	__ROCKER_TLV_TX_MAX,
255 	ROCKER_TLV_TX_MAX = __ROCKER_TLV_TX_MAX - 1,
256 };
257 
258 #define ROCKER_TX_OFFLOAD_NONE		0
259 #define ROCKER_TX_OFFLOAD_IP_CSUM	1
260 #define ROCKER_TX_OFFLOAD_TCP_UDP_CSUM	2
261 #define ROCKER_TX_OFFLOAD_L3_CSUM	3
262 #define ROCKER_TX_OFFLOAD_TSO		4
263 
264 #define ROCKER_TX_FRAGS_MAX		16
265 
266 enum {
267 	ROCKER_TLV_TX_FRAG_UNSPEC,
268 	ROCKER_TLV_TX_FRAG,		/* nest */
269 
270 	__ROCKER_TLV_TX_FRAG_MAX,
271 	ROCKER_TLV_TX_FRAG_MAX = __ROCKER_TLV_TX_FRAG_MAX - 1,
272 };
273 
274 enum {
275 	ROCKER_TLV_TX_FRAG_ATTR_UNSPEC,
276 	ROCKER_TLV_TX_FRAG_ATTR_ADDR,	/* u64 */
277 	ROCKER_TLV_TX_FRAG_ATTR_LEN,	/* u16 */
278 
279 	__ROCKER_TLV_TX_FRAG_ATTR_MAX,
280 	ROCKER_TLV_TX_FRAG_ATTR_MAX = __ROCKER_TLV_TX_FRAG_ATTR_MAX - 1,
281 };
282 
283 /* cmd info nested for OF-DPA msgs */
284 enum {
285 	ROCKER_TLV_OF_DPA_UNSPEC,
286 	ROCKER_TLV_OF_DPA_TABLE_ID,		/* u16 */
287 	ROCKER_TLV_OF_DPA_PRIORITY,		/* u32 */
288 	ROCKER_TLV_OF_DPA_HARDTIME,		/* u32 */
289 	ROCKER_TLV_OF_DPA_IDLETIME,		/* u32 */
290 	ROCKER_TLV_OF_DPA_COOKIE,		/* u64 */
291 	ROCKER_TLV_OF_DPA_IN_PPORT,		/* u32 */
292 	ROCKER_TLV_OF_DPA_IN_PPORT_MASK,	/* u32 */
293 	ROCKER_TLV_OF_DPA_OUT_PPORT,		/* u32 */
294 	ROCKER_TLV_OF_DPA_GOTO_TABLE_ID,	/* u16 */
295 	ROCKER_TLV_OF_DPA_GROUP_ID,		/* u32 */
296 	ROCKER_TLV_OF_DPA_GROUP_ID_LOWER,	/* u32 */
297 	ROCKER_TLV_OF_DPA_GROUP_COUNT,		/* u16 */
298 	ROCKER_TLV_OF_DPA_GROUP_IDS,		/* u32 array */
299 	ROCKER_TLV_OF_DPA_VLAN_ID,		/* __be16 */
300 	ROCKER_TLV_OF_DPA_VLAN_ID_MASK,		/* __be16 */
301 	ROCKER_TLV_OF_DPA_VLAN_PCP,		/* __be16 */
302 	ROCKER_TLV_OF_DPA_VLAN_PCP_MASK,	/* __be16 */
303 	ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION,	/* u8 */
304 	ROCKER_TLV_OF_DPA_NEW_VLAN_ID,		/* __be16 */
305 	ROCKER_TLV_OF_DPA_NEW_VLAN_PCP,		/* u8 */
306 	ROCKER_TLV_OF_DPA_TUNNEL_ID,		/* u32 */
307 	ROCKER_TLV_OF_DPA_TUNNEL_LPORT,		/* u32 */
308 	ROCKER_TLV_OF_DPA_ETHERTYPE,		/* __be16 */
309 	ROCKER_TLV_OF_DPA_DST_MAC,		/* binary */
310 	ROCKER_TLV_OF_DPA_DST_MAC_MASK,		/* binary */
311 	ROCKER_TLV_OF_DPA_SRC_MAC,		/* binary */
312 	ROCKER_TLV_OF_DPA_SRC_MAC_MASK,		/* binary */
313 	ROCKER_TLV_OF_DPA_IP_PROTO,		/* u8 */
314 	ROCKER_TLV_OF_DPA_IP_PROTO_MASK,	/* u8 */
315 	ROCKER_TLV_OF_DPA_IP_DSCP,		/* u8 */
316 	ROCKER_TLV_OF_DPA_IP_DSCP_MASK,		/* u8 */
317 	ROCKER_TLV_OF_DPA_IP_DSCP_ACTION,	/* u8 */
318 	ROCKER_TLV_OF_DPA_NEW_IP_DSCP,		/* u8 */
319 	ROCKER_TLV_OF_DPA_IP_ECN,		/* u8 */
320 	ROCKER_TLV_OF_DPA_IP_ECN_MASK,		/* u8 */
321 	ROCKER_TLV_OF_DPA_DST_IP,		/* __be32 */
322 	ROCKER_TLV_OF_DPA_DST_IP_MASK,		/* __be32 */
323 	ROCKER_TLV_OF_DPA_SRC_IP,		/* __be32 */
324 	ROCKER_TLV_OF_DPA_SRC_IP_MASK,		/* __be32 */
325 	ROCKER_TLV_OF_DPA_DST_IPV6,		/* binary */
326 	ROCKER_TLV_OF_DPA_DST_IPV6_MASK,	/* binary */
327 	ROCKER_TLV_OF_DPA_SRC_IPV6,		/* binary */
328 	ROCKER_TLV_OF_DPA_SRC_IPV6_MASK,	/* binary */
329 	ROCKER_TLV_OF_DPA_SRC_ARP_IP,		/* __be32 */
330 	ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK,	/* __be32 */
331 	ROCKER_TLV_OF_DPA_L4_DST_PORT,		/* __be16 */
332 	ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK,	/* __be16 */
333 	ROCKER_TLV_OF_DPA_L4_SRC_PORT,		/* __be16 */
334 	ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK,	/* __be16 */
335 	ROCKER_TLV_OF_DPA_ICMP_TYPE,		/* u8 */
336 	ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK,	/* u8 */
337 	ROCKER_TLV_OF_DPA_ICMP_CODE,		/* u8 */
338 	ROCKER_TLV_OF_DPA_ICMP_CODE_MASK,	/* u8 */
339 	ROCKER_TLV_OF_DPA_IPV6_LABEL,		/* __be32 */
340 	ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK,	/* __be32 */
341 	ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION,	/* u8 */
342 	ROCKER_TLV_OF_DPA_NEW_QUEUE_ID,		/* u8 */
343 	ROCKER_TLV_OF_DPA_CLEAR_ACTIONS,	/* u32 */
344 	ROCKER_TLV_OF_DPA_POP_VLAN,		/* u8 */
345 	ROCKER_TLV_OF_DPA_TTL_CHECK,		/* u8 */
346 	ROCKER_TLV_OF_DPA_COPY_CPU_ACTION,	/* u8 */
347 
348 	__ROCKER_TLV_OF_DPA_MAX,
349 	ROCKER_TLV_OF_DPA_MAX = __ROCKER_TLV_OF_DPA_MAX - 1,
350 };
351 
352 /* OF-DPA table IDs */
353 
354 enum rocker_of_dpa_table_id {
355 	ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT = 0,
356 	ROCKER_OF_DPA_TABLE_ID_VLAN = 10,
357 	ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC = 20,
358 	ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING = 30,
359 	ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING = 40,
360 	ROCKER_OF_DPA_TABLE_ID_BRIDGING = 50,
361 	ROCKER_OF_DPA_TABLE_ID_ACL_POLICY = 60,
362 };
363 
364 /* OF-DPA flow stats */
365 enum {
366 	ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC,
367 	ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION,	/* u32 */
368 	ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS,	/* u64 */
369 	ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS,	/* u64 */
370 
371 	__ROCKER_TLV_OF_DPA_FLOW_STAT_MAX,
372 	ROCKER_TLV_OF_DPA_FLOW_STAT_MAX = __ROCKER_TLV_OF_DPA_FLOW_STAT_MAX - 1,
373 };
374 
375 /* OF-DPA group types */
376 enum rocker_of_dpa_group_type {
377 	ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE = 0,
378 	ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE,
379 	ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST,
380 	ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST,
381 	ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD,
382 	ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE,
383 	ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST,
384 	ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP,
385 	ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY,
386 };
387 
388 /* OF-DPA group L2 overlay types */
389 enum rocker_of_dpa_overlay_type {
390 	ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST = 0,
391 	ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST,
392 	ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST,
393 	ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST,
394 };
395 
396 /* OF-DPA group ID encoding */
397 #define ROCKER_GROUP_TYPE_SHIFT 28
398 #define ROCKER_GROUP_TYPE_MASK 0xf0000000
399 #define ROCKER_GROUP_VLAN_SHIFT 16
400 #define ROCKER_GROUP_VLAN_MASK 0x0fff0000
401 #define ROCKER_GROUP_PORT_SHIFT 0
402 #define ROCKER_GROUP_PORT_MASK 0x0000ffff
403 #define ROCKER_GROUP_TUNNEL_ID_SHIFT 12
404 #define ROCKER_GROUP_TUNNEL_ID_MASK 0x0ffff000
405 #define ROCKER_GROUP_SUBTYPE_SHIFT 10
406 #define ROCKER_GROUP_SUBTYPE_MASK 0x00000c00
407 #define ROCKER_GROUP_INDEX_SHIFT 0
408 #define ROCKER_GROUP_INDEX_MASK 0x0000ffff
409 #define ROCKER_GROUP_INDEX_LONG_SHIFT 0
410 #define ROCKER_GROUP_INDEX_LONG_MASK 0x0fffffff
411 
412 #define ROCKER_GROUP_TYPE_GET(group_id) \
413 	(((group_id) & ROCKER_GROUP_TYPE_MASK) >> ROCKER_GROUP_TYPE_SHIFT)
414 #define ROCKER_GROUP_TYPE_SET(type) \
415 	(((type) << ROCKER_GROUP_TYPE_SHIFT) & ROCKER_GROUP_TYPE_MASK)
416 #define ROCKER_GROUP_VLAN_GET(group_id) \
417 	(((group_id) & ROCKER_GROUP_VLAN_ID_MASK) >> ROCKER_GROUP_VLAN_ID_SHIFT)
418 #define ROCKER_GROUP_VLAN_SET(vlan_id) \
419 	(((vlan_id) << ROCKER_GROUP_VLAN_SHIFT) & ROCKER_GROUP_VLAN_MASK)
420 #define ROCKER_GROUP_PORT_GET(group_id) \
421 	(((group_id) & ROCKER_GROUP_PORT_MASK) >> ROCKER_GROUP_PORT_SHIFT)
422 #define ROCKER_GROUP_PORT_SET(port) \
423 	(((port) << ROCKER_GROUP_PORT_SHIFT) & ROCKER_GROUP_PORT_MASK)
424 #define ROCKER_GROUP_INDEX_GET(group_id) \
425 	(((group_id) & ROCKER_GROUP_INDEX_MASK) >> ROCKER_GROUP_INDEX_SHIFT)
426 #define ROCKER_GROUP_INDEX_SET(index) \
427 	(((index) << ROCKER_GROUP_INDEX_SHIFT) & ROCKER_GROUP_INDEX_MASK)
428 #define ROCKER_GROUP_INDEX_LONG_GET(group_id) \
429 	(((group_id) & ROCKER_GROUP_INDEX_LONG_MASK) >> \
430 	 ROCKER_GROUP_INDEX_LONG_SHIFT)
431 #define ROCKER_GROUP_INDEX_LONG_SET(index) \
432 	(((index) << ROCKER_GROUP_INDEX_LONG_SHIFT) & \
433 	 ROCKER_GROUP_INDEX_LONG_MASK)
434 
435 #define ROCKER_GROUP_NONE 0
436 #define ROCKER_GROUP_L2_INTERFACE(vlan_id, port) \
437 	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE) |\
438 	 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_PORT_SET(port))
439 #define ROCKER_GROUP_L2_REWRITE(index) \
440 	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE) |\
441 	 ROCKER_GROUP_INDEX_LONG_SET(index))
442 #define ROCKER_GROUP_L2_MCAST(vlan_id, index) \
443 	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST) |\
444 	 ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
445 #define ROCKER_GROUP_L2_FLOOD(vlan_id, index) \
446 	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD) |\
447 	ROCKER_GROUP_VLAN_SET(ntohs(vlan_id)) | ROCKER_GROUP_INDEX_SET(index))
448 #define ROCKER_GROUP_L3_UNICAST(index) \
449 	(ROCKER_GROUP_TYPE_SET(ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST) |\
450 	 ROCKER_GROUP_INDEX_LONG_SET(index))
451 
452 /* Rocker general purpose registers */
453 #define ROCKER_CONTROL			0x0300
454 #define ROCKER_PORT_PHYS_COUNT		0x0304
455 #define ROCKER_PORT_PHYS_LINK_STATUS	0x0310 /* 8-byte */
456 #define ROCKER_PORT_PHYS_ENABLE		0x0318 /* 8-byte */
457 #define ROCKER_SWITCH_ID		0x0320 /* 8-byte */
458 
459 /* Rocker control bits */
460 #define ROCKER_CONTROL_RESET		BIT(0)
461 
462 #endif
463