1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/dmaengine.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/pinctrl/consumer.h>
13 #include <linux/platform_device.h>
14 #include <linux/spi/spi.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/scatterlist.h>
17
18 #define DRIVER_NAME "rockchip-spi"
19
20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
23 writel_relaxed(readl_relaxed(reg) | (bits), reg)
24
25 /* SPI register offsets */
26 #define ROCKCHIP_SPI_CTRLR0 0x0000
27 #define ROCKCHIP_SPI_CTRLR1 0x0004
28 #define ROCKCHIP_SPI_SSIENR 0x0008
29 #define ROCKCHIP_SPI_SER 0x000c
30 #define ROCKCHIP_SPI_BAUDR 0x0010
31 #define ROCKCHIP_SPI_TXFTLR 0x0014
32 #define ROCKCHIP_SPI_RXFTLR 0x0018
33 #define ROCKCHIP_SPI_TXFLR 0x001c
34 #define ROCKCHIP_SPI_RXFLR 0x0020
35 #define ROCKCHIP_SPI_SR 0x0024
36 #define ROCKCHIP_SPI_IPR 0x0028
37 #define ROCKCHIP_SPI_IMR 0x002c
38 #define ROCKCHIP_SPI_ISR 0x0030
39 #define ROCKCHIP_SPI_RISR 0x0034
40 #define ROCKCHIP_SPI_ICR 0x0038
41 #define ROCKCHIP_SPI_DMACR 0x003c
42 #define ROCKCHIP_SPI_DMATDLR 0x0040
43 #define ROCKCHIP_SPI_DMARDLR 0x0044
44 #define ROCKCHIP_SPI_VERSION 0x0048
45 #define ROCKCHIP_SPI_TXDR 0x0400
46 #define ROCKCHIP_SPI_RXDR 0x0800
47
48 /* Bit fields in CTRLR0 */
49 #define CR0_DFS_OFFSET 0
50 #define CR0_DFS_4BIT 0x0
51 #define CR0_DFS_8BIT 0x1
52 #define CR0_DFS_16BIT 0x2
53
54 #define CR0_CFS_OFFSET 2
55
56 #define CR0_SCPH_OFFSET 6
57
58 #define CR0_SCPOL_OFFSET 7
59
60 #define CR0_CSM_OFFSET 8
61 #define CR0_CSM_KEEP 0x0
62 /* ss_n be high for half sclk_out cycles */
63 #define CR0_CSM_HALF 0X1
64 /* ss_n be high for one sclk_out cycle */
65 #define CR0_CSM_ONE 0x2
66
67 /* ss_n to sclk_out delay */
68 #define CR0_SSD_OFFSET 10
69 /*
70 * The period between ss_n active and
71 * sclk_out active is half sclk_out cycles
72 */
73 #define CR0_SSD_HALF 0x0
74 /*
75 * The period between ss_n active and
76 * sclk_out active is one sclk_out cycle
77 */
78 #define CR0_SSD_ONE 0x1
79
80 #define CR0_EM_OFFSET 11
81 #define CR0_EM_LITTLE 0x0
82 #define CR0_EM_BIG 0x1
83
84 #define CR0_FBM_OFFSET 12
85 #define CR0_FBM_MSB 0x0
86 #define CR0_FBM_LSB 0x1
87
88 #define CR0_BHT_OFFSET 13
89 #define CR0_BHT_16BIT 0x0
90 #define CR0_BHT_8BIT 0x1
91
92 #define CR0_RSD_OFFSET 14
93 #define CR0_RSD_MAX 0x3
94
95 #define CR0_FRF_OFFSET 16
96 #define CR0_FRF_SPI 0x0
97 #define CR0_FRF_SSP 0x1
98 #define CR0_FRF_MICROWIRE 0x2
99
100 #define CR0_XFM_OFFSET 18
101 #define CR0_XFM_TR 0x0
102 #define CR0_XFM_TO 0x1
103 #define CR0_XFM_RO 0x2
104
105 #define CR0_OPM_OFFSET 20
106 #define CR0_OPM_HOST 0x0
107 #define CR0_OPM_TARGET 0x1
108
109 #define CR0_SOI_OFFSET 23
110
111 /* Bit fields in SER, 2bit */
112 #define SER_MASK 0x3
113
114 /* Bit fields in BAUDR */
115 #define BAUDR_SCKDV_MIN 2
116 #define BAUDR_SCKDV_MAX 65534
117
118 /* Bit fields in SR, 6bit */
119 #define SR_MASK 0x3f
120 #define SR_BUSY (1 << 0)
121 #define SR_TF_FULL (1 << 1)
122 #define SR_TF_EMPTY (1 << 2)
123 #define SR_RF_EMPTY (1 << 3)
124 #define SR_RF_FULL (1 << 4)
125 #define SR_TARGET_TX_BUSY (1 << 5)
126
127 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
128 #define INT_MASK 0x1f
129 #define INT_TF_EMPTY (1 << 0)
130 #define INT_TF_OVERFLOW (1 << 1)
131 #define INT_RF_UNDERFLOW (1 << 2)
132 #define INT_RF_OVERFLOW (1 << 3)
133 #define INT_RF_FULL (1 << 4)
134 #define INT_CS_INACTIVE (1 << 6)
135
136 /* Bit fields in ICR, 4bit */
137 #define ICR_MASK 0x0f
138 #define ICR_ALL (1 << 0)
139 #define ICR_RF_UNDERFLOW (1 << 1)
140 #define ICR_RF_OVERFLOW (1 << 2)
141 #define ICR_TF_OVERFLOW (1 << 3)
142
143 /* Bit fields in DMACR */
144 #define RF_DMA_EN (1 << 0)
145 #define TF_DMA_EN (1 << 1)
146
147 /* Driver state flags */
148 #define RXDMA (1 << 0)
149 #define TXDMA (1 << 1)
150
151 /* sclk_out: spi host internal logic in rk3x can support 50Mhz */
152 #define MAX_SCLK_OUT 50000000U
153
154 /*
155 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
156 * the controller seems to hang when given 0x10000, so stick with this for now.
157 */
158 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
159
160 #define ROCKCHIP_SPI_MAX_NATIVE_CS_NUM 2
161 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
162 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
163
164 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000
165
166 struct rockchip_spi {
167 struct device *dev;
168
169 struct clk *spiclk;
170 struct clk *apb_pclk;
171
172 void __iomem *regs;
173 dma_addr_t dma_addr_rx;
174 dma_addr_t dma_addr_tx;
175
176 const void *tx;
177 void *rx;
178 unsigned int tx_left;
179 unsigned int rx_left;
180
181 atomic_t state;
182
183 /*depth of the FIFO buffer */
184 u32 fifo_len;
185 /* frequency of spiclk */
186 u32 freq;
187
188 u8 n_bytes;
189 u8 rsd;
190
191 bool target_abort;
192 bool cs_inactive; /* spi target transmission stop when cs inactive */
193 bool cs_high_supported; /* native CS supports active-high polarity */
194
195 struct spi_transfer *xfer; /* Store xfer temporarily */
196 };
197
spi_enable_chip(struct rockchip_spi * rs,bool enable)198 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
199 {
200 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
201 }
202
wait_for_tx_idle(struct rockchip_spi * rs,bool target_mode)203 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool target_mode)
204 {
205 unsigned long timeout = jiffies + msecs_to_jiffies(5);
206
207 do {
208 if (target_mode) {
209 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) &&
210 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
211 return;
212 } else {
213 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
214 return;
215 }
216 } while (!time_after(jiffies, timeout));
217
218 dev_warn(rs->dev, "spi controller is in busy state!\n");
219 }
220
get_fifo_len(struct rockchip_spi * rs)221 static u32 get_fifo_len(struct rockchip_spi *rs)
222 {
223 u32 ver;
224
225 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
226
227 switch (ver) {
228 case ROCKCHIP_SPI_VER2_TYPE1:
229 case ROCKCHIP_SPI_VER2_TYPE2:
230 return 64;
231 default:
232 return 32;
233 }
234 }
235
rockchip_spi_set_cs(struct spi_device * spi,bool enable)236 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
237 {
238 struct spi_controller *ctlr = spi->controller;
239 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
240 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
241 bool cs_actual;
242
243 /*
244 * SPI subsystem tries to avoid no-op calls that would break the PM
245 * refcount below. It can't however for the first time it is used.
246 * To detect this case we read it here and bail out early for no-ops.
247 */
248 if (spi_get_csgpiod(spi, 0))
249 cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 1);
250 else
251 cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) &
252 BIT(spi_get_chipselect(spi, 0)));
253 if (unlikely(cs_actual == cs_asserted))
254 return;
255
256 if (cs_asserted) {
257 /* Keep things powered as long as CS is asserted */
258 pm_runtime_get_sync(rs->dev);
259
260 if (spi_get_csgpiod(spi, 0))
261 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
262 else
263 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER,
264 BIT(spi_get_chipselect(spi, 0)));
265 } else {
266 if (spi_get_csgpiod(spi, 0))
267 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
268 else
269 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER,
270 BIT(spi_get_chipselect(spi, 0)));
271
272 /* Drop reference from when we first asserted CS */
273 pm_runtime_put(rs->dev);
274 }
275 }
276
rockchip_spi_handle_err(struct spi_controller * ctlr,struct spi_message * msg)277 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
278 struct spi_message *msg)
279 {
280 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
281
282 /* stop running spi transfer
283 * this also flushes both rx and tx fifos
284 */
285 spi_enable_chip(rs, false);
286
287 /* make sure all interrupts are masked and status cleared */
288 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
289 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
290
291 if (atomic_read(&rs->state) & TXDMA)
292 dmaengine_terminate_async(ctlr->dma_tx);
293
294 if (atomic_read(&rs->state) & RXDMA)
295 dmaengine_terminate_async(ctlr->dma_rx);
296 }
297
rockchip_spi_pio_writer(struct rockchip_spi * rs)298 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
299 {
300 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
301 u32 words = min(rs->tx_left, tx_free);
302
303 rs->tx_left -= words;
304 for (; words; words--) {
305 u32 txw;
306
307 if (rs->n_bytes == 1)
308 txw = *(u8 *)rs->tx;
309 else
310 txw = *(u16 *)rs->tx;
311
312 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
313 rs->tx += rs->n_bytes;
314 }
315 }
316
rockchip_spi_pio_reader(struct rockchip_spi * rs)317 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
318 {
319 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
320 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
321
322 /* the hardware doesn't allow us to change fifo threshold
323 * level while spi is enabled, so instead make sure to leave
324 * enough words in the rx fifo to get the last interrupt
325 * exactly when all words have been received
326 */
327 if (rx_left) {
328 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
329
330 if (rx_left < ftl) {
331 rx_left = ftl;
332 words = rs->rx_left - rx_left;
333 }
334 }
335
336 rs->rx_left = rx_left;
337 for (; words; words--) {
338 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
339
340 if (!rs->rx)
341 continue;
342
343 if (rs->n_bytes == 1)
344 *(u8 *)rs->rx = (u8)rxw;
345 else
346 *(u16 *)rs->rx = (u16)rxw;
347 rs->rx += rs->n_bytes;
348 }
349 }
350
rockchip_spi_isr(int irq,void * dev_id)351 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
352 {
353 struct spi_controller *ctlr = dev_id;
354 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
355
356 /* When int_cs_inactive comes, spi target abort */
357 if (rs->cs_inactive &&
358 (readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE)) {
359 ctlr->target_abort(ctlr);
360 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
361 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
362
363 return IRQ_HANDLED;
364 }
365
366 if (rs->tx_left)
367 rockchip_spi_pio_writer(rs);
368
369 rockchip_spi_pio_reader(rs);
370 if (!rs->rx_left) {
371 spi_enable_chip(rs, false);
372 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
373 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
374 spi_finalize_current_transfer(ctlr);
375 }
376
377 return IRQ_HANDLED;
378 }
379
rockchip_spi_prepare_irq(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)380 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
381 struct spi_controller *ctlr,
382 struct spi_transfer *xfer)
383 {
384 rs->tx = xfer->tx_buf;
385 rs->rx = xfer->rx_buf;
386 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
387 rs->rx_left = xfer->len / rs->n_bytes;
388
389 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
390
391 spi_enable_chip(rs, true);
392
393 if (rs->tx_left)
394 rockchip_spi_pio_writer(rs);
395
396 if (rs->cs_inactive)
397 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
398 else
399 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
400
401 /* 1 means the transfer is in progress */
402 return 1;
403 }
404
rockchip_spi_dma_rxcb(void * data)405 static void rockchip_spi_dma_rxcb(void *data)
406 {
407 struct spi_controller *ctlr = data;
408 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
409 int state = atomic_fetch_andnot(RXDMA, &rs->state);
410
411 if (state & TXDMA && !rs->target_abort)
412 return;
413
414 if (rs->cs_inactive)
415 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
416
417 spi_enable_chip(rs, false);
418 spi_finalize_current_transfer(ctlr);
419 }
420
rockchip_spi_dma_txcb(void * data)421 static void rockchip_spi_dma_txcb(void *data)
422 {
423 struct spi_controller *ctlr = data;
424 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
425 int state = atomic_fetch_andnot(TXDMA, &rs->state);
426
427 if (state & RXDMA && !rs->target_abort)
428 return;
429
430 /* Wait until the FIFO data completely. */
431 wait_for_tx_idle(rs, ctlr->target);
432
433 spi_enable_chip(rs, false);
434 spi_finalize_current_transfer(ctlr);
435 }
436
rockchip_spi_calc_burst_size(u32 data_len)437 static u32 rockchip_spi_calc_burst_size(u32 data_len)
438 {
439 u32 i;
440
441 /* burst size: 1, 2, 4, 8 */
442 for (i = 1; i < 8; i <<= 1) {
443 if (data_len & i)
444 break;
445 }
446
447 return i;
448 }
449
rockchip_spi_prepare_dma(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)450 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
451 struct spi_controller *ctlr, struct spi_transfer *xfer)
452 {
453 struct dma_async_tx_descriptor *rxdesc, *txdesc;
454
455 atomic_set(&rs->state, 0);
456
457 rs->tx = xfer->tx_buf;
458 rs->rx = xfer->rx_buf;
459
460 rxdesc = NULL;
461 if (xfer->rx_buf) {
462 struct dma_slave_config rxconf = {
463 .direction = DMA_DEV_TO_MEM,
464 .src_addr = rs->dma_addr_rx,
465 .src_addr_width = rs->n_bytes,
466 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes),
467 };
468
469 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
470
471 rxdesc = dmaengine_prep_slave_sg(
472 ctlr->dma_rx,
473 xfer->rx_sg.sgl, xfer->rx_sg.nents,
474 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
475 if (!rxdesc)
476 return -EINVAL;
477
478 rxdesc->callback = rockchip_spi_dma_rxcb;
479 rxdesc->callback_param = ctlr;
480 }
481
482 txdesc = NULL;
483 if (xfer->tx_buf) {
484 struct dma_slave_config txconf = {
485 .direction = DMA_MEM_TO_DEV,
486 .dst_addr = rs->dma_addr_tx,
487 .dst_addr_width = rs->n_bytes,
488 .dst_maxburst = rs->fifo_len / 4,
489 };
490
491 dmaengine_slave_config(ctlr->dma_tx, &txconf);
492
493 txdesc = dmaengine_prep_slave_sg(
494 ctlr->dma_tx,
495 xfer->tx_sg.sgl, xfer->tx_sg.nents,
496 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
497 if (!txdesc) {
498 if (rxdesc)
499 dmaengine_terminate_sync(ctlr->dma_rx);
500 return -EINVAL;
501 }
502
503 txdesc->callback = rockchip_spi_dma_txcb;
504 txdesc->callback_param = ctlr;
505 }
506
507 /* rx must be started before tx due to spi instinct */
508 if (rxdesc) {
509 atomic_or(RXDMA, &rs->state);
510 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
511 dma_async_issue_pending(ctlr->dma_rx);
512 }
513
514 if (rs->cs_inactive)
515 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR);
516
517 spi_enable_chip(rs, true);
518
519 if (txdesc) {
520 atomic_or(TXDMA, &rs->state);
521 dmaengine_submit(txdesc);
522 dma_async_issue_pending(ctlr->dma_tx);
523 }
524
525 /* 1 means the transfer is in progress */
526 return 1;
527 }
528
rockchip_spi_config(struct rockchip_spi * rs,struct spi_device * spi,struct spi_transfer * xfer,bool use_dma,bool target_mode)529 static int rockchip_spi_config(struct rockchip_spi *rs,
530 struct spi_device *spi, struct spi_transfer *xfer,
531 bool use_dma, bool target_mode)
532 {
533 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
534 | CR0_BHT_8BIT << CR0_BHT_OFFSET
535 | CR0_SSD_ONE << CR0_SSD_OFFSET
536 | CR0_EM_BIG << CR0_EM_OFFSET;
537 u32 cr1;
538 u32 dmacr = 0;
539
540 if (target_mode)
541 cr0 |= CR0_OPM_TARGET << CR0_OPM_OFFSET;
542 rs->target_abort = false;
543
544 cr0 |= rs->rsd << CR0_RSD_OFFSET;
545 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
546 if (spi->mode & SPI_LSB_FIRST)
547 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
548 if ((spi->mode & SPI_CS_HIGH) && !(spi_get_csgpiod(spi, 0)))
549 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
550
551 if (xfer->rx_buf && xfer->tx_buf)
552 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
553 else if (xfer->rx_buf)
554 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
555 else if (use_dma)
556 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
557
558 switch (xfer->bits_per_word) {
559 case 4:
560 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
561 cr1 = xfer->len - 1;
562 break;
563 case 8:
564 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
565 cr1 = xfer->len - 1;
566 break;
567 case 16:
568 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
569 cr1 = xfer->len / 2 - 1;
570 break;
571 default:
572 /* we only whitelist 4, 8 and 16 bit words in
573 * ctlr->bits_per_word_mask, so this shouldn't
574 * happen
575 */
576 dev_err(rs->dev, "unknown bits per word: %d\n",
577 xfer->bits_per_word);
578 return -EINVAL;
579 }
580
581 if (use_dma) {
582 if (xfer->tx_buf)
583 dmacr |= TF_DMA_EN;
584 if (xfer->rx_buf)
585 dmacr |= RF_DMA_EN;
586 }
587
588 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
589 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
590
591 /* unfortunately setting the fifo threshold level to generate an
592 * interrupt exactly when the fifo is full doesn't seem to work,
593 * so we need the strict inequality here
594 */
595 if ((xfer->len / rs->n_bytes) < rs->fifo_len)
596 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
597 else
598 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
599
600 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
601 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
602 rs->regs + ROCKCHIP_SPI_DMARDLR);
603 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
604
605 /* the hardware only supports an even clock divisor, so
606 * round divisor = spiclk / speed up to nearest even number
607 * so that the resulting speed is <= the requested speed
608 */
609 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
610 rs->regs + ROCKCHIP_SPI_BAUDR);
611
612 return 0;
613 }
614
rockchip_spi_max_transfer_size(struct spi_device * spi)615 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
616 {
617 return ROCKCHIP_SPI_MAX_TRANLEN;
618 }
619
rockchip_spi_target_abort(struct spi_controller * ctlr)620 static int rockchip_spi_target_abort(struct spi_controller *ctlr)
621 {
622 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
623 u32 rx_fifo_left;
624 struct dma_tx_state state;
625 enum dma_status status;
626
627 /* Get current dma rx point */
628 if (atomic_read(&rs->state) & RXDMA) {
629 dmaengine_pause(ctlr->dma_rx);
630 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
631 if (status == DMA_ERROR) {
632 rs->rx = rs->xfer->rx_buf;
633 rs->xfer->len = 0;
634 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
635 for (; rx_fifo_left; rx_fifo_left--)
636 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
637 goto out;
638 } else {
639 rs->rx += rs->xfer->len - rs->n_bytes * state.residue;
640 }
641 }
642
643 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */
644 if (rs->rx) {
645 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
646 for (; rx_fifo_left; rx_fifo_left--) {
647 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
648
649 if (rs->n_bytes == 1)
650 *(u8 *)rs->rx = (u8)rxw;
651 else
652 *(u16 *)rs->rx = (u16)rxw;
653 rs->rx += rs->n_bytes;
654 }
655 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf);
656 }
657
658 out:
659 if (atomic_read(&rs->state) & RXDMA)
660 dmaengine_terminate_sync(ctlr->dma_rx);
661 if (atomic_read(&rs->state) & TXDMA)
662 dmaengine_terminate_sync(ctlr->dma_tx);
663 atomic_set(&rs->state, 0);
664 spi_enable_chip(rs, false);
665 rs->target_abort = true;
666 spi_finalize_current_transfer(ctlr);
667
668 return 0;
669 }
670
rockchip_spi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)671 static int rockchip_spi_transfer_one(
672 struct spi_controller *ctlr,
673 struct spi_device *spi,
674 struct spi_transfer *xfer)
675 {
676 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
677 int ret;
678 bool use_dma;
679
680 /* Zero length transfers won't trigger an interrupt on completion */
681 if (!xfer->len) {
682 spi_finalize_current_transfer(ctlr);
683 return 1;
684 }
685
686 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
687 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
688
689 if (!xfer->tx_buf && !xfer->rx_buf) {
690 dev_err(rs->dev, "No buffer for transfer\n");
691 return -EINVAL;
692 }
693
694 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
695 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
696 return -EINVAL;
697 }
698
699 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
700 rs->xfer = xfer;
701 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
702
703 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->target);
704 if (ret)
705 return ret;
706
707 if (use_dma)
708 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
709
710 return rockchip_spi_prepare_irq(rs, ctlr, xfer);
711 }
712
rockchip_spi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)713 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
714 struct spi_device *spi,
715 struct spi_transfer *xfer)
716 {
717 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
718 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
719
720 /* if the numbor of spi words to transfer is less than the fifo
721 * length we can just fill the fifo and wait for a single irq,
722 * so don't bother setting up dma
723 */
724 return xfer->len / bytes_per_word >= rs->fifo_len;
725 }
726
rockchip_spi_setup(struct spi_device * spi)727 static int rockchip_spi_setup(struct spi_device *spi)
728 {
729 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
730 u32 cr0;
731
732 if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
733 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
734 return -EINVAL;
735 }
736
737 pm_runtime_get_sync(rs->dev);
738
739 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
740
741 cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
742 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
743 if (spi->mode & SPI_CS_HIGH && spi_get_chipselect(spi, 0) <= 1)
744 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
745 else if (spi_get_chipselect(spi, 0) <= 1)
746 cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET);
747
748 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
749
750 pm_runtime_put(rs->dev);
751
752 return 0;
753 }
754
rockchip_spi_probe(struct platform_device * pdev)755 static int rockchip_spi_probe(struct platform_device *pdev)
756 {
757 struct device_node *np = pdev->dev.of_node;
758 struct spi_controller *ctlr;
759 struct rockchip_spi *rs;
760 struct resource *mem;
761 u32 rsd_nsecs, num_cs;
762 bool target_mode;
763 int ret;
764
765 target_mode = of_property_read_bool(np, "spi-slave");
766
767 if (target_mode)
768 ctlr = devm_spi_alloc_target(&pdev->dev, sizeof(*rs));
769 else
770 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*rs));
771
772 if (!ctlr)
773 return -ENOMEM;
774
775 platform_set_drvdata(pdev, ctlr);
776
777 rs = spi_controller_get_devdata(ctlr);
778
779 /* Get basic io resource and map it */
780 rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
781 if (IS_ERR(rs->regs))
782 return PTR_ERR(rs->regs);
783
784 rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
785 if (IS_ERR(rs->apb_pclk)) {
786 return dev_err_probe(&pdev->dev, PTR_ERR(rs->apb_pclk),
787 "Failed to get apb_pclk\n");
788 }
789
790 rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk");
791 if (IS_ERR(rs->spiclk)) {
792 return dev_err_probe(&pdev->dev, PTR_ERR(rs->spiclk),
793 "Failed to get spi_pclk\n");
794 }
795
796 spi_enable_chip(rs, false);
797
798 ret = platform_get_irq(pdev, 0);
799 if (ret < 0)
800 return ret;
801
802 ret = devm_request_irq(&pdev->dev, ret, rockchip_spi_isr, 0,
803 dev_name(&pdev->dev), ctlr);
804 if (ret)
805 return ret;
806
807 rs->dev = &pdev->dev;
808 rs->freq = clk_get_rate(rs->spiclk);
809
810 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
811 &rsd_nsecs)) {
812 /* rx sample delay is expressed in parent clock cycles (max 3) */
813 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 1000000000 >> 8);
814 if (!rsd) {
815 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
816 rs->freq, rsd_nsecs);
817 } else if (rsd > CR0_RSD_MAX) {
818 rsd = CR0_RSD_MAX;
819 dev_warn(rs->dev,
820 "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
821 rs->freq, rsd_nsecs, CR0_RSD_MAX * 1000000000U / rs->freq);
822 }
823 rs->rsd = rsd;
824 }
825
826 rs->fifo_len = get_fifo_len(rs);
827 if (!rs->fifo_len)
828 return dev_err_probe(&pdev->dev, -EINVAL, "Failed to get fifo length\n");
829
830 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
831 pm_runtime_use_autosuspend(&pdev->dev);
832 pm_runtime_set_active(&pdev->dev);
833 pm_runtime_enable(&pdev->dev);
834
835 ctlr->auto_runtime_pm = true;
836 ctlr->bus_num = pdev->id;
837 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
838 if (target_mode) {
839 ctlr->mode_bits |= SPI_NO_CS;
840 ctlr->target_abort = rockchip_spi_target_abort;
841 } else {
842 ctlr->flags = SPI_CONTROLLER_GPIO_SS;
843 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_NATIVE_CS_NUM;
844 /*
845 * rk spi0 has two native cs, spi1..5 one cs only
846 * if num-cs is missing in the dts, default to 1
847 */
848 if (of_property_read_u32(np, "num-cs", &num_cs))
849 num_cs = 1;
850 ctlr->num_chipselect = num_cs;
851 ctlr->use_gpio_descriptors = true;
852 }
853 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
854 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
855 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
856
857 ctlr->setup = rockchip_spi_setup;
858 ctlr->set_cs = rockchip_spi_set_cs;
859 ctlr->transfer_one = rockchip_spi_transfer_one;
860 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
861 ctlr->handle_err = rockchip_spi_handle_err;
862
863 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
864 if (IS_ERR(ctlr->dma_tx)) {
865 /* Check tx to see if we need to defer driver probing */
866 ret = dev_warn_probe(rs->dev, PTR_ERR(ctlr->dma_tx),
867 "Failed to request optional TX DMA channel\n");
868 if (ret == -EPROBE_DEFER)
869 goto err_disable_pm_runtime;
870 ctlr->dma_tx = NULL;
871 }
872
873 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
874 if (IS_ERR(ctlr->dma_rx)) {
875 /* Check rx to see if we need to defer driver probing */
876 ret = dev_warn_probe(rs->dev, PTR_ERR(ctlr->dma_rx),
877 "Failed to request optional RX DMA channel\n");
878 if (ret == -EPROBE_DEFER)
879 goto err_free_dma_tx;
880 ctlr->dma_rx = NULL;
881 }
882
883 if (ctlr->dma_tx && ctlr->dma_rx) {
884 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
885 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
886 ctlr->can_dma = rockchip_spi_can_dma;
887 }
888
889 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
890 case ROCKCHIP_SPI_VER2_TYPE2:
891 rs->cs_high_supported = true;
892 ctlr->mode_bits |= SPI_CS_HIGH;
893 if (ctlr->can_dma && target_mode)
894 rs->cs_inactive = true;
895 else
896 rs->cs_inactive = false;
897 break;
898 default:
899 rs->cs_inactive = false;
900 break;
901 }
902
903 ret = spi_register_controller(ctlr);
904 if (ret < 0) {
905 dev_err(&pdev->dev, "Failed to register controller\n");
906 goto err_free_dma_rx;
907 }
908
909 return 0;
910
911 err_free_dma_rx:
912 if (ctlr->dma_rx)
913 dma_release_channel(ctlr->dma_rx);
914 err_free_dma_tx:
915 if (ctlr->dma_tx)
916 dma_release_channel(ctlr->dma_tx);
917 err_disable_pm_runtime:
918 pm_runtime_disable(&pdev->dev);
919
920 return ret;
921 }
922
rockchip_spi_remove(struct platform_device * pdev)923 static void rockchip_spi_remove(struct platform_device *pdev)
924 {
925 struct spi_controller *ctlr = platform_get_drvdata(pdev);
926
927 pm_runtime_get_sync(&pdev->dev);
928
929 spi_unregister_controller(ctlr);
930
931 pm_runtime_put_noidle(&pdev->dev);
932 pm_runtime_disable(&pdev->dev);
933 pm_runtime_set_suspended(&pdev->dev);
934
935 if (ctlr->dma_tx)
936 dma_release_channel(ctlr->dma_tx);
937 if (ctlr->dma_rx)
938 dma_release_channel(ctlr->dma_rx);
939 }
940
941 #ifdef CONFIG_PM_SLEEP
rockchip_spi_suspend(struct device * dev)942 static int rockchip_spi_suspend(struct device *dev)
943 {
944 int ret;
945 struct spi_controller *ctlr = dev_get_drvdata(dev);
946
947 ret = spi_controller_suspend(ctlr);
948 if (ret < 0)
949 return ret;
950
951 ret = pm_runtime_force_suspend(dev);
952 if (ret < 0) {
953 spi_controller_resume(ctlr);
954 return ret;
955 }
956
957 pinctrl_pm_select_sleep_state(dev);
958
959 return 0;
960 }
961
rockchip_spi_resume(struct device * dev)962 static int rockchip_spi_resume(struct device *dev)
963 {
964 int ret;
965 struct spi_controller *ctlr = dev_get_drvdata(dev);
966
967 pinctrl_pm_select_default_state(dev);
968
969 ret = pm_runtime_force_resume(dev);
970 if (ret < 0)
971 return ret;
972
973 return spi_controller_resume(ctlr);
974 }
975 #endif /* CONFIG_PM_SLEEP */
976
977 #ifdef CONFIG_PM
rockchip_spi_runtime_suspend(struct device * dev)978 static int rockchip_spi_runtime_suspend(struct device *dev)
979 {
980 struct spi_controller *ctlr = dev_get_drvdata(dev);
981 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
982
983 clk_disable_unprepare(rs->spiclk);
984 clk_disable_unprepare(rs->apb_pclk);
985
986 return 0;
987 }
988
rockchip_spi_runtime_resume(struct device * dev)989 static int rockchip_spi_runtime_resume(struct device *dev)
990 {
991 int ret;
992 struct spi_controller *ctlr = dev_get_drvdata(dev);
993 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
994
995 ret = clk_prepare_enable(rs->apb_pclk);
996 if (ret < 0)
997 return ret;
998
999 ret = clk_prepare_enable(rs->spiclk);
1000 if (ret < 0)
1001 clk_disable_unprepare(rs->apb_pclk);
1002
1003 return 0;
1004 }
1005 #endif /* CONFIG_PM */
1006
1007 static const struct dev_pm_ops rockchip_spi_pm = {
1008 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
1009 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
1010 rockchip_spi_runtime_resume, NULL)
1011 };
1012
1013 static const struct of_device_id rockchip_spi_dt_match[] = {
1014 { .compatible = "rockchip,px30-spi", },
1015 { .compatible = "rockchip,rk3036-spi", },
1016 { .compatible = "rockchip,rk3066-spi", },
1017 { .compatible = "rockchip,rk3188-spi", },
1018 { .compatible = "rockchip,rk3228-spi", },
1019 { .compatible = "rockchip,rk3288-spi", },
1020 { .compatible = "rockchip,rk3308-spi", },
1021 { .compatible = "rockchip,rk3328-spi", },
1022 { .compatible = "rockchip,rk3368-spi", },
1023 { .compatible = "rockchip,rk3399-spi", },
1024 { .compatible = "rockchip,rv1108-spi", },
1025 { .compatible = "rockchip,rv1126-spi", },
1026 { },
1027 };
1028 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
1029
1030 static struct platform_driver rockchip_spi_driver = {
1031 .driver = {
1032 .name = DRIVER_NAME,
1033 .pm = &rockchip_spi_pm,
1034 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
1035 },
1036 .probe = rockchip_spi_probe,
1037 .remove = rockchip_spi_remove,
1038 };
1039
1040 module_platform_driver(rockchip_spi_driver);
1041
1042 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
1043 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
1044 MODULE_LICENSE("GPL v2");
1045