Home
last modified time | relevance | path

Searched refs:RLC_PG_CNTL (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4019 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4025 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4030 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
5231 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_static_mg_power_gating()
5237 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5243 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); in polaris11_enable_gfx_quick_mg_power_gating()
5249 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); in cz_enable_gfx_cg_power_gating()
5255 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); in cz_enable_gfx_pipeline_power_gating()
H A Dgfx_v9_0.c3005 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_sck_slow_down_on_power_up()
3019 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_sck_slow_down_on_power_down()
3033 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_cp_power_gating()
3046 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_cg_power_gating()
3059 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_pipeline_powergating()
3076 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_static_mg_power_gating()
3089 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_dynamic_mg_power_gating()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1425 #define RLC_PG_CNTL 0xC40C macro