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Searched refs:RLC_PG_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcik.c6357 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pu()
6363 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6371 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pd()
6377 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6384 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_cp_pg()
6390 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6397 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gds_pg()
6403 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6500 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6503 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
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H A Dsid.h1326 #define RLC_PG_CNTL 0xC35C macro
H A Dcikd.h1425 #define RLC_PG_CNTL 0xC40C macro
H A Dsi.c5243 tmp = RREG32(RLC_PG_CNTL); in si_enable_gfx_cgpg()
5245 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5265 tmp = RREG32(RLC_PG_CNTL); in si_init_gfx_cgpg()
5267 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c4012 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_up()
4018 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0); in cz_enable_sck_slow_down_on_power_down()
4023 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1); in cz_enable_cp_power_gating()
5326 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_static_mg_power_gating()
5332 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gfx_dynamic_mg_power_gating()
5338 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0); in polaris11_enable_gfx_quick_mg_power_gating()
5344 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0); in cz_enable_gfx_cg_power_gating()
5350 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0); in cz_enable_gfx_pipeline_power_gating()
H A Dgfx_v9_0.c2962 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_sck_slow_down_on_power_up()
2976 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_sck_slow_down_on_power_down()
2990 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_cp_power_gating()
3003 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_cg_power_gating()
3016 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_pipeline_powergating()
3033 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_static_mg_power_gating()
3046 data = REG_SET_FIELD(data, RLC_PG_CNTL, in gfx_v9_0_enable_gfx_dynamic_mg_power_gating()
H A Dsid.h1354 #define RLC_PG_CNTL 0x30D7 macro