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Searched refs:RLC_LB_CNTL (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1403 #define RLC_LB_CNTL 0xC364 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c1752 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, in gfx_v9_0_init_lbpw()
1753 * but used for RLC_LB_CNTL configuration */ in gfx_v9_0_init_lbpw()
1755 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_0_init_lbpw()
1756 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_0_init_lbpw()
1801 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, in gfx_v9_4_init_lbpw()
1802 * but used for RLC_LB_CNTL configuration */ in gfx_v9_4_init_lbpw()
1804 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_4_init_lbpw()
1805 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_4_init_lbpw()
1814 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v9_0_cp_jump_table_num()
H A Dgfx_v6_0.c2525 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()