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Searched refs:RLC_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dr600.c1704 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1836 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
3543 WREG32(RLC_CNTL, 0); in r600_rlc_stop()
3548 WREG32(RLC_CNTL, RLC_ENABLE); in r600_rlc_start()
H A Dcikd.h1393 #define RLC_CNTL 0xC300 macro
H A Devergreend.h384 #define RLC_CNTL 0x3f00 macro
H A Dr600d.h685 #define RLC_CNTL 0x3f00 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_1.c1857 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v12_1_xcc_rlc_stop()
1920 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v12_1_xcc_rlc_start()
3296 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v12_1_is_rlc_enabled()
H A Dgfx_v12_0.c1955 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v12_0_rlc_stop()
1996 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v12_0_rlc_start()
4026 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v12_0_is_rlc_enabled()
H A Dgfx_v9_4_3.c1458 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_stop()
1494 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, in gfx_v9_4_3_xcc_rlc_start()
H A Dgfx_v11_0.c2323 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v11_0_rlc_stop()
2364 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
5440 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v11_0_is_rlc_enabled()
H A Dgfx_v8_0.c4056 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4073 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v8_0_rlc_start()
H A Dgfx_v9_0.c3126 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v9_0_rlc_stop()
3145 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v9_0_rlc_start()
H A Dgfx_v10_0.c5483 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v10_0_rlc_stop()
5526 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v10_0_rlc_start()
7876 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; in gfx_v10_0_is_rlc_enabled()