1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd. 4 * 5 * Copyright (c) 2013 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 * 8 * With some ideas taken from pinctrl-samsung: 9 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 10 * http://www.samsung.com 11 * Copyright (c) 2012 Linaro Ltd 12 * https://www.linaro.org 13 * 14 * and pinctrl-at91: 15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 16 */ 17 18 #ifndef _PINCTRL_ROCKCHIP_H 19 #define _PINCTRL_ROCKCHIP_H 20 21 #define RK_GPIO0_A0 0 22 #define RK_GPIO0_A1 1 23 #define RK_GPIO0_A2 2 24 #define RK_GPIO0_A3 3 25 #define RK_GPIO0_A4 4 26 #define RK_GPIO0_A5 5 27 #define RK_GPIO0_A6 6 28 #define RK_GPIO0_A7 7 29 #define RK_GPIO0_B0 8 30 #define RK_GPIO0_B1 9 31 #define RK_GPIO0_B2 10 32 #define RK_GPIO0_B3 11 33 #define RK_GPIO0_B4 12 34 #define RK_GPIO0_B5 13 35 #define RK_GPIO0_B6 14 36 #define RK_GPIO0_B7 15 37 #define RK_GPIO0_C0 16 38 #define RK_GPIO0_C1 17 39 #define RK_GPIO0_C2 18 40 #define RK_GPIO0_C3 19 41 #define RK_GPIO0_C4 20 42 #define RK_GPIO0_C5 21 43 #define RK_GPIO0_C6 22 44 #define RK_GPIO0_C7 23 45 #define RK_GPIO0_D0 24 46 #define RK_GPIO0_D1 25 47 #define RK_GPIO0_D2 26 48 #define RK_GPIO0_D3 27 49 #define RK_GPIO0_D4 28 50 #define RK_GPIO0_D5 29 51 #define RK_GPIO0_D6 30 52 #define RK_GPIO0_D7 31 53 54 #define RK_GPIO1_A0 32 55 #define RK_GPIO1_A1 33 56 #define RK_GPIO1_A2 34 57 #define RK_GPIO1_A3 35 58 #define RK_GPIO1_A4 36 59 #define RK_GPIO1_A5 37 60 #define RK_GPIO1_A6 38 61 #define RK_GPIO1_A7 39 62 #define RK_GPIO1_B0 40 63 #define RK_GPIO1_B1 41 64 #define RK_GPIO1_B2 42 65 #define RK_GPIO1_B3 43 66 #define RK_GPIO1_B4 44 67 #define RK_GPIO1_B5 45 68 #define RK_GPIO1_B6 46 69 #define RK_GPIO1_B7 47 70 #define RK_GPIO1_C0 48 71 #define RK_GPIO1_C1 49 72 #define RK_GPIO1_C2 50 73 #define RK_GPIO1_C3 51 74 #define RK_GPIO1_C4 52 75 #define RK_GPIO1_C5 53 76 #define RK_GPIO1_C6 54 77 #define RK_GPIO1_C7 55 78 #define RK_GPIO1_D0 56 79 #define RK_GPIO1_D1 57 80 #define RK_GPIO1_D2 58 81 #define RK_GPIO1_D3 59 82 #define RK_GPIO1_D4 60 83 #define RK_GPIO1_D5 61 84 #define RK_GPIO1_D6 62 85 #define RK_GPIO1_D7 63 86 87 #define RK_GPIO2_A0 64 88 #define RK_GPIO2_A1 65 89 #define RK_GPIO2_A2 66 90 #define RK_GPIO2_A3 67 91 #define RK_GPIO2_A4 68 92 #define RK_GPIO2_A5 69 93 #define RK_GPIO2_A6 70 94 #define RK_GPIO2_A7 71 95 #define RK_GPIO2_B0 72 96 #define RK_GPIO2_B1 73 97 #define RK_GPIO2_B2 74 98 #define RK_GPIO2_B3 75 99 #define RK_GPIO2_B4 76 100 #define RK_GPIO2_B5 77 101 #define RK_GPIO2_B6 78 102 #define RK_GPIO2_B7 79 103 #define RK_GPIO2_C0 80 104 #define RK_GPIO2_C1 81 105 #define RK_GPIO2_C2 82 106 #define RK_GPIO2_C3 83 107 #define RK_GPIO2_C4 84 108 #define RK_GPIO2_C5 85 109 #define RK_GPIO2_C6 86 110 #define RK_GPIO2_C7 87 111 #define RK_GPIO2_D0 88 112 #define RK_GPIO2_D1 89 113 #define RK_GPIO2_D2 90 114 #define RK_GPIO2_D3 91 115 #define RK_GPIO2_D4 92 116 #define RK_GPIO2_D5 93 117 #define RK_GPIO2_D6 94 118 #define RK_GPIO2_D7 95 119 120 #define RK_GPIO3_A0 96 121 #define RK_GPIO3_A1 97 122 #define RK_GPIO3_A2 98 123 #define RK_GPIO3_A3 99 124 #define RK_GPIO3_A4 100 125 #define RK_GPIO3_A5 101 126 #define RK_GPIO3_A6 102 127 #define RK_GPIO3_A7 103 128 #define RK_GPIO3_B0 104 129 #define RK_GPIO3_B1 105 130 #define RK_GPIO3_B2 106 131 #define RK_GPIO3_B3 107 132 #define RK_GPIO3_B4 108 133 #define RK_GPIO3_B5 109 134 #define RK_GPIO3_B6 110 135 #define RK_GPIO3_B7 111 136 #define RK_GPIO3_C0 112 137 #define RK_GPIO3_C1 113 138 #define RK_GPIO3_C2 114 139 #define RK_GPIO3_C3 115 140 #define RK_GPIO3_C4 116 141 #define RK_GPIO3_C5 117 142 #define RK_GPIO3_C6 118 143 #define RK_GPIO3_C7 119 144 #define RK_GPIO3_D0 120 145 #define RK_GPIO3_D1 121 146 #define RK_GPIO3_D2 122 147 #define RK_GPIO3_D3 123 148 #define RK_GPIO3_D4 124 149 #define RK_GPIO3_D5 125 150 #define RK_GPIO3_D6 126 151 #define RK_GPIO3_D7 127 152 153 #define RK_GPIO4_A0 128 154 #define RK_GPIO4_A1 129 155 #define RK_GPIO4_A2 130 156 #define RK_GPIO4_A3 131 157 #define RK_GPIO4_A4 132 158 #define RK_GPIO4_A5 133 159 #define RK_GPIO4_A6 134 160 #define RK_GPIO4_A7 135 161 #define RK_GPIO4_B0 136 162 #define RK_GPIO4_B1 137 163 #define RK_GPIO4_B2 138 164 #define RK_GPIO4_B3 139 165 #define RK_GPIO4_B4 140 166 #define RK_GPIO4_B5 141 167 #define RK_GPIO4_B6 142 168 #define RK_GPIO4_B7 143 169 #define RK_GPIO4_C0 144 170 #define RK_GPIO4_C1 145 171 #define RK_GPIO4_C2 146 172 #define RK_GPIO4_C3 147 173 #define RK_GPIO4_C4 148 174 #define RK_GPIO4_C5 149 175 #define RK_GPIO4_C6 150 176 #define RK_GPIO4_C7 151 177 #define RK_GPIO4_D0 152 178 #define RK_GPIO4_D1 153 179 #define RK_GPIO4_D2 154 180 #define RK_GPIO4_D3 155 181 #define RK_GPIO4_D4 156 182 #define RK_GPIO4_D5 157 183 #define RK_GPIO4_D6 158 184 #define RK_GPIO4_D7 159 185 186 enum rockchip_pinctrl_type { 187 PX30, 188 RV1103B, 189 RV1106, 190 RV1108, 191 RV1126, 192 RK2928, 193 RK3066B, 194 RK3128, 195 RK3188, 196 RK3288, 197 RK3308, 198 RK3308B, 199 RK3328, 200 RK3368, 201 RK3399, 202 RK3506, 203 RK3528, 204 RK3562, 205 RK3568, 206 RK3576, 207 RK3588, 208 }; 209 210 /** 211 * struct rockchip_gpio_regs 212 * @port_dr: data register 213 * @port_ddr: data direction register 214 * @int_en: interrupt enable 215 * @int_mask: interrupt mask 216 * @int_type: interrupt trigger type, such as high, low, edge trriger type. 217 * @int_polarity: interrupt polarity enable register 218 * @int_bothedge: interrupt bothedge enable register 219 * @int_status: interrupt status register 220 * @int_rawstatus: int_status = int_rawstatus & int_mask 221 * @debounce: enable debounce for interrupt signal 222 * @dbclk_div_en: enable divider for debounce clock 223 * @dbclk_div_con: setting for divider of debounce clock 224 * @port_eoi: end of interrupt of the port 225 * @ext_port: port data from external 226 * @version_id: controller version register 227 */ 228 struct rockchip_gpio_regs { 229 u32 port_dr; 230 u32 port_ddr; 231 u32 int_en; 232 u32 int_mask; 233 u32 int_type; 234 u32 int_polarity; 235 u32 int_bothedge; 236 u32 int_status; 237 u32 int_rawstatus; 238 u32 debounce; 239 u32 dbclk_div_en; 240 u32 dbclk_div_con; 241 u32 port_eoi; 242 u32 ext_port; 243 u32 version_id; 244 }; 245 246 /** 247 * struct rockchip_iomux 248 * @type: iomux variant using IOMUX_* constants 249 * @offset: if initialized to -1 it will be autocalculated, by specifying 250 * an initial offset value the relevant source offset can be reset 251 * to a new value for autocalculating the following iomux registers. 252 */ 253 struct rockchip_iomux { 254 int type; 255 int offset; 256 }; 257 258 /* 259 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 260 */ 261 enum rockchip_pin_drv_type { 262 DRV_TYPE_IO_DEFAULT = 0, 263 DRV_TYPE_IO_1V8_OR_3V0, 264 DRV_TYPE_IO_1V8_ONLY, 265 DRV_TYPE_IO_1V8_3V0_AUTO, 266 DRV_TYPE_IO_3V3_ONLY, 267 DRV_TYPE_IO_LEVEL_2_BIT, 268 DRV_TYPE_IO_LEVEL_8_BIT, 269 DRV_TYPE_MAX 270 }; 271 272 /* 273 * enum type index corresponding to rockchip_pull_list arrays index. 274 */ 275 enum rockchip_pin_pull_type { 276 PULL_TYPE_IO_DEFAULT = 0, 277 PULL_TYPE_IO_1V8_ONLY, 278 PULL_TYPE_MAX 279 }; 280 281 /** 282 * struct rockchip_drv 283 * @drv_type: drive strength variant using rockchip_perpin_drv_type 284 * @offset: if initialized to -1 it will be autocalculated, by specifying 285 * an initial offset value the relevant source offset can be reset 286 * to a new value for autocalculating the following drive strength 287 * registers. if used chips own cal_drv func instead to calculate 288 * registers offset, the variant could be ignored. 289 */ 290 struct rockchip_drv { 291 enum rockchip_pin_drv_type drv_type; 292 int offset; 293 }; 294 295 /** 296 * struct rockchip_pin_bank 297 * @dev: the pinctrl device bind to the bank 298 * @reg_base: register base of the gpio bank 299 * @regmap_pull: optional separate register for additional pull settings 300 * @regmap_ioc: optional per-bank IO control regmap, for SoCs where each 301 * bank has its own IOC block 302 * @clk: clock of the gpio bank 303 * @db_clk: clock of the gpio debounce 304 * @irq: interrupt of the gpio bank 305 * @saved_masks: Saved content of GPIO_INTEN at suspend time. 306 * @pin_base: first pin number 307 * @nr_pins: number of pins in this bank 308 * @name: name of the bank 309 * @bank_num: number of the bank, to account for holes 310 * @iomux: array describing the 4 iomux sources of the bank 311 * @drv: array describing the 4 drive strength sources of the bank 312 * @pull_type: array describing the 4 pull type sources of the bank 313 * @valid: is all necessary information present 314 * @of_node: dt node of this bank 315 * @drvdata: common pinctrl basedata 316 * @domain: irqdomain of the gpio bank 317 * @gpio_chip: gpiolib chip 318 * @grange: gpio range 319 * @slock: spinlock for the gpio bank 320 * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode 321 * @recalced_mask: bit mask to indicate a need to recalulate the mask 322 * @route_mask: bits describing the routing pins of per bank 323 * @deferred_output: gpio output settings to be done after gpio bank probed 324 * @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl 325 */ 326 struct rockchip_pin_bank { 327 struct device *dev; 328 void __iomem *reg_base; 329 struct regmap *regmap_pull; 330 struct regmap *regmap_ioc; 331 struct clk *clk; 332 struct clk *db_clk; 333 int irq; 334 u32 saved_masks; 335 u32 pin_base; 336 u8 nr_pins; 337 char *name; 338 u8 bank_num; 339 struct rockchip_iomux iomux[4]; 340 struct rockchip_drv drv[4]; 341 enum rockchip_pin_pull_type pull_type[4]; 342 bool valid; 343 struct device_node *of_node; 344 struct rockchip_pinctrl *drvdata; 345 struct irq_domain *domain; 346 struct gpio_chip gpio_chip; 347 struct pinctrl_gpio_range grange; 348 raw_spinlock_t slock; 349 const struct rockchip_gpio_regs *gpio_regs; 350 u32 gpio_type; 351 u32 toggle_edge_mode; 352 u32 recalced_mask; 353 u32 route_mask; 354 struct list_head deferred_pins; 355 struct mutex deferred_lock; 356 }; 357 358 /** 359 * struct rockchip_mux_recalced_data: represent a pin iomux data. 360 * @num: bank number. 361 * @pin: pin number. 362 * @bit: index at register. 363 * @reg: register offset. 364 * @mask: mask bit 365 */ 366 struct rockchip_mux_recalced_data { 367 u8 num; 368 u8 pin; 369 u32 reg; 370 u8 bit; 371 u8 mask; 372 }; 373 374 enum rockchip_mux_route_location { 375 ROCKCHIP_ROUTE_SAME = 0, 376 ROCKCHIP_ROUTE_PMU, 377 ROCKCHIP_ROUTE_GRF, 378 }; 379 380 /** 381 * struct rockchip_mux_recalced_data: represent a pin iomux data. 382 * @bank_num: bank number. 383 * @pin: index at register or used to calc index. 384 * @func: the min pin. 385 * @route_location: the mux route location (same, pmu, grf). 386 * @route_offset: the max pin. 387 * @route_val: the register offset. 388 */ 389 struct rockchip_mux_route_data { 390 u8 bank_num; 391 u8 pin; 392 u8 func; 393 enum rockchip_mux_route_location route_location; 394 u32 route_offset; 395 u32 route_val; 396 }; 397 398 struct rockchip_pin_ctrl { 399 struct rockchip_pin_bank *pin_banks; 400 u32 nr_banks; 401 u32 nr_pins; 402 char *label; 403 enum rockchip_pinctrl_type type; 404 int grf_mux_offset; 405 int pmu_mux_offset; 406 int grf_drv_offset; 407 int pmu_drv_offset; 408 const struct rockchip_mux_recalced_data *iomux_recalced; 409 u32 niomux_recalced; 410 const struct rockchip_mux_route_data *iomux_routes; 411 u32 niomux_routes; 412 413 int (*pull_calc_reg)(struct rockchip_pin_bank *bank, 414 int pin_num, struct regmap **regmap, 415 int *reg, u8 *bit); 416 int (*drv_calc_reg)(struct rockchip_pin_bank *bank, 417 int pin_num, struct regmap **regmap, 418 int *reg, u8 *bit); 419 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 420 int pin_num, struct regmap **regmap, 421 int *reg, u8 *bit); 422 }; 423 424 struct rockchip_pin_config { 425 unsigned int func; 426 unsigned long *configs; 427 unsigned int nconfigs; 428 }; 429 430 enum pin_config_param; 431 432 struct rockchip_pin_deferred { 433 struct list_head head; 434 unsigned int pin; 435 enum pin_config_param param; 436 u32 arg; 437 }; 438 439 /** 440 * struct rockchip_pin_group: represent group of pins of a pinmux function. 441 * @name: name of the pin group, used to lookup the group. 442 * @pins: the pins included in this group. 443 * @npins: number of pins included in this group. 444 * @data: local pin configuration 445 */ 446 struct rockchip_pin_group { 447 const char *name; 448 unsigned int npins; 449 unsigned int *pins; 450 struct rockchip_pin_config *data; 451 }; 452 453 /** 454 * struct rockchip_pmx_func: represent a pin function. 455 * @name: name of the pin function, used to lookup the function. 456 * @groups: one or more names of pin groups that provide this function. 457 * @ngroups: number of groups included in @groups. 458 */ 459 struct rockchip_pmx_func { 460 const char *name; 461 const char **groups; 462 u8 ngroups; 463 }; 464 465 struct rockchip_pinctrl { 466 struct regmap *regmap_base; 467 int reg_size; 468 struct regmap *regmap_pull; 469 struct regmap *regmap_pmu; 470 struct regmap *regmap_ioc1; 471 struct device *dev; 472 struct rockchip_pin_ctrl *ctrl; 473 struct pinctrl_desc pctl; 474 struct pinctrl_dev *pctl_dev; 475 struct rockchip_pin_group *groups; 476 unsigned int ngroups; 477 struct rockchip_pmx_func *functions; 478 unsigned int nfunctions; 479 }; 480 481 #endif 482