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Searched refs:RING_HWS_PGA (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_execlist.c82 xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base), in __start_lrc()
84 xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base)); in __start_lrc()
H A Dxe_hw_engine.c334 xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0), in xe_hw_engine_enable_ring()
H A Dxe_guc_ads.c732 { .reg = RING_HWS_PGA(hwe->mmio_base), }, in guc_mmio_regset_write()
H A Dxe_guc_capture.c112 { RING_HWS_PGA(0), REG_32BIT, 0, 0, "RING_HWS_PGA"}, \
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h73 #define RING_HWS_PGA(base) XE_REG((base) + 0x80) macro
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c392 ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false); in guc_mmio_regset_init()
H A Dintel_guc_capture.c73 { RING_HWS_PGA(0), 0, 0, "HWS" }, \
H A Dintel_guc_submission.c4403 RING_HWS_PGA, in setup_hwsp()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ring_submission.c110 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
H A Dintel_execlists_submission.c2939 RING_HWS_PGA, in enable_execlists()
2941 ENGINE_POSTING_READ(engine, RING_HWS_PGA); in enable_execlists()
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c823 MMIO_RING_D(RING_HWS_PGA); in iterate_bdw_plus_mmio()
H A Di915_gpu_error.c1319 mmio = RING_HWS_PGA(engine->mmio_base); in engine_record_registers()
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c2556 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); in init_bdw_mmio_info()