| /linux/drivers/reset/ |
| H A D | reset-rzg2l-usbphy-ctrl.c | 17 #define RESET 0x000 macro
54 val = readl(base + RESET); in rzg2l_usbphy_ctrl_assert()
58 writel(val, base + RESET); in rzg2l_usbphy_ctrl_assert()
73 val = readl(base + RESET); in rzg2l_usbphy_ctrl_deassert()
77 writel(val, base + RESET); in rzg2l_usbphy_ctrl_deassert()
91 return !!(readl(priv->base + RESET) & port_mask); in rzg2l_usbphy_ctrl_status()
156 val = readl(priv->base + RESET); in rzg2l_usbphy_ctrl_probe()
158 writel(val, priv->base + RESET); in rzg2l_usbphy_ctrl_probe()
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| /linux/arch/mips/cobalt/ |
| H A D | reset.c | 21 #define RESET 0x0f macro
48 writeb(RESET, RESET_PORT); in cobalt_machine_restart()
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| /linux/drivers/misc/altera-stapl/ |
| H A D | altera-jtag.c | 35 /* RESET */ { RESET, IDLE },
44 /* IRSELECT */ { RESET, IRCAPTURE },
307 } else if (state == RESET) in altera_goto_jstate()
354 tms = (wait_state == RESET) ? TMS_HIGH : TMS_LOW; in altera_wait_cycles()
598 case RESET: in altera_irscan()
697 case RESET: in altera_swap_ir()
801 case RESET: in altera_drscan()
892 case RESET: in altera_swap_dr()
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| H A D | altera-jtag.h | 18 RESET = 0, enumerator
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| /linux/arch/arm/boot/dts/intel/pxa/ |
| H A D | pxa300-raumfeld-tuneable-clock.dtsi | 74 MFP_PIN_PXA300(120) MFP_AF0 /* RESET */
81 MFP_PIN_PXA300(111) MFP_AF0 /* RESET */
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| /linux/drivers/media/i2c/ |
| H A D | ov2640.c | 126 #define RESET 0xE0 /* Reset */ macro
382 { RESET, RESET_JPEG | RESET_DVP },
500 { RESET, RESET_DVP },
525 { RESET, 0x00}
601 { RESET, 0x00 },
611 { RESET, 0x00 },
619 { RESET, 0x00 },
627 { RESET, 0x00 },
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| H A D | mt9m111.c | 430 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_enable()
438 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_reset()
440 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC); in mt9m111_reset()
442 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE in mt9m111_reset()
917 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE); in mt9m111_suspend()
919 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC | in mt9m111_suspend()
923 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE); in mt9m111_suspend()
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| /linux/drivers/iio/chemical/ |
| H A D | sps30.c | 35 RESET, enumerator
72 if (state->state == RESET) { in sps30_do_meas()
98 state->state = RESET; in sps30_do_reset()
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| /linux/drivers/input/keyboard/ |
| H A D | qt1070.c | 39 #define RESET 0x39 macro
185 qt1070_write(client, RESET, 1); in qt1070_probe()
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| /linux/sound/isa/sb/ |
| H A D | sb_common.c | 66 outb(1, SBP(chip, RESET)); in snd_sbdsp_reset()
68 outb(0, SBP(chip, RESET)); in snd_sbdsp_reset()
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6ull-dhcor-maveo-box.dts | 77 "BUTTON-RESET", "", "", "",
123 "PSOC-SWD-IO", "PSOC-SWD-CLK", "PSOC-RESET", "ZIGBEE-PROG",
124 "ZIGBEE-RESET", "", "PSOC-PWR-FAIL-OUT", "NFC-ENABLE",
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| /linux/drivers/media/dvb-frontends/ |
| H A D | zl10353_priv.h | 45 RESET = 0x55, enumerator
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| H A D | mt352_priv.h | 66 RESET = 0x50, enumerator
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| H A D | mt312_priv.h | 35 RESET = 21, enumerator
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| H A D | bcm3510_priv.h | 40 u8 RESET :1; member
62 u8 RESET :1; member
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | pcm1789.txt | 13 - reset-gpios: GPIO to control the RESET pin
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| /linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am65-iot2050-common-pg2.dtsi | 29 "", "", "", "", "CP2102N-RESET";
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| /linux/drivers/gpu/drm/hisilicon/kirin/ |
| H A D | dw_dsi_reg.h | 18 #define RESET 0 macro
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| /linux/drivers/net/wireless/ath/ath9k/ |
| H A D | link.c | 49 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, in ath_tx_complete_check()
83 ath_dbg(common, RESET, in ath_hw_check()
105 ath_dbg(common, RESET, "PLL WAR, resetting the chip\n"); in ath_hw_pll_rx_hang_check()
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| H A D | ar9003_phy.c | 2054 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); in ar9003_hw_bb_watchdog_config()
2090 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", in ar9003_hw_bb_watchdog_config()
2119 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2121 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2133 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2136 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2141 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2145 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); in ar9003_hw_bb_watchdog_dbg_info()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv740d.h | 56 #define RESET (1 << 30) macro
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7981b-cudy-wr3000-v1.dts | 29 label = "RESET";
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| /linux/Documentation/devicetree/bindings/net/ieee802154/ |
| H A D | cc2520.txt | 15 - reset-gpio: GPIO spec for the RESET pin
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | repaper.txt | 11 - reset-gpios: RESET pin
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| /linux/drivers/firmware/arm_scmi/ |
| H A D | reset.c | 21 RESET = 0x4, enumerator
191 ret = ph->xops->xfer_get_init(ph, RESET, sizeof(*dom), 0, &t); in scmi_domain_reset()
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