Searched refs:REG_STRUCT (Results 1 – 10 of 10) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| H A D | irq_service_dcn351.c | 160 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
161 REG_STRUCT[base + reg_num].enable_mask = \
163 REG_STRUCT[base + reg_num].enable_value[0] = \
165 REG_STRUCT[base + reg_num].enable_value[1] = \
167 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
168 REG_STRUCT[base + reg_num].ack_mask = \
170 REG_STRUCT[base + reg_num].ack_value = \
174 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
175 REG_STRUCT[base].enable_mask = \
177 REG_STRUCT[base].enable_value[0] = \
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/ |
| H A D | irq_service_dcn36.c | 159 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
160 REG_STRUCT[base + reg_num].enable_mask = \
162 REG_STRUCT[base + reg_num].enable_value[0] = \
164 REG_STRUCT[base + reg_num].enable_value[1] = \
166 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
167 REG_STRUCT[base + reg_num].ack_mask = \
169 REG_STRUCT[base + reg_num].ack_value = \
173 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
174 REG_STRUCT[base].enable_mask = \
176 REG_STRUCT[base].enable_value[0] = \
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| H A D | irq_service_dcn35.c | 181 REG_STRUCT[base + reg_num].enable_reg = SRI(reg1, block, reg_num),\
182 REG_STRUCT[base + reg_num].enable_mask = \
184 REG_STRUCT[base + reg_num].enable_value[0] = \
186 REG_STRUCT[base + reg_num].enable_value[1] = \
188 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
189 REG_STRUCT[base + reg_num].ack_mask = \
191 REG_STRUCT[base + reg_num].ack_value = \
195 REG_STRUCT[base].enable_reg = SRI_DMUB(reg1),\
196 REG_STRUCT[base].enable_mask = \
198 REG_STRUCT[base].enable_value[0] = \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 117 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
124 REG_STRUCT[id].reg_name = value
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
158 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 132 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
139 REG_STRUCT[id].reg_name = value
142 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
146 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
153 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
173 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 112 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
119 REG_STRUCT[id].reg_name = value
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
126 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
133 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
153 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
124 REG_STRUCT[id].reg_name = value
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
157 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 100 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
103 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
106 REG_STRUCT[id].reg_name = value
109 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
120 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
123 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
126 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
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| /linux/drivers/gpu/drm/amd/display/dmub/src/ |
| H A D | dmub_dcn351.c | 19 #define REG_STRUCT regs in dmub_srv_dcn351_regs_init() macro
21 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); in dmub_srv_dcn351_regs_init()
26 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); in dmub_srv_dcn351_regs_init()
30 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); in dmub_srv_dcn351_regs_init()
33 #undef REG_STRUCT in dmub_srv_dcn351_regs_init()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
121 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
124 REG_STRUCT[id].reg_name = value
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
157 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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