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Searched refs:REG_GET_FIELD (Results 1 – 25 of 47) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v8_7.c64 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_ecc_info_query_correctable_error_count()
65 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_7_ecc_info_query_correctable_error_count()
81 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
82 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
84 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
85 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
86 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
149 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_ecc_info_query_error_address()
150 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) { in umc_v8_7_ecc_info_query_error_address()
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H A Dumc_v6_7.c66 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) in umc_v6_7_query_error_status_helper()
110 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_7_ecc_info_query_correctable_error_count()
111 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) { in umc_v6_7_ecc_info_query_correctable_error_count()
122 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v6_7_ecc_info_query_correctable_error_count()
151 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
152 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
153 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
154 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
155 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
156 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) { in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
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H A Dumc_v8_10.c118 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_10_query_correctable_error_count()
119 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_10_query_correctable_error_count()
134 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_10_query_uncorrectable_error_count()
135 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v8_10_query_uncorrectable_error_count()
136 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
137 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
138 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
139 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_10_query_uncorrectable_error_count()
222 addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb); in umc_v8_10_convert_error_address()
269 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_10_query_error_address()
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H A Dgfxhub_v1_1.c54 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
58 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
61 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
65 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
96 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, in gfxhub_v1_1_get_xgmi_info()
100 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, in gfxhub_v1_1_get_xgmi_info()
H A Ddf_v4_3.c39 v0 = REG_GET_FIELD(hw_assert_msklo, in df_v4_3_query_ras_poison_mode()
41 v1 = REG_GET_FIELD(hw_assert_msklo, in df_v4_3_query_ras_poison_mode()
43 v28 = REG_GET_FIELD(hw_assert_mskhi, in df_v4_3_query_ras_poison_mode()
45 v31 = REG_GET_FIELD(hw_assert_mskhi, in df_v4_3_query_ras_poison_mode()
H A Dgfx_v11_0_3.c53 if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) || in gfx_v11_0_3_rlc_gc_fed_irq()
54 REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR)) in gfx_v11_0_3_rlc_gc_fed_irq()
93 if (REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA0_FED_ERR) || in gfx_v11_0_3_poison_consumption_handler()
94 REG_GET_FIELD(rlc_status0, RLC_RLCS_FED_STATUS_0, SDMA1_FED_ERR)) { in gfx_v11_0_3_poison_consumption_handler()
H A Dsmuio_v13_0.c86 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_get_die_id()
103 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_get_socket_id()
120 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_is_host_gpu_xgmi_supported()
137 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_get_pkg_type()
H A Dsmuio_v13_0_3.c43 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_3_get_die_id()
60 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_3_get_socket_id()
79 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE); in smuio_v13_0_3_get_pkg_type()
H A Dgfxhub_v2_0.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
H A Dnbio_v7_9.c54 rev_id = REG_GET_FIELD(rev_id, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, in nbio_v7_9_get_rev_id()
400 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, in nbio_v7_9_get_compute_partition_mode()
411 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, in nbio_v7_9_is_nps_switch_requested()
423 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); in nbio_v7_9_get_memory_partition_mode()
530 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_9_handle_ras_controller_intr_no_bifring()
576 if (REG_GET_FIELD(bif_doorbell_intr_cntl, in nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring()
H A Diceland_ih.c203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
353 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
368 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
H A Dcz_ih.c203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
359 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
374 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
H A Dumc_v8_14.c73 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccErrCnt) - in umc_v8_14_query_correctable_error_count()
88 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccUnCorrErrCnt) - in umc_v8_14_query_uncorrectable_error_count()
H A Dmmhub_v2_0.c146 cid = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
148 rw = REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
158 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
161 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
164 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
167 REG_GET_FIELD(status, in mmhub_v2_0_print_l2_protection_fault_status()
H A Dmmhub_v2_3.c85 cid = REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
87 rw = REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
97 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
100 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
103 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
106 REG_GET_FIELD(status, in mmhub_v2_3_print_l2_protection_fault_status()
H A Damdgpu_amdkfd_gfx_v7.c398 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
402 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
403 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
410 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
561 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
H A Dgfxhub_v2_1.c82 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
104 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
H A Damdgpu_amdkfd_gfx_v8.c433 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
437 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
438 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
445 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
H A Dgfxhub_v12_1.c724 u32 cid = REG_GET_FIELD(status, in gfxhub_v12_1_print_l2_protection_fault_status()
735 REG_GET_FIELD(status, in gfxhub_v12_1_print_l2_protection_fault_status()
738 REG_GET_FIELD(status, in gfxhub_v12_1_print_l2_protection_fault_status()
741 REG_GET_FIELD(status, in gfxhub_v12_1_print_l2_protection_fault_status()
744 REG_GET_FIELD(status, in gfxhub_v12_1_print_l2_protection_fault_status()
747 REG_GET_FIELD(status, in gfxhub_v12_1_print_l2_protection_fault_status()
H A Damdgpu_amdkfd_gfx_v10.c254 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
563 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
567 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
568 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
575 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
842 *trap_mask_prev = REG_GET_FIELD(data, SPI_GDBG_TRAP_MASK, EXCP_EN); in kgd_gfx_v10_set_wave_launch_trap_override()
H A Damdgpu_amdkfd_gfx_v12.c264 uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN); in trap_mask_map_hw_to_sw()
266 if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START)) in trap_mask_map_hw_to_sw()
269 if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END)) in trap_mask_map_hw_to_sw()
H A Damdgpu_amdkfd_gfx_v12_1.c267 uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN); in trap_mask_map_hw_to_sw()
269 if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START)) in trap_mask_map_hw_to_sw()
272 if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END)) in trap_mask_map_hw_to_sw()
H A Dgfx_v11_0.c2042 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, in gfx_v11_0_get_sa_active_bitmap()
2046 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, in gfx_v11_0_get_sa_active_bitmap()
2061 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, in gfx_v11_0_get_rb_active_bitmap()
2065 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, in gfx_v11_0_get_rb_active_bitmap()
2182 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
2183 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); in gfx_v11_0_get_tcc_info()
2202 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); in gfx_v11_0_constants_init()
2573 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, in gfx_v11_0_config_me_cache()
2617 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, in gfx_v11_0_config_pfp_cache()
2662 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, in gfx_v11_0_config_mec_cache()
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H A Dgfx_v8_0.c1792 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1794 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg, in gfx_v8_0_gpu_early_init()
1802 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1803 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1806 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); in gfx_v8_0_gpu_early_init()
1807 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); in gfx_v8_0_gpu_early_init()
1826 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); in gfx_v8_0_gpu_early_init()
3437 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); in gfx_v8_0_get_rb_active_bitmap()
4823 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE) in gfx_v8_0_is_idle()
5468 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) in gfx_v8_0_set_safe_mode()
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H A Dgfx_v12_0.c1717 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, in gfx_v12_0_get_sa_active_bitmap()
1721 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, in gfx_v12_0_get_sa_active_bitmap()
1736 gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, in gfx_v12_0_get_rb_active_bitmap()
1740 gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, in gfx_v12_0_get_rb_active_bitmap()
1840 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE); in gfx_v12_0_constants_init()
2342 (REG_GET_FIELD(bootload_status, in gfx_v12_0_wait_for_rlc_autoload_complete()
2461 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2479 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2514 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, in gfx_v12_0_cp_gfx_load_pfp_microcode_rs64()
2605 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, in gfx_v12_0_cp_gfx_load_me_microcode_rs64()
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