1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * APM X-Gene SoC RNG Driver
4 *
5 * Copyright (c) 2014, Applied Micro Circuits Corporation
6 * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
7 * Shamal Winchurkar <swinchurkar@apm.com>
8 * Feng Kan <fkan@apm.com>
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/hw_random.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/timer.h>
21
22 #define RNG_MAX_DATUM 4
23 #define MAX_TRY 100
24 #define XGENE_RNG_RETRY_COUNT 20
25 #define XGENE_RNG_RETRY_INTERVAL 10
26
27 /* RNG Registers */
28 #define RNG_INOUT_0 0x00
29 #define RNG_INTR_STS_ACK 0x10
30 #define RNG_CONTROL 0x14
31 #define RNG_CONFIG 0x18
32 #define RNG_ALARMCNT 0x1c
33 #define RNG_FROENABLE 0x20
34 #define RNG_FRODETUNE 0x24
35 #define RNG_ALARMMASK 0x28
36 #define RNG_ALARMSTOP 0x2c
37 #define RNG_OPTIONS 0x78
38 #define RNG_EIP_REV 0x7c
39
40 #define MONOBIT_FAIL_MASK BIT(7)
41 #define POKER_FAIL_MASK BIT(6)
42 #define LONG_RUN_FAIL_MASK BIT(5)
43 #define RUN_FAIL_MASK BIT(4)
44 #define NOISE_FAIL_MASK BIT(3)
45 #define STUCK_OUT_MASK BIT(2)
46 #define SHUTDOWN_OFLO_MASK BIT(1)
47 #define READY_MASK BIT(0)
48
49 #define MAJOR_HW_REV_RD(src) (((src) & 0x0f000000) >> 24)
50 #define MINOR_HW_REV_RD(src) (((src) & 0x00f00000) >> 20)
51 #define HW_PATCH_LEVEL_RD(src) (((src) & 0x000f0000) >> 16)
52 #define MAX_REFILL_CYCLES_SET(dst, src) \
53 ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
54 #define MIN_REFILL_CYCLES_SET(dst, src) \
55 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
56 #define ALARM_THRESHOLD_SET(dst, src) \
57 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
58 #define ENABLE_RNG_SET(dst, src) \
59 ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
60 #define REGSPEC_TEST_MODE_SET(dst, src) \
61 ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
62 #define MONOBIT_FAIL_MASK_SET(dst, src) \
63 ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
64 #define POKER_FAIL_MASK_SET(dst, src) \
65 ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
66 #define LONG_RUN_FAIL_MASK_SET(dst, src) \
67 ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
68 #define RUN_FAIL_MASK_SET(dst, src) \
69 ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
70 #define NOISE_FAIL_MASK_SET(dst, src) \
71 ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
72 #define STUCK_OUT_MASK_SET(dst, src) \
73 ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
74 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
75 ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
76
77 struct xgene_rng_dev {
78 u32 irq;
79 void __iomem *csr_base;
80 u32 revision;
81 u32 datum_size;
82 u32 failure_cnt; /* Failure count last minute */
83 unsigned long failure_ts;/* First failure timestamp */
84 struct timer_list failure_timer;
85 struct device *dev;
86 };
87
xgene_rng_expired_timer(struct timer_list * t)88 static void xgene_rng_expired_timer(struct timer_list *t)
89 {
90 struct xgene_rng_dev *ctx = timer_container_of(ctx, t, failure_timer);
91
92 /* Clear failure counter as timer expired */
93 disable_irq(ctx->irq);
94 ctx->failure_cnt = 0;
95 timer_delete(&ctx->failure_timer);
96 enable_irq(ctx->irq);
97 }
98
xgene_rng_start_timer(struct xgene_rng_dev * ctx)99 static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
100 {
101 ctx->failure_timer.expires = jiffies + 120 * HZ;
102 add_timer(&ctx->failure_timer);
103 }
104
105 /*
106 * Initialize or reinit free running oscillators (FROs)
107 */
xgene_rng_init_fro(struct xgene_rng_dev * ctx,u32 fro_val)108 static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
109 {
110 writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
111 writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
112 writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
113 writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
114 }
115
xgene_rng_chk_overflow(struct xgene_rng_dev * ctx)116 static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
117 {
118 u32 val;
119
120 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
121 if (val & MONOBIT_FAIL_MASK)
122 /*
123 * LFSR detected an out-of-bounds number of 1s after
124 * checking 20,000 bits (test T1 as specified in the
125 * AIS-31 standard)
126 */
127 dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
128 if (val & POKER_FAIL_MASK)
129 /*
130 * LFSR detected an out-of-bounds value in at least one
131 * of the 16 poker_count_X counters or an out of bounds sum
132 * of squares value after checking 20,000 bits (test T2 as
133 * specified in the AIS-31 standard)
134 */
135 dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
136 if (val & LONG_RUN_FAIL_MASK)
137 /*
138 * LFSR detected a sequence of 34 identical bits
139 * (test T4 as specified in the AIS-31 standard)
140 */
141 dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
142 if (val & RUN_FAIL_MASK)
143 /*
144 * LFSR detected an outof-bounds value for at least one
145 * of the running counters after checking 20,000 bits
146 * (test T3 as specified in the AIS-31 standard)
147 */
148 dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
149 if (val & NOISE_FAIL_MASK)
150 /* LFSR detected a sequence of 48 identical bits */
151 dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
152 if (val & STUCK_OUT_MASK)
153 /*
154 * Detected output data registers generated same value twice
155 * in a row
156 */
157 dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
158
159 if (val & SHUTDOWN_OFLO_MASK) {
160 u32 frostopped;
161
162 /* FROs shut down after a second error event. Try recover. */
163 if (++ctx->failure_cnt == 1) {
164 /* 1st time, just recover */
165 ctx->failure_ts = jiffies;
166 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
167 xgene_rng_init_fro(ctx, frostopped);
168
169 /*
170 * We must start a timer to clear out this error
171 * in case the system timer wrap around
172 */
173 xgene_rng_start_timer(ctx);
174 } else {
175 /* 2nd time failure in lesser than 1 minute? */
176 if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
177 dev_err(ctx->dev,
178 "FRO shutdown failure error 0x%08X\n",
179 val);
180 } else {
181 /* 2nd time failure after 1 minutes, recover */
182 ctx->failure_ts = jiffies;
183 ctx->failure_cnt = 1;
184 /*
185 * We must start a timer to clear out this
186 * error in case the system timer wrap
187 * around
188 */
189 xgene_rng_start_timer(ctx);
190 }
191 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
192 xgene_rng_init_fro(ctx, frostopped);
193 }
194 }
195 /* Clear them all */
196 writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
197 }
198
xgene_rng_irq_handler(int irq,void * id)199 static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
200 {
201 struct xgene_rng_dev *ctx = id;
202
203 /* RNG Alarm Counter overflow */
204 xgene_rng_chk_overflow(ctx);
205
206 return IRQ_HANDLED;
207 }
208
xgene_rng_data_present(struct hwrng * rng,int wait)209 static int xgene_rng_data_present(struct hwrng *rng, int wait)
210 {
211 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
212 u32 i, val = 0;
213
214 for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
215 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
216 if ((val & READY_MASK) || !wait)
217 break;
218 udelay(XGENE_RNG_RETRY_INTERVAL);
219 }
220
221 return (val & READY_MASK);
222 }
223
xgene_rng_data_read(struct hwrng * rng,u32 * data)224 static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
225 {
226 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
227 int i;
228
229 for (i = 0; i < ctx->datum_size; i++)
230 data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
231
232 /* Clear ready bit to start next transaction */
233 writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
234
235 return ctx->datum_size << 2;
236 }
237
xgene_rng_init_internal(struct xgene_rng_dev * ctx)238 static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
239 {
240 u32 val;
241
242 writel(0x00000000, ctx->csr_base + RNG_CONTROL);
243
244 val = MAX_REFILL_CYCLES_SET(0, 10);
245 val = MIN_REFILL_CYCLES_SET(val, 10);
246 writel(val, ctx->csr_base + RNG_CONFIG);
247
248 val = ALARM_THRESHOLD_SET(0, 0xFF);
249 writel(val, ctx->csr_base + RNG_ALARMCNT);
250
251 xgene_rng_init_fro(ctx, 0);
252
253 writel(MONOBIT_FAIL_MASK |
254 POKER_FAIL_MASK |
255 LONG_RUN_FAIL_MASK |
256 RUN_FAIL_MASK |
257 NOISE_FAIL_MASK |
258 STUCK_OUT_MASK |
259 SHUTDOWN_OFLO_MASK |
260 READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
261
262 val = ENABLE_RNG_SET(0, 1);
263 val = MONOBIT_FAIL_MASK_SET(val, 1);
264 val = POKER_FAIL_MASK_SET(val, 1);
265 val = LONG_RUN_FAIL_MASK_SET(val, 1);
266 val = RUN_FAIL_MASK_SET(val, 1);
267 val = NOISE_FAIL_MASK_SET(val, 1);
268 val = STUCK_OUT_MASK_SET(val, 1);
269 val = SHUTDOWN_OFLO_MASK_SET(val, 1);
270 writel(val, ctx->csr_base + RNG_CONTROL);
271 }
272
xgene_rng_init(struct hwrng * rng)273 static int xgene_rng_init(struct hwrng *rng)
274 {
275 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
276
277 ctx->failure_cnt = 0;
278 timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
279
280 ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
281
282 dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
283 MAJOR_HW_REV_RD(ctx->revision),
284 MINOR_HW_REV_RD(ctx->revision),
285 HW_PATCH_LEVEL_RD(ctx->revision));
286
287 dev_dbg(ctx->dev, "Options 0x%08X",
288 readl(ctx->csr_base + RNG_OPTIONS));
289
290 xgene_rng_init_internal(ctx);
291
292 ctx->datum_size = RNG_MAX_DATUM;
293
294 return 0;
295 }
296
297 #ifdef CONFIG_ACPI
298 static const struct acpi_device_id xgene_rng_acpi_match[] = {
299 { .id = "APMC0D18" },
300 { }
301 };
302 MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
303 #endif
304
305 static struct hwrng xgene_rng_func = {
306 .name = "xgene-rng",
307 .init = xgene_rng_init,
308 .data_present = xgene_rng_data_present,
309 .data_read = xgene_rng_data_read,
310 };
311
xgene_rng_probe(struct platform_device * pdev)312 static int xgene_rng_probe(struct platform_device *pdev)
313 {
314 struct xgene_rng_dev *ctx;
315 struct clk *clk;
316 int rc = 0;
317
318 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
319 if (!ctx)
320 return -ENOMEM;
321
322 ctx->dev = &pdev->dev;
323
324 ctx->csr_base = devm_platform_ioremap_resource(pdev, 0);
325 if (IS_ERR(ctx->csr_base))
326 return PTR_ERR(ctx->csr_base);
327
328 rc = platform_get_irq(pdev, 0);
329 if (rc < 0)
330 return rc;
331 ctx->irq = rc;
332
333 dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
334 ctx->csr_base, ctx->irq);
335
336 rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
337 dev_name(&pdev->dev), ctx);
338 if (rc)
339 return rc;
340
341 /* Enable IP clock */
342 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
343 if (IS_ERR(clk))
344 return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Couldn't get the clock for RNG\n");
345
346 xgene_rng_func.priv = (unsigned long) ctx;
347
348 rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func);
349 if (rc)
350 return dev_err_probe(&pdev->dev, rc, "RNG registering failed\n");
351
352 rc = device_init_wakeup(&pdev->dev, 1);
353 if (rc)
354 return dev_err_probe(&pdev->dev, rc, "RNG device_init_wakeup failed\n");
355
356 return 0;
357 }
358
xgene_rng_remove(struct platform_device * pdev)359 static void xgene_rng_remove(struct platform_device *pdev)
360 {
361 int rc;
362
363 rc = device_init_wakeup(&pdev->dev, 0);
364 if (rc)
365 dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
366 }
367
368 static const struct of_device_id xgene_rng_of_match[] = {
369 { .compatible = "apm,xgene-rng" },
370 { }
371 };
372
373 MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
374
375 static struct platform_driver xgene_rng_driver = {
376 .probe = xgene_rng_probe,
377 .remove = xgene_rng_remove,
378 .driver = {
379 .name = "xgene-rng",
380 .of_match_table = xgene_rng_of_match,
381 .acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
382 },
383 };
384
385 module_platform_driver(xgene_rng_driver);
386 MODULE_DESCRIPTION("APM X-Gene RNG driver");
387 MODULE_LICENSE("GPL");
388