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Searched refs:REG (Results 1 – 25 of 198) sorted by relevance

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/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c72 REG(ANA_ADVLEARN, 0x009000),
73 REG(ANA_VLANMASK, 0x009004),
74 REG(ANA_PORT_B_DOMAIN, 0x009008),
75 REG(ANA_ANAGEFIL, 0x00900c),
76 REG(ANA_ANEVENTS, 0x009010),
77 REG(ANA_STORMLIMIT_BURST, 0x009014),
78 REG(ANA_STORMLIMIT_CFG, 0x009018),
79 REG(ANA_ISOLATED_PORTS, 0x009028),
80 REG(ANA_COMMUNITY_PORTS, 0x00902c),
81 REG(ANA_AUTOAGE, 0x009030),
[all …]
/linux/tools/perf/arch/csky/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[0] = REG(A0); in libdw__arch_set_initial_registers()
24 dwarf_regs[1] = REG(A1); in libdw__arch_set_initial_registers()
25 dwarf_regs[2] = REG(A2); in libdw__arch_set_initial_registers()
26 dwarf_regs[3] = REG(A3); in libdw__arch_set_initial_registers()
27 dwarf_regs[4] = REG(REGS0); in libdw__arch_set_initial_registers()
28 dwarf_regs[5] = REG(REGS1); in libdw__arch_set_initial_registers()
29 dwarf_regs[6] = REG(REGS2); in libdw__arch_set_initial_registers()
30 dwarf_regs[7] = REG(REGS3); in libdw__arch_set_initial_registers()
31 dwarf_regs[8] = REG(REGS in libdw__arch_set_initial_registers()
[all...]
/linux/tools/perf/arch/s390/util/
H A Dunwind-libdw.c17 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
26 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
27 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
28 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
29 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
30 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
31 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
32 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
33 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
34 dwarf_regs[8] = REG(R in libdw__arch_set_initial_registers()
[all...]
/linux/tools/perf/arch/arm64/util/
H A Dunwind-libdw.c14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
20 dwarf_regs[0] = REG(X0); in libdw__arch_set_initial_registers()
21 dwarf_regs[1] = REG(X1); in libdw__arch_set_initial_registers()
22 dwarf_regs[2] = REG(X2); in libdw__arch_set_initial_registers()
23 dwarf_regs[3] = REG(X3); in libdw__arch_set_initial_registers()
24 dwarf_regs[4] = REG(X4); in libdw__arch_set_initial_registers()
25 dwarf_regs[5] = REG(X5); in libdw__arch_set_initial_registers()
26 dwarf_regs[6] = REG(X6); in libdw__arch_set_initial_registers()
27 dwarf_regs[7] = REG(X7); in libdw__arch_set_initial_registers()
28 dwarf_regs[8] = REG(X in libdw__arch_set_initial_registers()
[all...]
/linux/tools/perf/arch/loongarch/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(R8); in libdw__arch_set_initial_registers()
31 dwarf_regs[9] = REG(R in libdw__arch_set_initial_registers()
[all...]
/linux/tools/perf/arch/riscv/util/
H A Dunwind-libdw.c16 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
23 dwarf_regs[1] = REG(RA); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(SP); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(GP); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(TP); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(T0); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(T1); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(T2); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(S0); in libdw__arch_set_initial_registers()
31 dwarf_regs[9] = REG(S in libdw__arch_set_initial_registers()
[all...]
/linux/tools/perf/arch/powerpc/util/
H A Dunwind-libdw.c23 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
29 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
30 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
31 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
32 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
33 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
34 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
35 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
36 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
37 dwarf_regs[8] = REG(R in libdw__arch_set_initial_registers()
[all...]
/linux/drivers/net/ethernet/apple/
H A Dmace.h9 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
12 REG(rcvfifo); /* receive FIFO */
13 REG(xmtfifo); /* transmit FIFO */
14 REG(xmtfc); /* transmit frame control */
15 REG(xmtfs); /* transmit frame status */
16 REG(xmtrc); /* transmit retry count */
17 REG(rcvfc); /* receive frame control */
18 REG(rcvfs); /* receive frame status (4 bytes) */
19 REG(fifofc); /* FIFO frame count */
20 REG(ir); /* interrupt register */
[all …]
/linux/tools/perf/arch/x86/util/
H A Dunwind-libdw.c15 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
22 dwarf_regs[0] = REG(AX); in libdw__arch_set_initial_registers()
23 dwarf_regs[1] = REG(CX); in libdw__arch_set_initial_registers()
24 dwarf_regs[2] = REG(DX); in libdw__arch_set_initial_registers()
25 dwarf_regs[3] = REG(BX); in libdw__arch_set_initial_registers()
26 dwarf_regs[4] = REG(SP); in libdw__arch_set_initial_registers()
27 dwarf_regs[5] = REG(BP); in libdw__arch_set_initial_registers()
28 dwarf_regs[6] = REG(SI); in libdw__arch_set_initial_registers()
29 dwarf_regs[7] = REG(DI); in libdw__arch_set_initial_registers()
30 dwarf_regs[8] = REG(I in libdw__arch_set_initial_registers()
[all...]
/linux/drivers/regulator/
H A Drn5t618-regulator.c25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/tools/perf/arch/arm/util/
H A Dunwind-libdw.c14 #define REG(r) ({ \ in libdw__arch_set_initial_registers() macro
20 dwarf_regs[0] = REG(R0); in libdw__arch_set_initial_registers()
21 dwarf_regs[1] = REG(R1); in libdw__arch_set_initial_registers()
22 dwarf_regs[2] = REG(R2); in libdw__arch_set_initial_registers()
23 dwarf_regs[3] = REG(R3); in libdw__arch_set_initial_registers()
24 dwarf_regs[4] = REG(R4); in libdw__arch_set_initial_registers()
25 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
26 dwarf_regs[6] = REG(R6); in libdw__arch_set_initial_registers()
27 dwarf_regs[7] = REG(R7); in libdw__arch_set_initial_registers()
28 dwarf_regs[8] = REG(R in libdw__arch_set_initial_registers()
[all...]
/linux/tools/testing/selftests/powerpc/nx-gzip/include/
H A Dnxu.h428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \ argument
429 & REG##_mask)
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \ argument
431 & REG##_mask)
432 #define get32(ST, REG) (be32toh(ST.REG)) argument
433 #define getp32(ST, REG) (be32toh((ST)->REG)) argument
434 #define get64(ST, REG) (be64toh(ST.REG)) argument
435 #define getp64(ST, REG) (be64toh((ST)->REG)) argument
437 #define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \ argument
438 << (31-REG##_offset)))
[all …]
/linux/arch/m68k/lib/
H A Dmulsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
H A Dmodsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
[all …]
H A Dumodsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
H A Ddivsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_translate_dcn30.c59 #undef REG
60 #define REG(reg_name)\ macro
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
163 case REG(DC_GPIO_DDC2_A): in offset_to_id()
166 case REG(DC_GPIO_DDC3_A): in offset_to_id()
169 case REG(DC_GPIO_DDC4_A): in offset_to_id()
172 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_translate_dcn20.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c36 #define REG(reg)\ macro
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B); in dwb3_program_ogam_luta_settings()
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G); in dwb3_program_ogam_luta_settings()
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R); in dwb3_program_ogam_luta_settings()
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B); in dwb3_program_ogam_luta_settings()
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G); in dwb3_program_ogam_luta_settings()
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R); in dwb3_program_ogam_luta_settings()
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B); in dwb3_program_ogam_luta_settings()
96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G); in dwb3_program_ogam_luta_settings()
97 gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R); in dwb3_program_ogam_luta_settings()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c42 #define REG(reg)\ macro
125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); in program_gamut_remap()
146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); in program_gamut_remap()
203 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in read_gamut_remap()
204 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in read_gamut_remap()
213 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in read_gamut_remap()
[all …]
/linux/arch/sparc/include/asm/
H A Dasm.h14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
15 brz,PREDICT REG, DEST
16 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
17 brz,a,PREDICT REG, DEST
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
19 brnz,PREDICT REG, DEST
20 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
21 brnz,a,PREDICT REG, DEST
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
28 cmp REG, 0; \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp_cm.c33 #define REG(reg)\ macro
244 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B); in dpp3_program_gamcor_lut()
245 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G); in dpp3_program_gamcor_lut()
246 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R); in dpp3_program_gamcor_lut()
247 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B); in dpp3_program_gamcor_lut()
248 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G); in dpp3_program_gamcor_lut()
249 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R); in dpp3_program_gamcor_lut()
250 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B); in dpp3_program_gamcor_lut()
251 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B); in dpp3_program_gamcor_lut()
252 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G); in dpp3_program_gamcor_lut()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_translate_dcn32.c52 #undef REG
53 #define REG(reg_name)\ macro
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
146 case REG(DC_GPIO_DDC1_A): in offset_to_id()
149 case REG(DC_GPIO_DDC2_A): in offset_to_id()
152 case REG(DC_GPIO_DDC3_A): in offset_to_id()
155 case REG(DC_GPIO_DDC4_A): in offset_to_id()
158 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]

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