1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2014-2025 Broadcom
4 */
5
6 #ifndef __BCMGENET_H__
7 #define __BCMGENET_H__
8
9 #include <linux/skbuff.h>
10 #include <linux/netdevice.h>
11 #include <linux/spinlock.h>
12 #include <linux/clk.h>
13 #include <linux/mii.h>
14 #include <linux/if_vlan.h>
15 #include <linux/phy.h>
16 #include <linux/dim.h>
17 #include <linux/ethtool.h>
18 #include <net/page_pool/helpers.h>
19
20 #include "../unimac.h"
21
22 /* Maximum number of hardware queues, downsized if needed */
23 #define GENET_MAX_MQ_CNT 4
24
25 /* total number of Buffer Descriptors, same for Rx/Tx */
26 #define TOTAL_DESC 256
27
28 /* which ring is descriptor based */
29 #define DESC_INDEX 16
30
31 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
32 * 1536 is multiple of 256 bytes
33 */
34 #define ENET_BRCM_TAG_LEN 6
35 #define ENET_PAD 8
36 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
37 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
38 #define DMA_MAX_BURST_LENGTH 0x10
39
40 /* misc. configuration */
41 #define MAX_NUM_OF_FS_RULES 16
42 #define CLEAR_ALL_HFB 0xFF
43 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4)
44 #define DMA_FC_THRESH_LO 5
45
46 /* 64B receive/transmit status block */
47 struct status_64 {
48 u32 length_status; /* length and peripheral status */
49 u32 ext_status; /* Extended status*/
50 u32 rx_csum; /* partial rx checksum */
51 u32 unused1[9]; /* unused */
52 u32 tx_csum_info; /* Tx checksum info. */
53 u32 unused2[3]; /* unused */
54 };
55
56 /* Rx status bits */
57 #define STATUS_RX_EXT_MASK 0x1FFFFF
58 #define STATUS_RX_CSUM_MASK 0xFFFF
59 #define STATUS_RX_CSUM_OK 0x10000
60 #define STATUS_RX_CSUM_FR 0x20000
61 #define STATUS_RX_PROTO_TCP 0
62 #define STATUS_RX_PROTO_UDP 1
63 #define STATUS_RX_PROTO_ICMP 2
64 #define STATUS_RX_PROTO_OTHER 3
65 #define STATUS_RX_PROTO_MASK 3
66 #define STATUS_RX_PROTO_SHIFT 18
67 #define STATUS_FILTER_INDEX_MASK 0xFFFF
68 /* Tx status bits */
69 #define STATUS_TX_CSUM_START_MASK 0X7FFF
70 #define STATUS_TX_CSUM_START_SHIFT 16
71 #define STATUS_TX_CSUM_PROTO_UDP 0x8000
72 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF
73 #define STATUS_TX_CSUM_LV 0x80000000
74
75 /* DMA Descriptor */
76 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */
77 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */
78 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */
79
80 /* Rx/Tx common counter group */
81 struct bcmgenet_pkt_counters {
82 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */
83 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */
84 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */
85 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */
86 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */
87 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */
88 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */
89 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/
90 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/
91 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/
92 };
93
94 /* RSV, Receive Status Vector */
95 struct bcmgenet_rx_counters {
96 struct bcmgenet_pkt_counters pkt_cnt;
97 u32 pkt; /* RO (0x428) Received pkt count*/
98 u32 bytes; /* RO Received byte count */
99 u32 mca; /* RO # of Received multicast pkt */
100 u32 bca; /* RO # of Receive broadcast pkt */
101 u32 fcs; /* RO # of Received FCS error */
102 u32 cf; /* RO # of Received control frame pkt*/
103 u32 pf; /* RO # of Received pause frame pkt */
104 u32 uo; /* RO # of unknown op code pkt */
105 u32 aln; /* RO # of alignment error count */
106 u32 flr; /* RO # of frame length out of range count */
107 u32 cde; /* RO # of code error pkt */
108 u32 fcr; /* RO # of carrier sense error pkt */
109 u32 ovr; /* RO # of oversize pkt*/
110 u32 jbr; /* RO # of jabber count */
111 u32 mtue; /* RO # of MTU error pkt*/
112 u32 pok; /* RO # of Received good pkt */
113 u32 uc; /* RO # of unicast pkt */
114 u32 ppp; /* RO # of PPP pkt */
115 u32 rcrc; /* RO (0x470),# of CRC match pkt */
116 };
117
118 /* TSV, Transmit Status Vector */
119 struct bcmgenet_tx_counters {
120 struct bcmgenet_pkt_counters pkt_cnt;
121 u32 pkts; /* RO (0x4a8) Transmited pkt */
122 u32 mca; /* RO # of xmited multicast pkt */
123 u32 bca; /* RO # of xmited broadcast pkt */
124 u32 pf; /* RO # of xmited pause frame count */
125 u32 cf; /* RO # of xmited control frame count */
126 u32 fcs; /* RO # of xmited FCS error count */
127 u32 ovr; /* RO # of xmited oversize pkt */
128 u32 drf; /* RO # of xmited deferral pkt */
129 u32 edf; /* RO # of xmited Excessive deferral pkt*/
130 u32 scl; /* RO # of xmited single collision pkt */
131 u32 mcl; /* RO # of xmited multiple collision pkt*/
132 u32 lcl; /* RO # of xmited late collision pkt */
133 u32 ecl; /* RO # of xmited excessive collision pkt*/
134 u32 frg; /* RO # of xmited fragments pkt*/
135 u32 ncl; /* RO # of xmited total collision count */
136 u32 jbr; /* RO # of xmited jabber count*/
137 u32 bytes; /* RO # of xmited byte count */
138 u32 pok; /* RO # of xmited good pkt */
139 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */
140 };
141
142 struct bcmgenet_mib_counters {
143 struct bcmgenet_rx_counters rx;
144 struct bcmgenet_tx_counters tx;
145 u32 rx_runt_cnt;
146 u32 rx_runt_fcs;
147 u32 rx_runt_fcs_align;
148 u32 rx_runt_bytes;
149 u32 rbuf_ovflow_cnt;
150 u32 rbuf_err_cnt;
151 u32 mdf_err_cnt;
152 u32 alloc_rx_buff_failed;
153 u32 tx_dma_failed;
154 u32 tx_realloc_tsb;
155 u32 tx_realloc_tsb_failed;
156 };
157
158 struct bcmgenet_tx_stats64 {
159 struct u64_stats_sync syncp;
160 u64_stats_t packets;
161 u64_stats_t bytes;
162 u64_stats_t errors;
163 u64_stats_t dropped;
164 };
165
166 struct bcmgenet_rx_stats64 {
167 struct u64_stats_sync syncp;
168 u64_stats_t bytes;
169 u64_stats_t packets;
170 u64_stats_t errors;
171 u64_stats_t dropped;
172 u64_stats_t multicast;
173 u64_stats_t broadcast;
174 u64_stats_t missed;
175 u64_stats_t length_errors;
176 u64_stats_t over_errors;
177 u64_stats_t crc_errors;
178 u64_stats_t frame_errors;
179 u64_stats_t fragmented_errors;
180 };
181
182 #define UMAC_MIB_START 0x400
183
184 #define UMAC_MDIO_CMD 0x614
185 #define MDIO_START_BUSY (1 << 29)
186 #define MDIO_READ_FAIL (1 << 28)
187 #define MDIO_RD (2 << 26)
188 #define MDIO_WR (1 << 26)
189 #define MDIO_PMD_SHIFT 21
190 #define MDIO_PMD_MASK 0x1F
191 #define MDIO_REG_SHIFT 16
192 #define MDIO_REG_MASK 0x1F
193
194 #define UMAC_RBUF_OVFL_CNT_V1 0x61C
195 #define RBUF_OVFL_CNT_V2 0x80
196 #define RBUF_OVFL_CNT_V3PLUS 0x94
197
198 #define UMAC_MPD_CTRL 0x620
199 #define MPD_EN (1 << 0)
200 #define MPD_PW_EN (1 << 27)
201 #define MPD_MSEQ_LEN_SHIFT 16
202 #define MPD_MSEQ_LEN_MASK 0xFF
203
204 #define UMAC_MPD_PW_MS 0x624
205 #define UMAC_MPD_PW_LS 0x628
206 #define UMAC_RBUF_ERR_CNT_V1 0x634
207 #define RBUF_ERR_CNT_V2 0x84
208 #define RBUF_ERR_CNT_V3PLUS 0x98
209 #define UMAC_MDF_ERR_CNT 0x638
210 #define UMAC_MDF_CTRL 0x650
211 #define UMAC_MDF_ADDR 0x654
212 #define UMAC_MIB_CTRL 0x580
213 #define MIB_RESET_RX (1 << 0)
214 #define MIB_RESET_RUNT (1 << 1)
215 #define MIB_RESET_TX (1 << 2)
216
217 #define RBUF_CTRL 0x00
218 #define RBUF_64B_EN (1 << 0)
219 #define RBUF_ALIGN_2B (1 << 1)
220 #define RBUF_BAD_DIS (1 << 2)
221
222 #define RBUF_STATUS 0x0C
223 #define RBUF_STATUS_WOL (1 << 0)
224 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1)
225 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2)
226
227 #define RBUF_CHK_CTRL 0x14
228 #define RBUF_RXCHK_EN (1 << 0)
229 #define RBUF_SKIP_FCS (1 << 4)
230 #define RBUF_L3_PARSE_DIS (1 << 5)
231
232 #define RBUF_ENERGY_CTRL 0x9c
233 #define RBUF_EEE_EN (1 << 0)
234 #define RBUF_PM_EN (1 << 1)
235
236 #define RBUF_TBUF_SIZE_CTRL 0xb4
237
238 #define RBUF_HFB_CTRL_V1 0x38
239 #define RBUF_HFB_FILTER_EN_SHIFT 16
240 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000
241 #define RBUF_HFB_EN (1 << 0)
242 #define RBUF_HFB_256B (1 << 1)
243 #define RBUF_ACPI_EN (1 << 2)
244
245 #define RBUF_HFB_LEN_V1 0x3C
246 #define RBUF_FLTR_LEN_MASK 0xFF
247 #define RBUF_FLTR_LEN_SHIFT 8
248
249 #define TBUF_CTRL 0x00
250 #define TBUF_64B_EN (1 << 0)
251 #define TBUF_BP_MC 0x0C
252 #define TBUF_ENERGY_CTRL 0x14
253 #define TBUF_EEE_EN (1 << 0)
254 #define TBUF_PM_EN (1 << 1)
255
256 #define TBUF_CTRL_V1 0x80
257 #define TBUF_BP_MC_V1 0xA0
258
259 #define HFB_CTRL 0x00
260 #define HFB_FLT_ENABLE_V3PLUS 0x04
261 #define HFB_FLT_LEN_V2 0x04
262 #define HFB_FLT_LEN_V3PLUS 0x1C
263
264 /* uniMac intrl2 registers */
265 #define INTRL2_CPU_STAT 0x00
266 #define INTRL2_CPU_SET 0x04
267 #define INTRL2_CPU_CLEAR 0x08
268 #define INTRL2_CPU_MASK_STATUS 0x0C
269 #define INTRL2_CPU_MASK_SET 0x10
270 #define INTRL2_CPU_MASK_CLEAR 0x14
271
272 /* INTRL2 instance 0 definitions */
273 #define UMAC_IRQ_SCB (1 << 0)
274 #define UMAC_IRQ_EPHY (1 << 1)
275 #define UMAC_IRQ_PHY_DET_R (1 << 2)
276 #define UMAC_IRQ_PHY_DET_F (1 << 3)
277 #define UMAC_IRQ_LINK_UP (1 << 4)
278 #define UMAC_IRQ_LINK_DOWN (1 << 5)
279 #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
280 #define UMAC_IRQ_UMAC (1 << 6)
281 #define UMAC_IRQ_UMAC_TSV (1 << 7)
282 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8)
283 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9)
284 #define UMAC_IRQ_HFB_SM (1 << 10)
285 #define UMAC_IRQ_HFB_MM (1 << 11)
286 #define UMAC_IRQ_MPD_R (1 << 12)
287 #define UMAC_IRQ_WAKE_EVENT (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM | \
288 UMAC_IRQ_MPD_R)
289 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
290 #define UMAC_IRQ_RXDMA_PDONE (1 << 14)
291 #define UMAC_IRQ_RXDMA_BDONE (1 << 15)
292 #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE
293 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
294 #define UMAC_IRQ_TXDMA_PDONE (1 << 17)
295 #define UMAC_IRQ_TXDMA_BDONE (1 << 18)
296 #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE
297
298 /* Only valid for GENETv3+ */
299 #define UMAC_IRQ_MDIO_DONE (1 << 23)
300 #define UMAC_IRQ_MDIO_ERROR (1 << 24)
301 #define UMAC_IRQ_MDIO_EVENT (UMAC_IRQ_MDIO_DONE | \
302 UMAC_IRQ_MDIO_ERROR)
303
304 /* INTRL2 instance 1 definitions */
305 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF
306 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF
307 #define UMAC_IRQ1_RX_INTR_SHIFT 16
308
309 /* Register block offsets */
310 #define GENET_SYS_OFF 0x0000
311 #define GENET_GR_BRIDGE_OFF 0x0040
312 #define GENET_EXT_OFF 0x0080
313 #define GENET_INTRL2_0_OFF 0x0200
314 #define GENET_INTRL2_1_OFF 0x0240
315 #define GENET_RBUF_OFF 0x0300
316 #define GENET_UMAC_OFF 0x0800
317
318 /* SYS block offsets and register definitions */
319 #define SYS_REV_CTRL 0x00
320 #define SYS_PORT_CTRL 0x04
321 #define PORT_MODE_INT_EPHY 0
322 #define PORT_MODE_INT_GPHY 1
323 #define PORT_MODE_EXT_EPHY 2
324 #define PORT_MODE_EXT_GPHY 3
325 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4))
326 #define PORT_MODE_EXT_RVMII_50 4
327 #define LED_ACT_SOURCE_MAC (1 << 9)
328
329 #define SYS_RBUF_FLUSH_CTRL 0x08
330 #define SYS_TBUF_FLUSH_CTRL 0x0C
331 #define RBUF_FLUSH_CTRL_V1 0x04
332
333 /* Ext block register offsets and definitions */
334 #define EXT_EXT_PWR_MGMT 0x00
335 #define EXT_PWR_DOWN_BIAS (1 << 0)
336 #define EXT_PWR_DOWN_DLL (1 << 1)
337 #define EXT_PWR_DOWN_PHY (1 << 2)
338 #define EXT_PWR_DN_EN_LD (1 << 3)
339 #define EXT_ENERGY_DET (1 << 4)
340 #define EXT_IDDQ_FROM_PHY (1 << 5)
341 #define EXT_IDDQ_GLBL_PWR (1 << 7)
342 #define EXT_PHY_RESET (1 << 8)
343 #define EXT_ENERGY_DET_MASK (1 << 12)
344 #define EXT_PWR_DOWN_PHY_TX (1 << 16)
345 #define EXT_PWR_DOWN_PHY_RX (1 << 17)
346 #define EXT_PWR_DOWN_PHY_SD (1 << 18)
347 #define EXT_PWR_DOWN_PHY_RD (1 << 19)
348 #define EXT_PWR_DOWN_PHY_EN (1 << 20)
349
350 #define EXT_RGMII_OOB_CTRL 0x0C
351 #define RGMII_MODE_EN_V123 (1 << 0)
352 #define RGMII_LINK (1 << 4)
353 #define OOB_DISABLE (1 << 5)
354 #define RGMII_MODE_EN (1 << 6)
355 #define ID_MODE_DIS (1 << 16)
356
357 #define EXT_GPHY_CTRL 0x1C
358 #define EXT_CFG_IDDQ_BIAS (1 << 0)
359 #define EXT_CFG_PWR_DOWN (1 << 1)
360 #define EXT_CK25_DIS (1 << 4)
361 #define EXT_CFG_IDDQ_GLOBAL_PWR (1 << 3)
362 #define EXT_GPHY_RESET (1 << 5)
363
364 /* DMA rings size */
365 #define DMA_RING_SIZE (0x40)
366 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1))
367
368 /* DMA registers common definitions */
369 #define DMA_RW_POINTER_MASK 0x1FF
370 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF
371 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16
372 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF
373 #define DMA_BUFFER_DONE_CNT_SHIFT 16
374 #define DMA_P_INDEX_MASK 0xFFFF
375 #define DMA_C_INDEX_MASK 0xFFFF
376
377 /* DMA ring size register */
378 #define DMA_RING_SIZE_MASK 0xFFFF
379 #define DMA_RING_SIZE_SHIFT 16
380 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
381
382 /* DMA interrupt threshold register */
383 #define DMA_INTR_THRESHOLD_MASK 0x01FF
384
385 /* DMA XON/XOFF register */
386 #define DMA_XON_THREHOLD_MASK 0xFFFF
387 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF
388 #define DMA_XOFF_THRESHOLD_SHIFT 16
389
390 /* DMA flow period register */
391 #define DMA_FLOW_PERIOD_MASK 0xFFFF
392 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF
393 #define DMA_MAX_PKT_SIZE_SHIFT 16
394
395
396 /* DMA control register */
397 #define DMA_EN (1 << 0)
398 #define DMA_RING_BUF_EN_SHIFT 0x01
399 #define DMA_RING_BUF_EN_MASK 0xFFFF
400 #define DMA_TSB_SWAP_EN (1 << 20)
401
402 /* DMA status register */
403 #define DMA_DISABLED (1 << 0)
404 #define DMA_DESC_RAM_INIT_BUSY (1 << 1)
405
406 /* DMA SCB burst size register */
407 #define DMA_SCB_BURST_SIZE_MASK 0x1F
408
409 /* DMA activity vector register */
410 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF
411
412 /* DMA backpressure mask register */
413 #define DMA_BACKPRESSURE_MASK 0x1FFFF
414 #define DMA_PFC_ENABLE (1 << 31)
415
416 /* DMA backpressure status register */
417 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF
418
419 /* DMA override register */
420 #define DMA_LITTLE_ENDIAN_MODE (1 << 0)
421 #define DMA_REGISTER_MODE (1 << 1)
422
423 /* DMA timeout register */
424 #define DMA_TIMEOUT_MASK 0xFFFF
425 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */
426
427 /* TDMA rate limiting control register */
428 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF
429
430 /* TDMA arbitration control register */
431 #define DMA_ARBITER_MODE_MASK 0x03
432 #define DMA_RING_BUF_PRIORITY_MASK 0x1F
433 #define DMA_RING_BUF_PRIORITY_SHIFT 5
434 #define DMA_PRIO_REG_INDEX(q) ((q) / 6)
435 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
436 #define DMA_RATE_ADJ_MASK 0xFF
437
438 /* Tx/Rx Dma Descriptor common bits*/
439 #define DMA_BUFLENGTH_MASK 0x0fff
440 #define DMA_BUFLENGTH_SHIFT 16
441 #define DMA_OWN 0x8000
442 #define DMA_EOP 0x4000
443 #define DMA_SOP 0x2000
444 #define DMA_WRAP 0x1000
445 /* Tx specific Dma descriptor bits */
446 #define DMA_TX_UNDERRUN 0x0200
447 #define DMA_TX_APPEND_CRC 0x0040
448 #define DMA_TX_OW_CRC 0x0020
449 #define DMA_TX_DO_CSUM 0x0010
450 #define DMA_TX_QTAG_SHIFT 7
451
452 /* Rx Specific Dma descriptor bits */
453 #define DMA_RX_CHK_V3PLUS 0x8000
454 #define DMA_RX_CHK_V12 0x1000
455 #define DMA_RX_BRDCAST 0x0040
456 #define DMA_RX_MULT 0x0020
457 #define DMA_RX_LG 0x0010
458 #define DMA_RX_NO 0x0008
459 #define DMA_RX_RXER 0x0004
460 #define DMA_RX_CRC_ERROR 0x0002
461 #define DMA_RX_OV 0x0001
462 #define DMA_RX_FI_MASK 0x001F
463 #define DMA_RX_FI_SHIFT 0x0007
464 #define DMA_DESC_ALLOC_MASK 0x00FF
465
466 #define DMA_ARBITER_RR 0x00
467 #define DMA_ARBITER_WRR 0x01
468 #define DMA_ARBITER_SP 0x02
469
470 struct enet_cb {
471 struct sk_buff *skb;
472 struct page *rx_page;
473 unsigned int rx_offset;
474 unsigned int rx_size;
475 void __iomem *bd_addr;
476 DEFINE_DMA_UNMAP_ADDR(dma_addr);
477 DEFINE_DMA_UNMAP_LEN(dma_len);
478 };
479
480 /* power management mode */
481 enum bcmgenet_power_mode {
482 GENET_POWER_CABLE_SENSE = 0,
483 GENET_POWER_PASSIVE,
484 GENET_POWER_WOL_MAGIC,
485 };
486
487 struct bcmgenet_priv;
488
489 /* We support both runtime GENET detection and compile-time
490 * to optimize code-paths for a given hardware
491 */
492 enum bcmgenet_version {
493 GENET_V1 = 1,
494 GENET_V2,
495 GENET_V3,
496 GENET_V4,
497 GENET_V5
498 };
499
500 #define GENET_IS_V1(p) ((p)->version == GENET_V1)
501 #define GENET_IS_V2(p) ((p)->version == GENET_V2)
502 #define GENET_IS_V3(p) ((p)->version == GENET_V3)
503 #define GENET_IS_V4(p) ((p)->version == GENET_V4)
504 #define GENET_IS_V5(p) ((p)->version == GENET_V5)
505
506 /* Hardware flags */
507 #define GENET_HAS_40BITS (1 << 0)
508 #define GENET_HAS_EXT (1 << 1)
509 #define GENET_HAS_MDIO_INTR (1 << 2)
510 #define GENET_HAS_MOCA_LINK_DET (1 << 3)
511 #define GENET_HAS_EPHY_16NM (1 << 4)
512
513 /* BCMGENET hardware parameters, keep this structure nicely aligned
514 * since it is going to be used in hot paths
515 */
516 struct bcmgenet_hw_params {
517 u8 tx_queues;
518 u8 tx_bds_per_q;
519 u8 rx_queues;
520 u8 rx_bds_per_q;
521 u8 bp_in_en_shift;
522 u32 bp_in_mask;
523 u8 hfb_filter_cnt;
524 u8 hfb_filter_size;
525 u8 qtag_mask;
526 u16 tbuf_offset;
527 u32 hfb_offset;
528 u32 hfb_reg_offset;
529 u32 rdma_offset;
530 u32 tdma_offset;
531 u32 words_per_bd;
532 };
533
534 struct bcmgenet_skb_cb {
535 struct enet_cb *first_cb; /* First control block of SKB */
536 struct enet_cb *last_cb; /* Last control block of SKB */
537 unsigned int bytes_sent; /* bytes on the wire (no TSB) */
538 };
539
540 #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb))
541
542 struct bcmgenet_tx_ring {
543 spinlock_t lock; /* ring lock */
544 struct napi_struct napi; /* NAPI per tx queue */
545 struct bcmgenet_tx_stats64 stats64;
546 unsigned int index; /* ring index */
547 struct enet_cb *cbs; /* tx ring buffer control block*/
548 unsigned int size; /* size of each tx ring */
549 unsigned int clean_ptr; /* Tx ring clean pointer */
550 unsigned int c_index; /* last consumer index of each ring*/
551 unsigned int free_bds; /* # of free bds for each ring */
552 unsigned int write_ptr; /* Tx ring write pointer SW copy */
553 unsigned int prod_index; /* Tx ring producer index SW copy */
554 unsigned int cb_ptr; /* Tx ring initial CB ptr */
555 unsigned int end_ptr; /* Tx ring end CB ptr */
556 struct bcmgenet_priv *priv;
557 };
558
559 struct bcmgenet_net_dim {
560 u16 use_dim;
561 u16 event_ctr;
562 unsigned long packets;
563 unsigned long bytes;
564 struct dim dim;
565 };
566
567 struct bcmgenet_rx_ring {
568 struct napi_struct napi; /* Rx NAPI struct */
569 struct bcmgenet_rx_stats64 stats64;
570 unsigned int index; /* Rx ring index */
571 struct enet_cb *cbs; /* Rx ring buffer control block */
572 unsigned int size; /* Rx ring size */
573 unsigned int c_index; /* Rx last consumer index */
574 unsigned int read_ptr; /* Rx ring read pointer */
575 unsigned int cb_ptr; /* Rx ring initial CB ptr */
576 unsigned int end_ptr; /* Rx ring end CB ptr */
577 unsigned int old_discards;
578 struct bcmgenet_net_dim dim;
579 u32 rx_max_coalesced_frames;
580 u32 rx_coalesce_usecs;
581 struct page_pool *page_pool;
582 struct bcmgenet_priv *priv;
583 };
584
585 enum bcmgenet_rxnfc_state {
586 BCMGENET_RXNFC_STATE_UNUSED = 0,
587 BCMGENET_RXNFC_STATE_DISABLED,
588 BCMGENET_RXNFC_STATE_ENABLED
589 };
590
591 struct bcmgenet_rxnfc_rule {
592 struct list_head list;
593 struct ethtool_rx_flow_spec fs;
594 enum bcmgenet_rxnfc_state state;
595 };
596
597 /* device context */
598 struct bcmgenet_priv {
599 void __iomem *base;
600 /* reg_lock: lock to serialize access to shared registers */
601 spinlock_t reg_lock;
602 enum bcmgenet_version version;
603 struct net_device *dev;
604
605 /* transmit variables */
606 void __iomem *tx_bds;
607 struct enet_cb *tx_cbs;
608 unsigned int num_tx_bds;
609
610 struct bcmgenet_tx_ring tx_rings[GENET_MAX_MQ_CNT + 1];
611
612 /* receive variables */
613 void __iomem *rx_bds;
614 struct enet_cb *rx_cbs;
615 unsigned int num_rx_bds;
616 struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES];
617 struct list_head rxnfc_list;
618
619 struct bcmgenet_rx_ring rx_rings[GENET_MAX_MQ_CNT + 1];
620
621 /* other misc variables */
622 const struct bcmgenet_hw_params *hw_params;
623 u32 flags;
624 unsigned autoneg_pause:1;
625 unsigned tx_pause:1;
626 unsigned rx_pause:1;
627
628 /* MDIO bus variables */
629 wait_queue_head_t wq;
630 bool internal_phy;
631 struct device_node *phy_dn;
632 struct device_node *mdio_dn;
633 struct mii_bus *mii_bus;
634 u16 gphy_rev;
635 struct clk *clk_eee;
636 bool clk_eee_enabled;
637
638 /* PHY device variables */
639 phy_interface_t phy_interface;
640 int phy_addr;
641 int ext_phy;
642
643 /* Interrupt variables */
644 struct work_struct bcmgenet_irq_work;
645 int irq0;
646 int irq1;
647 int wol_irq;
648 bool wol_irq_disabled;
649
650 /* shared status */
651 spinlock_t lock;
652 unsigned int irq0_stat;
653
654 /* HW descriptors/checksum variables */
655 bool crc_fwd_en;
656
657 u32 dma_max_burst_length;
658
659 u32 msg_enable;
660
661 struct clk *clk;
662 struct platform_device *pdev;
663 struct platform_device *mii_pdev;
664
665 /* WOL */
666 struct clk *clk_wol;
667 u32 wolopts;
668 u8 sopass[SOPASS_MAX];
669
670 struct bcmgenet_mib_counters mib;
671 };
672
bcmgenet_has_40bits(struct bcmgenet_priv * priv)673 static inline bool bcmgenet_has_40bits(struct bcmgenet_priv *priv)
674 {
675 return !!(priv->flags & GENET_HAS_40BITS);
676 }
677
bcmgenet_has_ext(struct bcmgenet_priv * priv)678 static inline bool bcmgenet_has_ext(struct bcmgenet_priv *priv)
679 {
680 return !!(priv->flags & GENET_HAS_EXT);
681 }
682
bcmgenet_has_mdio_intr(struct bcmgenet_priv * priv)683 static inline bool bcmgenet_has_mdio_intr(struct bcmgenet_priv *priv)
684 {
685 return !!(priv->flags & GENET_HAS_MDIO_INTR);
686 }
687
bcmgenet_has_moca_link_det(struct bcmgenet_priv * priv)688 static inline bool bcmgenet_has_moca_link_det(struct bcmgenet_priv *priv)
689 {
690 return !!(priv->flags & GENET_HAS_MOCA_LINK_DET);
691 }
692
bcmgenet_has_ephy_16nm(struct bcmgenet_priv * priv)693 static inline bool bcmgenet_has_ephy_16nm(struct bcmgenet_priv *priv)
694 {
695 return !!(priv->flags & GENET_HAS_EPHY_16NM);
696 }
697
698 #define GENET_IO_MACRO(name, offset) \
699 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \
700 u32 off) \
701 { \
702 /* MIPS chips strapped for BE will automagically configure the \
703 * peripheral registers for CPU-native byte order. \
704 */ \
705 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
706 return __raw_readl(priv->base + offset + off); \
707 else \
708 return readl_relaxed(priv->base + offset + off); \
709 } \
710 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
711 u32 val, u32 off) \
712 { \
713 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
714 __raw_writel(val, priv->base + offset + off); \
715 else \
716 writel_relaxed(val, priv->base + offset + off); \
717 }
718
719 GENET_IO_MACRO(ext, GENET_EXT_OFF);
720 GENET_IO_MACRO(umac, GENET_UMAC_OFF);
721 GENET_IO_MACRO(sys, GENET_SYS_OFF);
722
723 /* interrupt l2 registers accessors */
724 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
725 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
726
727 /* HFB register accessors */
728 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
729
730 /* GENET v2+ HFB control and filter len helpers */
731 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
732
733 /* RBUF register accessors */
734 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
735
736 /* MDIO routines */
737 int bcmgenet_mii_init(struct net_device *dev);
738 int bcmgenet_mii_config(struct net_device *dev, bool init);
739 int bcmgenet_mii_probe(struct net_device *dev);
740 void bcmgenet_mii_exit(struct net_device *dev);
741 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx);
742 void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
743 void bcmgenet_mii_setup(struct net_device *dev);
744
745 /* Wake-on-LAN routines */
746 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
747 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
748 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
749 enum bcmgenet_power_mode mode);
750 int bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
751 enum bcmgenet_power_mode mode);
752
753 void bcmgenet_eee_enable_set(struct net_device *dev, bool enable);
754
755 #endif /* __BCMGENET_H__ */
756