xref: /linux/include/dt-bindings/clock/r9a07g044-cpg.h (revision 619b92b9c8fe5369503ae948ad4e0a9c195c2c4a)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2  *
3  * Copyright (C) 2021 Renesas Electronics Corp.
4  */
5 #ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
6 #define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
7 
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
9 
10 /* R9A07G044 CPG Core Clocks */
11 #define R9A07G044_CLK_I			0
12 #define R9A07G044_CLK_I2		1
13 #define R9A07G044_CLK_G			2
14 #define R9A07G044_CLK_S0		3
15 #define R9A07G044_CLK_S1		4
16 #define R9A07G044_CLK_SPI0		5
17 #define R9A07G044_CLK_SPI1		6
18 #define R9A07G044_CLK_SD0		7
19 #define R9A07G044_CLK_SD1		8
20 #define R9A07G044_CLK_M0		9
21 #define R9A07G044_CLK_M1		10
22 #define R9A07G044_CLK_M2		11
23 #define R9A07G044_CLK_M3		12
24 #define R9A07G044_CLK_M4		13
25 #define R9A07G044_CLK_HP		14
26 #define R9A07G044_CLK_TSU		15
27 #define R9A07G044_CLK_ZT		16
28 #define R9A07G044_CLK_P0		17
29 #define R9A07G044_CLK_P1		18
30 #define R9A07G044_CLK_P2		19
31 #define R9A07G044_CLK_AT		20
32 #define R9A07G044_OSCCLK		21
33 #define R9A07G044_CLK_P0_DIV2		22
34 
35 /* R9A07G044 Module Clocks */
36 #define R9A07G044_CA55_SCLK		0
37 #define R9A07G044_CA55_PCLK		1
38 #define R9A07G044_CA55_ATCLK		2
39 #define R9A07G044_CA55_GICCLK		3
40 #define R9A07G044_CA55_PERICLK		4
41 #define R9A07G044_CA55_ACLK		5
42 #define R9A07G044_CA55_TSCLK		6
43 #define R9A07G044_GIC600_GICCLK		7
44 #define R9A07G044_IA55_CLK		8
45 #define R9A07G044_IA55_PCLK		9
46 #define R9A07G044_MHU_PCLK		10
47 #define R9A07G044_SYC_CNT_CLK		11
48 #define R9A07G044_DMAC_ACLK		12
49 #define R9A07G044_DMAC_PCLK		13
50 #define R9A07G044_OSTM0_PCLK		14
51 #define R9A07G044_OSTM1_PCLK		15
52 #define R9A07G044_OSTM2_PCLK		16
53 #define R9A07G044_MTU_X_MCK_MTU3	17
54 #define R9A07G044_POE3_CLKM_POE		18
55 #define R9A07G044_GPT_PCLK		19
56 #define R9A07G044_POEG_A_CLKP		20
57 #define R9A07G044_POEG_B_CLKP		21
58 #define R9A07G044_POEG_C_CLKP		22
59 #define R9A07G044_POEG_D_CLKP		23
60 #define R9A07G044_WDT0_PCLK		24
61 #define R9A07G044_WDT0_CLK		25
62 #define R9A07G044_WDT1_PCLK		26
63 #define R9A07G044_WDT1_CLK		27
64 #define R9A07G044_WDT2_PCLK		28
65 #define R9A07G044_WDT2_CLK		29
66 #define R9A07G044_SPI_CLK2		30
67 #define R9A07G044_SPI_CLK		31
68 #define R9A07G044_SDHI0_IMCLK		32
69 #define R9A07G044_SDHI0_IMCLK2		33
70 #define R9A07G044_SDHI0_CLK_HS		34
71 #define R9A07G044_SDHI0_ACLK		35
72 #define R9A07G044_SDHI1_IMCLK		36
73 #define R9A07G044_SDHI1_IMCLK2		37
74 #define R9A07G044_SDHI1_CLK_HS		38
75 #define R9A07G044_SDHI1_ACLK		39
76 #define R9A07G044_GPU_CLK		40
77 #define R9A07G044_GPU_AXI_CLK		41
78 #define R9A07G044_GPU_ACE_CLK		42
79 #define R9A07G044_ISU_ACLK		43
80 #define R9A07G044_ISU_PCLK		44
81 #define R9A07G044_H264_CLK_A		45
82 #define R9A07G044_H264_CLK_P		46
83 #define R9A07G044_CRU_SYSCLK		47
84 #define R9A07G044_CRU_VCLK		48
85 #define R9A07G044_CRU_PCLK		49
86 #define R9A07G044_CRU_ACLK		50
87 #define R9A07G044_MIPI_DSI_PLLCLK	51
88 #define R9A07G044_MIPI_DSI_SYSCLK	52
89 #define R9A07G044_MIPI_DSI_ACLK		53
90 #define R9A07G044_MIPI_DSI_PCLK		54
91 #define R9A07G044_MIPI_DSI_VCLK		55
92 #define R9A07G044_MIPI_DSI_LPCLK	56
93 #define R9A07G044_LCDC_CLK_A		57
94 #define R9A07G044_LCDC_CLK_P		58
95 #define R9A07G044_LCDC_CLK_D		59
96 #define R9A07G044_SSI0_PCLK2		60
97 #define R9A07G044_SSI0_PCLK_SFR		61
98 #define R9A07G044_SSI1_PCLK2		62
99 #define R9A07G044_SSI1_PCLK_SFR		63
100 #define R9A07G044_SSI2_PCLK2		64
101 #define R9A07G044_SSI2_PCLK_SFR		65
102 #define R9A07G044_SSI3_PCLK2		66
103 #define R9A07G044_SSI3_PCLK_SFR		67
104 #define R9A07G044_SRC_CLKP		68
105 #define R9A07G044_USB_U2H0_HCLK		69
106 #define R9A07G044_USB_U2H1_HCLK		70
107 #define R9A07G044_USB_U2P_EXR_CPUCLK	71
108 #define R9A07G044_USB_PCLK		72
109 #define R9A07G044_ETH0_CLK_AXI		73
110 #define R9A07G044_ETH0_CLK_CHI		74
111 #define R9A07G044_ETH1_CLK_AXI		75
112 #define R9A07G044_ETH1_CLK_CHI		76
113 #define R9A07G044_I2C0_PCLK		77
114 #define R9A07G044_I2C1_PCLK		78
115 #define R9A07G044_I2C2_PCLK		79
116 #define R9A07G044_I2C3_PCLK		80
117 #define R9A07G044_SCIF0_CLK_PCK		81
118 #define R9A07G044_SCIF1_CLK_PCK		82
119 #define R9A07G044_SCIF2_CLK_PCK		83
120 #define R9A07G044_SCIF3_CLK_PCK		84
121 #define R9A07G044_SCIF4_CLK_PCK		85
122 #define R9A07G044_SCI0_CLKP		86
123 #define R9A07G044_SCI1_CLKP		87
124 #define R9A07G044_IRDA_CLKP		88
125 #define R9A07G044_RSPI0_CLKB		89
126 #define R9A07G044_RSPI1_CLKB		90
127 #define R9A07G044_RSPI2_CLKB		91
128 #define R9A07G044_CANFD_PCLK		92
129 #define R9A07G044_GPIO_HCLK		93
130 #define R9A07G044_ADC_ADCLK		94
131 #define R9A07G044_ADC_PCLK		95
132 #define R9A07G044_TSU_PCLK		96
133 
134 /* R9A07G044 Resets */
135 #define R9A07G044_CA55_RST_1_0		0
136 #define R9A07G044_CA55_RST_1_1		1
137 #define R9A07G044_CA55_RST_3_0		2
138 #define R9A07G044_CA55_RST_3_1		3
139 #define R9A07G044_CA55_RST_4		4
140 #define R9A07G044_CA55_RST_5		5
141 #define R9A07G044_CA55_RST_6		6
142 #define R9A07G044_CA55_RST_7		7
143 #define R9A07G044_CA55_RST_8		8
144 #define R9A07G044_CA55_RST_9		9
145 #define R9A07G044_CA55_RST_10		10
146 #define R9A07G044_CA55_RST_11		11
147 #define R9A07G044_CA55_RST_12		12
148 #define R9A07G044_GIC600_GICRESET_N	13
149 #define R9A07G044_GIC600_DBG_GICRESET_N	14
150 #define R9A07G044_IA55_RESETN		15
151 #define R9A07G044_MHU_RESETN		16
152 #define R9A07G044_DMAC_ARESETN		17
153 #define R9A07G044_DMAC_RST_ASYNC	18
154 #define R9A07G044_SYC_RESETN		19
155 #define R9A07G044_OSTM0_PRESETZ		20
156 #define R9A07G044_OSTM1_PRESETZ		21
157 #define R9A07G044_OSTM2_PRESETZ		22
158 #define R9A07G044_MTU_X_PRESET_MTU3	23
159 #define R9A07G044_POE3_RST_M_REG	24
160 #define R9A07G044_GPT_RST_C		25
161 #define R9A07G044_POEG_A_RST		26
162 #define R9A07G044_POEG_B_RST		27
163 #define R9A07G044_POEG_C_RST		28
164 #define R9A07G044_POEG_D_RST		29
165 #define R9A07G044_WDT0_PRESETN		30
166 #define R9A07G044_WDT1_PRESETN		31
167 #define R9A07G044_WDT2_PRESETN		32
168 #define R9A07G044_SPI_RST		33
169 #define R9A07G044_SDHI0_IXRST		34
170 #define R9A07G044_SDHI1_IXRST		35
171 #define R9A07G044_GPU_RESETN		36
172 #define R9A07G044_GPU_AXI_RESETN	37
173 #define R9A07G044_GPU_ACE_RESETN	38
174 #define R9A07G044_ISU_ARESETN		39
175 #define R9A07G044_ISU_PRESETN		40
176 #define R9A07G044_H264_X_RESET_VCP	41
177 #define R9A07G044_H264_CP_PRESET_P	42
178 #define R9A07G044_CRU_CMN_RSTB		43
179 #define R9A07G044_CRU_PRESETN		44
180 #define R9A07G044_CRU_ARESETN		45
181 #define R9A07G044_MIPI_DSI_CMN_RSTB	46
182 #define R9A07G044_MIPI_DSI_ARESET_N	47
183 #define R9A07G044_MIPI_DSI_PRESET_N	48
184 #define R9A07G044_LCDC_RESET_N		49
185 #define R9A07G044_SSI0_RST_M2_REG	50
186 #define R9A07G044_SSI1_RST_M2_REG	51
187 #define R9A07G044_SSI2_RST_M2_REG	52
188 #define R9A07G044_SSI3_RST_M2_REG	53
189 #define R9A07G044_SRC_RST		54
190 #define R9A07G044_USB_U2H0_HRESETN	55
191 #define R9A07G044_USB_U2H1_HRESETN	56
192 #define R9A07G044_USB_U2P_EXL_SYSRST	57
193 #define R9A07G044_USB_PRESETN		58
194 #define R9A07G044_ETH0_RST_HW_N		59
195 #define R9A07G044_ETH1_RST_HW_N		60
196 #define R9A07G044_I2C0_MRST		61
197 #define R9A07G044_I2C1_MRST		62
198 #define R9A07G044_I2C2_MRST		63
199 #define R9A07G044_I2C3_MRST		64
200 #define R9A07G044_SCIF0_RST_SYSTEM_N	65
201 #define R9A07G044_SCIF1_RST_SYSTEM_N	66
202 #define R9A07G044_SCIF2_RST_SYSTEM_N	67
203 #define R9A07G044_SCIF3_RST_SYSTEM_N	68
204 #define R9A07G044_SCIF4_RST_SYSTEM_N	69
205 #define R9A07G044_SCI0_RST		70
206 #define R9A07G044_SCI1_RST		71
207 #define R9A07G044_IRDA_RST		72
208 #define R9A07G044_RSPI0_RST		73
209 #define R9A07G044_RSPI1_RST		74
210 #define R9A07G044_RSPI2_RST		75
211 #define R9A07G044_CANFD_RSTP_N		76
212 #define R9A07G044_CANFD_RSTC_N		77
213 #define R9A07G044_GPIO_RSTN		78
214 #define R9A07G044_GPIO_PORT_RESETN	79
215 #define R9A07G044_GPIO_SPARE_RESETN	80
216 #define R9A07G044_ADC_PRESETN		81
217 #define R9A07G044_ADC_ADRST_N		82
218 #define R9A07G044_TSU_PRESETN		83
219 
220 /* Power domain IDs. */
221 #define R9A07G044_PD_ALWAYS_ON		0
222 #define R9A07G044_PD_GIC		1
223 #define R9A07G044_PD_IA55		2
224 #define R9A07G044_PD_MHU		3
225 #define R9A07G044_PD_CORESIGHT		4
226 #define R9A07G044_PD_SYC		5
227 #define R9A07G044_PD_DMAC		6
228 #define R9A07G044_PD_GTM0		7
229 #define R9A07G044_PD_GTM1		8
230 #define R9A07G044_PD_GTM2		9
231 #define R9A07G044_PD_MTU		10
232 #define R9A07G044_PD_POE3		11
233 #define R9A07G044_PD_GPT		12
234 #define R9A07G044_PD_POEGA		13
235 #define R9A07G044_PD_POEGB		14
236 #define R9A07G044_PD_POEGC		15
237 #define R9A07G044_PD_POEGD		16
238 #define R9A07G044_PD_WDT0		17
239 #define R9A07G044_PD_WDT1		18
240 #define R9A07G044_PD_SPI		19
241 #define R9A07G044_PD_SDHI0		20
242 #define R9A07G044_PD_SDHI1		21
243 #define R9A07G044_PD_3DGE		22
244 #define R9A07G044_PD_ISU		23
245 #define R9A07G044_PD_VCPL4		24
246 #define R9A07G044_PD_CRU		25
247 #define R9A07G044_PD_MIPI_DSI		26
248 #define R9A07G044_PD_LCDC		27
249 #define R9A07G044_PD_SSI0		28
250 #define R9A07G044_PD_SSI1		29
251 #define R9A07G044_PD_SSI2		30
252 #define R9A07G044_PD_SSI3		31
253 #define R9A07G044_PD_SRC		32
254 #define R9A07G044_PD_USB0		33
255 #define R9A07G044_PD_USB1		34
256 #define R9A07G044_PD_USB_PHY		35
257 #define R9A07G044_PD_ETHER0		36
258 #define R9A07G044_PD_ETHER1		37
259 #define R9A07G044_PD_I2C0		38
260 #define R9A07G044_PD_I2C1		39
261 #define R9A07G044_PD_I2C2		40
262 #define R9A07G044_PD_I2C3		41
263 #define R9A07G044_PD_SCIF0		42
264 #define R9A07G044_PD_SCIF1		43
265 #define R9A07G044_PD_SCIF2		44
266 #define R9A07G044_PD_SCIF3		45
267 #define R9A07G044_PD_SCIF4		46
268 #define R9A07G044_PD_SCI0		47
269 #define R9A07G044_PD_SCI1		48
270 #define R9A07G044_PD_IRDA		49
271 #define R9A07G044_PD_RSPI0		50
272 #define R9A07G044_PD_RSPI1		51
273 #define R9A07G044_PD_RSPI2		52
274 #define R9A07G044_PD_CANFD		53
275 #define R9A07G044_PD_ADC		54
276 #define R9A07G044_PD_TSU		55
277 
278 #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
279