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Searched refs:R5 (Results 1 – 25 of 37) sorted by relevance

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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a.dtsi113 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
114 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
115 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
116 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
122 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
123 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
130 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
131 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
143 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
144 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
H A Dk3-am62.dtsi112 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
113 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
131 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
132 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
H A Dk3-am62p.dtsi126 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
127 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
140 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
141 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
H A Dk3-j722s.dtsi209 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
210 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
223 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
224 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
/linux/drivers/tty/serial/
H A Dpmac_zilog.c135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
167 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
539 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
540 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
542 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
544 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
677 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
678 uap->curregs[R5] = new_reg; in pmz_break_ctl()
679 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
[all …]
H A Dsunzilog.c207 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
254 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
660 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
661 up->curregs[R5] &= ~clear_bits; in sunzilog_set_mctrl()
662 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_set_mctrl()
768 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
769 if (new_reg != up->curregs[R5]) { in sunzilog_break_ctl()
770 up->curregs[R5] = new_reg; in sunzilog_break_ctl()
773 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_break_ctl()
788 up->curregs[R5] |= TxENAB; in __sunzilog_startup()
[all …]
H A Dzs.h65 #define R5 5 macro
H A Dsunzilog.h36 #define R5 5 macro
H A Dip22zilog.h44 #define R5 5 macro
H A Dpmac_zilog.h122 #define R5 5 macro
/linux/tools/perf/arch/arm/tests/
H A Dregs_load.S9 #define R5 0x28 macro
46 str r5, [r0, #R5]
/linux/tools/perf/arch/powerpc/tests/
H A Dregs_load.S10 #define R5 5 * 8 macro
49 std 5, R5(3)
/linux/Documentation/bpf/standardization/
H A Dabi.rst20 * R1 - R5: arguments for function calls
24 R0 - R5 are scratch registers and BPF programs needs to spill/fill them if
/linux/lib/
H A Dtest_bpf.c44 #define R5 BPF_REG_5 macro
1643 i += __bpf_ld_imm64(&insns[i], R5, keep); in __bpf_emit_atomic64()
1655 insns[i++] = BPF_JMP_REG(BPF_JEQ, R0, R5, 1); in __bpf_emit_atomic64()
1690 i += __bpf_ld_imm64(&insns[i], R5, keep); in __bpf_emit_atomic32()
1702 insns[i++] = BPF_JMP_REG(BPF_JEQ, R0, R5, 1); in __bpf_emit_atomic32()
3803 BPF_ALU64_IMM(BPF_MOV, R5, 5),
3813 BPF_ALU64_IMM(BPF_ADD, R5, 20),
3823 BPF_ALU64_IMM(BPF_SUB, R5, 10),
3833 BPF_ALU64_REG(BPF_ADD, R0, R5),
3845 BPF_ALU64_REG(BPF_ADD, R1, R5),
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_entry.S57 { memd(R0 + #_PT_R0504) = R5:4; \
100 memd(R0 + #_PT_R0504) = R5:4; \
136 { R5:4 = memd(R0 + #_PT_R0504); \
168 { R5:4 = memd(R0 + #_PT_R0504); \
/linux/arch/powerpc/platforms/pseries/
H A DhvCall.S38 std r5,STK_PARAM(R5)(r1); \
50 ld r5,STACK_FRAME_MIN_SIZE+STK_PARAM(R5)(r1); \
185 HCALL_INST_PRECALL(R5)
294 HCALL_INST_PRECALL(R5)
/linux/drivers/net/hamradio/
H A Dscc.c805 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */ in init_channel()
937 or(scc,R5, TxENAB); in scc_key_trx()
938 scc->wreg[R5] |= RTS; in scc_key_trx()
940 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ in scc_key_trx()
943 cl(scc,R5,RTS|TxENAB); in scc_key_trx()
971 or(scc,R5, TxENAB); in scc_key_trx()
972 scc->wreg[R5] |= RTS; in scc_key_trx()
974 or(scc,R5,RTS|TxENAB); /* enable tx */ in scc_key_trx()
977 cl(scc,R5,RTS|TxENAB); /* disable tx */ in scc_key_trx()
1110 if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) ) in is_grouped()
[all …]
H A Dz8530.h12 #define R5 5 macro
/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
65 place function arguments into R1 to R5 registers to satisfy calling
67 to in-kernel function. If R1 - R5 registers are mapped to CPU registers
74 After an in-kernel function call, R1 - R5 are reset to unreadable and R0 has
123 R5 - r8
139 bpf_mov R5, 5
146 bpf_mov R5, 9
188 interpreter. R0-R5 are scratch registers, so eBPF program needs to preserve
198 After the call the registers R1-R5 contain junk values and cannot be read.
/linux/arch/hexagon/lib/
H A Dmemcpy.S164 #define ptr_in_p_128 R5 /* pointer for prefetch of input data */
167 #define shift2 R5 /* in epilog to workshifter to extract bytes */
177 #define ptr_in_p_128kernel R5:4 /* packed fetch pointer & kernel cnt */
/linux/tools/perf/arch/arm/util/
H A Dunwind-libdw.c25 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux/tools/perf/arch/loongarch/util/
H A Dunwind-libdw.c27 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux/tools/perf/arch/s390/util/
H A Dunwind-libdw.c31 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux/tools/perf/arch/powerpc/util/
H A Dunwind-libdw.c34 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux/arch/powerpc/kvm/
H A Dbookehv_interrupts.S180 PPC_STL r5, VCPU_GPR(R5)(r4)
287 PPC_STL r5, VCPU_GPR(R5)(r11)
314 PPC_STL r5, VCPU_GPR(R5)(r11)
665 PPC_LL r5, VCPU_GPR(R5)(r4)

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